19th week of 2014 patent applcation highlights part 30 |
Patent application number | Title | Published |
20140126262 | INVERTER CIRCUIT - An inverter circuit includes a DC-AC inverter, a sampling circuit, a voltage-current conversion circuit, an isolation circuit and an electronic starter switch. The sampling circuit includes a first and a second diode connected in parallel and opposite in polarity. A forward voltage drop at the first diode blocks the conductance of a first transistor of the voltage-current conversion circuit when there is no load, and a forward voltage drop at the second diode turns on the first transistor when there is a load. The connection of the first and second diodes to a second AC output terminal of the DC-AC inverter nearly has no impact on the AC output of the inverter circuit. These enable the inverter circuit to have low power consumption when there is no load and to be immediately activated upon connection of a load, thereby achieving detection of a load smaller than 0.1 W. | 2014-05-08 |
20140126263 | POWER CONVERSION DEVICE - There is disclosed a power conversion apparatus | 2014-05-08 |
20140126264 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 2014-05-08 |
20140126265 | SEMICONDUCTOR MEMORY DEVICES - Semiconductor memory devices include unit cells two-dimensionally arranged along rows and columns in one cell array block. The unit cells are classified into a plurality of cell subgroups, and each of the cell subgroups includes the unit cells constituting a plurality of the rows. Each of the unit cells includes a selection element and a data storage part. A word line is connected to gate electrodes of selection elements of the unit cells constituting each column. Bit lines are connected to data storage parts of the unit cells constituting the rows. A source line, parallel to the bit line, is electrically connected to source terminals of the selection elements of the unit cells in each cell subgroup. The source line is parallel to the bit line. A distance between the source line and the select bit line is equal to a distance between the bit lines adjacent to each other. | 2014-05-08 |
20140126266 | ONE-TIME PROGRAMMABLE MEMORIES USING POLYSILICON DIODES AS PROGRAM SELECTORS - Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device can have an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. | 2014-05-08 |
20140126267 | VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE - Provided is a variable resistance element (Rij) the resistance state of which is reversibly changed by applying electrical signals of different polarities; and a current steering element (Dij) in which a first current is larger than a second current, the first current being a current which flows when a voltage of the first polarity having a first value is applied, the first value being less than a predetermined voltage value and having an absolute value greater than zero, the second current being a current which flows when a voltage of the second polarity having an absolute value which is the first value is applied, the second polarity being different from the first polarity, in which Rij and Dij are connected in series such that the polarity of a voltage to be applied to Dij is the second polarity when the resistance state of Rij is changed to high resistance state. | 2014-05-08 |
20140126268 | METHOD OF DRIVING NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE - A method of driving a nonvolatile memory element including a variable resistance element having a state reversibly changing between low and high resistance states by an applied electrical signal and a transistor serially connected to the variable resistance element. The method including: setting the variable resistance element to the low resistance state by applying a first gate voltage to a gate of the transistor and applying a first write voltage negative with respect to a first electrode; and changing a resistance value of the transistor obtained in a low-resistance write operation, when a value of current passing through the variable resistance element in the setting of the low resistance state or a resistance value of the nonvolatile memory element in the case where the variable resistance element is in the low resistance state is outside a predetermined range. | 2014-05-08 |
20140126269 | RESISTIVE MEMORY - A memory device includes an upper conductive layer, a lower layer, and a resistive, optical or magnetic matrix positioned between the upper and lower layers. | 2014-05-08 |
20140126270 | SEMICONDUCTOR MEMORY DEVICE - A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases. | 2014-05-08 |
20140126271 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - To provide a semiconductor device in which power consumption can be reduced and operation delay due to a stop and a restart of supply of power supply voltage can be suppressed and a driving method thereof. A potential corresponding to data held in a period during which power supply voltage is continuously supplied is saved to a node connected to a capacitor before the supply of power supply voltage is stopped. By utilizing change of channel resistance of a transistor whose gate is the node, data is loaded when the supply of power supply voltage is restarted. | 2014-05-08 |
20140126272 | MEMORY CIRCUIT, MEMORY UNIT, AND SIGNAL PROCESSING CIRCUIT - A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit. | 2014-05-08 |
20140126273 | POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a precharge device connected between a voltage supply and the local bit line, and global bit line (GBL) discharge logic connected between a local bit line and a GBL. The GBL discharge logic transfers a logic value of the local bit line to the GBL during a read operation. GBL precharge logic connects the GBL to a global precharge input. The GBL precharge logic is adapted to draw the GBL to a precharge voltage above a discharge voltage and below a supply voltage during a precharge operation. | 2014-05-08 |
20140126274 | MEMORY CIRCUIT AND METHOD OF OPERATING THE MEMORY CIRCUI - A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals. | 2014-05-08 |
20140126275 | SYSTEM AND METHOD FOR TUNING A SUPPLY VOLTAGE FOR DATA RETENTION - A processor and a system are provided for tuning a supply voltage for data retention. The contents of data storage circuitry are read and a data verification indication corresponding to the contents is computed. Then, the supply voltage provided to the data storage circuitry is reduced to a low voltage level that is intended to retain the contents of the data storage circuitry. | 2014-05-08 |
20140126276 | POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT - A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a precharge device connected between a voltage supply and the local bit line, and global bit line (GBL) discharge logic connected between a local bit line and a GBL. The GBL discharge logic transfers a logic value of the local bit line to the GBL during a read operation. GBL precharge logic connects the GBL to a global precharge input. The GBL precharge logic is adapted to draw the GBL to a precharge voltage above a discharge voltage and below a supply voltage during a precharge operation. | 2014-05-08 |
20140126277 | SRAM WITH BUFFERED-READ BIT CELLS AND ITS TESTING - An SRAM with buffered-read bit cells is disclosed ( | 2014-05-08 |
20140126278 | SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE - Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented. | 2014-05-08 |
20140126279 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A magnetoresistive random access memory (MRAM) apparatus includes a first conductive line and a second conductive line. A magnetic tunnel junction is in electrical communication with the first conductive line and the second conductive line. The magnetic tunnel junction includes at least one programmable magnetic layer. The MRAM apparatus also includes an insulating layer radially surrounding the magnetic tunnel junction, and the insulating layer has a cavity adjacent to the magnetic tunnel junction. | 2014-05-08 |
20140126280 | MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION - A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance. | 2014-05-08 |
20140126281 | MULTIPLE BIT NONVOLATILE MEMORY BASED ON CURRENT INDUCED DOMAIN WALL MOTION IN A NANOWIRE MAGNETIC TUNNEL JUNCTION - A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance. | 2014-05-08 |
20140126282 | READING A CROSS POINT CELL ARRAY - A mechanism is provided for reading a cross point cell array. Voltage biasing is applied to the cross point cell array to determine a state of a target cell on a selected bit line. A negative magnetic field is generated for a selected write bit line corresponding to the target cell. A first current is measured through a selected word line responsive to the negative magnetic field. A positive magnetic field is generated for the selected write bit line corresponding to the target cell. A second current is measured through the selected word line responsive to the positive magnetic field. The state of the target cell is determined based on the first current relative to the second current. | 2014-05-08 |
20140126283 | MULTILEVEL MAGNETIC ELEMENT - The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line. | 2014-05-08 |
20140126284 | MRAM SENSING WITH MAGNETICALLY ANNEALED REFERENCE CELL - Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising at least one magnetic storage cell, wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element is configured to establish a reference voltage during a read operation. | 2014-05-08 |
20140126285 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device and an operating method of the semiconductor memory device change a read voltage used in a read operation by performing a moving read operation, a randomize operation, and a program/erase compensation operation independently or in combination, thereby stably performing the read operation without an error and reducing a time for the read operation even when distribution of threshold voltages of the memory cells is changed according to a program/erase cycling effect or a retention effect. | 2014-05-08 |
20140126286 | SINGLE-LEVEL CELL ENDURANCE IMPROVEMENT WITH PRE-DEFINED BLOCKS - Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel oxide may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner tunnel oxide in SLC blocks may allow a lower program voltage to be used, which may improve endurance. A thicker tunnel oxide in MLC blocks may improve data retention. A thinner IPD may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner IPD may provide a higher coupling ratio, which may allow a lower program voltage. A lower program voltage in SLC blocks can improve endurance. A thicker IPD in MLC blocks can prevent or reduce read disturb. SLC blocks may have a different number of data word lines than MLC blocks. | 2014-05-08 |
20140126287 | Methods And Apparatus For Storing Data In A Multi-Level Cell Flash Memory Device With Cross-Page Sectors, Multi-Page Coding And Per-Page Coding - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 2014-05-08 |
20140126288 | Methods And Apparatus For Storing Data In A Multi-Level Cell Flash Memory Device With Cross-Page Sectors, Multi-Page Coding And Per-Page Coding - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 2014-05-08 |
20140126289 | Methods And Apparatus For Storing Data In A Multi-Level Cell Flash Memory Device With Cross-Page Sectors, Multi-Page Coding And Per-Page Coding - Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided. | 2014-05-08 |
20140126290 | MEMORY ARRAYS WITH A MEMORY CELL ADJACENT TO A SMALLER SIZE OF A PILLAR HAVING A GREATER CHANNEL LENGTH THAN A MEMORY CELL ADJACENT TO A LARGER SIZE OF THE PILLAR AND METHODS - The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size. | 2014-05-08 |
20140126291 | 3D STACKED NON-VOLATILE STORAGE PROGRAMMING TO CONDUCTIVE STATE - Programming NAND strings in a 3D stacked storage device to a conductive state is disclosed. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided. | 2014-05-08 |
20140126292 | Flash Memory with Data Retention Bias - Charge leakage from a floating gate in a NAND flash memory die is reduced by applying a data retention bias to a word line extending over the floating gates. The data retention bias is applied to one or more selected word lines when the memory die is in idle mode, when no read, write, erase, or other commands are being executed in the memory die. | 2014-05-08 |
20140126293 | Centralized Variable Rate Serializer and Deserializer for Bad Column Management - A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. | 2014-05-08 |
20140126294 | UPDATING REFERENCE VOLTAGES TO COMPENSATE FOR CHANGES IN THRESHOLD VOLTAGE DISTRIBUTIONS OF NONVOLATILE MEMORY CELLS - A system including a reference voltage module configured to generate one or more reference voltages for determining states of a plurality of memory cells of a nonvolatile memory, where the plurality of memory cells have a threshold voltage distribution. A divider module divides, in response to a change in the threshold voltage distribution, a voltage range into a plurality of regions. An update module updates, to compensate for the change in the threshold voltage distribution, one of the reference voltages to a voltage value associated with one of the plurality of regions. | 2014-05-08 |
20140126295 | APPARATUSES AND METHODS OF REPROGRAMMING MEMORY CELLS - Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having a first program verify voltage associated therewith; and reprogramming the number of memory cells such that at least one of the number of memory cells is reprogrammed to a third program state having a second program verify voltage associated therewith, wherein those of the number of memory cells having a threshold voltage less than the second program verify voltage represent a same data value. | 2014-05-08 |
20140126296 | FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is an integer greater than 2. The memory array includes a plurality of memory cells and is connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. Each of the page buffers is connected to N bit lines of the bit lines, and N is an integer equal to or greater than 3. A j | 2014-05-08 |
20140126297 | ACCESS LINE MANAGEMENT IN A MEMORY DEVICE - Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device. | 2014-05-08 |
20140126298 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device may include increasing threshold voltage of memory cells by performing an LSB program operation on the memory cells having first state, decreasing threshold voltage of memory cells to be programmed to second state of the memory cells to a level lower than a first level in unit of a memory cell for an MSB program operation, and increasing threshold voltage of memory cells to be programmed to third state of the memory cells to a level higher than a second level, which is higher than the first level, in unit of a memory cell for an MSB program operation. | 2014-05-08 |
20140126299 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor layer, a floating gate electrode provided over the semiconductor layer via a first insulation film, and an erase gate electrode to which an erase voltage is applied. The floating gate electrode has an opposing region that opposes via a second insulation film to the erase gate electrode. The opposing region has such a shape that multiple electric field concentrating portions are formed when the erase voltage is applied to the erase gate electrode. | 2014-05-08 |
20140126300 | Semiconductor Memory Device, Information Processing System Including the Same, and Controller - To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased. | 2014-05-08 |
20140126301 | MEMORY DEVICE AND TEST METHOD THEREOF - A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and matching the memory bank address and the row address with each other and programming the matched address to a nonvolatile memory when the data read from the multiple memory banks are different from each other. | 2014-05-08 |
20140126302 | MEMORY DEVICE AND TEST METHOD THEREOF - A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and programming the row address to locations designated by the bank address latched in the latching in a nonvolatile memory when the data read from the multiple memory banks are different from each other. | 2014-05-08 |
20140126303 | Adaptive FIFO - An adaptive synchronous FIFO includes a plurality of input data latch stages that sample variable-length input data at a write clock frequency, and a data compression circuit that combines the variable-length input data, together with partial-row data from a row of the FIFO storage array, and writes the combined data at a read clock frequency. The number of data latch stages is adaptive according to the ratio of the read and write clock frequencies. | 2014-05-08 |
20140126304 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory system includes one or more memory chips, and a repair information storage chip including a nonvolatile memory configured to store a repair information of the one or more memory chips, wherein during an initial operation of the memory system, the repair information stored in the repair information storage chip is transmitted to the one or more memory chips. | 2014-05-08 |
20140126305 | DATA CAPTURE SYSTEM AND METHOD, AND MEMORY CONTROLLERS AND DEVICES - Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits. | 2014-05-08 |
20140126306 | Electronic Device with a Plurality of Memory Cells and with Physically Unclonable Function - An electronic device includes a non-volatile memory having a plurality of memory cells, a memory controller, and an evaluator. The memory controller is configured to provide control signals to the non-volatile memory causing the non-volatile memory, or a selected memory section of the non-volatile memory, to be in one of a read state and a weak erase state, wherein the weak erase state causes the plurality of memory cells to maintain different states depending on different physical properties of the plurality of memory cells. The evaluator is configured to read out the plurality of memory cells and to provide a readout pattern during the read state, wherein the readout pattern that is provided after a preceding weak erase state corresponds to a physically unclonable function (PUF) response of the electronic device uniquely identifying the electronic device. | 2014-05-08 |
20140126307 | TECHNIQUES FOR REFRESHING A SEMICONDUCTOR MEMORY DEVICE - Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region. | 2014-05-08 |
20140126308 | INTEGRATED CIRCUIT AND MEMORY DEVICE - A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed. | 2014-05-08 |
20140126309 | SHIFTABLE MEMORY - A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset. | 2014-05-08 |
20140126310 | SYSTEMS AND METHODS FOR DATA STROBE CALIBRATION FOR TIMING VARIATIONS - A strobe calibration component for a memory control device includes a tri-state detection receiver, an edge detection component, and an extension gate generation component. The tri-state detection receiver is configured to identify states of an input signal. One of the states includes a high impedance state. The edge detection component is configured to identify valid edges from a sequence of states provided from the tri-state detection receiver. The extension gate generation component is configured to generate a calibrated gate signal according to the valid edges from the edge detection component. | 2014-05-08 |
20140126311 | REFRESH CONTROL CIRCUIT OF SEMICONDUCTOR APPARATUS - A refresh control circuit of a semiconductor apparatus includes a variable delay unit configured to delay a signal that is activated quickest among a plurality of row address strobe signals activated at a predetermined time interval by a predetermined time, and to generate a preliminary pulse signal, and a piled delay unit configured to delay the preliminary pulse signal by various times, and to generate a plurality of refresh period pulse signals that are sequentially activated. | 2014-05-08 |
20140126312 | SENSE AMPLIFIER SOFT-FAIL DETECTION CIRCUIT - Embodiments of a sense amplifier test circuit are disclosed that may allow for detecting soft failures. The sense amplifier test circuit may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier. | 2014-05-08 |
20140126313 | CHIP WITH EMBEDDED NON-VOLATILE MEMORY AND TESTING METHOD THEREFOR - A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit. | 2014-05-08 |
20140126314 | Memory Architecture With Local And Global Control Circuitry - A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global sense amplifier operable to receive a sensed data state from the local sense amplifier. | 2014-05-08 |
20140126315 | CIRCUIT AND METHOD FOR IMPROVING SENSE AMPLIFIER REACTION TIME IN MEMORY READ OPERATIONS - A sense amplifier circuit, a method of modifying a differential voltage in a sense amplifier circuit and a memory system incorporating the sense amplifier circuit or the method. In one embodiment, the sense amplifier circuit includes: (1) a differential amplifier having first and second inputs respectively couplable to first and second complimentary bit lines and configured to receive a differential voltage therefrom representing a current logic value to be read and (2) a sense speed alteration circuit having first and second outputs respectively coupled to the first and second inputs via respective first and second capacitors and configured to cause one of the first and second capacitors to discharge to increase the differential voltage when a previously read logic value is opposite the current logic value to be read. | 2014-05-08 |
20140126316 | CIRCUIT AND METHOD FOR DYNAMICALLY CHANGING A TRIP POINT IN A SENSING INVERTER - A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit associated with the base inverter circuit and configured to employ the previous logic-level voltage to decouple one of the logic-high and logic-low voltage sources from one of the inputs and thereby shift a trip voltage of the base inverter circuit toward the input voltage. | 2014-05-08 |
20140126317 | E-FUSE ARRAY CIRCUIT - An e-fuse array circuit includes a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage, a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage, a program/read line supplied with the high voltage when a program operation is activated, a read voltage, which is lower than the high voltage, when a read operation is activated, or the negative voltage when deactivated, a row line supplied with the ground voltage when the row line is activated or the negative voltage when the row line is deactivated, an e-fuse device supplied with voltage of the program/read line, a switch device controlled by the row line and configured to electrically connect the e-fuse device with a column line, and a column circuit configured to supply the negative voltage to the column line when the column line is activated. | 2014-05-08 |
20140126318 | INTEGRATED CIRCUIT INCLUDING E-FUSE ARRAY CIRCUIT - An integrated circuit includes a high voltage generator generating a high voltage, a negative voltage generator generating a negative voltage, a divided voltage generator generating a divided voltage by dividing the power source voltage and supplying it to a read voltage terminal, a first power gate supplying the high voltage or the divided voltage to a program voltage terminal, a second power gate supplying the negative voltage or the ground voltage to a deactivation voltage terminal, a third power gate supplying the ground voltage or the divided voltage to an activation voltage terminal, and an e-fuse array circuit operating using voltage of the program voltage terminal as a program voltage, voltage of the divided voltage terminal as a read voltage, voltage of the activation voltage terminal as an activation voltage, and voltage of the deactivation voltage terminal as a deactivation voltage. | 2014-05-08 |
20140126319 | SETTING INFORMATION STORAGE CIRCUIT AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME - A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data. | 2014-05-08 |
20140126320 | DEVICE FOR MIXING AND DISPENSING A PASTY MASS - A device, for mixing and dispensing a pasty mass, comprising a cartridge that is open or can be opened on two ends and has a mixing element and a feed plunger arranged in it, whereby the feed plunger, in a starting position, is arranged in the region of a first cartridge end, the mixing element is arranged on a mixing rod, the mixing rod extends through the feed plunger into the inside of the cartridge, the mixing rod and the feed plunger and the cartridge together form a tight connection that seals the cartridge inside of the device with respect to the exterior, whereby the feed plunger is arranged on the mixing rod and such that it can move in the cartridge in axial direction and whereby at least one clamping jaw is arranged on the feed plunger in appropriate manner such that the clamping jaw can be pressed onto the mixing rod by means of a locking element such that the mixing rod can no longer be shifted with respect to the feed plunger. | 2014-05-08 |
20140126321 | NAIL POLISH MIXING APPARATUS - A nail polish mixing apparatus for stirring the mixing balls and nail polish contained with a nail polish bottle comprises a base, a vertical support column having an opening defined by a slot, and a motor in connection with a first end of a shaft. A linkage includes a top end that is rotatably fixed to a guide pin sized and configured to move up and down within the slot, and a bottom end that is rotatably fixed to a peripheral edge of a wheel that is in connection with a second end of the shaft. A ring on the linkage is provided for securing the nail polish bottle. Upon activation, the motor rotates the wheel, causing the bottom end of the linkage to move in a circular motion and the top end of the linkage to move up and down, thereby mixing the contents in the nail polish bottle. | 2014-05-08 |
20140126322 | ACOUSTICALLY TRANSPARENT AND ACOUSTIC WAVE STEERING MATERIALS FOR ACOUSTIC CLOAKING AND METHODS OF FABRICATION THEREOF - Disclosed an acoustically transparent material including an acoustic wave steering material, and methods for fabrication and use thereof. The materials are specially designed structures of homogenous isotropic metals. These structures are constructed to propagate waves according to Pentamode elastic theory. The metamaterial structures are two-dimensional, intended to propagate acoustic waves in the plane in a manner which closely emulates the propagation of waves in water. The acoustically transparent materials described herein have particular utility as acoustic wave steering materials and acoustic cloaks. | 2014-05-08 |
20140126323 | ULTRASOUND IMAGING SYSTEM - An ultrasonic imaging system for generating an ultrasonic image of a motion status of an object according to at least an ultrasonic motion signal generated by detecting the motion of the object is provided. The ultrasonic imaging system includes a demodulation module, an analog sub-array beamformer, a filter, an analog-to-digital converter and an image processing module. The demodulation module receives and demodulates the ultrasonic motion signal so as to generate and send at least a demodulated signal. The analog sub-array beamformer receives the demodulated signal, generates and sends an analog sub-array beam signal according to the demodulated signal. The filter receives and filtering the analog sub-array beam signal. The analog-to-digital converter converts the analog sub-array beam signal filtered by the filter into a digital sub-array beam signal. The image processing module receives the digital sub-array beam signal so as to generate an ultrasonic image of the motion of the object. | 2014-05-08 |
20140126324 | ACOUSTO-OPTIC IMAGE CAPTURE DEVICE - An acousto-optic image capture device includes: an acoustic beam source, an acoustic lens system; an acousto-optic medium portion arranged on the path of the scattered wave transmitted through the acoustic lens system; a light source that emits a light beam including monochromatic rays of light toward the acousto-optic medium portion obliquely; an imaging lens system that condenses diffracted rays of light produced by the acousto-optic medium; and an image receiving section that detects the rays of light condensed by the imaging lens system. The acoustic lens system includes at least a telecentric acoustic system and a sound-collecting acoustic system arranged on the image space. The distance between acoustic systems is equal to the sum of the respective focal lengths of the telecentric acoustic system and the sound-collecting acoustic system. The light beam is transmitted at the focal point of the sound-collecting acoustic system through the acousto-optic medium portion. | 2014-05-08 |
20140126325 | ENHANCED SEISMIC SURVEYING - Embodiments of the present invention help in the processing and interpretation of seismic survey data, by correlating or otherwise comparing or associating seismic data obtained from a seismic survey with flow information obtained from a well or borehole in the surveyed area. In particular, embodiments of the present invention allow for flow data representing a flow profile along a well that is being monitored by a distributed acoustic sensor to be determined, such that regions of higher flow in the well can be determined. For example, in the production zone the well will be perforated to allow oil to enter the well, but it has not previously been possible to determine accurately where in the production zone the oil is entering the well. However, by determining a flow rate profile along the well using the i)AS then this provides information as to where in the perforated production zone oil is entering the well, and hence the location of oil bearing sands. This location can then be combined or otherwise correlated, used, or associated with petroleum reservoir location information obtained from the seismic survey, to improve the confidence and/or accuracy in the determined petroleum reservoir location. | 2014-05-08 |
20140126326 | METHOD AND SEISMIC VIBRATOR GUIDANCE SYSTEM BASED ON A FIELD ACQUIRED TRAJECTORY - A method for improving a 4-dimensional (4D) repeatability by modifying a given path to be followed by a source during a seismic survey. The method includes receiving the given path at a control device associated with a vehicle that caries the source; following the given path during a first seismic survey that is a baseline survey for the 4D seismic survey; deviating from the given path to follow a new path when encountering an obstacle on the given path; and updating the given path, based on the new path, to obtain an updated given path when a deviation condition is met. | 2014-05-08 |
20140126327 | SEISMIC SENSING DEVICE - In one example, a land based seismic sensing device includes: a seismic sensing unit having a seismic sensor in a housing configured to be buried in the ground; a control unit including a battery in a weather resistant housing configured to be exposed above ground; and a flexible cable mechanically and electrically connecting the seismic sensing unit and the control unit. The cable includes a weather resistant jacket and an electrically conductive element inside the jacket detachably connected between electronic circuitry in the sensing unit and electronic circuitry in the control unit. In one example, the control unit housing includes a first compartment configured to stow the seismic sensing unit and a second compartment configured to stow the cable. | 2014-05-08 |
20140126328 | Methods and Systems for Improving Microseismic Event Detection and Location - Methods and systems for location and/or direction of a hypocenter. The methods may involve one or more of: a) computing a joint probability density function (PDF) which includes polarization PDF and onset time PDF or a time integral of product of detection transforms to estimate the location and/or direction of a hypocenter, where the polarization PDF is generated using a weighted average of differences between measured and computed polarizations; b) computing a time integral of product of modified detection transforms associated with onset times from received data in Coalescence Microsesimic Mapping where modified detection transform is defined as (ε, fd(t)−1); c) resolving 180 degree ambiguities in polarization estimated according to Hodogram; d) using polynomial interpolation to tune the location of a hypocenter; and e) computing an integration time interval of 4-D (t,x,y,z) PDF or product of modified detection transform and the restriction on grid nodes. | 2014-05-08 |
20140126329 | LAND BASED UNIT FOR SEISMIC DATA ACQUISITION - In one aspect, a seismic data acquisition unit is disclosed including a closed housing containing: a seismic sensor; a processor operatively coupled to the seismic sensor; a memory operatively coupled to the processor to record seismic data from the sensor; and a power source configured to power the sensor, processor and memory. The sensor, processor, memory and power source are configured to be assemble as an operable unit in the absence of the closed housing. | 2014-05-08 |
20140126330 | COILED TUBING CONDITION MONITORING SYSTEM - A system and techniques for acoustically establishing the onset of an emergent condition relative coiled tubing in a well. The system may include fiber optic line run through the coiled tubing for sake of vibration detection in coiled tubing indicative of buckling, structural defects or other downhole coiled tubing conditions. Thus, application optimization action may be undertaken in a manner that enhances coiled tubing operational efficacy. | 2014-05-08 |
20140126331 | ACOUSTIC TELEMETRY WITH DISTRIBUTED ACOUSTIC SENSING SYSTEM - An acoustic telemetry method for use with a subterranean well can include positioning a well tool in the well, the well tool including an acoustic transmitter and a sensor, and an acoustic receiver in the well receiving an acoustic signal transmitted by the transmitter, the acoustic signal including information representative of a measurement by the sensor. A system for use with a subterranean well can include a well tool positioned in the well, the well tool including an acoustic transmitter and a sensor, the acoustic transmitter transmits an acoustic signal including information representative of a measurement by the sensor to an acoustic receiver positioned in the well. | 2014-05-08 |
20140126332 | VERIFICATION OF WELL TOOL OPERATION WITH DISTRIBUTED ACOUSTIC SENSING SYSTEM - A system for use with a subterranean well can include a well tool which generates an acoustic signal in response to operation of the well tool, the acoustic signal being detected by an acoustic receiver in the well. A method for verification of operation of a well tool can include operating the well tool, thereby generating an acoustic signal, and an acoustic receiver receiving the acoustic signal generated by the well tool, the acoustic signal including information indicative of the well tool operating. Another system for use with a subterranean well can include a well tool which generates an acoustic signal in response to operation of the well tool, an optical waveguide which receives the acoustic signal, and an optical interrogator connected to the optical waveguide. The optical interrogator detects the acoustic signal, which is indicative of the well tool operation. | 2014-05-08 |
20140126333 | Doppler Angle of Attack Sensor System for Watercraft - A watercraft angle of attack system includes sensors having a position locator; a heading sensor; a tilt sensor; an acoustic Doppler velocity sensor that measures velocity of the boat relative to a volume of water remote from the boat so as to reduce the boat-induced disturbance of the velocity in the volume; and a processor programmed to receive real time data from the sensors; and to compute and display angle of attack of the watercraft relative to the water. | 2014-05-08 |
20140126334 | UNDERWATER ACOUSTIC NAVIGATION SYSTEMS AND METHODS - An acoustic underwater navigation system is disclosed. For instance, an underwater receiver determines its position using signals broadcast from an array of acoustic transmitters located near the surface. The position of the array is measured using global positioning system (GPS) technology and the transmitters collectively produce an acoustic signal in which the position and attitude of the array and the GPS time of transmission are encoded. An underwater receiver which is synchronized with the GPS time uses the transmitted position and attitude of the array and the transmission time information to calculate its position. | 2014-05-08 |
20140126335 | Endoscopic Device for Generating Acoustic Waves With Variable Focus - An endoscopic device for generating acoustic waves with a sheath defining a center axis contains a first transducer for generating a first beam of acoustic energy radiating outwards of the endoscope sheath and a second transducer for generating a second beam of acoustic energy radiating outwards of the endoscope sheath. Both beams have different directions and intersect outside of the endoscope forming a focus spot. The second transducer is linearly movable parallel to the center axis with respect to the first transducer to displace the second beam and therefore to displace the intersection of the beams and therefore of the focus spot. | 2014-05-08 |
20140126336 | ASTRONOMICAL WATCH - Mechanism for displaying the day and phase of at least a first celestial body, comprising a gear train for a constant frequency gear drive on an output of a timepiece movement. This mechanism includes a means for the three-dimensional display of the day and phase of said first celestial body represented by a first mobile component, which is driven by the gear train, which includes a phase train and a day train, each in mesh on an output of this same movement. | 2014-05-08 |
20140126337 | Timepiece with Wireless Communication Function - A timepiece with a wireless function comprises a movement that displays time; a conductive case that holds the movement; a crystal that is disposed on a face side of the case and covers a face side of the movement; a conductive plate that is disposed between the movement and the crystal and reflects radio waves; an antenna that has a substantially annular, conductive antenna electrode and is disposed along an outside edge of the conductive plate between the conductive plate and the crystal as seen in a lateral view; and a dial ring that is made of non-conductive material and has a channel in which the antenna is held. The antenna electrode is configured to receive the radio waves reflected by the conductive plate. | 2014-05-08 |
20140126338 | TIMEPIECE - A timepiece includes: a frame; a mobile body of a finishing gear train; and a tourbillon mechanism including a holder supporting a balance and at least one escapement. The tourbillon mechanism includes: an outer ring rotatably mounted onto the frame about a first axis; at least one inner ring inside the outer ring and rotatable relative to the outer ring about a second axis, the holder being pivotably mounted in the inner ring and secured to a shaft around which the inner ring is freely and rotatably mounted about a third axis; a first toothed member mounted onto the frame; a first pinion secured to the shaft of the holder to engage with the first toothed member to rotate the holder; and a unit driving the inner ring, engaging with the movable body of the finishing gear train and arranged to move the inner ring and, consequently, the outer ring. | 2014-05-08 |
20140126339 | INFORMATION RECORDING MEDIUM, AND RECORDING METHOD AND REPRODUCING METHOD THEREOF - An information recording medium in which bottoms of a guide groove and a pit array formed on a disc substrate are allocated on a same flat plane and shaped in flat. Further, in a transition area from a pit array to a guide groove or from a guide groove to a pit array, the information recording medium is provided with an intermediate area composed of a pit array of which height changes from a height between a bottom and a side of a groove to another height between the bottom and a side of the pit array. | 2014-05-08 |
20140126340 | ARCHIVE SYSTEM FOR DOUBLE SIDED OPTICAL DISC - Disclosed is an archive system for a double sided optical disc, in which optical disc drives for recording or reading data on second surfaces of double sided optical discs are mounted in at least one of first and second drive bays respectively mounted at left and right sides of a disc picker robot, so that data recording or reading operations on first and second surfaces of double sided optical discs can be automatically performed. | 2014-05-08 |
20140126341 | LENS DRIVING DEVICE AND OPTICAL PICKUP - A lens driving device includes a lens holder that holds a lens, a driving portion that drives the lens holder through a magnetic force produced using a coil and a magnet, and a guide shaft that supports the lens holder movably. When moving the lens holder to a target position, an AC voltage is applied to the coil over a specific interval from a beginning of movement of the lens holder. Further, an amplitude of the AC voltage is reduced stepwise with the passage of time. | 2014-05-08 |
20140126342 | METHOD AND APPARATUS FOR OFFSET AND GAIN CORRECTION - Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation. | 2014-05-08 |
20140126343 | Rotary Head Data Storage and Retrieval System and Method for Data Erasure - A data storage and retrieval system includes a head carriage unit adapted for rotational motion and having multiple heads disposed at a working surface, the head carriage unit adapted for rotational motion. The system also includes a tape drive unit configured to move a tape media past the working surface of the head carriage unit, the tape media having a width approximately equal to a width of the working surface of the head carriage unit. As the head carriage unit rotates and the tape moves past the working surface, a first head is configured to write a data track on the tape and a second head is configured to thereafter read the data track, where data read by the second head is for use in verifying data erasure. | 2014-05-08 |
20140126344 | Rotary Head Data Storage and Retrieval System and Method for Data Verification - A data storage and retrieval system includes a head carriage unit adapted for rotational motion and having multiple heads disposed at a working surface. The system also includes a tape drive unit configured to move a tape media past the working surface of the head carriage unit, the tape media having a width approximately equal to a width of the working surface. As the head carriage unit rotates and the tape moves past the working surface, a first head is configured to write a data track to the tape and a second head is configured to thereafter read the data track, where data read by the second head is for use in verifying data integrity and performing error correction. | 2014-05-08 |
20140126345 | Simplified multi-modulation coding set (MCS) or multiple profile transmission (MPT) scheme for communications - A communication device includes a media access control (MAC) and a physical layer (PHY) processor and supports multi-profile communications with one or more other communication devices. The PHY processor selects a profile based on one or more characteristics of a communication pathway between the device and the one or more other communication devices. A profile may include operational parameters such as modulation coding set (MCS), forward error correction (FEC) and/or error correction code (ECC), a number of bits per symbol per sub-carrier and/or sub-carrier mapping (e.g., such as based on orthogonal frequency division multiplexing (OFDM) or orthogonal frequency division multiple access (OFDMA)), cyclic prefix, channel(s) used in transmission, bit-filling and shortening, unicast and/or multicast transmission, and/or other operational parameters. The PHY processor also may be configured to operate within at least two different operational modes including a first mode of packet aggregation and a second mode of bit-filling and shortening. | 2014-05-08 |
20140126346 | APPROACH FOR EXTENDED BATTERY LIFE NETWORK NODES - In an embodiment, triplets of network-enabled FCIs operate to monitor the three phases of a power distribution system. In being network-enabled, the FCIs also operate as nodes of an RF mesh network. In an embodiment, upon the detection of a power failure, the triplet of network FCIs is serially operated so as to extend their networking capabilities by approximately three times. | 2014-05-08 |
20140126347 | Address Processing Method, Gateway Device, and Access Point - Embodiments of the present invention relate to an address processing method, a gateway device, and an access point. An access point sends a request message to a gateway device. The access point obtains an address of an access controller from the gateway device. The address of the access controller is an address of an access controller selected by the gateway device. The access point establishes a CAPWAP tunnel with the access controller selected by the gateway device. | 2014-05-08 |
20140126348 | IP PACKET TRANSMISSION USING VEHICULAR TRANSPORT - In one embodiment, a first stationary router may detect a disconnected backhaul link to a destination. In response to detecting the disconnected backhaul link, the first stationary router may send a message to a first traveling mobile device, to cause the message to be sent toward the destination via a second stationary router. The second stationary router may receive the message from the first traveling mobile device, and in response to forwarding the message to the destination over its connected backhaul link, may send an acknowledgment toward the first stationary router via a second traveling mobile device. The first stationary router may then, in response to receiving the acknowledgment, cease sending copies of the message to other traveling mobile devices. | 2014-05-08 |
20140126349 | REROUTING T1 SIGNAL OVER A WIDE AREA NETWORK - The instant application describes a method and an apparatus for restoring T1 service in the event of a copper cable failure. The apparatus includes an interface configured to receive a T1 signal from a first customer device experiencing the copper cable failure; a converter configured to receive the T1 signal from the interface and place the T1 signal inside an IP packet routable over a wide area network; and a router configured to receive the IP packet from converter and send the IP packet over the wide area network to a central hub for conversion back into the T1 signal and delivery to a second customer device. The method requires equipment on one side of the T1 (e.g., at the location of the failure), and does not need knowledge of the customer's network addressing scheme. Solution is completely layer 2 and needs no input from the customer to re-establish service. | 2014-05-08 |
20140126350 | FATE SHARING SEGMENT PROTECTION - The present invention relates to a method and system of fate sharing segment protection. In one embodiment, this can be accomplished by monitoring the infrastructure segments, detecting a fault at the infrastructure segment, provisioning protection group between the source node and the destination node as outer work and outer protect (Outer Protection Group, OPG), and between at least two intermediate nodes as inner work and inner protect (Inner Protection Group IPG) and provisioning at least one supplementary outer protect on the same port of the OPG nodes where the OPG is provisioned, such that the outer supplementary protect diverge in such a way that mirrors the behavior (or shares the fate) of the inner work and inner protect. | 2014-05-08 |
20140126351 | COMMUNICATION SYSTEM AND NETWORK RELAY DEVICE - There is provided port switches SWP | 2014-05-08 |
20140126352 | COMMUNICATION SYSTEM AND NETWORK RELAY DEVICE - In order to provide a communication system and a communication system processing method with which fault resistance is improved and also signal loopback can be prevented, a communication system is provided with, for example, port switches SWP | 2014-05-08 |
20140126353 | BUILDING BASEBAND UNIT, BASEBAND PROCESSING PANEL, AND FAILURE PROCESSING METHOD FOR BASEBAND PROCESSING PANEL - Disclosed are a building baseband unit, a baseband processing panel, and a failure processing method for the baseband processing panel. A direct path is introduced respectively for a baseband processing module and a power supply module in a baseband processing panel; when the baseband processing module has failed, the baseband processing module is directly bypassed, and a part of the baseband processing resources of a baseband processing panel in normal operation is allocated to an RRU corresponding to the failed baseband processing panel via a back panel and the direct path; and when both the baseband processing module and the power supply module have failed, both of them are directly bypassed, and a part of the baseband processing resources of a baseband processing panel in normal operation is allocated to the RRU corresponding to the failed baseband processing panel via the back panel and the direct path, and at the same time the power required for working is provided to an optical module via the back panel and another direct path. Applying the solution of the present invention can reduce implementation costs. | 2014-05-08 |
20140126354 | SEAMLESS MULTIPATH RETRANSMISSION USING SOURCE-ROUTED TUNNELS - In one embodiment, a device receives a destination unreachable message originated by a particular node along a first source route, the message carrying an encapsulated packet as received by the particular node. In response, the device may determine a failed link along the first source route based on a tunnel header and the particular node. Once determining an alternate source route without the failed link, the device may re-encapsulate and re-transmit the original packet on an alternate source route with a new tunnel header indicating the alternate source route (e.g., and a new hop limit count for the tunnel header and an adjusted hop limit count in the original packet). | 2014-05-08 |
20140126355 | IDENTIFYING, TRANSLATING AND FILTERING SHARED RISK GROUPS IN COMMUNICATIONS NETWORKS - A method, apparatus, and computer-readable storage medium are disclosed for processing shared risk group (SRG) information in communications networks. The method includes obtaining at least one SRG identifier by processing SRG information included in network information received at a first network layer from a second network layer, and processing the at least one SRG identifier using one or more operations configured to ensure that the SRG identifier is unique among a plurality of SRG identifiers. The apparatus includes a network interface adapted to receive network information comprising SRG information, a processor coupled to the network interface, and a memory coupled to the processor and adapted to obtain at least one SRG identifier by processing the SRG information and to process the at least one SRG identifier. The computer-readable storage medium is configured to store program instructions that when executed are configured to cause a processor to perform the method. | 2014-05-08 |
20140126356 | Intelligent Network - Systems and methods for providing services are disclosed. One aspect comprises determining a plurality of services to be provided over a first communication path to a destination, determining a select service of the plurality of services to be provided over a failover path to the destination, detecting a failure of the first communication path, and routing the select service over the failover path in response to the failure of the first communication path. | 2014-05-08 |
20140126357 | ECN-ENABLED MULTICAST PROTOCOL FOR WIRELESS COMMUNICATION SYSTEMS UNDER BLOCKAGE - A system and method are provided for implementing performance improvements in a multicast protocol for networks that support incipient congestion indications via packet marking in instances of packet loss in the network during time-correlated blockages by providing indications in the physical (PHY) layer. A receiver rate calculation is adjusted so that a loss due to blockage is ignored completely and only packets marked using an Explicit Congestion Notification (ECN) packet marking protocol are treated as losses. Receiver rates are modified based on ECN principles to ignore losses. A NORM receiver rate equation may remain substantially unchanged while a sender is enabled to keep sending at a higher data rate, even in instances of blockage in support of higher system throughputs without defining a completely new receiver rate equation. Time-correlated blockages are not treated as losses. | 2014-05-08 |
20140126358 | Mobile Backhaul Dynamic QoS Bandwidth Harmonization - An embodiment includes determining estimate(s) of bandwidth for class(es) of quality of service to be implemented in base station(s) for service(s) provided to user equipment by the base station(s), determining expiration time(s) for corresponding ones of the estimate(s) of bandwidth, and communicating indications of the same toward mobile backhaul node(s). At a backhaul node, the indications are received and, based on the received indications, downstream bandwidth is modified for user equipment of different quality of service classes, wherein the downstream bandwidth passes through the mobile backhaul node toward the base station(s). Apparatus, software, and computer program produces are also disclosed. | 2014-05-08 |
20140126359 | Selecting Transmission Parameters for Downlink Transmissions Based on Retransmission Rates - A supporting node maintains a retransmission database that stores information about the historical retransmission rates of user terminals served by the network. The supporting network node provides the information about the retransmission rates of the user terminals to the base stations that are serving the user terminals. When a user terminal is being scheduled to receive a downlink transmission, the scheduler at the base station may use historical retransmission rates of the user terminal to select transmission parameters, e.g. modulation and coding scheme (MCS) and/or transport block (TBS), for the downlink transmission. | 2014-05-08 |
20140126360 | System and Method for WiFi Offload - Embodiments are provided for enabling WiFi offload by integrating the WiFi and cellular networks operations at a radio access network level. The embodiments include a WiFi network component configured to determine whether to send over a cellular air interface a packet designated for WiFi according to a predefined rule. If the rule is met, the WiFi network component sends the packet to a cellular network component over the cellular air interface. The cellular network component is configured to process the received packet for cellular transmission, and transmit the packet using the cellular air interface to a receiver device. The predefined rule comprises at least one of sending the packet using the cellular air interface if the packet belongs to a predefined packet type, if the packet has a size below a predefined threshold size, and if the nature of the destination address for the packet is a broadcast address. | 2014-05-08 |
20140126361 | CONGESTION CONTROL METHODS FOR DUAL PRIORITY DEVICES AND APPARATUSES USING THE SAME - A mobile communication device configured for dual priority is provided with a wireless module and a controller module. The wireless module performs wireless transmission and reception to and from a service network. The controller module starts an SM congestion control back-off timer for an APN in response to an SM procedure being rejected by the service network, which was initiated for the APN with a first low priority indicator indicating that the mobile communication device was configured for NAS signaling low priority. The controller module does not stop the SM congestion control back-off timer for the APN in response to a second SM procedure being initiated by the service network for the APN and being related to an existed PDP context previously requested by the mobile communication device with a second low priority indicator indicating that the mobile communication device was not configured for NAS signaling low priority. | 2014-05-08 |