| 19th week of 2014 patent applcation highlights part 21 |
| Patent application number | Title | Published |
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| 20140125362 | SEMICONDUCTOR DEVICE AND DETECTION METHOD THEREOF - A semiconductor device and a detection method thereof are provided. The semiconductor device includes a resistor terminal, a dummy pull up driver, a comparator and a detection state machine. The resistor terminal is connected to an external resistor. The dummy pull up driver provides driving operations of 2 | 2014-05-08 |
| 20140125363 | SYSTEMS AND METHODS FOR TESTING ELECTRONIC DEVICES THAT INCLUDE LOW POWER OUTPUT DRIVERS - Systems and methods for testing a device under test (DUT) that includes a low power output driver. The methods include providing an input signal to the DUT. The low power output driver is configured to generate a data signal responsive to receipt of the input signal by the DUT and provide the data signal to a signal analyzer via a data signal transmission line. The methods further include determining an expected data signal to be received from the low power output driver and charging at least a portion of the data signal transmission line with a co-drive output signal that is based, at least in part, on the expected data signal. The methods further include receiving a composite data signal with the signal analyzer. The systems include probe heads with a plurality of data signal transmission lines and a plurality of co-drive conductors. | 2014-05-08 |
| 20140125364 | SYSTEM AND METHOD FOR COMPENSATING MEASURED IDDQ VALUES - An IDDQ test system and method that, in one embodiment,deg includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQ | 2014-05-08 |
| 20140125365 | Testing Electronic Components on Electronic Assemblies with Large Thermal Mass - An approach is provided in which a system under test is subjected to thermal cycling that include transferring the system under test between two different environments that generate two different ambient temperatures. In turn, a test system tests the electronic assembly in response to the electronic assembly being subjected to the thermal cycles. | 2014-05-08 |
| 20140125366 | METHOD FOR ESTIMATING THE END OF LIFETIME FOR A POWER SEMICONDUCTOR DEVICE - The invention regards an method for estimating the end of lifetime for a power semiconductor device, such as an IGBT power module, comprising the steps of; establishing the temperature of the power semiconductor device, determining the voltage drop over the power semiconductor device for at least one predetermined current where the current is applied when the power semiconductor device is not in operation, wherein the end of lifetime is established dependent on the change in a plurality of determined voltage drops. | 2014-05-08 |
| 20140125367 | SEAL METHOD FOR DIRECT LIQUID COOLING OF PROBES USED AT FIRST LEVEL INTERCONNECT - Embodiments of an apparatus and method for providing cooling of probes for testing of integrated circuits are generally described herein. In some embodiments, an apparatus comprises a probe head assembly configured to hold one or more probes that are adapted to provide electrical contact with an integrated circuit device under test (DUT), a DUT chuck adapted to hold the DUT for contact with the probes, a seal arranged between the probe head assembly and the DUT chuck to form a chamber when the seal is in contact with the probe head assembly and the DUT chuck, and a first port and a second port arranged to provide fluid flow into and fluid flow out of the chamber. | 2014-05-08 |
| 20140125368 | Apparatus And Method For Obtaining Uniform Light Source - An apparatus and method for increasing uniformity in light from a light source at a plurality of targets of the light include a plurality of movable aperture elements, locatable between the light source and the targets, each aperture element defining an aperture through which the light passes from the light source to an associated one of the plurality of targets associated with the aperture element along a longitudinal axis of the aperture element. A holder movably holds the plurality of aperture elements, each of the plurality of aperture elements being movable within the holder along the longitudinal axis of the aperture element to change a feature of light incident on the target associated with the aperture element. | 2014-05-08 |
| 20140125369 | Method For Testing Through-Silicon Vias At Wafer Sort Using Electron Beam Deflection - Through-silicon vias (TSVs) are tested using a modified integrated circuit test probe array, an electron beam generation device, a beam direction control device and an electron beam detection device. The TSV extends through a silicon substrate with end portions exposed or accessible by contacts disposed on opposing upper and lower surfaces of the substrate. The test probe array includes a test probe that accesses the lower TSV end portion and applies an AC test signal. An electron beam is directed by the beam direction control device onto the upper substrate surface such that a beam portion reflected from the upper TSV end portion is captured by the electron beam detection device. Reflected beam data is then analyzed to verify the TSV is properly formed. Various scan patterns, different test signal frequencies and an optional resistive coating are used to enhance the TSV testing process. | 2014-05-08 |
| 20140125370 | Image Sensor Testing Probe Card - A probe card for use in testing a wafer and a method of making the probe card include a printed circuit board (PCB) formed with a conductor pattern and a probe head in proximity to the PCB, the probe head defining at least one hole through the probe head, and the probe head being made of an electrically insulating material. At least one conductive pogo pin is disposed respectively in the at least one hole, the pogo pin having a first end electrically connected to the conductor pattern on the PCB. At least one conductive probe pin includes a cantilever portion and a tip portion. The cantilever portion is in contact with and electrically connected to a second end of the pogo pin, and the tip portion is electrically connectable to the wafer to electrically connect the wafer to the conductor pattern on the PCB. The cantilever portion of the probe pin is fixedly attached to the probe head. | 2014-05-08 |
| 20140125371 | STAND ALONE MULTI-CELL PROBE CARD FOR AT-SPEED FUNCTIONAL TESTING - A probe card includes at least two connection arrangements on a printed circuit board and a daughter board connected to the printed circuit board through one of the connection arrangements. The daughter board includes a plurality of cell modules, with each of the cell modules having a socket for receiving a device under test and each of the connection arrangements of the printed circuit board being connectable to each of predetermined daughter boards respectively. | 2014-05-08 |
| 20140125372 | PROBE CARD AND METHOD OF MANUFACTURING THE SAME - A probe card includes a wiring substrate including an opening portion and a connection pad arranged on an upper face of the wiring substrate located on the periphery of the opening portion, a resin portion formed in the opening portion of the wiring substrate, and the resin portion formed of a material having elasticity, a contact terminal arranged to protrude from the lower face of the resin portion, and wire buried in the resin portion and connecting the contact terminal and the connection pad, wherein the contact terminal is formed of an end part of the wire, and is formed integrally with the wire. | 2014-05-08 |
| 20140125373 | SEMICONDUCTOR ELEMENT INSPECTION DEVICE AND INSPECTION METHOD - A semiconductor inspection device ( | 2014-05-08 |
| 20140125374 | METHOD FOR EVALUATING WAFER DEFECTS - Provided is a method for evaluating defects in a wafer. The method for evaluating the wafer defects includes preparing a wafer sample, forming an oxidation layer on the wafer sample, measuring a diffusion distance of a minority carrier using a surface photovoltage (SPV), and determining results of a contamination degree. | 2014-05-08 |
| 20140125375 | BOARD INSPECTION APPARATUS SYSTEM AND BOARD INSPECTION METHOD - A board inspection apparatus system includes a first apparatus, a second apparatus, a third apparatus and an information transfer section. The first apparatus acquires first three-dimensional information of a solder paste on a board, and inspects whether the solder paste is formed good by a first tolerance based on the first three-dimensional information. The second apparatus mounts an electronic component on the board to join the electronic component and the solder paste. The third apparatus acquires second three-dimensional information of a solder joint, and inspects whether the electronic component is mounted good by a second tolerance based on the second three-dimensional information. The information transfer section transfers the first three-dimensional information to the third apparatus, or transfers the second three-dimensional information to the first apparatus. Thus, a more effective inspection condition may be established, and a rate of defect for each apparatus may be greatly reduced. | 2014-05-08 |
| 20140125376 | GENERATED POWER OUTPUT MEASURING APPARATUS - A generated power output measuring apparatus is connected to a connecting wire between a power generator using natural energy and a power conditioner configured to supply electric power of the power generator to an external load. The generated power output measuring apparatus includes a load unit configured to draw a current from the power generator, a measuring unit configured to measure a voltage and current of the power generator via the load unit, and a control unit configured to increase the current flowing through the load unit and causing the measuring unit to make a measurement when the voltage measured by the measuring unit is in a range of operating voltage of the power conditioner. | 2014-05-08 |
| 20140125377 | DUAL FLIP-FLOP CIRCUIT - A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions. | 2014-05-08 |
| 20140125378 | LOGIC DEVICE AND OPERATING METHOD THEREOF - A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks connected to first connection lines and the second logic blocks connected to second connection lines. The connection block electrically connected to the first and second logic blocks via the first connection lines and the second connection lines, respectively. The connection block including connection cells configured to select one of multiple connection configurations between the first connection lines and the second connection lines based on a desired function. | 2014-05-08 |
| 20140125379 | SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOGIC IN A HYBRID INTEGRATED DEVICE - Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block. | 2014-05-08 |
| 20140125380 | HIGH SPEED BUFFER WITH HIGH NOISE IMMUNITY - This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes a second buffer configured to receive the incoming signal and to generate a second output signal. The second buffer exhibits hysteresis with lower and upper thresholds. The circuit also includes an output block configured to receive the first and second output signals and to generate a third output signal. The output block is configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal. | 2014-05-08 |
| 20140125381 | VOLTAGE-AWARE SIGNAL PATH SYNCHRONIZATION - An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions. | 2014-05-08 |
| 20140125382 | EDGE SELECTION TECHNIQUES FOR CORRECTING CLOCK DUTY CYCLE - Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit. | 2014-05-08 |
| 20140125383 | SIGNAL GENERATING CIRCUITS FOR GENERATING FAN DRIVING SIGNAL - A signal generating circuit for generating a fan driving signal includes a phase adjusting circuit, a direct digital frequency synthesizer, a first operating circuit, a driving signal generator and a second operating circuit. The phase adjusting circuit receives a hall signal and adjusts a phase of the hall signal to generate a synchronization signal. The direct digital frequency synthesizer generates a modulating signal according to the synchronization signal. The first operating circuit receives a load current and generates a modulated signal according to the load current. The driving signal generator generates an original driving signal according to the synchronization signal. The second operating circuit generates a control signal according to the modulating signal and the modulated signal. The original driving signal is selectively outputted as the fan driving signal in response to the control signal. | 2014-05-08 |
| 20140125384 | Systems, Methods, and Apparatus to Drive Reactive Loads - Systems, methods, and apparatus to drive reactive loads are disclosed. An example apparatus to drive a reactive load includes a reactive component in circuit with the reactive load, a first switching element in circuit with the reactive load to selectively hold the reactive load in a first energy state and to selectively allow the reactive load to change from the first energy state to a second energy state, a second switching element in circuit with the reactive load to selectively hold the reactive load in the second energy state and to selectively allow the reactive load to change from the second energy state to the first energy state, and a controller to detect a current in the reactive load, and to control the first and second switching elements to hold the reactive load in the first or the second energy state when the current traverses a threshold. | 2014-05-08 |
| 20140125385 | LEVEL SHIFTER CAPABLE OF PULSE FILTERING AND BRIDGE DRIVER USING THE SAME - A level shifter capable of pulse filtering and a bridge driver using the same, the level shifter capable of pulse filtering being used for up shifting a first clock signal and a second clock signal to provide a set signal and a reset signal, and for preventing noise on the first clock signal or on the second clock signal from altering the states of the set signal and the reset signal. | 2014-05-08 |
| 20140125386 | GATE DRIVING CIRCUIT - A gate driving circuit is provided which is capable of alleviating the effect of a switching noise generated when an IGBT is turned on/off or a common mode noise on a gate driving signal. The gate driving circuit, a primary side and a secondary side thereof being insulated from each other by a pulse transformer; the primary side of the pulse transformer being grounded to a first ground potential point; the secondary side of the pulse transformer being grounded to a second ground potential point insulated from the first ground potential point; and a gate driving signal generated in a secondary winding of the pulse transformer being outputted through a receiver having impedance matching resistors on the input side, includes an electrostatic shield plate between a primary winding of the pulse transformer and the secondary winding, the electrostatic shield plate being grounded to the second ground potential point. | 2014-05-08 |
| 20140125387 | SEMICONDUCTOR DEVICE INCLUDING A DELAY LOCKED LOOP CIRCUIT - A method for initializing a delay locked loop having a delay circuit includes a plurality of serially connected delay elements and a counter circuit for selecting an output of one of the delay elements as an output clock signal. The method includes resetting an initial delay control circuit, generating, with the initial delay control circuit, a pulse based on a period of an input clock signal, determining, with the initial delay control circuit, a number of delay elements required to produce a delay time at least substantially equivalent to a pulse width for a preset signal, initializing the counter circuit based on the preset signal and adjusting the counter circuit in response to phases of the input and output clock signals. | 2014-05-08 |
| 20140125388 | OPTIMIZING PRE-DRIVER CONTROL FOR DIGITAL INTEGRATED CIRCUITS - Disclosed is a wave shaping apparatus and a method for shaping an input pulse train signal alternating between a low level and a high level to provide a signal delaying a turn on of one output transistor with respect to a turn off of the other output transistor thus decreasing time, when both the transistors would be simultaneously conducting current. | 2014-05-08 |
| 20140125389 | EDGE RATE CONTROL GATE DRIVE CIRCUIT AND SYSTEM FOR LOW SIDE DEVICES WITH CAPACITOR - An apparatus, comprising: a PMOS current mirror have a first PFET and a second PFET coupled at their respective gates; a first current source coupled to drain of the first PFET; a second current source configured to have a current that is greater than the first current source, coupled to the drain of the second PFET; a capacitor coupled to the gates of the PFET current mirror; a third PFET gate-coupled to the current mirror; a driver NFET having a gate coupled to the drain of the third PFET, wherein a drain of the driver NFET is coupled to the capacitor. | 2014-05-08 |
| 20140125390 | APPARATUSES AND METHODS FOR DUTY CYCLE ADJUSTMENT - Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. The duty cycle adjustment circuit may further be configured, after adjusting the duty cycle of the signal a first amount, to adjust the duty cycle of the signal a second amount different from the first amount using a fine adjustment to provide a duty cycle adjusted signal. | 2014-05-08 |
| 20140125391 | DUTY CYCLE CORRECTION APPARATUS - Disclosed is a duty cycle correction apparatus. The apparatus of the present invention adjusts signal widths of an input signal, averages the widths of the signal, and inverts the signal, then averages the widths of the inverted signal, compares the two averaged signals, and outputs the difference between the two averaged signals. | 2014-05-08 |
| 20140125392 | LOW POWER LATCHING CIRCUITS - A latching circuit has an input for receiving the data value, an output for outputting a value indicative of the data value, a clock signal input for receiving a clock signal; and a pass gate. A feedback loop has two switching circuits arranged in parallel between two inverting devices, a first of the two switching circuits is configured to be off and not conduct in response to a control signal having a predetermined control value and a second of the two switching circuits is configured to be on and conduct in response to the control signal having the predetermined control value. A control signal controlling the two switching circuits is linked such that the switching devices switch their conduction status and the access control device act together to update the data value within the feedback loop. | 2014-05-08 |
| 20140125393 | LATCH CIRCUIT WITH A BRIDGING DEVICE - One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors. | 2014-05-08 |
| 20140125394 | PHASE INTERPOLATOR HAVING ADAPTIVELY BIASED PHASE MIXER - A phase interpolator includes an adaptively biased phase mixer, phase control circuitry and an adaptive bias generator. The adaptively biased phase mixer has mixing transistor circuitry configured to provide an output phase signal in response to a plurality of phase control signals, a bias current, and a number of phase input signals offset in phase from one another. The adaptively biased phase mixer further has adjustable bias transistor circuitry configured to adjust the bias current provided to the mixing transistor circuitry in response to an adaptive bias signal. | 2014-05-08 |
| 20140125395 | One-Wire Communication Circuit and One-Wire Communication Method - A communication circuit facilitating communication between a first equipment and a second equipment including a conversion circuit, an input port, an output port, and a communication port is disclosed. The conversion circuit converts an input signal to a first intermediate signal, and converts a second intermediate signal to an output signal. The input port inputs the input signal to the first conversion circuit. The output port outputs the output signal to the control unit. The communication port inputs the second intermediate signal to the conversion circuit, and outputs the first intermediate signal to the second equipment. A voltage of the first intermediate signal is determined based on a voltage of a power source if the first intermediate signal is logic high, and a voltage of the second intermediate signal is determined based on the voltage of the power source if the second intermediate signal is logic high. | 2014-05-08 |
| 20140125396 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PERFORMING LEVEL SHIFTING - A system, method, and computer program product are provided for performing level shifting. In use, level shifting is performed utilizing a native transistor, where the level shifting is performed utilizing a feedback based topology. | 2014-05-08 |
| 20140125397 | LEVEL CONVERTER FOR CONTROLLING SWITCH - Provided is a power amplifier using a differential structure. The power amplifier includes: first and second transistors whose first terminals are each connected to a first power supply source supplying a first voltage and into which signals having the same size and opposite polarities are input; third and fourth transistors whose first terminals are respectively connected to the first terminals of the first and second transistors; and a fifth transistor whose first terminal is connected to second terminals of the third and fourth transistors and controlling oscillation of the third or fourth transistor. | 2014-05-08 |
| 20140125398 | Driver Integrated Circuit - Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. | 2014-05-08 |
| 20140125399 | CHARGE MEASUREMENT - An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output. The apparatus also comprises a controllable current source coupled to the first input of the comparator and configured for supplying or drawing current. The apparatus also comprises a digital logic circuit that is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for measuring a charge associated with an external source that is coupled to the first input of the comparator. | 2014-05-08 |
| 20140125400 | Detecting a Periodic Timing Reference in a Received Signal - An apparatus for detecting a periodic timing reference in a received signal comprises a correlator and an integrator. The correlator is configured to correlate the received signal with a template to produce a correlated signal indicating the presence of the periodic timing reference in the received signal. The integrator is configured to produce an accumulated signal by overlaying one or more delayed versions of the accumulated signal onto the correlated signal, and is further configured to delay the accumulated signals by integer multiples L of a period of the periodic timing reference, the integer multiples L being at least two. | 2014-05-08 |
| 20140125401 | SYSTEM FOR CONTROLLIING GATINGS OF A MULTI-CORE PROCESSOR - A system for controlling gatings of a multi-core processor, the system includes a pulse width modulation generator for generating a control square wave; and a phase shifter for shifting a phase of the control square wave to generate control square waves with different phases, and respectively inputting the control square waves with the different phases to a gating of each of multiple processing engines in the multi-core processor. A multi-core processor is provided that includes multiple processing engines. Each processing engine includes a gating, and a system for controlling the gating. Accordingly, in the multi-core processor, the load to be processed in a certain period of a working cycle can be averaged to be processed in a longer period of the working cycle. Consequently, current noise and voltage noise and temperature growth due to the load change can be reduced. | 2014-05-08 |
| 20140125402 | SWITCHING CIRCUIT, RADIO SWITCHING CIRCUIT, AND SWITCHING METHOD THEREOF - The present disclosure discloses a radio frequency switching circuit including an antenna terminal, a transmitter terminal, a receiver terminal, a first switching module, a second switching module, a first switching component, and a second switching component. The first switching module is connected between the antenna terminal and the transmitter terminal. The second switching module is connected between the antenna terminal and the receiver terminal. The first and second switching modules include several transistors respectively, and each of the transistors includes a gate terminal, a drain terminal, a source terminal, and a bulk. The first switching component has a first anode terminal connecting with the gate terminal, and a first cathode terminal connecting with the drain terminal. The second switching component has a second anode terminal connecting with the gate terminal, and a second cathode terminal connecting with the source terminal. | 2014-05-08 |
| 20140125403 | Resistive Interpolation for a Touch Sensor with Opaque Conductive Material - In one embodiment, an apparatus comprises a substrate. The apparatus further comprises a plurality of drive electrodes disposed on the substrate. Each of the plurality of drive electrodes is formed of an opaque conductive material. The apparatus further comprises a plurality of resistors. For each adjacent pair of drive electrodes of the plurality of drive electrodes, a resistor of the plurality of resistors is coupled between the pair of drive electrodes. | 2014-05-08 |
| 20140125404 | HIGH-VOLTAGE TOLERANT BIASING ARRANGEMENT USING LOW-VOLTAGE DEVICES - A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly. | 2014-05-08 |
| 20140125405 | SEMICONDUCTOR DEVICE - A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V | 2014-05-08 |
| 20140125406 | SWITCHING SYSTEM AND METHOD FOR CONTROL THEREOF - The invention provides a switching system. The switching system comprises an H bridge, a current router, and a control circuit. The H bridge comprises a first switch and a second switch coupled to a first output node and a third switch and a fourth switch coupled to a second output node, wherein a load is coupled between the first output node and the second output node. The current router comprises a first shunt switch and a second shunt switch coupled between the first output node and the second output node. The control circuit generates a first control signal to control the first switch and the fourth switch, generates a second control signal to control the second switch and the third switch, generates a third control signal to control the first shunt switch, and generates a fourth control signal to control the second shunt switch. | 2014-05-08 |
| 20140125407 | BANDWIDTH LIMITING FOR AMPLIFIERS - An apparatus for limiting the bandwidth of an amplifier provides for the design of an input impedance, a feedback impedance, and a load impedance such that the load impedance is proportional to the sum of the input impedance and feedback impedance. A sampling circuit has a load impedance including a resistor and capacitor in series to reduce the effective amplifier transconductance, which decreases bandwidth without increasing noise density or making this circuit more difficult to drive than a conventional circuit. | 2014-05-08 |
| 20140125408 | OUTPUT IMPEDANCE COMPENSATION OF A PSEUDO-ENVELOPE FOLLOWER POWER MANAGEMENT SYSTEM - A switch mode power supply converter, a parallel amplifier, and a parallel amplifier output impedance compensation circuit are disclosed. The switch mode power supply converter provides a switching voltage and generates an estimated switching voltage output, which is indicative of the switching voltage. The parallel amplifier generates a power amplifier supply voltage at a power amplifier supply output based on a combination of a V | 2014-05-08 |
| 20140125409 | AMPLIFIER CALIBRATION - A system and method of calibrating an amplifier are presented. The amplifier has a first amplification path and a second amplification path. A first state of the amplifier is identified defining a first phase shift of the first path and a second phase shift of the second path resulting in a maximum efficiency of the amplifier when an attenuation of the first path and an attenuation of the second path are set to first attenuation values. The attenuation of the first path and the attenuation of the second path is set to achieve a maximum efficiency of the amplifier when the phase shift of the first path and the phase shift of the second path are set according to the first state. | 2014-05-08 |
| 20140125410 | DIGITAL POLAR AND ZVS CONTOUR BASED HYBRID POWER AMPLIFIER - A power amplifier (PA) which improves dynamic range of previous ZVS contour-based power amplifier architectures is presented. The inventive circuit combines ZVS contour-based power amplification with a current mode digital-to-analog converter (DAC) based digital polar power amplifier. The inventive elements interoperate to provide high efficiency even at large peak power back-off levels and increased dynamic range. The invention is particularly well-suited for use in modulation schemes (e.g., WLAN/LTE/WIMAX) having large peak-to-average output power ratios. Utilizing the inventive PA in generating modulation in these systems can increase RF transmitter efficiency of by approximately two-fold. | 2014-05-08 |
| 20140125411 | METHOD AND APPARATUS FOR FILTER-LESS ANALOG INPUT CLASS D AUDIO AMPLIFIER CLIPPING - An integrated circuit (IC) chip has a class D PWM (pulse width modulation) amplifier configured for generating first and second PWM signals. The class-D PWM modulator includes a differential output driver configured for driving a first and a second output signals in response to the first and the second PWM signals. A clipping detection circuit is configured to turn on a clipping indication signal when one or both of the first PWM signal and the second PWM signal maintain the same state between two consecutive edges of the oscillator clock signal. The clipping detection circuit is also configured to turn off the clipping indication signal when both the first PWM signal and the second PWM signal change states between two consecutive edges of the oscillator clock signal. | 2014-05-08 |
| 20140125412 | Asymmetric Multilevel Outphasing Architecture For RF Amplifiers - A radio frequency (RF) circuit includes a power supply configured to generate a plurality of voltages, a plurality of power amplifiers, each having an RF output port and a power supply input port, a switch network having a plurality of input ports coupled to the power supply and a plurality of switch network output ports coupled to the power supply input ports of the plurality of power amplifiers, wherein the switch network is configured to output selected ones of the plurality of voltages from the plurality of switch network output ports, at least two of the switch network output port voltages capable of being different ones of the plurality of voltages, and an RF power combiner circuit having a plurality of input ports coupled to RF output ports of the plurality of power amplifiers and an output port at which is provided an output signal of the RF circuit. | 2014-05-08 |
| 20140125413 | INSTRUMENTATION AMPLIFIER WITH RAIL-TO-RAIL INPUT RANGE - A system and method for adjusting a common mode output voltage in an instrumentation amplifier is provided. In one aspect, the common mode output voltage is increased or decreased with respect to the common mode input voltage to enable high amplification of the signal input to the instrumentation amplifier. Moreover, the common mode output voltage can be driven to (or approximately to) a target voltage value such as, but not limited to, half the supply, even if the common mode input voltage is close to supply or ground rail voltage. Thus, a high amplification of the differential input voltage can be obtained and utilized for various applications requiring rail to rail input. | 2014-05-08 |
| 20140125414 | OPERATIONAL AMPLIFIER CIRCUIT - An operational amplifier circuit includes an output stage circuit. The output stage circuit includes a first and a second output transistors, a capacitor unit, and a switch unit. A drain of the first output transistor is coupled to a drain of the second output transistor via an output terminal of the output stage circuit. The switch unit is coupled between gates of the first and the second output transistors and coupled to a first terminal of the capacitor unit. A second terminal of the capacitor unit is coupled to the output terminal of the output stage circuit. The switch unit determines to conduct a signal transmission path between the gate of the first output transistor and the first terminal of the capacitor unit or conduct a signal transmission path between the gate of the second output transistor and the first terminal of the capacitor unit according to a control signal. | 2014-05-08 |
| 20140125415 | Power Amplifier Device and Power Amplifier Circuit Thereof - The present invention relates to a power amplifier apparatus and power amplifier circuit, and the power amplifier circuit uses the Doherty circuit structure, and uses a high voltage heterojunction bipolor transistor (HVHBT) power amplifier to achieve a Carrier amplifier of the Doherty circuit structure, and uses lateral double-diffused metal oxide semiconductor (LDMOS) to achieve a Peak amplifier. The power amplifier apparatus and power amplifier circuit in the present invention improves the efficiency of the power amplifier. | 2014-05-08 |
| 20140125416 | Amplifier Linearization Using Non-Standard Feedback - An amplification unit is provided. The amplification unit, comprises a first amplifier, a second amplifier, a first sensor, a first predistortion component, and a signal combiner. The first amplifier amplifies a first signal to produce a second signal. The first sensor produces a third signal based on the second signal. The second amplifier turns on and to amplifies a fourth signal to produce a fifth signal when the amplitude of the fourth signal exceeds a threshold amplitude and turns off when the amplitude of the fourth signal is less than the threshold amplitude. The first predistortion component produces the first signal based on a first input signal, based on the third signal, and based on an on-off state of the second amplifier. The signal combiner produces an output of the amplification unit based on the second signal and the fifth signal. | 2014-05-08 |
| 20140125417 | SYSTEMS AND METHODS FOR BOOSTING A RECEIVED AC SIGNAL USING A POWER AMPLIFIER INCLUDING PHASE CONDITIONERS - A power amplifier configured to boost an AC signal. The power amplifier includes a first transistor, a second transistor, a first inductor connected between the first transistor and a voltage source, and a second inductor connected between the second transistor and ground. A first phase conditioner arranged at an input of the first transistor is configured to condition a phase of the AC signal such that the AC signal as received by the first transistor is out of phase with respect to the AC signal as received by the first inductor. A second phase conditioner arranged at an input of the second transistor is configured to condition a phase of the AC signal such that the AC signal as received by the second transistor is out of phase with respect to the AC signal as received by the second inductor. | 2014-05-08 |
| 20140125418 | Method and Apparatus to Improve Performance of GPSDO's and other Oscillators - In one embodiment, the present invention includes a method of correcting the frequency of a crystal oscillator. The method includes establishing an operating baseline for the crystal oscillator using a frequency reference, storing information in memory, and adjusting the frequency according to the information. The information corresponds to the operating baseline. Adjusting the frequency occurs in response to a power-on event and the absence of the frequency reference. | 2014-05-08 |
| 20140125419 | METHOD AND SYSTEM FOR TESTING OSCILLATOR CIRCUIT - An oscillator circuit generates a voltage signal. The magnitude of the voltage signal is measured and compared with predetermined upper and lower voltage signals by an internal test circuit. If the magnitude of the voltage signal is between the predetermined upper and lower voltage signals, then a pass test status signal is generated. If the magnitude of the voltage signal is not between the predetermined upper and lower voltage signals then a fail test status signal is generated. | 2014-05-08 |
| 20140125420 | PIEZOELECTRIC DEVICE AND ELECTRONIC APPARATUS - A piezoelectric device includes an insulating substrate, a piezoelectric vibration device that is mounted on a device mounting pad, a metal lid member that seals the piezoelectric vibration device in an airtight manner, an external pad that is arranged outside the insulating substrate, an oscillation circuit, a temperature compensation circuit, and a temperature sensor. The lid member and the temperature sensor or the lid member and the IC component are connected to each other so as to be heat-transferable, and a heat transfer member having thermal conductivity higher than that of the material of the insulating substrate is additionally included. | 2014-05-08 |
| 20140125421 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device including an oscillator arid a manufacturing method thereof, in which cost is low and design flexibility is high. The semiconductor device includes a wiring structure region and an oscillator region. The semiconductor device also includes, in the oscillator region, a metal resistive element as the same layer as a conducting film over uppermost metal wiring in the wiring structure region. | 2014-05-08 |
| 20140125422 | SELF-OSCILLATION CIRCUIT - A self-oscillation circuit includes an oscillating unit, an amplifying unit, and a resonator. The oscillating unit is configured to self-oscillate. The amplifying unit is configured to amplify a frequency signal oscillated at the oscillating unit and to feed back the amplified frequency signal to the oscillating unit. The resonator is disposed in an oscillation loop that includes the oscillating unit and the amplifying unit. The resonator has a resonant frequency near an oscillation frequency of the oscillating unit and has a higher Q-value than a Q-value of the oscillating unit. | 2014-05-08 |
| 20140125423 | METHOD AND DEVICE FOR DIGITAL MODULATION WITH LOW TRANSITION DENSITY - The present invention relates to a digital modulation method and a corresponding modulator. The modulator comprises a transcoder ( | 2014-05-08 |
| 20140125424 | ADAPTIVE ON DIE DECOUPLING DEVICES AND METHODS - Semiconductor dies and methods are described, such as those including a first capacitive pathway having a first effective series resistance (ESR) and a second capacitive pathway having an adjustable ESR. One such device provides for optimizing the semiconductor die for different operating conditions such as operating frequency. As a result, semiconductor dies can be manufactured in a single configuration for several different operating frequencies, and each die can be tuned to reduce (e.g. minimize) supply noise, such as by varying the ESR or the capacitance of at least one of the pathways. | 2014-05-08 |
| 20140125425 | COMPACT MICROSTRIP TO WAVEGUIDE DUAL COUPLER TRANSITION - A compact microstrip to waveguide dual coupler transition includes a multilayer printed circuit board configured with a rectangular region on an upper surface of the multilayer printed circuit board, wherein the rectangular region has a pair of long edges and a pair of short edges; a transition probe configured on the upper surface of the multilayer printed circuit board, wherein a terminal of the transition probe extends into the rectangular region through a long edge of the rectangular region, and another terminal of the transition probe is electrically connected to a power amplifier; a first coupler probe configured on the upper surface of the multilayer printed circuit board, wherein a terminal of the first coupler probe extends into the rectangular region; and a second coupler probe configured on the upper surface of the multilayer printed circuit board, wherein a terminal of the second coupler probe extends into the rectangular region. | 2014-05-08 |
| 20140125426 | HIGH-FREQUENCY SIGNAL TRANSMISSION LINE AND ELECTRONIC APPARATUS - An easily bendable high-frequency signal transmission line includes a dielectric body including a protection layer and dielectric sheets laminated on each other, a surface and an undersurface. A signal line is a linear conductor disposed in the dielectric body. A ground conductor is disposed in the dielectric body, faces the signal line via the dielectric sheet, and continuously extends along the signal line. A ground conductor is disposed in the dielectric body, faces the ground conductor via the signal line sandwiched therebetween, and includes a plurality of openings arranged along the signal line. The surface of the dielectric body on the side of the ground conductor with respect to the signal line is in contact with a battery pack. | 2014-05-08 |
| 20140125427 | WIDE BAND SUM & DIFFERENCE CIRCUIT FOR MONOLITHIC MICROWAVE INTEGRATED CIRCUIT - Disclosed is a wide band sum & difference circuit for a monolithic microwave integrated circuit according to an exemplary embodiment of the present invention. The wide band sum & difference circuit for a monolithic microwave integrated circuit according to an exemplary embodiment of the present invention, including: a Range coupler having one terminal connected to a plurality of first ports that receive a signal and the other terminal connected to a plurality of second ports that output signals; one λ/4 line that is connected between one output terminal and one second port of the Range coupler in series; and one short stub λ/4 line that is connected with the other output terminal and the other second port of the Range coupler in parallel. | 2014-05-08 |
| 20140125428 | SWITCHING DEVICE AND MODULE - A switching device includes: a switch that selects and connects one of input-output terminals to a common terminal; and a delay line that is connected in parallel to the switch between two terminals of the input-output terminals and delays a signal by using an acoustic wave. | 2014-05-08 |
| 20140125429 | SHUNT RESISTOR DEVICE - Provided is a voltage detection circuit, which can remove influence of error voltage caused by tiny amount of self-inductance existing in a shunt resistor, though in the resistor for large current usage, which is impossible to surface-mount on a voltage detection circuit board. The shunt resistor device comprises: a resistance body ( | 2014-05-08 |
| 20140125430 | NOISE FILTER - A noise filter includes a first magnetic core that includes a plurality of leg portions, and a first connection portion and a second connection portion, which connect both ends of the leg portions, a plurality of coils that are wound on the leg portions, respectively, and a second magnetic core that is configured to be attachable to and detachable from the first magnetic core such that a closed magnetic path, which intersects with each of the first connection portion and the second connection portion and which passes through the leg portions, is formed, in which the first magnetic core includes a normal mode inductance, and the closed magnetic path includes a common mode inductance. | 2014-05-08 |
| 20140125431 | TUNABLE AND SWITCHABLE RESONATOR AND FILTER STRUCTURES IN SINGLE CRYSTAL PIEZOELECTRIC MEMS DEVICES USING BIMORPHS - A MEMS device includes a substrate, one or more anchors formed on a first surface of the substrate, and a piezoelectric layer suspended over the first surface of the substrate by the one or more anchors. Notably, the piezoelectric layer is a bimorph including a first bimorph layer and a second bimorph layer. A first electrode may be provided on a first surface of the piezoelectric layer facing the first surface of the substrate, such that the first electrode is in contact with the first bimorph layer of the piezoelectric layer. A second electrode may be provided on a second surface of the piezoelectric layer opposite the substrate, such that the second electrode is in contact with the second bimorph layer of the piezoelectric layer. The second electrode may include a first conducting section and a second conducting section, which are inter-digitally dispersed on the second surface. | 2014-05-08 |
| 20140125432 | SELECTIVE TUNING OF ACOUSTIC DEVICES - This disclosure provides implementations of methods, apparatus and systems for producing acoustic wave devices and for selectively modifying one or more acoustic or electromechanical characteristics of such devices. In one aspect, a method includes depositing a structural layer over a substrate. The structural layer includes a plurality of structural portions, each being positioned over a corresponding device region. The method also includes arranging a mask layer over the structural layer. The mask layer includes a plurality of mask portions, each including a number of mask openings that expose a corresponding region of the structural portion. The method also includes accelerating dopant particles toward the mask layer. The accelerated dopant particles that proceed through the mask openings are impacted into the corresponding structural portion. The impacted dopant particles modify material properties in the structural portion, which then effect a change in the acoustic or electromechanical characteristics of the acoustic wave device. | 2014-05-08 |
| 20140125433 | RESONANTOR STRUCTURE FOR WIRELESS POWER TRANSFER SYSTEM - A resonator structure for a wireless power transfer system Includes resonators, which are to transfer wireless power, and a dielectric substance, which includes at least one exposure region formed on the dielectric substance to fix the resonators in a covered shape and to selectively expose parts of the resonators. | 2014-05-08 |
| 20140125434 | HIGH-FREQUENCY SIGNAL TRANSMISSION LINE AND ELECTRONIC APPARATUS - An easily bendable high-frequency signal transmission line includes a dielectric body including a protection layer and dielectric sheets laminated on each other, a surface and an undersurface. A signal line is a linear conductor disposed in the dielectric body. A ground conductor is disposed in the dielectric body, faces the signal line via the dielectric sheet, and continuously extends along the signal line. A ground conductor is disposed in the dielectric body, faces the ground conductor via the signal line sandwiched therebetween, and includes a plurality of openings arranged along the signal line. The surface of the dielectric body on the side of the ground conductor with respect to the signal line is in contact with a battery pack. | 2014-05-08 |
| 20140125435 | EQUALIZER ASSEMBLY FOR LOSS-COMPENSATION OF HIGH-FREQUENCY SIGNALS GENERATED IN TRANSMISSION CHANNELS - An equalizer assembly for compensating transmission losses of electronic communication signals includes a circuit board and a first equalizer and a second equalizer. Two input pins of each equalizer are parallel to each other. The input pins of the first equalizer are perpendicular to the input pins of the second equalizer. | 2014-05-08 |
| 20140125436 | MAGNETIC CIRCUIT AND KEY INPUT DEVICE - There is provided a magnetic circuit including a first magnetic body configured to include a magnet and a yoke plate, and a second magnetic body. The yoke plate forms an opening space at a position facing the second magnetic body. The magnet is disposed in the opening space or at a position sandwiched between the yoke plates. | 2014-05-08 |
| 20140125437 | ELECTROMAGNETIC ACTUATOR DEVICE - An electromagnetic actuator device, comprising a coil unit ( | 2014-05-08 |
| 20140125438 | EXCITED FERRO ELECTRO DYNAMO - Excited ferro electro dynamo is a green energy invention that generates a ferro electro mechanical energy. This energy is the outcome of the angular momentum of the rotor, a permanent magnet, along the excited helical magnetic force S (FIG. | 2014-05-08 |
| 20140125439 | INSULATION FORMULATIONS - A curable epoxy resin formulation composition useful as insulation for an electrical apparatus including (a) at least one liquid epoxy resin; (b) at least one liquid cyclic anhydride hardener; (c) at least one thermally conducting and electrically insulating filler, wherein the filler includes an epoxy-silane treated filler; and (d) at least one cure catalyst with no amine hydrogens; wherein the epoxy resin formulation composition upon curing provides a cured product with a requisite balance of electrical, mechanical, and thermal properties such as Tg, tensile strength, dielectric strength, and volume resistivity such that the cured product can be used in applications operated at a temperature of greater than or equal to 120° C. | 2014-05-08 |
| 20140125440 | INDUCTOR AND MANUFACTURING METHOD THEREFOR - An inductor that has the following: an inductor core comprising a plurality of core members arranged in a ring with gaps therebetween; primary insert-molded resin parts comprising a thermoplastic resin covering the outside surface of the inductor core, excluding the surfaces of the core members that face each other; coils disposed around the aforementioned gaps and the primary insert-molded resin parts on the inductor core; and secondary insert-molded resin parts comprising a thermoplastic resin insert-molded around the coils to affix said coils to the inductor core. This allows high-cycle manufacturing of inductors without a thermosetting-resin potting step in a vacuum furnace or a heat curing treatment in a heating furnace. | 2014-05-08 |
| 20140125441 | LARGE-CURRENT TRANSFORMER FOR ELECTRONIC ROUND POWER METER AND METHOD OF MAKING - Disclosed is a large-current transformer for an electronic round power meter, including a current sampling coil ( | 2014-05-08 |
| 20140125442 | TRANSFORMER AND FLAT PANEL DISPLAY DEVICE INCLUDING THE SAME - There are provided a thin transformer capable of being used in a slim display device such as a liquid crystal display (LCD) device and a light emitting diode (LED) display device, and a flat panel display device including the same. The transformer includes: a bobbin part including a plurality of bobbins, each including a pipe shaped body part having a through-hole formed in an inner part thereof and a flange part protruding outwardly from both ends of the body part; coils respectively wound around the bobbins; and a core electromagnetically coupled to the coils to thereby form a magnetic path, wherein at least one of the bobbins includes a coil skip part which is a route through which lead wires of the coil skipped through the flange part is disposed on an outer surface of the flange part. | 2014-05-08 |
| 20140125443 | TRANSFORMER - A transformer, according to one possible embodiment, includes: a bobbin part formed by stacking a plurality of bobbins including external connection terminals; and coils respectively wound around the plurality of bobbins. At least one bobbin of the plurality of bobbins includes withdrawing grooves formed in a space between the external connection terminals, the respective coil wound around the at least one bobbin being withdrawn outside the bobbin via the withdrawing grooves and coupled to the external connection terminal. | 2014-05-08 |
| 20140125444 | Combined structure of hollow bobbin and conductive sheet, hollow bobbin, and conductive sheet - A combined structure of hollow bobbin and conductive sheet for a transformer includes a hollow bobbin and at least one conductive sheet. The hollow bobbin includes an outer surface and at least one positioning structure formed on the outer surface. The conductive sheet is fit on the outer surface of the hollow bobbin and includes a main body and at least one engaging structure. The main body has a hollow portion, making the main body to have an inner circumference. The engaging structure is formed on the inner circumference of the main body and is engaged with the positioning structure of the hollow bobbin. The transformer includes at least one winding disposed on the outer surface of the hollow bobbin and abutting against the conductive sheet. | 2014-05-08 |
| 20140125445 | COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a common mode filter and a method of manufacturing the same. The common mode filter includes: a primary coil that includes a primary coil body forming a plane in a vortex structure; and a secondary coil that includes a secondary coil body forming a co-plane in the same vortex structure as the primary coil body and forms a 180° rotational symmetry with the primary coil body, having the same length, width, and turn number as the primary coil body. Further, the method of manufacturing a common mode filter is proposed. | 2014-05-08 |
| 20140125446 | SUBSTRATE INDUCTIVE DEVICE METHODS AND APPARATUS - An improved low cost and highly consistent inductive apparatus. In one embodiment, the low cost and highly consistent inductive apparatus addresses concerns with so called conductive anodic filament (CAF) that occurs within these laminate structures. These conditions include high humidity, high bias voltage (i.e. a large voltage differential), high-moisture content, surface and resin ionic impurities, glass to resin bond weakness and exposure to high assembly temperatures that can occur, for example, during lead free solder bonding application. Methods of manufacturing and using the aforementioned substrate inductive devices are also disclosed. | 2014-05-08 |
| 20140125447 | Resistance calibrating circuit - A resistance calibrating circuit includes an external power source; a reference unit, a current calibrating circuit and a voltage calibrating unit which are respectively connected to the external power source; an external reference voltage which is respectively connected to the reference unit and the voltage calibrating unit; an to-be-calibrated voltage-controlled resistor which is respectively connected to the current calibrating unit and the voltage calibrating unit, wherein the current calibrating unit is further connected to the reference unit. The resistance calibrating circuit is capable of automatically adjusting a resistance of the to-be-calibrated voltage-controlled resistor highly precisely and highly efficiently. | 2014-05-08 |
| 20140125448 | CHIP THERMISTOR - A chip thermistor comprises a thermistor element body and a pair of outer electrodes. The thermistor element body has a pair of end faces opposing each other and a main face connecting the end faces to each other. The pair of outer electrodes are arranged on the pair of end faces, respectively. The pair of outer electrodes have a width in a direction intersecting the opposing direction of the pair of end faces made narrower with distance from the thermistor element body. | 2014-05-08 |
| 20140125449 | NON-LINEAR RESISTIVE ELEMENT - Provided is a non-linear resistive element which improves the degree of freedom of design of its mounting space. A ceramic sheet | 2014-05-08 |
| 20140125450 | APPARATUSES, SYSTEM AND PROCESS FOR THE PERSONAL PROTECTION - An apparatus for the personal protection is described. The apparatus has at least one main control unit which is connected to one or more main sensors and to a first main transceiver for transmitting and receiving on a first radio channel control signals and/or activation signals, wherein the main control unit is also connected to a second main transceiver for transmitting and receiving on a second radio channel control signals and/or activation signals. Vehicles and a system which comprise the apparatus are also described. The vehicles and the system also include a secondary apparatus and a protective garment which can communicate with the apparatus. A process which can be carried out by the system is also described. | 2014-05-08 |
| 20140125451 | AUDIO ILLUMINATION APPARATUS AND STORAGE MEDIUM - There is provided an audio illumination apparatus including an illumination unit, an audio output unit, a setting unit configured to set a parameter of at least one of illumination of the illumination unit and audio output of the audio output unit in accordance with a recognized user who is in a neighborhood, a transmission unit configured to transmit the parameter set by the setting unit to an audio illumination apparatus in the neighborhood, and a control unit configured to control the at least one of the illumination of the illumination unit and the audio output of the audio output unit in accordance with the set parameter. | 2014-05-08 |
| 20140125452 | Changing the operating mode of an electronic device associated with a transport unit - It is inter alia disclosed an apparatus ( | 2014-05-08 |
| 20140125453 | SYSTEM AND METHOD FOR ACCESSING A STRUCTURE USING DIRECTIONAL ANTENNAS AND A WIRELESS TOKEN - A wireless device access system that employs directional antennas for short-range wireless communication to detect the proximity and orientation of a user device with respect to a structure is disclosed. The access system receives and authenticates an unlock request and confirms the proximity and orientation of the user device prior to transmitting an unlock command to the structure. Additionally, the wireless device may require the proximity of a user token prior to operation and/or the access system may include an override within the structure blocking any unlock command. | 2014-05-08 |
| 20140125454 | LOCKBOX STORAGE APPARATUS - A lockbox storage apparatus comprising a pair of side walls on each side of said lockbox storage apparatus, a door attached to a front portion of said lockbox storage apparatus, where said door is attached between said pair of side walls, a top panel affixed to a top portion of said lockbox storage apparatus, a lock attached to said door, where said lock secures said door against one of said pair of side wall, a back wall opposite to said door, where said back wall is attached between said pair of side walls, an inner panel fastened within said lockbox storage apparatus, where said inner panel rest against said back wall, a plurality of attachment means arranged against said inner panel, and a plurality of lockboxes hanging from said attachment means wherein said plurality of lockboxes include a key to enable a user to access a property. | 2014-05-08 |
| 20140125455 | SYSTEMS AND ALGORITHMS FOR CLASSIFICATION OF USER BASED ON THEIR PERSONAL FEATURES - A system and algorithms to authenticate a person where a system only has some standard personal text data about the person, and cannot have a real biometric template obtained using an enrollment procedure. The authentication allows access to restricted resources by the person. This method is especially useful when it is used as an auxiliary authentication service with other methods such as password or Callback that dramatically lower the chances for an imposter. | 2014-05-08 |
| 20140125456 | PROVIDING AN IDENTITY - Providing an identity is described herein. One method includes receiving identity information associated with a person, determining a level of correlation between the identity information and identity information associated with a known identity, and providing the known identity to a user based, at least in part, on the correlation exceeding a threshold. | 2014-05-08 |
| 20140125457 | Underground Asset Management System - A system for managing underground assets with RFID tags provides for expanded virtual storage by wirelessly linking the field RFID tag reader to a centralized database through a unique series code in the RFID tag. Real-time updating of information about underground assets coordination between multiple users may be accomplished through use of the central database as an information broker | 2014-05-08 |
| 20140125458 | MEMS Sensor Enabled RFID System and Method for Operating the Same - A method for providing environmental monitoring of an item with an electronic system includes the steps of operating the electronic system in a deep-sleep mode at a minimal level of power consumption by disabling operation of nonessential portions of the electronic system; activating the electronic system at a monitoring rate to sense an environmental parameter to which the item is subjected; sensing a value of the environmental parameter to which the item is subjected; comparing the sensed environmental parameter with the value of the environmental parameter just previously sensed to derive a rate of change of the environmental parameter; adjusting the monitoring rate to track the rate of change of the environmental parameter; storing the value of the sensed environmental parameter; and returning the electronic system to the deep-sleep mode. | 2014-05-08 |
| 20140125459 | SYSTEM AND METHOD FOR TRACKING - A tracking system comprising: a transmitter configured to steer an RF beam across a detection range, a passive RFID tag configured to be enabled for locating substantially when located in the centre of the RF beam of the transmitter, and an RFID reader configured to detect the tag | 2014-05-08 |
| 20140125460 | RFID PASSIVE REFLECTOR FOR HIDDEN TAGS - The subject matter relates to methods for communicating with an RFID tag that is positioned out of the line-of-sight of a communications device. A passive reflector is provided corresponding to an antenna resonant at the operating frequency of the tag. The antemia may be supported by an insulative or conductive wand for manual placement within the line-of-sight of both the tag and a communications device wishing to communicate with the tag. The passive reflector receives signals from either or both the tag and communications device and retransmits the signals. In this manner signals are able to “turn a comer” to improve communications capabilities. | 2014-05-08 |
| 20140125461 | SIMPLE AND PRECISE RADIO FREQUENCY LOCATING SYSTEM AND METHOD - Disclosed are a radio frequency locating system and method, which efficiently solve the problem of precise locating a moving target tag in a complex environment by using a method where location information is provided for a mobile tag by using low-cost fixed active RFID tags in place of a plurality of readers requiring network connection, and the location information of the mobile tag is directly transferred to a reader at the center of a locating area from a long distance by using a mobile or fixed location tag. The present invention uses a long-distance coordinator and clock information in a transmission instruction to coordinate and schedule communication time between the mobile tag and the location tag, thereby ensuring a super long battery life of the mobile tag and the location tag. | 2014-05-08 |
