19th week of 2015 patent applcation highlights part 16 |
Patent application number | Title | Published |
20150123100 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE THIN FILM TRANSISTOR - A thin film transistor includes a gate electrode and an organic semiconductor overlapping the gate electrode. A gate insulating layer is disposed between the gate electrode and the organic semiconductor. A source electrode and a drain electrode are disposed on and electrically connected to the organic semiconductor. A solvent selective photosensitive pattern is disposed on the organic semiconductor and between the source electrode and the drain electrode. An electronic device may include the thin film transistor. | 2015-05-07 |
20150123101 | LIGHTING EMITTING DEVICE, MANUFACTURING METHOD OF THE SAME, ELECTRONIC DEVICE HAVING THE SAME - One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface. | 2015-05-07 |
20150123102 | ORGANIC LIGHT EMITTING DISPLAY - An organic light emitting display includes a first substrate comprising a major surface, and a pixel array formed over the major surface of the first substrate. The pixel array comprises a plurality of pixels formed over the first substrate and a plurality of spacers arranged over the first substrate. Each pixel comprises a first electrode and an organic emission layer formed over the first electrode. The pixel array provides a plurality of recesses and a plurality of bumps, and the plurality of recesses correspond to the first electrodes of the plurality of pixels and the plurality of bumps corresponds to the plurality of spacers. When viewing the pixel array from the top in a first direction perpendicular to the major surface, each spacer is interposed between two immediately neighboring recesses and a row of spacers are arranged along a first axis, and each recess has a first width taken along the first axis and a second width taken along a second axis parallel to the first axis, the first width being smaller than the second width. | 2015-05-07 |
20150123103 | ORGANIC ELECTROLUMINESCENCE DEVICE - An organic electroluminescence device comprise an organic electroluminescence element including a pair of electrodes and an organic layer disposed between the pair of electrodes and a sealing resin layer covering a surface of the organic electroluminescence element. The organic layer includes an emitting layer. The sealing resin layer includes a thermoplastic resin composite. The thermoplastic resin composite contains a matrix resin component constituted by at least one resin having a molecular weight of 5000 or more. A content of an organic component having a molecular weight of less than 500 in the thermoplastic resin composite is less than 6 ppm. | 2015-05-07 |
20150123104 | DISPLAY PANEL WITH VARYING CONDUCTIVE PATTERN ZONE - An organic electroluminescence display panel comprises a first substrate, a second substrate assembled to the first substrate, an organic light-emitting layer positioned between the first and second substrates, a sealant positioned between the first and second substrates, a varying pattern zone, and supplemental pattern zone. The second substrate comprises a sealant dispensing area, a metal region, and a non-metal region adjacent to the metal region. The metal region includes plural traces. The sealant is formed in the sealant dispensing area of the second substrate. The varying pattern zone is formed at one of the traces of the metal region, and is corresponding to the sealant dispensing area. The varying pattern zone comprises plural conductive portions. The supplemental pattern zone comprising plural supplemental conductive portions is formed at the non-metal region. A width of the conductive portions is larger than a width of the supplemental conductive portions. | 2015-05-07 |
20150123105 | OFF-CENTER SPIN-COATING AND SPIN-COATED APPARATUSES - Various aspects of the instant disclosure are directed to methods and to apparatuses involving spin-coating and spin-coated materials. As may be implemented in connection with one or more embodiments, a solution having objects dispersed therein is applied to a substrate and the substrate is spun about an axis that is off-center relative to a center of the substrate. The objects are thus aligned along a predominantly unidirectional orientation. The solution is solidified with the objects aligned to one another along the predominantly unidirectional orientation. | 2015-05-07 |
20150123106 | Peeling Method and Light-Emitting Device - The yield of a peeling process is improved. A first step of forming a peeling layer to a thickness of greater than or equal to 0.1 nm and less than 10 nm over a substrate; a second step of forming, on the peeling layer, a layer to be peeled including a first layer in contact with the peeling layer; a third step of separating parts of the peeling layer and parts of the first layer to form a peeling trigger; and a fourth step of separating the peeling layer and the layer to be peeled are performed. The use of the thin peeling layer can improve the yield of a peeling process regardless of the structure of the layer to be peeled. | 2015-05-07 |
20150123107 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes: an emission unit including an organic light emitting diode, a pixel circuit unit including: a circuit configured to drive the emission unit, and a line configured to apply a signal to the circuit, and a light blocking layer covering the pixel circuit unit, and configured to block light input to the pixel circuit unit, and a repair part disposed in the light blocking layer, the repair part being configured for repairing the line when a defect occurs in a pixel that includes the pixel circuit unit. | 2015-05-07 |
20150123108 | ORGANIC ELECTROLUMINESCENCE ELEMENT, METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENCE ELEMENT AND ORGANIC ELECTROLUMINESCENCE MODULE - Provided is an organic electroluminescence element that eliminates uneven light emission and changes a light emitting pattern. The organic electroluminescence element including: a supporting substrate; a first electrode; N sets of light emitting units including one or more organic functional layers, where N represents an integer of 2 or more; and one or more (N−1) sets of intermediate metal layers with optical transparency, each disposed between the adjacent light emitting units; and a second electrode. Herein, at least one organic functional layer of each light emitting unit is a layer subjected to patterning using a mask during formation of the organic functional layer, a layer subjected to patterning via light irradiation after formation of the organic functional layer, or a layer subjected to patterning using a mask during formation of the organic functional layer and further subjected to patterning via light irradiation after the formation of the organic functional layer. | 2015-05-07 |
20150123109 | DRIVING METHOD OF LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE - A driving method of a light emitting device, in which when an N-type driving TFT is connected to an anode of a light emitting element or a P-type driving TFT is connected to a cathode thereof, the driving TFT operates in a saturation region and an image can be displayed with a desired gray scale level depending on a video signal. In addition, a light emitting device adopting the driving method is provided. According to the invention, when a potential having image data is supplied to a gate of a driving TFT depending on a video signal, a reverse bias voltage is applied to the driving TFT and a light emitting element which are connected in series with each other. Meanwhile, when a pixel displays an image depending on the video signal, a forward bias voltage is applied to the driving TFT and the light emitting element. | 2015-05-07 |
20150123110 | OXIDE SEMICONDUCTOR COMPOSITION AND MANUFACTURING METHOD THEREOF, OXIDE THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - An oxide semiconductor composition comprises graphene, a metal oxide precursor, and a solvent. Based on a total weight of the oxide semiconductor composition, a concentration of the graphene is between 0.01 and 10 wt %, a concentration of the metal oxide is between 0.01 and 30 wt %, and a concentration of the solvent is between 60 and 99.98 wt %. | 2015-05-07 |
20150123111 | PIXEL STRUCTURE AND FABRICATION METHOD THEREOF - A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode. | 2015-05-07 |
20150123112 | THIN FILM TRANSISTOR SUBSTRATE, DISPLAY APPARATUS HAVING THE SAME, AND MANUFACTURING METHOD THEREOF - Each pixel of a thin film transistor substrate includes a base substrate including a pixel display area and a pixel non-display area surrounding the pixel display area, a gate electrode on the base substrate in the pixel non-display area, a first insulating layer which is on the base substrate in the pixel non-display area and covers the gate electrode, a semiconductor layer on the first insulating layer, of which a predetermined portion thereof overlaps the gate electrode, a source electrode and a drain electrode which are spaced apart from each other and on the semiconductor layer, a second insulating layer which is on the first insulating layer and the base substrate and covers the source electrode and the drain electrode, and a pixel electrode on the second insulating layer in the pixel display area. | 2015-05-07 |
20150123113 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel according to an exemplary embodiment of the invention includes: an insulating substrate; a gate line disposed on the insulating substrate and including a gate pad portion; a data line insulated from and crossing the gate line, and including a source electrode and a data pad portion; a drain electrode facing the source electrode; an organic insulating layer disposed on the data line and the drain electrode, and including a first contact hole; a common electrode disposed on the organic insulating layer, and including a second contact hole; a passivation layer disposed on the common electrode, and including a third contact hole; and a pixel electrode disposed on the passivation layer, and being in contact with the drain electrode, in which the third contact hole is disposed to be adjacent to one surface of the first contact hole for improvement of an aperture ratio and a stable electrode connection. | 2015-05-07 |
20150123114 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel includes a substrate, a gate line extending in a first direction on the substrate, a data line extending in a second direction on the substrate and intersecting the gate line, a thin film transistor connected to the gate line and the data line, an insulating layer on the gate line, the data line, and the thin film transistor, a first auxiliary line on the insulating layer and connected to the gate line, a second auxiliary line on the insulating layer and connected to the data line, and a pixel electrode connected to the thin film transistor. | 2015-05-07 |
20150123115 | METHOD FOR PRODUCING AN OXIDE FILM USING A LOW TEMPERATURE PROCESS, AN OXIDE FILM AND AN ELECTRONIC DEVICE THEREOF - Disclosed are a method for producing an oxide film using a low temperature process, an oxide film and an electronic device. The method for producing an oxide film according to an embodiment of the present invention includes the steps of coating a substrate with an oxide solution, and irradiating the oxide solution coat with ultraviolet rays under an inert gas atmosphere. | 2015-05-07 |
20150123116 | THIN FILM TRANSISTOR - Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IZTO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; Ga: 5% or more; In: 25% or less (excluding 0%); Zn: 35 to 65%; and Sn: 8 to 30%. | 2015-05-07 |
20150123117 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A TFT substrate ( | 2015-05-07 |
20150123118 | ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - An array substrate for an electronic display includes a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; an oxide semiconductor layer on the gate insulating layer; a source electrode and a drain electrode on the oxide semiconductor layer; a silicide layer on the source and drain electrodes; and a first passivation layer on the source electrode and the drain electrode. The array substrate and fabrication method thereof prevent degradation of a thin-film transistor (TFT) used in driving pixels of the electronic display. | 2015-05-07 |
20150123119 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - Provided are an image sensor and a method of manufacturing method of manufacturing the image sensor. The image sensor includes a substrate, photoelectric transducers and switching elements formed in layers on the substrate in this order. Each of the photoelectric transducers includes a hydrogenated amorphous silicon layer. Each of the switching elements includes an amorphous oxide semiconductor layer. The image sensor further includes a blocking layer arranged between the hydrogenated amorphous silicon layers of the photoelectric transducers and the amorphous oxide semiconductor layers of the switching elements, where the blocking layer suppresses penetration of hydrogen separated from the hydrogenated amorphous silicon layers. | 2015-05-07 |
20150123120 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - A highly reliable semiconductor device including an oxide semiconductor is provided. The concentration of impurities contained in an oxide semiconductor of a semiconductor device including the oxide semiconductor is reduced. Electrical characteristics of a semiconductor device including an oxide semiconductor are improved. The semiconductor device includes an oxide semiconductor film; a gate electrode layer overlapping with the oxide semiconductor film; a gate insulating film between the oxide semiconductor film and the gate electrode layer; a metal oxide film overlapping with the gate insulating film with the oxide semiconductor film positioned therebetween; and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor film. The metal oxide film covers at least a channel region and a side surface of the oxide semiconductor film. | 2015-05-07 |
20150123121 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device with a structure in which an increase in the number of oxygen vacancies in an oxide semiconductor layer can be suppressed and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an oxide insulating layer; intermediate layers apart from each other over the oxide insulating layer; a source electrode layer and a drain electrode layer over the intermediate layers; an oxide semiconductor layer that is electrically connected to the source electrode layer and the drain electrode layer and is in contact with the oxide insulating layer; a gate insulating film over the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate electrode layer that is over the gate insulating film and overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer. | 2015-05-07 |
20150123122 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object of an embodiment of the present invention is to manufacture a highly-reliable semiconductor device comprising a transistor including an oxide semiconductor, in which change of electrical characteristics is small. In the transistor including an oxide semiconductor, oxygen-excess silicon oxide (SiO | 2015-05-07 |
20150123123 | TRANSISTOR AND DISPLAY DEVICE USING THE SAME - The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×10 | 2015-05-07 |
20150123124 | ROTATED CHANNEL FIELD EFFECT TRANSISTOR - A transistor device, such as a rotated channel metal oxide/insulator field effect transistor (RC-MO(I)SFET), includes a substrate including a non-polar or semi-polar wide band gap substrate material such as an Al | 2015-05-07 |
20150123125 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to improve reliability of a light-emitting device. A light-emitting device has a driver circuit portion including a transistor for a driver circuit and a pixel portion including a transistor for a pixel over one substrate. The transistor for the driver circuit and the transistor for the pixel are inverted staggered transistors each including an oxide semiconductor layer in contact with part of an oxide insulating layer. In the pixel portion, a color filter layer and a light-emitting element are provided over the oxide insulating layer. In the transistor for the driver circuit, a conductive layer overlapping with a gate electrode layer and the oxide semiconductor layer is provided over the oxide insulating layer. The gate electrode layer, a source electrode layer, and a drain electrode layer are formed using metal conductive films. | 2015-05-07 |
20150123126 | SEMICONDUCTOR DEVICE - A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor. | 2015-05-07 |
20150123127 | SEMICONDUCTOR DEVICE - High field-effect mobility is provided for a semiconductor device including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a transistor in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween, an oxide semiconductor layer functioning as a current path (channel) of the transistor and containing an n-type impurity is sandwiched between oxide semiconductor layers having lower conductivity than the oxide semiconductor layer. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side contains the n-type impurity at a higher concentration than a region on the back channel side. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed. | 2015-05-07 |
20150123128 | ARRAY SUBSTRATE - The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT. | 2015-05-07 |
20150123129 | WAFER LEVEL PACKAGING TECHNIQUES - In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer. | 2015-05-07 |
20150123130 | TEST KEY STRUCTURE - A test key structure is provided. The test key structure comprises at least one semiconductor element. Each of the at least one semiconductor element including a well, a source region, a drain region and a gate. The source region is disposed in the well. The drain region is disposed in the well and separated from the source region. The gate is disposed above the well. The source region, the drain region and the well have the same type of doping. | 2015-05-07 |
20150123131 | Semiconductor Devices and Methods of Formation Thereof - In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node. | 2015-05-07 |
20150123132 | SEMICONDUCTOR SYSTEM - A semiconductor system may include a first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad. | 2015-05-07 |
20150123133 | INTEGRATED CIRCUIT FOR DETECTING DEFECTS OF THROUGH CHIP VIA - An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode. | 2015-05-07 |
20150123134 | INFRARED DETECTOR, INFRARED DETECTION SENSOR HAVING AN INFRARED DETECTOR AND METHOD OF MANUFACTURING THE SAME - An infrared detector includes a substrate, a light blocking layer on the substrate, a lower electrode on the light blocking layer, the lower electrode electrically connected to the light blocking layer, a lower insulating layer on the light blocking layer, a first semiconductor layer on the lower insulating layer, a first source electrode and a first drain electrode on the first semiconductor layer, an upper insulating layer on the first semiconductor layer, and a first gate electrode on the upper insulating layer, the first gate electrode electrically connected to the lower electrode, where the first semiconductor layer includes a zinc and a nitrogen, and the first semiconductor layer is configured to generate electric charges by reacting with an infrared ray. | 2015-05-07 |
20150123135 | ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND LIQUID CRYSTAL PANEL - An array substrate, a method for fabricating the same and a liquid crystal panel are disclosed. The array substrate includes a display region and a frame region surrounding the display region. The display region includes a plurality of data lines, a plurality of scan lines and a plurality of scan connection lines. The plurality of data lines and the plurality of scan lines intersect each other to divide the display region into a plurality of pixel regions. The plurality of scan lines are electrically connected to the plurality of scan connection lines in a one-to-one correspondence in the display region. | 2015-05-07 |
20150123136 | Array Substrate For Display Panel And Method For Manufacturing Thereof - Disclosed are an array substrate and a method of fabricating the same. The array substrate includes an active area including a plurality of pixels defined at an intersection area of a gate line and a data line, a gate driving circuit formed at one side of a non-active area and a signal line extending in parallel with the data line in the non-active area to transfer a signal to the gate driving circuit. The signal line includes a first line with a plurality of segmental lines, and at least one additional line formed of a different material and formed at a different layer than the first line. The at least one additional line electrically connects two segmental lines of the first line adjacent to each other. | 2015-05-07 |
20150123137 | FLEXIBLE DISPLAY DEVICE AND CURVED DISPLAY DEVICE - Provided is a configuration for a semiconductor layer and a line for reducing the segment length of the semiconductor layer with respect to the bending direction of the flexible substrate. Such a configuration reduces the probability of cracks occurring in the semiconductor layer of the thin-film transistor, thereby improving the stability and durability of the thin-film transistor employed in a curved or a flexible display device. The configuration includes a thin-film transistor (TF) on the flexible substrate. The TFT includes the semiconductor layer extending obliquely with respect to the direction of the line. | 2015-05-07 |
20150123138 | HIGH POWER GALLIUM NITRIDE ELECTRONICS USING MISCUT SUBSTRATES - An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer. | 2015-05-07 |
20150123139 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a high electron mobility transistor and/or a method of manufacturing the same. The high electron mobility transistor includes a channel layer, a channel supply layer formed on the channel layer to generate a two-dimensional electron gas (2DEG), a depletion forming layer formed on the channel supply layer, a gate electrode formed on the depletion forming layer, and a barrier layer formed between the depletion forming layer and the gate electrode. Holes may be prevented from being injected into the depletion forming layer from the gate electrode, thereby reducing a gate forward current. | 2015-05-07 |
20150123140 | SEMIPOLAR NITRIDE SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7≦k≦13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0. | 2015-05-07 |
20150123141 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes. | 2015-05-07 |
20150123142 | POWER SEMICONDUCTOR DEVICE INCLUDING A COOLING MATERIAL - A power semiconductor device includes a wiring structure adjoining at least one side of a semiconductor body and comprising at least one electrically conductive compound. The power semiconductor device further includes a cooling material in the wiring structure. The cooling material is characterized by a change in structure by means of absorption of energy at a temperature T | 2015-05-07 |
20150123143 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device of an embodiment includes a semiconductor layer formed of a III-V group nitride semiconductor, a first silicon nitride film formed on the semiconductor layer, a gate electrode formed on the first silicon nitride film, a source electrode and a drain electrode formed on the semiconductor layer such that the gate electrode is interposed between the source electrode and the drain electrode, and a second silicon nitride film formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode and having an oxygen atom density lower than that of the first silicon nitride film. | 2015-05-07 |
20150123144 | Semiconductor Structures and Methods with High Mobility and High Energy Bandgap Materials - An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin. | 2015-05-07 |
20150123145 | Semiconductor Device and Method for Producing the Same - A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided. | 2015-05-07 |
20150123146 | INCREASED SPACE BETWEEN EPITAXY ON ADJACENT FINS OF FINFET - A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume. | 2015-05-07 |
20150123147 | SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches. | 2015-05-07 |
20150123148 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - [Problem] To provide a semiconductor device in which the surface of a metal electrode arranged on the outermost surface can be made flat or smooth, and a method for producing said semiconductor device. | 2015-05-07 |
20150123149 | Semiconductor Device and Method for Producing the Same - A semiconductor device comprises a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, comprising amorphous metal nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided. | 2015-05-07 |
20150123150 | DISPLAY DEVICE - When the plane shape of a bank edge, that is, the direction of a line segment connecting the centers of pixels adjacent to each other (the direction of the pixels) is orthogonal to the direction of a line segment formed by the bank edge, light leaks from the adjacent pixels. The shape of the luminous region of the pixel of a display device, that is, the edge shape of a bank opening is formed as follows. The direction of an approximately linear portion (a line segment) formed by a bank edge is not orthogonal to the direction of the most closely adjacent pixel (an acute angle or an obtuse angle is formed by the directions). | 2015-05-07 |
20150123151 | LIGHT EMITTING DEVICE - A light-emitting structure includes a transparent substrate; a first transparent conductive layer formed on the transparent substrate and having a first top surface and a second top surface substantially coplanar with the first top surface; a first light-emitting stack formed on the first top surface; and a first electrode directly formed on the second top surface. | 2015-05-07 |
20150123152 | LIGHT-EMITTING ELEMENT - A light-emitting element includes a light-emitting stacked layer including an upper surface, wherein the upper surface includes a first flat region; a protective layer including a current blocking region on the first flat region; and a cap region on the upper surface, wherein the current blocking region is spatially separate from the cap region; and a first electrode covering the current blocking region. | 2015-05-07 |
20150123153 | LED PACKAGE WITH RED-EMITTING PHOSPHORS - A process for fabricating an LED lighting apparatus comprising a color stable Mn | 2015-05-07 |
20150123154 | Light Emitting Diode Structure - A light emitting diode structure includes a first type semiconductor layer, an illumination layer, a second type semiconductor layer, a plurality of first light extraction improvement structures and a transparent conductive layer. The illumination layer is disposed on the first type semiconductor layer. The second type semiconductor layer is disposed on the illumination layer, and the refractive index thereof is n | 2015-05-07 |
20150123155 | PHOSPHORS, SUCH AS NEW NARROW-BAND RED EMITTING PHOSPHORS FOR SOLID STATE LIGHTING - The invention provides, amongst others for application in a lighting unit, a phosphor having the formula M | 2015-05-07 |
20150123156 | Optoelectronic Semiconductor Component - An optoelectronic semiconductor component having a light source, which emits primary radiation, a housing, and electrical terminals, wherein a conversion element, which is based on a matrix and at least two phosphors, is connected upstream of the optoelectronic semiconductor component. The matrix contains metal phosphate and preferably consists of metal phosphate. The phosphors partially or completely convert primary radiation. At least one first phosphor powder is embedded and fixed in a first inorganic matrix based on a metal phosphate, and at least one second phosphor powder is embedded and fixed in a second matrix based on a metal phosphate. | 2015-05-07 |
20150123157 | VERTICAL INTEGRATION OF CMOS ELECTRONICS WITH PHOTONIC DEVICES - A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure. | 2015-05-07 |
20150123158 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a light extraction layer provided over the substrate and a light emitting structure provided over the light extraction layer. The light extraction layer has a refraction index higher than a refraction index of the substrate and lower than a refraction index of the light emitting structure. The light extraction layer has a first region contacting the substrate and a second region provided opposite to the first region. The first region has a greater cross-sectional area than a cross-sectional area of the second region. | 2015-05-07 |
20150123159 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to an embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, an second electrode, a first insulating film, a first interconnection and a second interconnection. The semiconductor layer includes a luminous portion and a non-luminous portion. The first electrode is provided on the luminous portion, and the second electrode is provided on the non-luminous portion. The first insulating film is provided on the semiconductor layer, the first electrode and the second electrode. The first interconnection having a first protrusion is provided on the first insulating film and electrically connected to the first electrode. The second interconnection having a second protrusion is provided on the first insulating film and electrically connected to the second electrode. A tip end of the first protrusion faces a tip end of a second protrusion, being apart therefrom with a minimum gap between the first interconnection and the second interconnection. | 2015-05-07 |
20150123160 | FLIP CHIP LIGHT-EMITTING DIODE PACKAGE STRUCTURE - A flip chip light-emitting diode (LED) package structure includes a circuit board, an electrical conducting layer and a plurality of flip chip light-emitting elements. The circuit board includes a bearing surface. The electrical conducting layer is formed on the bearing surface, and includes a plurality of electrical connection regions independent of each other. Each flip chip light-emitting element includes a p-type electrode and an n-type electrode. The p-type electrodes and the n-type electrodes of the flip chip light-emitting elements are electrically connected to the electrical connection regions, so that the flip chip light-emitting elements are electrically connected in series to form a package structure. During packaging of the flip chip light-emitting elements, the structure formed by the serial connection forms a circuit that can withstand a high voltage, and further reduce the current. | 2015-05-07 |
20150123161 | LED PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method is provided for manufacturing a LED package base including providing a metal core substrate having a top surface and a bottom surface and forming two first trenches in the metal core substrate. The first trenches extend from the top surface to the bottom surface, The method further includes at least partially filling in the first trenches with first dielectric material to form dielectric isolations. The dielectric isolations divide the metal core substrate into three metal core portions. Two of the metal core portions may be configured to serve as LED package electrodes. The method also includes applying a second dielectric material to cover at least a portion of the first dielectric material, and forming a conductive layer over the second dielectric material to form circuit contacts. The conductive layer includes a first conductive material. | 2015-05-07 |
20150123162 | LIGHT EMITTING DIODE AND FORMING METHOD THEREOF - A light emitting diode (LED) and a forming method thereof are provided. The LED includes a semiconductor substrate, a bonding layer formed on a surface of the semiconductor substrate, and a LED die formed on a surface of the bonding layer. The effective lighting area of the LED may be increased, heat radiation may be improved, and lighting efficiency may be enhanced. | 2015-05-07 |
20150123163 | LIGHT EMITTING DEVICE PACKAGE - Embodiments include a light emitting device package. The light emitting device package comprises a housing including a cavity; a light emitting device positioned in the cavity; a lead frame including a first section electrically connected to the light emitting device in the cavity, a second section, which penetrates the housing, extending from the first section and a third section, which is exposed to outside air, extending from the second section; and a metal layer positioned on an area defined by a distance which is distant from the housing in the second section of the lead frame. | 2015-05-07 |
20150123164 | POWER SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A power semiconductor device may include a first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed on an upper portion of the first semiconductor region; a first conductivity type third semiconductor region formed in an upper inner side of the second semiconductor region; a trench gate formed to penetrate through a portion of the first semiconductor region from the third semiconductor region; and a first conductivity type fourth semiconductor region formed below the second semiconductor region while being spaced apart from the trench gate. | 2015-05-07 |
20150123165 | HIGH-VOLTAGE INSULATED GATE TYPE POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A high-voltage insulated gate type power semiconductor device includes a low-concentration first conductivity type base layer; a plurality of trenches selectively formed with large intervals and narrow intervals provided alternately, in a front surface of the low-concentration first conductivity type base layer; a gate insulating film formed on a surface of each of the plurality of trenches; a gate electrode formed inside the gate insulating film; and a second conductivity type base layer selectively formed between the adjacent trenches sharing the narrow interval. The high-voltage insulated gate type power semiconductor device includes a high-concentration first conductivity type source layer selectively formed on a front surface of the second conductivity type base layer. | 2015-05-07 |
20150123166 | METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS - are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques. | 2015-05-07 |
20150123167 | METHOD AND GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION IN TRANSISTORS - A method of fabricating a semiconductor device. A substrate (PMOS/NMOS regions) is prepared. A high-k dielectric layer is formed over the substrate. A threshold voltage modulation layer is formed over the dielectric layer of the NMOS region. A first work function layer is formed over the threshold voltage modulation layer and the dielectric layer of the PMOS region. An oxidation suppressing layer is formed over the first work function layer of the NMOS region. A second work function layer is formed over the oxidation suppressing layer and the first work function layer of the PMOS region. A first gate stack including the dielectric layer, the first work function layer and the second work function layer is formed over the PMOS region. A second gate stack including the dielectric layer, the threshold voltage modulation layer, the first work function layer and the oxidation suppressing layer is formed over NMOS region. | 2015-05-07 |
20150123168 | MISHFET AND SCHOTTKY DEVICE INTEGRATION - A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate. | 2015-05-07 |
20150123169 | REFRACTORY METAL BARRIER IN SEMICONDUCTOR DEVICES - Gate metallization structures and methods for semiconductor devices are disclosed, wherein a refractory metal barrier is implemented to provide performance improvements. Transistor devices are disclosed having a compound semiconductor substrate and an electron-beam evaporated gate structure including a layer of tantalum nitride (TaNx), a layer of titanium (Ti) and a layer of gold (Au). | 2015-05-07 |
20150123170 | HEMT-Compatible Lateral Rectifier Structure - The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier (L-FER) device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A passivation layer is located over the electron supply layer and the layer of doped III-N semiconductor material. A gate structure is disposed over the layer of doped III-N semiconductor material and the passivation layer. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the passivation layer improves reliability of the L-FER device by mitigating current degradation due to high-temperature reverse bias (HTRB) stress. | 2015-05-07 |
20150123171 | CONDUCTIVITY IMPROVEMENTS FOR III-V SEMICONDUCTOR DEVICES - Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device. | 2015-05-07 |
20150123172 | BIG-SMALL PIXEL SCHEME FOR IMAGE SENSORS - An image sensor pixel for use in a high dynamic range image sensor includes a first photodiode, a plurality of photodiodes, a shared floating diffusion region, a first transfer gate, and a second transfer gate. The first photodiode is disposed in a semiconductor material. The first photodiode has a first light exposure area and a first doping concentration. The plurality of photodiodes is also disposed in the semiconductor material. Each photodiode in the plurality of photodiodes has the first light exposure area and the first doping concentration. The first transfer gate is coupled to transfer first image charge from the first photodiode to the shared floating diffusion region. The second transfer gate is coupled to transfer distributed image charge from each photodiode in the plurality of photodiodes to the shared floating diffusion region. | 2015-05-07 |
20150123173 | 3D STACKED IMAGE SENSOR WITH PMOS COMPONENTS - An active pixel sensor comprises a sensor die and a circuit die. The sensor die comprises a plurality of pixels, wherein each pixel includes a light sensitive element and a transfer gate, a floating diffusion region, wherein the plurality of pixels include at least one reset gate. The circuit die comprises a plurality of processing and amplification circuits associated with the reset gates of the sensor die. The sensor die is interconnected with the circuit die utilizing a plurality of inter-die interconnects each coupled to a source node of a reset gate on the sensor die and a node of a processing and amplification circuit on the circuit die. The plurality of processing and amplification circuits each comprises a source follower transistor, wherein the source follower transistor uses a PMOS. | 2015-05-07 |
20150123174 | MATRIX IMAGE SENSOR PROVIDING BIDIRECTIONAL CHARGE TRANSFER WITH ASYMMETRIC GATES - In the field of image sensors, more particularly time-delay integration linear sensors or TDI sensors, a sensor comprises rows of photodiodes alternating with rows of gates adjacent to the photodiodes. The gates are asymmetric, adjacent on one side to a photodiode and having, on the other side, narrow gate fingers extending toward another photodiode. Owing to their very narrow width, the fingers endow the transfer of charges with a directionality. Between two successive photodiodes there are two gates, the two being adjacent to the two photodiodes, the first having its narrow fingers turned toward the first photodiode, the second having its narrow fingers turned toward the second photodiode. The direction of transfer of the charges in the sensor may be chosen by neutralizing either the first gate or the second gate, the other gate receiving alternating potentials allowing the transfer of charges from one photodiode to the other. | 2015-05-07 |
20150123175 | MECHANISMS FOR SEMICONDUCTOR DEVICE STRUCTURE - Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. In addition, a method for forming the semiconductor device structure is also provided. | 2015-05-07 |
20150123176 | SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN - A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets. | 2015-05-07 |
20150123177 | Patterned Poly Silicon Structure as Top Electric Contact to MOS-Type Optical Modulators - A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate. | 2015-05-07 |
20150123178 | SOLID-STATE IMAGE SENSING DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention improves the performance of an image sensor. In a planar view, fluorine is introduced into a part overlapping with a channel region in a gate electrode GE | 2015-05-07 |
20150123179 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging device includes two-dimensionally arranged pixels, and each pixel includes a photoelectric conversion element configured to generate charges according to a light amount of incident light and accumulate the charges therein; and at least one of an amplification transistor configured to amplify a voltage corresponding to the charges accumulated in the photoelectric conversion element, a readout transistor configured to read a signal of the voltage amplified by the amplification transistor, and a reset transistor configured to reset the charges accumulated in the photoelectric conversion element, a channel region of each transistor being formed in a direction perpendicular to a substrate. | 2015-05-07 |
20150123180 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE DEVICE - Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region. | 2015-05-07 |
20150123181 | CAPACITORS POSITIONED AT THE DEVICE LEVEL IN AN INTEGRATED CIRCUIT PRODUCT AND METHODS OF MAKING SUCH CAPACITORS - One illustrative integrated circuit product disclosed herein includes a metal-1 metallization layer positioned above a semiconducting substrate, a capacitor positioned between a surface of the substrate and a bottom of the metal-1 metallization layer, wherein the capacitor includes a plurality of conductive plates that are oriented in a direction that is substantially normal relative to the surface of the substrate, and at least one region of insulating material positioned between the plurality of conductive plates. | 2015-05-07 |
20150123182 | TRANSISTOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern. | 2015-05-07 |
20150123183 | SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved. | 2015-05-07 |
20150123184 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE - A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor. | 2015-05-07 |
20150123185 | METHODS FOR ISOLATING PORTIONS OF A LOOP OF PITCH-MULTIPLIED MATERIAL AND RELATED STRUCTURES - Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other. | 2015-05-07 |
20150123186 | MEMORY CELL THAT PREVENTS CHARGE LOSS - A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer. | 2015-05-07 |
20150123187 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes: forming a first well of the first conductivity type in a substrate; forming a second well of the first conductivity type in a first region of the substrate; forming a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate; forming a fourth well, that surrounds the second well and has the second conductivity type, in the first region of the substrate; forming a fifth well of the first conductivity type above the first well in the second region of the substrate; and forming a sixth well of the second conductivity type above the first well in the second region of the substrate. | 2015-05-07 |
20150123188 | METHODS AND APPARATUSES HAVING STRINGS OF MEMORY CELLS INCLUDING A METAL SOURCE - Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material. | 2015-05-07 |
20150123189 | METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC SEMICONDUCTOR CHANNEL - Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material. | 2015-05-07 |
20150123190 | NON-VOLATILE MEMORY DEVICE INTEGRATED WITH CMOS SOI FET ON A SINGLE CHIP - A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region. | 2015-05-07 |
20150123191 | Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation - High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction. | 2015-05-07 |
20150123192 | MEMORY ARCHITECTURE OF 3D ARRAY WITH DIODE IN MEMORY STRING - A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. | 2015-05-07 |
20150123193 | SGT-INCLUDING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming an SGT in a semiconductor pillar on a semiconductor substrate and forming a wiring semiconductor layer so as to contact a side surface of an impurity region present in a center portion of the semiconductor pillar or a side surface of a gate conductor layer. A first alloy layer formed in a side surface of the wiring semiconductor layer is directly connected to the impurity region and the gate conductor layer and is connected to an output wiring metal layer through a contact hole formed on an upper surface of a second alloy layer formed in an upper surface and the side surface of the wiring semiconductor layer. | 2015-05-07 |
20150123194 | Deep Silicon Via As A Drain Sinker In Integrated Vertical DMOS Transistor - A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDS | 2015-05-07 |
20150123195 | RECESSED CHANNEL ACCESS TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF - A recessed channel access transistor device is provided. A semiconductor substrate having thereon a trench is provided. The trench extends from a main surface of the semiconductor substrate to a predetermined depth. A buried gate electrode is disposed at a lower portion of the trench. A gate oxide layer is formed between the buried gate electrode and the semiconductor substrate. A drain doping region on a first side (cell side) of the trench in the semiconductor substrate and a source doping region on a second side (digit side) of the trench are formed. The source doping region has a junction depth that is deeper than that of the drain doping region. An L-shaped channel is defined along a sidewall surface on the first side and along a bottom surface of the trench between the drain doping region and the source doping region. | 2015-05-07 |
20150123196 | DATA STORAGE DEVICE AND METHODS OF MANUFACTURING THE SAME - Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively. | 2015-05-07 |
20150123197 | LATERAL-DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided. | 2015-05-07 |
20150123198 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region. | 2015-05-07 |
20150123199 | LATERAL DIFFUSED SEMICONDUCTOR DEVICE - A lateral diffused semiconductor device is disclosed, including: a substrate; a first isolation and a second isolation comprising at least portions disposed in the substrate to define an active area; a first drift region and a second drift region disposed in the active area, wherein the first drift region is disposed in the second drift region; a gate structure on the substrate; a source region in the first drift region; a drain region in the second drift region; and a ring-shaped field plate on the substrate, wherein the ring-shaped field plate surrounds at least one of the source and the drain region. | 2015-05-07 |