19th week of 2009 patent applcation highlights part 59 |
Patent application number | Title | Published |
20090119408 | METHOD FOR MANAGING EXECUTION BY A SERVER OF AN APPLICATION PROVIDING AT LEAST ONE INTERACTIVE MULTIMEDIA SERVICE TO AT LEAST ONE TERMINAL, CORRESPONDING COMPUTER PROGRAM PRODUCT AND SERVER - A method is provided for managing execution by a server of an application providing at least one interactive multimedia service to at least one terminal connected to the server via a communication network. The method includes the following steps performed by the server: converting outputs of the application in the form of at least one first multimedia stream capable of being presented by the at least one terminal; and transmitting the at least one first multimedia stream to the at least one terminal, via a communication set up between the server and the at least one terminal. In one particular example, the method further includes the following steps performed by the server: receiving inputs of the application, which the at least one terminal transmits to the server via the communication; and converting the application inputs into commands for monitoring the application. | 2009-05-07 |
20090119409 | ORIGIN REQUEST WITH PEER FULFILLMENT - A method, apparatus and system for data transfer is disclosed. For example, settings from multiple entities arranged in a multi-tier control plane are used to set data transfer policies. The policies are use to govern data transfers such as between end users or from an origin server. | 2009-05-07 |
20090119410 | MIDDLEWARE ARCHITECTURE FOR IPTV MULTIMEDIA STREAMING - A media content distribution system for distributed multimedia streaming communicates over a network and incorporates multiple independent media stations, each having a media director for control and a number of media engines for storage, retrieval and streaming of media content. A middleware system employing a execution engine for service platform middleware and a presentation engine for terminal middleware is provided for flexible interfacing with network transport and home network elements respectively and the IPTV applications supported. | 2009-05-07 |
20090119411 | Synchronous rate adapter - Systems and methods for transporting client data received at a first rate over an interconnect at a second, higher rate, wherein the client data is combined with dummy data according to a pattern that minimizes the amount of buffer space required to store the received client data. In one embodiment, a method comprises receiving client data at the first rate, buffering the client data, retrieving the client data, combining the client data with dummy data according to the pattern, and transmitting the combined data at the second rate. The pattern comprises K blocks, of which a first number contain P w-bytes of client data, and of which the remainder contain P+1 w-bytes of client data. The remainder of the space in the blocks is stuffed with dummy data. The pattern may also include a residual slot that contains one or more bytes of client data. | 2009-05-07 |
20090119412 | Support for avoidance of unnecessary tunneling - A system can include an access router and a proxy mobile internet protocol aware client mobile internet protocol node. The access router can include a storage unit configured to store a local care-of-address. The access router can also include a sending unit configured to send the proxy mobile internet protocol aware client mobile internet protocol node the local care-of-address. The proxy mobile internet protocol aware client mobile internet protocol node can include a receiving unit configured to receive local care-of-address from an access router. The proxy mobile internet protocol aware client mobile internet protocol node can also include a processing unit configured to process the local care-of-address. | 2009-05-07 |
20090119413 | ADDRESSES ASSIGNMENT FOR ADAPTOR INTERFACES - Provided are a method and device for address assignment for adaptor interfaces. An initial configuration is maintained assigning multiple local interfaces to one initial local address. For each local interface, a remote address of a remote interface on at least one remote device to which the local interface connects is received. The initial local address is used to identify the local interfaces assigned to the initial local address in response to receiving a same remote address for each remote interface connected to the local interfaces assigned the initial local address. | 2009-05-07 |
20090119414 | Method and System Using ARP Cache Data to Enhance Accuracy of Asset Inventories - A technique for improving accuracy in an inventory containing assets associated with a network. Information pertaining to computer devices connected to a specified network is updated. Each device sends packets through at least one router in a set of routers, and each packet contains an element uniquely identifying its sending computer device. An inventory is maintained that identifies at least some of the computer devices as assets of an entity associated with the network. Data is acquired from ARP caches that are located within the routers. The acquired cache data is processed to detect all of the identifying elements that identify computer devices of the group. A database is constructed from information in the cache data that pertains to detected identifying elements. Information contained in the database is compared with information contained in the inventory to update the inventory. | 2009-05-07 |
20090119415 | SYSTEM AND METHOD FOR REPRESENTING MFS CONTROL BLOCKS IN XML FOR MFS-BASED IMS APPLICATIONS - A system and method for representing MFS control blocks in XML for MFS-based IMS applications utilizes an MFS XML adapter and an MFS XML repository to translate between XML and MFS. The repository contains XML files for DOF/MOD and XML files for DIF/MID. When an XML request is received, the XML request is transformed to a byte stream by retrieving the relevant information from the MFS XML repository. The byte stream can then be placed in an IMS message queue to await processing by an MFS-based IMS application program. A byte stream response is generated by the MFS-based IMS application and is transformed into an XML response, again, by retrieving the relevant information from the MFS XML repository. | 2009-05-07 |
20090119416 | DATA TRANSFORMATION AND EXCHANGE - A data transformation and exchange server receives an input data stream from one or more application servers and/or computing devices. The data stream includes a plurality of input records and each input record can be in a different input protocol and/or character encoding. The transformation and exchange server determines each input record in the input data stream based on one or more boundary points and determines a template from a plurality of templates based on the input record. The transformation and exchange server transforms the input record into an output record based on the template and communicates the output record via an output data stream. | 2009-05-07 |
20090119417 | FEDERATED MULTIPROTOCOL COMMUNICATION - Methods, apparatus, and business techniques are disclosed for use in distributed communication systems comprising a plurality of communication protocols. In one embodiment a first air interface is used to initiate communication between a wireless client and a remote server at least partially using a first wireless access point. The server sends the wireless client a stub of a distributed object. The stub is used to instantiate an object class. The object class defines an interface that the remote client can use to communicate with the remote server using an upper layer interface. The distributed object stub also provides an implementation of a software radio configuration for a set of lower protocol layers in a second air interface. The wireless client can thereby communicate with a second wireless access point using said second air interface protocol. Exemplary embodiments of the present invention are disclosed that focus on toll-tag and electronic-commerce related highway systems, distributed federated wireless access systems, and wide area wireless system capacity augmentation. | 2009-05-07 |
20090119418 | CONTROL DEVICE, AND CONTROLLED DEVICE - The invention provides a control device and a controlled device capable of reducing a management burden on a manufacturer by means of an easy-to-use method. A TV is a control device which controls a DVD recorder, including: a device ID acquisition unit which requests the DVD recorder to transmit a device ID, and receives the device ID from the DVD recorder; a device ID determination unit which determines whether or not the device ID is an initial value; a device ID generation unit which generates a new device ID in the case where the device ID is determined to be the initial value; a device ID update unit which requests the DVD recorder to update to the new device ID; a device ID/attribute information storing unit which stores the new device ID as the device ID of the DVD recorder; and a connected device control unit which controls the DVD recorder by using the device ID stored in the device ID/attribute information storing unit. | 2009-05-07 |
20090119419 | Semiconductor memory device with high-speed data transmission capability, system having the same, and method for operating the same - Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits. | 2009-05-07 |
20090119420 | APPARATUS AND METHOD FOR SCALEABLE EXPANDERS IN SYSTEMS MANAGEMENT - Embodiments of the present invention provide a method, system and computer program product for generating scalable addressing for expansion units. The method, system and computer program product for generate scalable addressing for an expansion unit is provided. The method, system and computer program product can include detecting a multiplexer of an expansion unit via a serial bus (e.g., an I2C bus), setting an address for the multiplexer of the first expansion unit, and upon accessing the multiplexer, switching the multiplexer to a first position to pass the serial bus to a second expansion unit to detect a multiplexer of the second expansion unit. The method can further include attempting to access the multiplexer of the second expansion unit and upon accessing the multiplexer of the second expansion unit, incrementing the address of the multiplexer of first expansion unit to set the address for the multiplexer of the second expansion unit. | 2009-05-07 |
20090119421 | APPARATUS AND METHOD FOR CONNECTIVITY IN NETWORKS CAPABLE OF NON-DISRUPTIVELY DISCONNECTING PERIPHERAL DEVICES - An apparatus and method for connectivity in networks configured for non-disruptive disconnection of one or more peripheral devices are disclosed. The apparatus includes a first logical layer associated with a first peripheral device, the first peripheral device arranged in a network configured for non-disruptive disconnection of at least one peripheral device, at least a second logical layer associated with at least a second peripheral device, the at least a second peripheral device arranged in the network configured for non-disruptive disconnection of at least one peripheral device, at least one power source associated with the first logical layer and the at least a second logical layer, and a first electrically conductive link coupled to the first logical layer, the at least a second logical layer, and the at least one power source associated with the first logical layer and the at least a second logical layer. | 2009-05-07 |
20090119422 | METHOD AND APPARATUS FOR PERFORMING MAINTENANCE OPERATIONS ON PERIPHERAL DEVICES - The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for performing maintenance operations on a first set of peripheral devices. The method initiates communication to the first set of peripheral devices using a radio frequency transmission link. A set of diagnostic routines is initiated on the first set of peripheral devices. Data associated with the diagnostic routines from the first set of peripheral devices is received. A number of maintenance updates from a plurality of maintenance updates is selected for each peripheral device in the first set of peripheral devices using the data associated with the set of diagnostic routines. Maintenance operations are performed simultaneously, over the radio frequency transmission link, for each peripheral device in the first set of peripheral devices utilizing the number of maintenance updates. | 2009-05-07 |
20090119423 | Transfer control device, LSI, and LSI package - A transfer control device is arranged between a bus and a bus interface. The transfer control device includes a bus connecting unit that is connected to plural signal lines of the bus, an interface connecting unit that is connected to plural signal lines of the bus interface, and a connection control unit that connects, when a defective signal line exists in the plural signal lines of the bus, a signal line corresponding to the defective signal line out of the plural signal lines of the bus interface and a signal line other than the defective signal line out of the plural signal lines of the bus. | 2009-05-07 |
20090119424 | METHOD FOR STORING DATA - A method for storing data is disclosed. The method is used for storing data into a program memory used for storing program codes. The program memory is divided into a first buffer storage area and a second buffer storage area. By alternate accessing of the first buffer storage area and the second buffer storage area, instantly accessible data can be stored in the program memory, such that the conventional data memory can be replaced by the program memory of the present invention and the cost of the product can be reduced. | 2009-05-07 |
20090119425 | DATA COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD FOR BUFFERING DATA - A data communication unit comprises a host processor operably coupled to a communication controller having a plurality of buffers comprising a plurality of data elements. The plurality of data elements comprise a lock data element for access by the host processor to acquire sole use of a respective buffer of the plurality of buffers and a commit data element for access by the host processor once sole use of the respective buffer has been acquired wherein use of the lock data element enables the host processor to un-commit a transmit buffer that has previously been committed for transmission by the communication controller. | 2009-05-07 |
20090119426 | Serial Data Interface System and Method Using A Selectively Accessed Tone Pattern Generator - A system and method performs speed and connection handshaking between Beta signal ports and/or Bilingual ports in a serial data interface system. A tone pattern generator (e.g., a flip-flop) can be used to generate a tone pattern signal representing approximately 49 MHz to approximately 62 MHz. A selecting system (e.g., a multiplexer, a digital multiplexer, or the like) selectively transmits either the tone pattern signal or a data input signal. These signals include a driver control signal. A serializer serializes either the tone pattern signal or the data input signal. A clock device (e.g., a clock divider) drives the tone pattern generator and the serializer. A driver receives and differentially transmits, along a twister-wire pair, either the serialized tone pattern signal or the serialized data input signal. | 2009-05-07 |
20090119427 | Radio Communication Apparatus, Communication Control Method, and Computer-Readable Program - A radio communication apparatus configured to perform radio communication according to a first radio communication protocol includes an identification information memory unit configured to store first identification information identifying a host apparatus and second identification information identifying the host apparatus based on a second radio communication protocol, the first and second identification information being associated with each other; an identification information reception unit; an identification information acquisition unit; and a connection request transmission unit. | 2009-05-07 |
20090119428 | Method and Apparatus for Indirect Interface with Enhanced Programmable Direct Port - Device, apparatus and methods for implementing a direct address mode to directly access registers by passing an indirect interface includes a display controller. A plurality of direct access registers for bypassing indirect interface is defined within the display controller. The display controller includes a bus interface having a first pin that is configured to activate the direct address mode and a second pin that configured to identify one of the direct access registers. The first pin in conjunction with the second pin provides a direct address mode through which the non-direct access registers may be directly accessed bypassing the indirect interface so that register index cycle, when accessing memory, may be avoided. | 2009-05-07 |
20090119429 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to an aspect of the invention includes a plurality of master devices which issue data transfer requests, at least one slave device which performs data transfer in accordance with the data transfer requests, and a network which arbitrates the plurality of data transfer requests respectively issued from the plurality of master devices, and informs the slave device of the arbitration result, thereby performing data transfer between the master devices and the slave device, wherein when issuing the data transfer request, the master device informs the network of a period which extends from the issuance of the data transfer request to the start of the data transfer. | 2009-05-07 |
20090119430 | SEMICONDUCTOR DEVICE - The router which relays a transfer request and a reply between master and slave components has request-control circuits provided therein. The request-control circuits judge the slave component to transfer a request from each master component to, and arbitrate the conflict between requests to one slave component. Further, for the router, a slave-component-allocation-control circuit which variably allocates the slave components to be connected to the request-control circuits to the request-control circuits is adopted. In case that a slave component in connection with one request-control circuit is subjected to no access, changing the allocation of the slave component in connection with the one request-control circuit makes possible to utilize the resource of the one request-control circuit. | 2009-05-07 |
20090119431 | Multi-purpose flight attendant panel - A flight attendant panel, in which a plurality of computer units can be coupled to a common input/output device by a circuitry. One of the computer units is designated as the master computer unit and controls the circuitry in order to specify which of the computer units should be coupled to the input/output device. The actuation of a switch makes it possible to once again return the flight attendant panel into an original state, in which the master computer unit is coupled to the input/output device by the circuitry. | 2009-05-07 |
20090119432 | Starvation Prevention Scheme for a Fixed Priority PCE-Express Arbiter with Grant Counters using Arbitration Pools - Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams. When the resource buffer for the low priority stream becomes available and a corresponding request is arbitrated in the high priority arbitration pool, a grant for the request can be immediately made since grant counts for the stream already exist. | 2009-05-07 |
20090119433 | DATA PROCESSING SYSTEM AND METHOD FOR MEMORY ARBITRATION - The present invention relates to a data processing system is provided which comprises at least one first processing unit (CPU), at least one second processing unit (PU), at least one memory module (MEM), and an interconnect. The memory module (MEM) serves to store data from said at least one first and second processing unit (CPU, PU). The interconnecting means couples the memory module (MEM) to the first and second processing units (CPU, PU). In addition, an arbitration unit (AU.) is provided for performing the arbitration to the memory module (MEM) of the first and second processing units (CPU, PU). The arbitration is performed on a time window basis. A first access time during which the second processing unit (PU) has accessed the memory module and a second access time which is still required by the second processing unit (PU) to complete its processing are monitored during a predefined time window by the arbitration unit (AU). The second access time is compared to the remaining access time in the time window and if the remaining access time is larger than the second access time, the arbitration unit (AU) allows said at least one first processing unit (CPU) to access the memory module in said time window. Otherwise, the arbitration unit (AU) restricts the access of the at least one first processing units (CPU) and allows the at least one second processing unit (PU) to access the memory module (MEM). | 2009-05-07 |
20090119434 | METHOD AND APPARATUS FOR BINDING SHADOW REGISTERS TO VECTORED INTERRUPTS - A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond to the interrupts. The exception vector considers the type of interrupt and the priority level of the interrupt when selecting the exception vector. Shadow set mapping logic is coupled to the vector generator. The mapping logic contains a number of fields that correspond to the different exception vectors that may be generated. The fields are programmable by kernel mode instructions, and contain data mapping each field to one of a number of shadow register sets. When an interrupt occurs, the vector generator generates a corresponding exception vector. In addition, the shadow set mapping logic looks at the field corresponding to the exception vector, and retrieves the data stored therein. The data is used to switch to one of the shadow register sets for use by an interrupt routine. Upon return from the interrupt routine, the previously used register set is selected. | 2009-05-07 |
20090119435 | Portable computer systems with thermal enhancements and multiple power modes of operation - A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation. | 2009-05-07 |
20090119436 | Portable computer systems with thermal enhancements and multiple power modes of operation - A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation. | 2009-05-07 |
20090119437 | Method for Data Communication of Bus Users in an Open Automation System - A method for data communication of bus users of an open automation system such that any bus user with an individual and interactive communication may be connected, provides for a communication controller (KC) made up of at least one freely-programmable communication-ALU (RPA, TPA, PEA), with several commands being encoded on a command code for the communication-ALU optimized for particular communication functions, and logic function blocks (FI, Z, V, CRC) arranged in parallel in the communication ALU (RPA, TPA), which carry out particular communication functions, the communication functions not being definitively defined but rather being formed on the basis of the freely-programmable and communication function optimized communication ALUs (RPA, TPA, PEA), wherein several commands are carried out in a system cycle and transitions between various networks can be carried out. | 2009-05-07 |
20090119438 | Data Processing Device Adaptable to Variable External Memory Size and Endianess - A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data. The data processing device (D) also comprises a configuration means (CM) coupled to the embedded processor (EP) and to the external memory interface (EMI) and arranged to deduce from at least one part of 8 bits of this N-bit data word (C), read by the external memory interface at the chosen address of the external memory (EM), the size and the Endian form of storage of the external memory, and to set the width of the external memory interface (EMI) according to the deduced external memory size and the data processing mode of the embedded processor (EP) according to the deduced Endian form of storage. | 2009-05-07 |
20090119439 | STRUCTURE COMPATIBLE WITH I2C BUS AND SYSTEM MANAGEMENT BUS AND TIMING BUFFERING APPARATUS THEREOF - A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the SM bus interface. The timing buffering apparatus provides a time delay when the first device sends data to the second device so as to meet the requirement of the second device to data holding time. | 2009-05-07 |
20090119440 | SELF-CONFIGURING BUS FOR CONNECTING ELECTRONIC DEVICES - A design structure for an apparatus for connecting electronic devices having a flexible cable bus housing containing a plurality of same or different communication and power channels extending along a length thereof and a plurality of bus ports at different locations along the bus housing length. Each bus port is capable of being operatively connected to one of the communication or power channels. There is further included a plurality of device connectors adapted to connect to a bus port at one end thereof and to a discrete device at another end thereof. Each connector at the device end has a different plug conforming to one of the communication or power channels. There is preferably further included a switch for connecting each bus port to the communication or power channel conforming to the device end plug when a device connector is connected to the bus port on the bus housing. | 2009-05-07 |
20090119441 | Heterogeneous Parallel Bus Switch - A parallel bus switch has an input stage configured to convert a bus signal from a first bus having a first configuration to a second configuration, an internal standard bus configured to receive the bus signal in the second configuration and transport the bus signal to an output stage. The output stage is configured to convert the bus signal from the second configuration to a third configuration used by a data recipient and transmit the bus signal to a second bus corresponding to the data recipient. | 2009-05-07 |
20090119442 | Managing Write-to-Read Turnarounds in an Early Read After Write Memory System - Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank. | 2009-05-07 |
20090119443 | METHODS FOR PROGRAM DIRECTED MEMORY ACCESS PATTERNS - Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller. | 2009-05-07 |
20090119444 | MULTIPLE WRITE CYCLE MEMORY USING REDUNDANT ADDRESSING - The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit is useful for both providing upgrade capability to electronic computational systems and data robustness to logic storage systems. Less configurable non-volatile memory (NVM) block | 2009-05-07 |
20090119445 | COMPUTER MEMORY ACCESSIBLE IN EITHER POWER STATE OF THE COMPUTER - A system on a computer for providing access to data stored on the computer in either power state is provided. The system can include a memory module and an external data interface connector. The system can further include a data interface controller for managing a data interface to the memory module and a data interface to the external data interface connector. The system can further include a multiplexer conductively connecting the data interface controller with the memory module when the computer is powered on, the multiplexer conductively disconnecting the data interface controller from the memory module when the computer is powered off and the multiplexer conductively connecting the external data interface connector with the memory module when the computer is powered on. | 2009-05-07 |
20090119446 | DIVIDED BITLINE FLASH MEMORY ARRAY WITH LOCAL SENSE AND SIGNAL TRANSMISSION - A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment and the data cache. A read operation of selected bitlines of a selected memory segment is performed by a segment data handler coupled to the selected memory segment locally and the read data is transmitted to the data cache. A segment data handler is configured to get read data from the selected bitlines by first pre-charging the bitlines and sensing the bitlines. Further, the read data is transmitted to the data cache through all of the segment data handlers in a sequential manner, if present between the selected memory segment and the data cache. | 2009-05-07 |
20090119447 | CONTROLLED BIT LINE DISCHARGE FOR CHANNEL ERASES IN NONVOLATILE MEMORY - Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring. | 2009-05-07 |
20090119448 | Memory Apparatus, and Method of Averagely Using Blocks of a Flash Memory - A flash memory controller for averagely using blocks of a flash memory and the method thereof are provided. The flash memory controller is configured to process wear-leveling by allocating frequently updated data in less-erased blocks, and, allocating less-updated data in frequently erased blocks to achieve dynamic uniformity of times of erasion of blocks. | 2009-05-07 |
20090119449 | Apparatus and method for use of redundant array of independent disks on a muticore central processing unit - The invention is based on running the entire RAID stack on a dedicated core of one of the cores of the multi-core CPU. This makes it possible to eliminate the use of a conventional separate RAID controller and replace its function with a special flash memory chip that contains a program, which isolates the dedicated cores from the rest of the operating system and converts it into a powerful RAID engine. A part of the memory of the flash memory chip can also be used for storing data at power failure. This makes it possible to avoid having the battery backup module. The invention of the method of RAID on multi-core CPU may have many useful applications on an enterprise level, e.g., for increased accessibility and preserving critical data. | 2009-05-07 |
20090119450 | MEMORY DEVICE, MEMORY MANAGEMENT METHOD, AND PROGRAM - A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages access to the non-volatile memory. The control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in translation units (TUs) each being an integer fraction of a size of the block and an integer multiple of a page size. | 2009-05-07 |
20090119451 | Redriven/Retimed Registered Dual Inline Memory Module - A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips. | 2009-05-07 |
20090119452 | METHOD AND SYSTEM FOR A SHARABLE STORAGE DEVICE - Systems and methods for sharable tape devices are presented. More particularly, embodiments of a virtual tape server may automatically create a virtual tape device for an identified host such that hosts may interact with corresponding virtual tape devices. Thus, rather than having multiple hosts share a limited number of virtual tape devices, each host may interact with a virtual tape device corresponding only to that host (or a limited number of hosts), allowing substantially simultaneous interactions to take place between multiple hosts and multiple virtual tape devices and substantially alleviating the need of an application on a particular host to take into account other hosts or other applications when scheduling operations. | 2009-05-07 |
20090119453 | DATA READING METHOD - According to an aspect of an embodiment, a method for controlling a controller connected to a plurality of storage units which are arranged in a redundant configuration, the controller reading data stored in the plurality of storage units in accordance with requests received from a host computer, the method comprising the steps of: receiving requests to read data successively from one of the storage units from the host computer; reading a part of requested target data from said one of the storage units; reading associated data and parity data stored in other storage units corresponding to other part of requested target data; generating other part of requested target data on the basis of the associated data and the parity data read out from the other storage units; and transmitting the part of the target data and the other part of the target data to the host computer. | 2009-05-07 |
20090119454 | Method and Apparatus for Video Motion Process Optimization Using a Hierarchical Cache - There are provided method and apparatus for video motion process optimization using a hierarchical cache. A storage method for a video motion process includes configuring a hierarchical cache to have one or more levels, each of the levels of the hierarchical cache corresponding to a respective one of a plurality of levels of a calculation hierarchy associated with calculating sample values for the video motion process. The method also includes storing a particular value for a sample relating to the video motion process in a corresponding level of the hierarchical cache based on which of the plurality of levels of the calculation hierarchy the particular value corresponds to, when the particular value is non-existent in the hierarchical cache. | 2009-05-07 |
20090119455 | METHOD FOR CACHING CONTENT DATA PACKAGES IN CACHING NODES - A method for caching content data packages in caching nodes | 2009-05-07 |
20090119456 | PROCESSOR AND MEMORY CONTROL METHOD - A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports. | 2009-05-07 |
20090119457 | MULTITHREADED CLUSTERED MICROARCHITECTURE WITH DYNAMIC BACK-END ASSIGNMENT - A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units. | 2009-05-07 |
20090119458 | OPPORTUNISTIC BLOCK TRANSMISSION WITH TIME CONSTRAINTS - A technique for determining a data window size allows a set of predicted blocks to be transmitted along with requested blocks. A stream enabled application executing in a virtual execution environment may use the blocks when needed. | 2009-05-07 |
20090119459 | LATE LOCK ACQUIRE MECHANISM FOR HARDWARE LOCK ELISION (HLE) - A method and apparatus for a late lock acquire mechanism is herein described. In response to detecting a late-lock acquire event, such as expiration of a timer, a full cachet set, and an irrevocable event, a late-lock acquire may be initiated. Consecutive critical sections are stalled until a late-lock acquire is completed utilizing fields of access buffer entries associated with consecutive critical section operations. | 2009-05-07 |
20090119460 | Storing Portions of a Data Transfer Descriptor in Cached and Uncached Address Space - Methods, apparatuses, and software for storing a first portion of a data transfer descriptor in cached address space, and storing a second portion of the data transfer descriptor in uncached address space. Also, methods, apparatuses, and software for reading at least a portion of a data transfer descriptor from cached address space, initiating a memory transfer based on the data transfer descriptor, and storing a parameter indicating a status of the data transfer descriptor in uncached address space. | 2009-05-07 |
20090119461 | MAINTAINING CACHE COHERENCE USING LOAD-MARK METADATA - Embodiments of the present invention provide a system that maintains load-marks on cache lines. The system includes: (1) a cache which accommodates a set of cache lines, wherein each cache line includes metadata for load-marking the cache line, and (2) a local cache controller for the cache. Upon determining that a remote cache controller has made a request for a cache line that would cause the local cache controller to invalidate a copy of the cache line in the cache, the local cache controller determines if there is a load-mark in the metadata for the copy of the cache line. If not, the local cache controller invalidates the copy of the cache line. Otherwise, the local cache controller signals a denial of the invalidation of the cache line and retains the copy of the cache line and the load-mark in the metadata for the copy of the cache line. | 2009-05-07 |
20090119462 | REPEATED CONFLICT ACKNOWLEDGEMENTS IN A CACHE COHERENCY PROTOCOL - In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict resolution, which may reduce system inefficiencies. | 2009-05-07 |
20090119463 | SYSTEM AND ARTICLE OF MANUFACTURE FOR DUMPING DATA IN PROCESSING SYSTEMS TO A SHARED STORAGE - Provided are a system and article of manufacture for dumping data in processing systems to a shared storage. A plurality of processing systems receive a signal indicating an event. Each of the processing systems write data used by the processing system to a shared storage device in response to receiving the signal, wherein each processing system writes the data to the shared storage device. | 2009-05-07 |
20090119464 | MEMORY CHAIN - A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed. | 2009-05-07 |
20090119465 | Dynamic Loading of Virtual Volume Data in a Virtual Tape Server - Disclosed are a system, a method, and article of manufacture to provide for obtaining data storage device specific information from a data storage device using standard read/write commands. This method uses a host application to write a unique sequence of records to a logical volume of the data storage device. The data storage device detects the unique sequence of records for the logical volume and writes device specific information to the logical volume allowing the host application the ability to read the data storage device specific information using a read command for the logical volume. | 2009-05-07 |
20090119466 | SYSTEMS FOR PROVIDING PERFORMANCE MONITORING IN A MEMORY SYSTEM - Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation. | 2009-05-07 |
20090119467 | STORAGE SYSTEM AND STORAGE SUBSYSTEM - In the storage system, a storage apparatus includes a disk device for storing write data from a host computer as a primary volume and copied data of write data as a secondary volume, and a disk controller for collecting and managing status information of a plurality of copy pairs from the disk device with a primary volume and a secondary volume as a single copy pair. The disk controller monitors the status information of the plurality of copy pairs according to the status of failure, and, upon receiving a status notification command, transfers the detailed information concerning a copy pair as the status information of the copy pair subject to a failure, and flag information showing the overall status of all other copy pairs as status information of such other copy pairs. | 2009-05-07 |
20090119468 | SYSTEMS, METHODS, AND APPARATUSES FOR ERASING MEMORY ON WIRELESS DEVICES - A wireless device having a memory is provided. The memory or a protected portion of the memory is subject to a hard erasure of the memory vs. a soft erasure of the memory if a plurality of sensors indicate a threat to the device exists. The threat may be detected by a plurality of sensors, such as, a timer, a connectivity sensor, a location sensor or geo-fence, a breech sensor, an authentication procedure or the like. | 2009-05-07 |
20090119469 | Procedure for Time-Limited Storage of Data on Storage Media - There is described a procedure for temporally limiting the storage of data on storage media, in which the data are provided with an expiry date when being stored on a storage medium. When access is made to these data by a read/write device, the expiry date is compared with a current date. When the expiry date is reached or exceeded, a pre-specified action is initiated—for example the deletion of the data from the storage medium or access being made to the data only by authorization. Based upon the procedure it is possible, on the one hand, to easily render sensitive information such as personal data unusable upon expiration of a storage period, if for example the expiry date is set to coincide with the date when the storage period elapses. On the other hand, copyright and marketing rights for digital data can thereby be easily protected without the additional use of licensing servers of the installation of executable programs. | 2009-05-07 |
20090119470 | Probabilistic Method for Performing Memory Prefetching - A method for preforming memory prefetching is disclosed. A stream length histogram (SLH) is initially generated based on a stream of Read and Write requests intended for a system memory. A determination is then made whether or not to issue a prefetch command after a Read request based on information within the generated SLH. In a determination that a prefetch command should be issued, prefetch command to be sent to the system memory is issued along with other commands. | 2009-05-07 |
20090119471 | Priority-Based Memory Prefetcher - A method for preforming memory prefetching and scheduling prefetch commands inside the memory controller is disclosed. A set of prefetch commands is generated based on a stream of Read requests intended for a system memory, and the prefetch commands are stored in a low priority queue (LPQ). A set of regular commands is generated based on a stream of Read and Write requests intended for the system memory, and the regular commands are stored in a centralized arbiter queue. One of the prefetch commands is issued from the LPQ depending on the status of the other queues in the memory controller. | 2009-05-07 |
20090119472 | CONTROL CIRCUIT IN A MEMORY CHIP - Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a write control circuit for executing write commands, wherein the write control circuit is designed to start executing a write command when a write signal is applied to the write signal connection during an edge of the system clock signal. | 2009-05-07 |
20090119473 | STORAGE SYSTEM - When a computer | 2009-05-07 |
20090119474 | PARTITION REDISPATCHING USING PAGE TRACKING - Illustrated embodiments provide a computer implemented method and data processing system for redispatching a partition by tracking a set of memory pages, belonging to the dispatched partition. In one illustrative embodiment the computer implemented method comprises finding an effective page address to real page address mapping for a page address miss to create a found real page address and page size combination, responsive to determining the page address miss in a page addressing buffer, and saving the found real page address and page size combination as an entry in set of entries in an array. Further in the computer implemented method, creating a preserved array from the array, responsive to determining the dispatched partition to be an undispatched partition. The computer implemented method further, analyzing each entry of the preserved array for a compressed page, responsive to determining the undispatched partition is now redispatched, and invoking a partition management firmware function to decompress the compressed page, prior to the partition being redispatched, responsive to determining a compressed page. | 2009-05-07 |
20090119475 | TIME BASED PRIORITY MODULUS FOR SECURITY CHALLENGES - Systems, methods, and computer readable media are disclosed for making dictionary based attacks difficult and/or time consuming for attackers. In one example embodiment, this can be accomplished by equipping a security service with software and/or circuitry operable to select security questions from different partitions of a question table. | 2009-05-07 |
20090119476 | DATA MIGRATION - Data is extracted from at least one data source. The data is translated according to a metadata model and is stored in a staging data store. A migration management user interface is provided that includes a mechanism for indicating at least some of the data to be included in a migration event. The migration event is initiated based at least in part on the input received via the user interface. The at least some of the data is migrated from the staging data store to a target data store according to a hierarchy of controls. | 2009-05-07 |
20090119477 | Configurable Translation Lookaside Buffer - The disclosure includes a method and system of configuring a translation lookaside buffer (TLB). In an embodiment, the TLB includes a first portion and a second portion. The first portion or the second portion may be selectively disabled in response to a value of a TLB configuration indicator. | 2009-05-07 |
20090119478 | Memory Controller and Method for Multi-Path Address Translation in Non-Uniform Memory Configurations - In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected. | 2009-05-07 |
20090119479 | INTEGRATED CIRCUIT ARRANGEMENT FOR CARRYING OUT BLOCK AND LINE BASED PROCESSING OF IMAGE DATA - An integrated circuit arrangement has a processor array ( | 2009-05-07 |
20090119480 | Method, System and Program for Developing and Scheduling Adaptive Integrated Circuitry and Corresponding Control or Configuration Information - A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit. The compiler generates the configuration information, from the scheduled algorithm and the selected adaptive computing circuit version, for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiments, multiple versions of configuration information may be generated, for different circuit versions, different feature sets, different operating conditions, and different operating modes. | 2009-05-07 |
20090119481 | Computer memory architecture for hybrid serial and parallel computing systems - In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties. For example, towards switching between the serial mode and the parallel mode, the serial processor is configured to send a signal to start pre-fetching of data from the shared memory. | 2009-05-07 |
20090119482 | Image forming device, image formation controlling method, and image formation controlling program - An image forming device includes a plurality of input units, a plurality of processing units, and a plurality of output units which are arranged to perform image-data processing. The image forming device includes a processing operation executing unit configured to instruct a processing operation of each of a predetermined input unit, a predetermined processing unit, and a predetermined output unit. A controlled unit reporting unit is configured in the processing operation executing unit to notify a controlled unit of processing to be performed, to each of the predetermined input unit, the predetermined processing unit, and the predetermined output unit. | 2009-05-07 |
20090119483 | SYSTEMS, METHODS, AND COMPUTER READABLE MEDIA FOR PREEMPTION IN ASYNCHRONOUS SYSTEMS USING ANTI-TOKENS - Systems, methods, and computer program products for preemption in asynchronous systems using anti-tokens are disclosed. According to one aspect, configurable system for constructing asynchronous application specific integrated data pipeline circuits with preemption includes a plurality of modular circuit stages that are connectable with each other and with other circuit elements to form multi-stage asynchronous application specific integrated data pipeline circuits for asynchronously sending data and tokens in a forward direction through the pipeline and for asynchronously sending anti-tokens in a backward direction through the pipeline. Each stage is configured to perform a handshaking protocol with other pipeline stages, the protocol including receiving either a token from the previous stage or an anti-token from the next stage, and in response, sending both a token forward to the next stage and an anti-token backward to the previous stage. | 2009-05-07 |
20090119484 | Method and Apparatus for Implementing Digital Logic Circuitry - A method of generating digital control parameters for implementing digital logic circuitry comprising functional nodes with at least one input or at least one output and connections indicating interconnections between said functional nodes, wherein said digital logic circuitry comprises a first path streamed by successive tokens, and a second path streamed by said tokens is disclosed. The method comprises determining a necessary relative throughput for data flow to said paths; assigning buffers to one of said paths to balance throughput of said paths; removing assigned buffers until said necessary relative throughput is obtained with minimized number of buffers; and generating digital control parameters for implementing said digital logic circuitry comprising said minimized number of buffers. An apparatus, a computer implemented digital logic circuitry, a Data Flow Machine, methods and computer program products are also disclosed. | 2009-05-07 |
20090119485 | Predecode Repair Cache For Instructions That Cross An Instruction Cache Line - A predecode repair cache is described in a processor capable of fetching and executing variable length instructions having instructions of at least two lengths which may be mixed in a program. An instruction cache is operable to store in an instruction cache line instructions having at least a first length and a second length, the second length longer than the first length. A predecoder is operable to predecode instructions fetched from the instruction cache that have invalid predecode information to form repaired predecode information. A predecode repair cache is operable to store the repaired predecode information associated with instructions of the second length that span across two cache lines in the instruction cache. Methods for filling the predecode repair cache and for executing an instruction that spans across two cache lines are also described. | 2009-05-07 |
20090119486 | Method and a System for Accelerating Procedure Return Sequences - A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a return address from a software stack. The method further identifies a branch instruction operable to branch to the return address. The method retrieves the return address from the link stack, in response to both the instruction and the branch instruction being identified and fetches instructions using the return address. | 2009-05-07 |
20090119487 | ARITHMETIC PROCESSING APPARATUS FOR EXECUTING INSTRUCTION CODE FETCHED FROM INSTRUCTION CACHE MEMORY - An arithmetic processing apparatus includes a cache block which stores a plurality of instruction codes from a main memory, a central processing unit which fetch-accesses the cache block and sequentially loads and executes the plurality of instruction codes, and a repeat buffer which stores an instruction code group corresponding to a buffer size, the instruction code group ranging from a head instruction code to a terminal instruction code among the head instruction code to an end instruction code of a repeat block repeatedly executed in the processing program, in the plurality of instruction codes stored in the cache block. The arithmetic processing apparatus further includes an instruction cache control unit which performs control so that the instruction code group stored in the repeat buffer is selected and supplied to the central processing unit when the repeat block is repeatedly executed. | 2009-05-07 |
20090119488 | Prefetch Unit - In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache. | 2009-05-07 |
20090119489 | Methods and Apparatus for Transforming, Loading, and Executing Super-Set Instructions - Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form of an original instruction that was stored in the program memory. The transformation is from an encoded assembly level format to a binary machine level format. In one technique, the transformation mechanism is invoked by a transform and load instruction that causes an instruction retrieved from program memory to be transformed into a new language format and then loaded into a transformed instruction memory. The format of the transformed instruction may be optimized to the implementation requirements, such as improving critical path timing. The transformation of instructions may extend to other needs beyond timing path improvement, for example, requiring super-set instructions for increased functionality and improvements to instruction level parallelism. Techniques for transforming, loading, and executing super-set instructions are described. | 2009-05-07 |
20090119490 | PROCESSOR AND INSTRUCTION SCHEDULING METHOD - An instruction scheduling method and a processor using an instruction scheduling method are provided. The instruction scheduling method includes selecting a first instruction that has a highest priority from a plurality of instructions, and allocating the selected first instruction and a first time slot to one of the functional units, allocating a second instruction and a second time slot to one of the functional units, wherein the second instruction is dependent on the first instruction. | 2009-05-07 |
20090119491 | DATA PROCESSING DEVICE - A data processing device comprises a state manager for determining a logic number of configurational information to be used in a next state, the logic number representing information on a mutual relationship between items of configurational information included in an object code, based on a present operational state, a group of candidates for a state to transit to next, and an event signal issued from arithmetic units, a configuration number converter for outputting a real number corresponding to the logic number determined by the state manager, the configuration number converter having conversion information for converting the logic number into a real number representing a location where the corresponding configurational information is actually stored, and a configurational information storage for storing the configurational information and indicating configurational information corresponding to the real number output from the configuration number converter, to the arithmetic units and an interconnector. | 2009-05-07 |
20090119492 | Data Processing Apparatus and Method for Handling Procedure Call Instructions - A data processing apparatus and method are provided for handling procedure call instructions. The data processing apparatus has processing logic for performing data processing operations specified by program instructions fetched from a sequence of addresses, at least one of the program instructions being a procedure call instruction specifying a branch operation to be performed. Further, a control value is stored within control storage, and the processing logic is operable in response to a control value modifying instruction to modify that control value. If the control value is clear, the processing logic is operable in response to the procedure call instruction to generate a return address value in addition to performing the branch operation, whereas if the control value is set, the processing logic is operable in response to the procedure call instruction to suppress generation of the return address value and to cause the control value to be clear in addition to performing the branch operation. This provides significant flexibility in how procedure call instructions are used within the data processing apparatus. | 2009-05-07 |
20090119493 | Using Branch Instruction Counts to Facilitate Replay of Virtual Machine Instruction Execution - A method and computer program product for logging non-deterministic events of a virtual machine executing a sequence guest instructions, the method including tracking an execution point in the sequence of executing guest instructions, the tracking of the execution point including determining a branch count of executed branch instructions; and detecting an occurrence of a non-deterministic event directed to the virtual machine during execution of the sequence of guest instructions, and recording information which includes an identifier of a current execution point, wherein the identifier includes the branch count. | 2009-05-07 |
20090119494 | DESIGN STRUCTURE FOR PREDICTIVE DECODING - A design structure embodied in a machine readable medium used in a design process includes an apparatus for predictive decoding, the apparatus including register logic for fetching an instruction; predictor logic containing predictor information including prior instruction execution characteristics; logic for obtaining predictor information for the fetched instruction from the predictor; and decode logic for generating a selected one of a plurality of decode operation streams corresponding to the fetched instruction, wherein the decode operation stream is selected based on the predictor information. | 2009-05-07 |
20090119495 | Architectural Enhancements to CPU Microde Load Mechanism for Information Handling Systems - A method for loading microcode to a plurality of cores within a processor. The method includes loading the microcode to a first core of the plurality of cores within the processor system and generating a broadcast inter process interrupt (IPI) message via the first core. The IPI message causes other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core. The synchronizing loads microcode to the plurality of cores without requiring independent loads of microcode to each core. | 2009-05-07 |
20090119496 | Method and apparatus to support booting despite deficient resources - A method and related apparatuses support booting despite deficient system resources. In one embodiment, a processing system includes two or more devices in a peripheral connect interface (PCI) subsystem, as well as instructions encoded in a machine accessible medium. The instructions, when executed during a process of booting the processing system, may determine whether sufficient resources are available for the devices. The instructions may also retrieve boot information from an extended firmware interface (EFI) environment of the processing system, and may automatically identify a device as boot-critical, based on that boot information. The instructions may also identify a device to be rejected, and may automatically allocate resources for the boot-critical device but not for the rejected device, before the processing system boots the OS, if sufficient resources for the devices are not available. Other embodiments are described and claimed. | 2009-05-07 |
20090119497 | System and Method for Managing Booting of an Information Handling System - Systems and methods for managing booting of an information handling system are disclosed. A method for managing the booting of an information handling system may include receiving user input for booting an information handling system to a first partition or a second partition. The user input may be used to determine whether the received user input is for booting to the first partition or to the second partition. In response to determining that the received user input is for booting to the second partition, a determination may be made whether the information handling system is authorized to boot to the second partition. In response to determining that the information handling system is authorized to boot to the second partition, the information handling system may be booted to the second partition. In response to determining that the information handling system is not authorized to boot to the second partition, the information handling system may be booted to the first partition. | 2009-05-07 |
20090119498 | HOT-PLUGGING A MEMORY DEVICE - An extensible firmware interface (EFI) framework is to enable hot-plugging and hot-removal of memory devices. The security phase of the EFI may enable a cache to operate as RAM (CAR mode) to support execution of pre-EFI (PEI) tasks. In one embodiment, the PEI phase may move the memory reference code (MRC) as a driver to the driver execution phase and hand-over the CAR information to the driver execution environment (DXE). The MRC driver may be registered as a run-time API, which may be called by the operating system to receive a dynamically created memory map. In other embodiment, the PEI phase executes the MRC and may hand-over the memory information and a memory pointer to the MRC to the DXE. The OS may call the DMD driver provisioned in the DXE, which in turn may call the MRC provisioned in the PEI to dynamically create a memory map. | 2009-05-07 |
20090119499 | METHOD AND MICRO-SYSTEM FOR UPDATING CONFIGURATIONS OF TARGET SYSTEM IN COMPUTER - A technique for updating configurations of a target system in a computer. The method comprises booting, based on Preboot Execution Environment technology, a micro-system for updating configurations of a target system before booting the target system, the micro-system performing the steps of: (a) acquiring target configuration packages via a network from a server; (b) extracting target configuration data from said target configuration packages; and (c) updating the configurations of said target system by using said target configuration data, wherein said micro-system is independent of said target system. | 2009-05-07 |
20090119500 | Managing software configuration using mapping and repeatable processes - The embodiments described herein generally relate to a method and system of injecting automated repeatable processes, or workflows, into software configuration management sequences. The benefits of such a system include the ability to delegate configurability change abilities to an IT administrator while still maintaining efficiency and management control over such changes. A request made by a system administrator to process configuration data may be subject to multiple phases of processing, such as, authentication, authorization, and action. A declarative mapping associates workflows, or meaningful repeatable processes, with the configuration process request criteria and processing phase. The mapping may be created by, or at the direction of, management through the application of the processing concept in API or UI. Upon a triggering event, e.g., receiving a configuration processing request, a stored mapping based on the attributes of the principal and request type may be consulted to determine the workflows which may then execute. | 2009-05-07 |
20090119501 | Method, Computer System and Computer Program Product - A method for maintaining a computer system on the basis of an access profile and a change profile is disclosed. The computer system includes at least one workstation computer and a maintenance computer. The invention further relates to a method for providing an access profile and a method for assessing a software correction. | 2009-05-07 |
20090119502 | Apparatus and Method for Securing Data on a Portable Storage Device - A portable storage device including a microprocessor and a secure user data area, the microprocessor operable to perform on-the-fly encryption/decryption of secure data stored on the storage device under a user password, the microprocessor also operable to exclude access to the secure user data area unless the user password is provided. | 2009-05-07 |
20090119503 | SECURE PROGRAMMABLE HARDWARE COMPONENT - A cryptographic device may include a programmable hardware component, such as a Field Programmable Gate Array for example, and a processor. The programmable hardware component may encrypt and decrypt data. The programmable hardware component may be securely configured via cryptographically signed and encrypted configuration package. The configuration package may contain a hardware image and executable code. The processor may load the new hardware image onto the programmable hardware device and may execute the executable code to test an operation of the programmable hardware component and the new hardware image. The processor and the programmable hardware component may be physically and/or operationally independent of one another; thus, a security compromise associated with one may not affect the other. Once the programmable hardware component and the hardware image have been tested according to the executable code, the cryptographic device may be ready to encrypt and decrypt user data. | 2009-05-07 |
20090119504 | INTERCEPTING AND SPLIT-TERMINATING AUTHENTICATED COMMUNICATION CONNECTIONS - Systems and methods are provided for enabling optimization of communications within a networked computing environment requiring secure, authenticated client-server communication connections. Optimization is performed by a pair of intermediary network devices installed in a path of communications between the client and the server. A secure, authenticated communication connection between the client and server is split-terminated at a pair of intermediary network devices by intercepting a request from the client for a client-server connection, authenticating the client at the intermediaries, establishing a first secure, authenticated connection to the client, authenticating the client or an intermediary to the server, and establishing a second secure, authenticate connection to the server. Depending on the operative authentication protocol (e.g., NTLM, Kerberos), an intermediary may interface with a domain controller, key distribution center or other entity. | 2009-05-07 |
20090119505 | Transaction method and verification method - In a method for performing an electronic transaction a first transaction part generates a digital signature and an encrypted digital signature. The second transaction party receives both signatures. The second party is enabled to verify the digital signature, but cannot verify or (re)generate the encrypted digital signature. A trusted third party is enabled to verify the encrypted digital signature if the digital signature is also provided, since the trusted third party cannot (re)generate the digital signature. Thus, no other party than the first transaction party can (re)generate both the digital signature and the encrypted digital signature. Therefore, no other party presenting himself as the first transaction party can be verified as being the first transaction party. | 2009-05-07 |
20090119506 | Method and Apparatus for Secure Assertion of Resource Identifier Aliases - A method and apparatus for secure assertion of a user identifier alias. The method comprises receiving at an application server from a first device a first user identifier, a first device identifier and a first authentication key associated with the first device; receiving at the application server from the first device a second user identifier, the first device identifier and a second authentication key associated with the first device; comparing the first authentication key to the second authentication key; and storing the second user identifier at the application server as an alias of the first user identifier if the first authentication key matches the second authentication key. | 2009-05-07 |
20090119507 | Reference Monitor for Enforcing Information Flow Policies - A reference monitor that authorizes information flows between elements of a data processing system is provided. The elements of the data processing system are associated with security data structures in a reference monitor. An information flow request is received from a first element to authorize an information flow from the first element to a second element. A first security data structure associated with the first element and a second security data structure associated with the second element are retrieved. At least one set theory operation is then performed on the first security data structure and the second security data structure to determine if the information flow from the first element to the second element is to be authorized. The security data structures may be labelsets having one or more labels identifying security policies to be applied to information flows involving the associated element. | 2009-05-07 |