19th week of 2009 patent applcation highlights part 42 |
Patent application number | Title | Published |
20090117693 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a semiconductor device having a raised source and drain structure, in forming a raised region by etching, etching of an island-like semiconductor film which is an active layer is inhibited. In a method for manufacturing a semiconductor device, an insulating film is formed by oxidizing or nitriding the surface of an island-like semiconductor film, a semiconductor film is formed on a region which is a part of the insulating film, a gate electrode is formed over the insulating film, an impurity element imparting one conductivity type is added to the island-like semiconductor film and the semiconductor film using the gate electrode as a mask, the impurity element is activated by heating the island-like semiconductor film and the semiconductor film, and the part of the insulating film between the island-like semiconductor film and the semiconductor film disappears by heating the island-like semiconductor film and the semiconductor film. | 2009-05-07 |
20090117694 | NANOWIRE BASED NON-VOLATILE FLOATING-GATE MEMORY - A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation. | 2009-05-07 |
20090117695 | BiCMOS Performance Enhancement by Mechanical Uniaxial Strain and Methods of Manufacture - A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT. | 2009-05-07 |
20090117696 | Fully logic process compatible non-volatile memory cell with a high coupling ratio and process of making the same - A fully logic process compatible non-volatile memory cell has a well on a substrate, a pair of source and drain outside the well, a channel between the source and drain, a control gate in the well, and a floating gate having a first portion above the channel, and a second portion above the well. The control gate includes two regions having opposite conductivity types and a third region between the two regions and under the second portion of the floating gate, and thus eliminates the parasitic depletion capacitor in the coupling path of the cell, thereby improving the coupling ratio. | 2009-05-07 |
20090117697 | Nonvolatile memory device including nano dot and method of fabricating the same - A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current. | 2009-05-07 |
20090117698 | EEPROM and Method of Manufacturing the Same - An EEPROM includes a substrate, a first semiconductor layer and a second semiconductor layer formed on the substrate. The first semiconductor layer is isolated from the second semiconductor layer by a trench. A first source and a first drain are located at two opposing sides of the first semiconductor layer. A first dielectric layer is formed on the first semiconductor layer, and a first floating gate is formed on the first dielectric layer. A second source and a second drain are located at two opposing sides of the second semiconductor layer. A second dielectric layer is formed on the second semiconductor layer, and a second floating gate is formed on the second dielectric layer. The first floating gate and the second floating gate are electrically connected. | 2009-05-07 |
20090117699 | METHOD FOR PREPARING A RECESSED TRANSISTOR STRUCTURE - A method for preparing a recessed transistor structure comprises the steps of performing an implanting process to form a doped layer in a substrate, forming a plurality of gate-isolation blocks on the substrate, forming a plurality of first spacers on sidewalls of the gate-isolation blocks, removing a portion of the substrate not covered by the first spacers and the gate-isolation blocks to form a plurality of depressions in the substrate between the first spacers, forming a gate oxide layer on inner sidewalls of the depressions, and forming a gate structure on the gate oxide layer to complete the recessed transistor structure. | 2009-05-07 |
20090117700 | Method for Manufacturing a Trench Power Transistor - A method for manufacturing a trench power transistor includes providing a substrate, forming an epitaxy layer on the substrate, performing a dry etching process on the epitaxy layer for generating a first trench, forming a gate oxide layer in the first trench and depositing poly-Si on the gate oxide layer in the first trench, performing a boron implant process on regions outside the first trench and inside the epitaxy layer, performing an arsenic implant process on regions beside the first trench and inside the epitaxy layer, depositing a first dielectric material on the surface of the epitaxy layer, performing a dry etching process on the epitaxy layer for generating a second trench, depositing a conductive material in the second trench for forming a p-well junction on sidewalls of the second trench, and performing a wet immersion process for forming a contact hole, and depositing frontside and backside metal. | 2009-05-07 |
20090117701 | METHOD FOR MANUFACTURING A MOS TRANSISTOR - A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility. | 2009-05-07 |
20090117702 | Method of Forming an Inductor on a Semiconductor Wafer - A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. An insulating layer is formed over the passivation layer. The insulating layer is removed over the first contact pad, but not from the second contact pad. A metal layer is formed over the first contact pad. The metal layer is coiled on the surface of the substrate to produce inductive properties. The formation of the metal layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the insulating layer. The insulating layer is removed from the second contact pad after forming the metal layer over the first contact pad. An external connection is formed on the second contact pad. | 2009-05-07 |
20090117703 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A method for manufacturing a semiconductor substrate is provided, which includes a step of forming a buffer layer over a first semiconductor substrate, a step of forming a damaged region in the first semiconductor substrate by irradiating the first semiconductor substrate with ions, a step of bonding the first semiconductor substrate and a second semiconductor substrate with the buffer layer interposed between, a step of separating the first semiconductor substrate with a single crystal semiconductor layer left over the second semiconductor substrate by heating the first semiconductor substrate and the second semiconductor substrate, and a step of irradiating the single crystal semiconductor layer with a laser beam and heating the single crystal semiconductor layer. | 2009-05-07 |
20090117704 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - As a base substrate, a substrate having an insulating surface such as a glass substrate is used. Then, a single crystal semiconductor layer is formed over the base substrate with the use of a large-sized semiconductor substrate. Note that, it is preferable that the base substrate be provided with a plurality of single crystal semiconductor layers. After that, the single crystal semiconductor layers are cut to divide the single crystal semiconductor layers into a plurality of single crystal semiconductor regions by patterning. Next, the single crystal semiconductor regions are irradiated with laser light or heat treatment is performed on the single crystal semiconductor regions in order to improve the planarity of surfaces and reduce defects. Peripheral portions of the single crystal semiconductor regions are not used as semiconductor elements, and central portions of the single crystal semiconductor regions are used as the semiconductor elements. | 2009-05-07 |
20090117705 | METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR MEMORY DEVICE - The present invention relates to a method of forming isolation layers of a semiconductor device. According to a method of forming isolation layers of a semiconductor device in accordance with an aspect of the present invention, a tunnel insulating layer, a charge trap layer, and a hard mask layer are sequentially formed over a semiconductor substrate. First trenches are formed by etching the hard mask layer, the charge trap layer, the tunnel insulating layer, and the semiconductor substrate. A spacer layer is formed on the entire surface including the first trenches. Second trenches are formed by etching the spacer layer, which is formed at a bottom of the first trenches, and the semiconductor substrate. An insulating layer for isolation is formed on the entire surface including the second trenches. | 2009-05-07 |
20090117706 | Manufacturing Method of SOI Wafer and SOI Wafer Manufactured by This Method - There is provided a method of manufacturing an SOI wafer by an ion implantation delamination method, comprising at least: forming an oxide film on a surface of at least one of a base wafer and a bond wafer functioning as an SOI layer; implanting at least one of a hydrogen ion and a rare gas ion from a surface of the bond wafer to form an ion implanted layer; subsequently bringing the bond wafer into close contact with the base wafer via the oxide film; performing a heat treatment to cause delamination in the ion implanted layer so that the SOI layer is formed; then conducing a heat treatment in an oxidizing atmosphere to form an oxide film on the surface of the SOI layer; subsequently removing the oxide film by etching; then cleaning the surface of the SOI layer by using ozone water; and polishing the same. As a result, in an ion implantation delamination method, a method of manufacturing a high-quality SOI wafer which can remove a damaged layer and surface roughness remaining on the SOI layer surface after delamination while maintaining film thickness uniformity of the SOI layer is provided. | 2009-05-07 |
20090117707 | METHOD FOR MANUFACTURING SOI SUBSTRATE AND SEMICONDUCTOR DEVICE - An object is to provide a method for manufacturing an SOI substrate provided with a single crystal semiconductor layer which can be used practically even when a substrate having a low heat resistant temperature, such as a glass substrate or the like, is used. Another object is to manufacture a highly reliable semiconductor device using such an SOI substrate. An SOI substrate having a single crystal semiconductor layer which is transferred from a single crystal semiconductor substrate to a supporting substrate, and an entire region of which is melted by laser light irradiation to cause re-single-crystallization is used. Accordingly, the single crystal semiconductor layer has reduced crystal defects, high crystallinity and high planarity. | 2009-05-07 |
20090117708 | METHOD FOR MANUFACTURING SOI SUBSTRATE - A method for manufacturing an SOI substrate includes steps of forming a first oxide film on a surface of a first silicon substrate; implanting hydrogen ions into the surface of the first silicon substrate on which the first oxide film is formed to form an ion implant region inside the first silicon substrate; removing the entire or the portion of first oxide film; forming a laminate by bonding the second silicon substrate to a hydrogen ion-implanted surface of the first silicon substrate with the first oxide film, or second oxide film formed on a surface of the second silicon substrate, or the first oxide film and second oxide film, interposed therebetween; and subjecting the laminate to a heat treatment at a predetermined temperature to separate the first silicon substrate along the ion implant region, thereby obtaining an SOI substrate including a thin SOI layer formed on the second silicon substrate with the oxide film interposed therebetween. The method can reduce a degree of contamination from heavy metals inside the SOI substrate. | 2009-05-07 |
20090117709 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The technology in which lowering of the manufacturing yield of the semiconductor products resulting from contamination impurities can be suppressed is offered. | 2009-05-07 |
20090117710 | METHOD OF CUTTING SEMICONDUCTOR WAFER, SEMICONDUCTOR CHIP APPARATUS, AND CHAMBER TO CUT WAFER - A method of cutting a semiconductor wafer includes preparing a semiconductor wafer including a scribe region and a chip region, forming a groove in the scribe region, loading the semiconductor wafer with the groove formed therein in a chamber, and cutting the semiconductor wafer into a plurality of chips through increasing a pressure of the chamber by a first pressure change rate, and then reducing the pressure of the chamber by a second pressure change rate. | 2009-05-07 |
20090117711 | Method for Laterally Cutting Through a Semiconductor Wafer and Optoelectronic Component - In a method for laterally dividing a semiconductor wafer ( | 2009-05-07 |
20090117712 | LASER PROCESSING METHOD - A laser processing method for preventing particles from occurring from cut sections of chips obtained by cutting a silicon wafer is provided. An irradiation condition of laser light L for forming modified regions | 2009-05-07 |
20090117713 | Reduction of Attraction Forces Between Silicon Wafers - The present invention is related to a method for reducing attraction forces between wafers ( | 2009-05-07 |
20090117714 | Method of producing semiconductor device, and substrate processing apparatus - Disclosed is a method of producing a semiconductor device, comprising the steps of carrying a substrate with an insulating film formed on its surface into a processing chamber; processing the substrate to form silicon grains on the insulating film formed on the surface of the substrate by introducing at least a silicon-base gas into the processing chamber; and carrying the processed substrate out of the processing chamber, wherein in the processing step, a silicon-base gas and a dopant gas are introduced into the processing chamber with the temperature and the pressure inside the processing chamber being so controlled that, when the silicon-base gas is introduced singly, the silicon-base gas is not thermally decomposed under the controlled condition, in such a manner that the flow rate of the dopant gas could be equal to or more than the flow rate of the silicon-base gas. | 2009-05-07 |
20090117715 | Semiconductor device fabricated by selective epitaxial growth method - A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established. | 2009-05-07 |
20090117716 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - To provide a high-performance semiconductor device using an SOI substrate in which a substrate having low heat resistance is used as a base substrate, to provide a high-performance semiconductor device without performing mechanical polishing, and to provide an electronic device using the semiconductor device, planarity of a semiconductor layer is improved and defects in the semiconductor layer are reduced by laser beam irradiation. Accordingly, a high-performance semiconductor device can be provided without performing mechanical polishing. In addition, a semiconductor device is manufactured using a region having the most excellent characteristics in a region irradiated with the laser beam. Specifically, instead of the semiconductor layer in a region which is irradiated with the edge portion of the laser beam, the semiconductor layer in a region which is irradiated with portions of the laser beam except the edge portion is used as a semiconductor element. Accordingly, performance of the semiconductor device can be greatly improved. Moreover, an excellent electronic device can be provided. | 2009-05-07 |
20090117717 | METHODS OF SELECTIVELY DEPOSITING SILICON-CONTAINING FILMS - An embodiment provides a method for selectively depositing a single crystalline film. The method includes providing a substrate, which includes a first surface having a first surface morphology and a second surface having a second surface morphology different from the first surface morphology. A silicon precursor and BCl | 2009-05-07 |
20090117718 | METHODS FOR INFUSING ONE OR MORE MATERIALS INTO NANO-VOIDS IF NANOPOROUS OR NANOSTRUCTURED MATERIALS - A method of forming composite nanostructures using one or more nanomaterials. The method provides a nanostructure material having a surface region and one or more nano void regions within a first thickness in the surface region. The method subjects the surface region of the nanostructure material with a fluid. An external energy is applied to the fluid and/or the nanostructure material to drive in a portion of the fluid into one or more of the void regions and cause the one or more nano void regions to be substantially filled with the fluid and free from air gaps. | 2009-05-07 |
20090117719 | HIGH FREQUENCY DIODE AND METHOD FOR PRODUCING SAME - A high frequency diode comprising: a P type region, a N type region, and an I layer as a high resistivity layer interposed between the P type region and the N type region, wherein the I layer is made of a silicon wafer that has a carbon concentration of 5×10 | 2009-05-07 |
20090117720 | STRAINED SEMICONDUCTOR-ON-INSULATOR BY Si:C COMBINED WITH POROUS PROCESS - A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer. | 2009-05-07 |
20090117721 | Vapor phase growth apparatus - A method of cooling a complex electronic system includes preventing system air from passing through a front side and a rear side of a server system main board, organizing a plurality of electronic segments of the server system main board, providing cool air horizontally to the server system main board through a cool air intake provided at a position located underneath the front side and at a bottom side of the server system main board, using the cool air intake to provide the cool air to a plurality of cooling segments that redirect the cool air vertically at a 90° angle, and using a hot air exhaust after the hot air reaches the top side of the server system main board to redirect the hot air horizontally at a 90° angle and exhaust the hot air. | 2009-05-07 |
20090117722 | METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURES - A method for fabricating a semiconductor structure includes forming a carbon masking layer on a semiconductor layer, forming a protective layer on the carbon masking layer. The method further includes forming an opening in the protective layer and the carbon masking layer and processing the semiconductor layer through the opening to form a first processed region in the semiconductor layer. The method further includes enlarging the opening in the carbon masking layer and performing an additional processing step on the semiconductor layer through the enlarged opening to form a second processed region in the semiconductor layer. | 2009-05-07 |
20090117723 | Methods of forming a conductive pattern in semiconductor devices and methods of manufacturing semiconductor devices having a conductive pattern - In a method of forming a conductive pattern in a semiconductor device, a conductive layer including a metal is formed on a substrate. A mask including carbon is provided on the conductive layer, and the conductive pattern is formed on the substrate by etching the conductive layer using the mask as an etching mask. The mask is removed from the conductive pattern by an oxygen plasma ashing process. An oxidized portion of the conductive pattern is reduced. The conductive pattern may have a desired resistance by reducing the oxidized portion to improve electrical characteristics and reliability of the semiconductor device. | 2009-05-07 |
20090117724 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes the steps of forming an insulating film having a prescribed repetition pattern on one surface of a semiconductor substrate and then depositing semiconductor layers on the one surface of the semiconductor substrate; forming trenches from the other surface of the semiconductor substrate in such a manner that the trenches come into contact with the semiconductor layer, that plural trenches are formed for each semiconductor chip to be formed on the semiconductor substrate, and that at least one pattern of the insulating film is exposed through the bottom of each trench; and covering the inside surfaces of the trenches and the other surface of the semiconductor substrate with a metal electrode. | 2009-05-07 |
20090117725 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device includes forming a line pattern over a semiconductor substrate, and then forming a first dielectric spacer having a vertically extending portion formed on sidewalls of the line pattern and a horizontally extending portion formed over and contacting the semiconductor substrate, and then removing the horizontally extending portion of the first dielectric spacer, and then forming a second dielectric spacer layer on the sidewall of the vertically extending portion of the first dielectric spacer and on the area of the semiconductor substrate where the horizontally extending portion of the first dielectric spacer was removed. | 2009-05-07 |
20090117726 | Integration Scheme for an NMOS Metal Gate - A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor. | 2009-05-07 |
20090117727 | METHOD OF FORMING A FLASH MEMORY - A method of forming a flash memory is provided. The method includes the steps of providing a substrate; forming a plurality of floating gates on the substrate; forming a first conformal dielectric layer to cover the substrate and the plurality of floating gates; forming a second conformal dielectric layer to cover the first conformal dielectric layer; partially removing the second conformal dielectric layer to partially expose the first conformal dielectric layer; forming a conformal precursor layer to cover the second conformal dielectric layer and the exposed portion of the-first conformal dielectric layer; oxidizing the conformal precursor layer to form a control gate dielectric layer between the plurality of floating gates; and forming a control gate on the control gate dielectric layer. | 2009-05-07 |
20090117728 | METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - A method for fabricating a nonvolatile memory device includes forming a tunneling insulation layer and a conductive layer for a floating gate over a substrate, partially etching the conductive layer, the tunneling insulation layer, and the substrate to form a trench, forming an isolation layer filling a portion of the trench, forming spacers on both sidewalls of the conductive layer not covered by the isolation layer, recessing a portion of the exposed isolation layer using the spacers as an etch barrier layer to form wing spacers, removing the spacers, performing a primary cleaning process on the resulting substrate using a mixed solution of H | 2009-05-07 |
20090117729 | Electrostatic Discharge (ESD) Protection Structure - A semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. A solder bump is formed on the contact pad. An electrostatic discharge (ESD) bump electrode is formed on the contact pad. The ESD bump electrode has a tip. The ESD bump electrode is made with gold. A chip carrier substrate has a contact pad metallurgically connected to the solder bump. The chip carrier substrate also has a ground plate. The ground plate is a low impedance ground point. The tip of the ESD bump electrode is separated from the ground plate by a distance according to ESD sensitivity of the active devices. The distance is determined by a ratio of a discharging threshold voltage for ESD sensitivity of the active device to be protected to an atmosphere discharging voltage. | 2009-05-07 |
20090117730 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED DEVICE - Manufacture of semiconductor products such as LCD driver requires a bump plating step for forming a gold bump electrode having a size of from about 15 to 20 μm. This bump plating step is performed by electroplating with a predetermined plating solution, but projections intermittently appear on the bump electrode during a mass production process. In the invention, abnormal growth of projections over the gold bump electrode is prevented by adding, prior to the gold bump plating step, a step of circulating and stirring a plating solution while erecting a plating cup and efficiently dissolving/discharging a precipitate. This step is performed for each wafer to be treated. | 2009-05-07 |
20090117731 | SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening. | 2009-05-07 |
20090117732 | METHOD OF FABRICATING SEMICONDCUTOR DEVICE - A method of fabricating a semiconductor device that may include forming an insulating interlayer on and/or over a semiconductor substrate, and then forming a damascene structure by patterning the insulating interlayer, and then forming a metal layer on and/or over the insulating interlayer and filling the damascene structure, and then forming a metal line by planarizing the metal layer until an upper surface of the insulating interlayer is exposed, and then forming pores in the insulating interlayer by performing thermal treatment of the planarized structure. | 2009-05-07 |
20090117733 | Protection of seedlayer for electroplating - The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. | 2009-05-07 |
20090117734 | PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS - A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed. | 2009-05-07 |
20090117735 | IMPLANTATION OF MULTIPLE SPECIES TO ADDRESS COPPER RELIABILITY - A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible. | 2009-05-07 |
20090117736 | AMMONIA-BASED PLASMA TREATMENT FOR METAL FILL IN NARROW FEATURES - A method for fabricating a semiconductor device is described. A substrate is provided having a patterned dielectric layer disposed thereon. A trench is formed in the dielectric layer. The surfaces of the trench are treated with an ammonia-based plasma process. A metal layer is then formed in the trench. | 2009-05-07 |
20090117737 | POLYCONDUCTOR LINE END FORMATION AND RELATED MASK - Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching. | 2009-05-07 |
20090117738 | METHOD FOR PRODUCING SUBSTRATE - A metallic film | 2009-05-07 |
20090117739 | METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE - A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region. | 2009-05-07 |
20090117740 | FLUID-CONFINING APPARATUS AND METHOD OF OPERATING THE SAME - The fluid-confining apparatus includes at least a substrate holder, at least a confining fluid supplying tube, at least a confining fluid recovering tube, at least a process fluid supplying tube, and at least a process fluid recovering tube. The process fluid supplying tube supplies at least a process fluid, and makes the process fluid contact with at least a treatment region of a wafer. The confining fluid supplying tube continuity supplies at least a confining fluid. The confining fluid does not dissolve the process fluid. The flowing confining fluid can contact with at least a non-treatment region of the wafer, and confines the process fluid into a predetermined space. | 2009-05-07 |
20090117741 | METHOD FOR FABRICATING MONOLITHIC TWO-DIMENSIONAL NANOSTRUCTURES - A patterning method for the creation of two-dimensional nanowire structures. Nanowire patterning methods are used with lithographical patterning approaches to form patterns in a layer of epoxy and resist material. These patterns are then transferred to an underlying thin film to produce a two-dimensional structure with desired characteristics. | 2009-05-07 |
20090117742 | METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a pattern in a semiconductor device includes a single polysilicon hard mask by appropriately selecting spacer material in an SPT, thereby decreasing the number of fabrication processes. Furthermore, since the spacers are easily removed, it is possible to prevent the formation of a step between patterns of a cell region and a peripheral region. | 2009-05-07 |
20090117743 | Film formation apparatus and method for using same - A method for using a film formation apparatus for a semiconductor process to form a thin film on a target substrate inside a reaction chamber includes performing a cleaning process to remove a by-product film deposited on a predetermined region in a gas route from a film formation gas supply system, which supplies a film formation gas contributory to film formation, through the reaction chamber to an exhaust system, by alternately repeating an etching step and an exhaust step a plurality of times in a state where the reaction chamber does not accommodate the target substrate. The etching step includes supplying a cleaning gas in an activated state for etching the by-product film onto the predetermined region, thereby etching the by-product film. The exhaust step includes stopping supply of the cleaning gas and exhausting gas by the exhaust system from a space in which the predetermined region is present. | 2009-05-07 |
20090117744 | Ion implantation mask forming method - A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern. | 2009-05-07 |
20090117745 | METHODS FOR SELECTIVELY ETCHING A BARRIER LAYER IN DUAL DAMASCENE APPLICATIONS - Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer and/or a hardmask layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in an etch reactor, flowing a gas mixture containing SiF | 2009-05-07 |
20090117746 | GAS SUPPLY DEVICE, SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A gas supply mechanism includes a gas introduction member having gas inlet portions through which a gas is introduced into a processing chamber, a processing gas supply unit, a processing gas supply path, branch paths, an additional gas supply unit and an additional gas supply path. The gas inlet portions includes inner gas inlet portions for supplying the gas toward a region where a target substrate is positioned in the chamber and an outer gas inlet portion for introducing the gas toward a region outside an outermost periphery of the target substrate. The branch paths are connected to the inner gas inlet portions, and the additional gas supply path is connected to the outer gas inlet portion. | 2009-05-07 |
20090117747 | Method for Surface Treating Semiconductor - [Task] Native oxide film on a semiconductor silicon wafer(s) is dry etched at a temperature of 50° C. or less. Hydrogen treatment is then carried out a temperature of 100° C. or more to bond the dangling bonds with hydrogen. A jig | 2009-05-07 |
20090117748 | METHOD FOR MANUFACTURING A PHASE CHANGE MEMORY DEVICE CAPABLE OF IMPROVING THERMAL EFFICIENCY OF PHASE CHANGE MATERIAL - A method for manufacturing a phase change memory device, capable of improving reset current characteristics of a phase change layer by preventing thermal loss of the phase change layer. An interlayer dielectric layer having a lower electrode contact is formed on a semiconductor substrate. A phase change layer and an upper electrode layer are sequentially formed on the interlayer dielectric layer. Then, an upper electrode and a phase change pattern are formed by etching predetermined portions of the upper electrode layer and the phase change layer using an etching gas having chlorine gas. | 2009-05-07 |
20090117749 | Etching Method of Single Wafer - Local shape collapse of a wafer end portion is suppressed to the minimum level, and a wafer front surface as well as a wafer end portion is uniformly etched while preventing an etchant from flowing to a wafer rear surface. | 2009-05-07 |
20090117750 | Methods of Forming a Semiconductor Device - The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å. | 2009-05-07 |
20090117751 | METHOD FOR FORMING RADICAL OXIDE LAYER AND METHOD FOR FORMING DUAL GATE OXIDE LAYER USING THE SAME - A method for fabricating a radical oxide layer includes providing a substrate, forming an oxide layer over the substrate through a radical oxidation process, and performing a thermal treatment on the oxide layer by using oxygen (O | 2009-05-07 |
20090117752 | Semiconductor device manufacturing method and substrate processing apparatus - A high quality interface is formed at a low oxygen-carbon density between a substrate and a thin film while preventing heat damage on the substrate and increase of thermal budget. This method includes a step of loading a wafer into a reaction furnace, a step of pretreating the wafer in the reaction furnace, a step of performing a main processing of the pretreated wafer in the reaction furnace, and a step of unloading the wafer from the reaction furnace after the main processing. Hydrogen gas is continuously supplied to the reaction furnace in the period from the end of the pretreating step to the start of the main processing and at least during vacuum-exhausting an interior of the reaction furnace. | 2009-05-07 |
20090117753 | BODY CONFORMABLE ELECTRICAL NETWORK - An entirely wearable electrical connector for power/data connectivity. The principal element of a modular network is the wearable electrical connector, which is integrated into a personal area network with USB compatibility. | 2009-05-07 |
20090117754 | MINI DISPLAYPORT - Connectors having a smaller profile. These connectors are useful as a reduced form factor DisplayPort connector. Keys on a receptacle are used to indicate when an insert is fully engaged. Edges of the receptacle and insert are chamfered in such a way as to prevent the pins of the connector from being damaged when an improper insertion is attempted. User experience is also enhanced by the use of one or more latches. As the connector is inserted, the latch provides resistance that builds until the connector is inserted a certain distance, after which the latch enters a cutout portion of the insert thus releasing the pressure and letting the user know the connection has been made. Fingers are employed to provide mechanical stability and electrical connection between receptacle and insert. | 2009-05-07 |
20090117755 | CONNECTOR - A press-in hole ( | 2009-05-07 |
20090117756 | Connector arrangement for printed circuit boards and the like - A connector arrangement serves to connect a plurality of the circuits of a printed circuit board with a plurality of electrical conductors, respectively, including a locking member for locking together a first connector member having terminals connected with the electrical conductors, respectively, and a second connector member having a plurality of conductive pins connected with the printed circuit board circuits, respectively. In a first embodiment, the locking pin is connected with the first connector member for longitudinal sliding displacement between unlocked and locked positions relative to a second connector member electrically connected with the first conductor member. Pairs of auxiliary contacts may be provided that are operable when the locking member is in the locked position. In a second embodiment, the locking member is pivotally connected with the first connector member for pivotal displacement between the unlocked and locked positions relative to the other connector member. | 2009-05-07 |
20090117757 | CONNECTING STRUCTURE OF CIRCUIT BOARDS, CONNECTING METHOD OF CIRCUIT BOARDS, AND COMPRESSING TOOL FOR CONNECTING CIRCUIT BOARDS - An object of the invention is to provide a connecting structure of circuit boards in which whether or not the circuit boards have been favorably connected can be more easily judged as compared with the prior art, even in case where connecting portions have been connected with pressure by arranging the connecting portions face to face, a connecting method of the circuit boards, and a compressing tool for connecting the circuit boards. A connecting structure | 2009-05-07 |
20090117758 | Electrical junction box - An electrical junction box comprising a casing body including a bottom wall and a side wall extending upward from the bottom wall; a circuit board contained in the casing body; a connector housing disposed in a cutout section in the side wall and adapted to be coupled to a mating member; a filler filled in a space enclosed by the bottom wall, side wall and connector housing; and a packing disposed in a clearance between the cutout section and an outer peripheral surface of the connector housing to seal the clearance. | 2009-05-07 |
20090117759 | ELECTRICAL CONNECTING APPARATUS - The present invention prevents damage of adjacent mounting portions caused by heat at the time of mounting of contactors and further reduces the arrangement pitch of the contactors. An electrical connecting apparatus uses at least four types of contactors different in terms of at least the shapes of seat portions and the height positions of arm portions. Each of such contactors has a seat portion mounted on a mounting portion of a board, an arm portion extending in the left-right direction from the lower end of the seat portion, and a probe tip portion extending downward from the tip end portion of the arm portion and having a probe tip at the lower end. These contactors are mounted in parallel in a cantilevered manner alternately in the front-back direction with the mounting positions to the board displaced in the left-right direction. | 2009-05-07 |
20090117760 | TERMINAL CONNECTING STRUCTURE - A terminal connecting structure includes a connector housing which has a connector terminal and a retaining member, and a board which has a board terminal and a terminal insertion hole for receiving the connector terminal projected toward the board. The retaining member of the connector housing retains the board at a provisionally-retaining position and a completely-retaining position. A retaining position of the connector housing with respect to the board is changed between the provisionally-retaining position and the completely-retaining position when the connector housing is slid with respect to the board in a first direction. The terminal insertion hole is configured so that the connector terminal is movable in the terminal insertion hole along the first direction when the retaining position is changed between the provisionally-retaining position and the completely-retaining position. The connector terminal is connected to the board terminal in the completely-retaining position. | 2009-05-07 |
20090117761 | ELECTRICAL FITTING AND SAFETY COVER - A safety cover for a socket or switch has a frame arranged to extend on three sides of a rectangular faceplate of the socket or switch and a cover panel hinged to the frame for pivotal movement towards and away from a position in which the cover panel conceals the faceplate. The frame is of U-shape and defines an opening in which the faceplate is received. The frame has inwardly directed lips contiguous with a rear face of the frame that locate behind the faceplate on opposite sides of the opening clear of the fixing screws used to secure the faceplate to a mounting box. The safety cover can be fitted by partially releasing the screws and sliding the lips under the faceplate as the frame is positioned around the faceplate and then tightening the screws to secure the faceplate and hold the frame in place by securing the lips under the faceplate. | 2009-05-07 |
20090117762 | PROTECTIVE BOOT AND UNIVERSAL CAP - A protective endcap for use with a triaxial cable connector. The endcap is sized to fit about a mating end of the triaxial connector. A pair of protective boots for use with coaxial cable connectors. Each protective boot includes an interior space for receiving a triaxial cable connector. Each interior space includes ridges for engaging grooves about the connector. Each boot includes a mating circumferential lip about a connector end. Each boot includes a tapered cable end with an opening for a cable from a connector to extend through from the interior space. A triaxial cable connector assembly including a connector, a protective boot and an endcap. The connector is positioned within an interior opening of the boot with ridges of an inner wall of the opening engaging grooves of the connector. A cable extending from the connector extends through a cable end of the boot. A mating end of the connector is adjacent a connector end of the boot. The endcap is mounted about the mating end of the connector and includes a circumferential lip which engages a mating circumferential lip of boot. | 2009-05-07 |
20090117763 | CARD FIXER - A card fixer is suitable to assist a card to be fixed in a slot of an electronic device. The card fixer includes a body and a clipping structure, wherein the body has a first side and a second side parallel to the first side. A hook is disposed on the first side of the body. The clipping structure extends out of the second side of the body for clipping the card thereon. When the clipping structure of the card fixer clips the card and the assembly of the card fixer with the card is inserted into the slot, the hook is locked on an inside wall of the slot. | 2009-05-07 |
20090117764 | Lever-Type Connector - A lever is attached to a connector housing in a rotatable manner. This lever includes a pair of arm plates having rotation supporting points at one ends and a connection bar linking the other ends of the arm plates. This lever has a substantially U-like shape. According to this lever, when one ends of the pair of arm plates are opened to the outer sides, the rotation supporting point of the lever is attached, in a rotatable manner, to a rotation supporting pivot of the outer face of the connector housing. By this structure, the lever is rotated for operation to realize a cam action to assist the connectors to be fitted to each other and to be disengaged from one another. According to this lever-type connector, the lever is attached to the connector housing, and subsequently the connection between the arm plates at a position closer to the rotation supporting point of the lever than to the connection bar is provided as a link member linking the arm plates. The movable element of the fitting sensing switch constitutes this link member. | 2009-05-07 |
20090117765 | ELECTRONIC DEVICE HAVING REPLACEABLE PLUG - An electronic device includes a main body, a plug and a fixing member. The main body includes a plug-receiving portion and a plurality of conductive portions. The plug-receiving portion is defined by a first sidewall, a second sidewall and a bottom surface. The first sidewall is opposed to the second sidewall. The bottom surface is connected to the first sidewall and the second sidewall. An inclined angle between the bottom surface and at least one of the first sidewall and the second sidewall is smaller than 90 degrees. The plug includes a plurality of conductive terminals, a first slant corresponding to the first sidewall, and a second slant corresponding to the second sidewall. The fixing member is used for facilitating fixing the plug in the plug-receiving portion of the main body such that the conductive terminals of the plug are electrically connected to the conductive portions of the main body. | 2009-05-07 |
20090117766 | High density coaxial switching jack - A coaxial switching jack with a pair of coaxial assemblies mounted within a housing having a pair of front openings. The coaxial assemblies each include a center conductor and a shell conductor. The center conductors are connected by a first spring and the shell conductors are connected by a second spring. Insertion of a coaxial cable connector within one of the front openings deflects the springs from the corresponding coaxial assembly and disconnects the center and shell conductors of the two assemblies. The jack may also be configured to provide an electrical connection between the center and shell conductors of the second coaxial assembly if a coaxial cable connector is inserted within the first coaxial assembly. The connection between the center and shell conductors of the second coaxial assembly may allow for selection of a desired electrical impedance. | 2009-05-07 |
20090117767 | Complex coupler for cold cathode fluorescent lamp - A complex coupler for cold cathode fluorescent lamp (CCFL) is used as a lamp lead wire coupling terminal, which includes a main body, a CCFL socket, and a cable socket. The main body is in the shape of an elongated column with a complex structure consisting of an inner conductive body and an outer enclosing insulative layer. The main body has a lamp coupling surface, on which the CCFL socket is formed for receiving an end of a CCFL and a lamp lead wire provided on that end of the CCFL, and a conductor coupling surface, on which the conductor socket is formed for a cable to connect thereto. The lamp lead wire of the CCFL and the cable can be electrically connected to each other via the lamp lead wire coupling terminal. | 2009-05-07 |
20090117768 | Adapter having connecting arms - An adapter has connecting arms and includes a casing, a first plugging element and a second plugging element. The casing has connecting arms and is provided with pivoting portions. The side edges of the casing are formed with first sliding grooves. The first and the second plugging element are electrically connected inside the casing, and face in opposite directions. Via this arrangement, the adapter can be assembled with a plug and can be assembled with other adapters of different specifications and types, thereby providing more functionality. | 2009-05-07 |
20090117769 | APPARATUS FOR HOLDING A SIM CARD - The invention relates to a device for holding a SIM card with a SIM card reader, wherein the SIM card reader has a push-push mechanism by means of which the SIM card can be latched into a reading position and unlatched from the reading position into a removal position by repeatedly pressing the SIM card in a direction of insertion. In this arrangement, the SIM card reader is arranged on a rocker which is suspended to pivot between two end positions in a slot of a housing, wherein the SIM card reader is covered by a cover, wherein the cover closes off the slot in the first end position of the rocker and wherein the cover can be displaced against a restoring mechanism in the direction of insertion of the SIM card in the second end position of the rocker. | 2009-05-07 |
20090117770 | CONNECTOR - When a male connector housing | 2009-05-07 |
20090117771 | Electrical connector with a sliding plate moveing in along a vertical direction of the connector thereof - An electrical connector ( | 2009-05-07 |
20090117772 | SNAGLESS PLUG AND BOOT CONNECTION - A boot for supporting a plug connected to a cable, the plug including a flexible tab attached thereto and comprising a housing having a front opening for accommodating the plug and an opposite back opening for receiving the cable and allowing the cable to pass therethrough to the plug, a recess formed in said housing; and a tab protector engaged with said recess for engaging the flexible tab of the plug. | 2009-05-07 |
20090117773 | TERMINAL FITTING - A terminal fitting ( | 2009-05-07 |
20090117774 | SURFACE MOUNT CRIMP TERMINAL AND METHOD OF CRIMPING AN INSULATED CONDUCTOR THEREIN - A surface mount insulation terminal is formed of flat deformable conductive member to provide a substantially uniform U-shaped cross-section to form a wire-receiving channel. One or more piercing spikes are formed on a bottom wall of the channel and point to an opposing open side through which a conductor may be introduced. Ribs inside the channel provide an interference fit with a conductor introduced into the channel. A crimping tool lowered into engagement with the terminal after it has been soldered to a PCB increasingly deforms the side walls of the terminal inwardly towards each other and towards the bottom wall to enhance the electrical and mechanical properties of the resulting termination. | 2009-05-07 |
20090117775 | Wire retention connector system - A wire retaining connector, connector system and method of connecting wires to connectors to reduce or eliminate unintentional wire disconnection from wire connectors, including disconnection of poke-in connectors. The connectors and connector systems include a connector body having at least one opening configured to receive a wire, the wire including a partially exposed conductor and insulation. The connector body further includes a wire retention member having at least one surface onto which a wire may be engaged. The wire retention member provides sufficient retention of the wire to resist disconnection of the wire from the connector body. A method for connecting wires to the connectors is also provided. | 2009-05-07 |
20090117776 | Easy-pull type swivel plug - An easy-pull type swivel plug includes a body, a rotatable disk and a handle. The rotatable disk is rotatably provided on one side of the body. The rotatable disk is provided with two conductive pieces. The two conductive pieces extend beyond the body. The handle is pivoted to the other side of the body opposite to the rotatable disk in a liftable and foldable manner. The pivoting position between the handle and body corresponds to the center of the rotatable disk. Via this arrangement, the deformation of the conductive pieces caused by a torque generated in misalignment with the center can be avoided and the user can unplug more easily with less labor. | 2009-05-07 |
20090117777 | KEYBOARD, VIDEO AND MOUSE (KVM) SWITCH - A cable device including a plurality of cables and connecting ports. The cable device may act as a keyboard, video and mouse (KVM) switch system that facilitates controlling different computers with one set of keyboard, video and mouse. In one embodiment, a cable device includes a switching circuit, a plurality of connector ports electrically coupled to the switching circuit, a first cable fixedly connected to the switching circuit, the first cable comprising at least one first connector plug, and a second cable fixedly connected to the switching circuit, the second cable comprising at least one second connector plug, wherein the switching circuit operably selects which of the first and second cables is in communication with the connector ports. | 2009-05-07 |
20090117778 | CONNECTOR - A connector includes a connector housing which has a pair of side walls, a plurality of terminals which are accommodated in the connector housing, and a pair of metal fixing members. Each metal fixing members includes a board fixing portion and a housing mounting portion. Slots are formed in the side walls. Each housing mounting portion is inserted into each slot from the lower side thereof. The each slot has an upper portion and a lower portion smaller in width than the upper portion. The each slot has a pair of retaining step portions. The each housing mounting portion has a pair of arms. Hooks are formed on upper end portions of the arms. When the housing mounting portion is inserted into the slot, the hooks are engaged with the retaining step portions. A convex portion is formed on an inner wall of the slot. | 2009-05-07 |
20090117779 | Coaxial electrical connector - A coaxial electrical connector to be connected to a printed circuit board, includes an outer conductor ( | 2009-05-07 |
20090117780 | Connector for Coaxial Cable - A coaxial cable connector has a connector body and a securing ring. The connector body includes a tubular insertion section that is insertable between an insulation member around a core conductor of the coaxial cable and a woven conductor around the insulation member, a flange section that is provided around the insertion section and with which both the woven conductor of the coaxial cable and a cover member around the woven conductor come into contact when the insertion section is inserted in the coaxial cable to position the insertion section, and an annular fitting section that is provided at the insertion section, on the opposite side of the coaxial cable, and into which an object to be connected is insertable. The securing ring is used to pressure-bond and fix the coaxial cable to the insertion section from the periphery of the coaxial cable after the insertion section of the connector body is inserted in the coaxial cable. The connector has a fixation section for fixing the connector body and the securing ring together. | 2009-05-07 |
20090117781 | ELECTRICAL CONNECTOR SYSTEM WITH ORTHOGONAL CONTACT TAILS - Disclosed are electrical connectors and methods of assembling an electrical connector having “standard” (i.e., with electrical contacts having in-line tails), jogged (i.e., with electrical contacts having jogged tails but not connected orthogonally to another connector through a substrate), and/or “orthogonal” (i.e., with electrical contacts having jogged tails that are used in an orthogonal application) leadframe assemblies in the same connector. This provides the flexibility of using some of the available contacts in an orthogonal application and, at the same time, having remaining contacts available for routing on the midplane PCB. Though this could be done using only orthogonal leadframe assemblies, the combination of standard leadframe assemblies with orthogonal leadframe assemblies creates additional spacing between the PCB vias, so that signal traces can be more easily routed on the midplane PCB. | 2009-05-07 |
20090117782 | Card connector - A card connector includes a first housing, a plurality of first terminals, a second housing and a plurality of second terminals. A plurality of accepting grooves are arranged in the first housing. An inserting groove is opened in the inner side of the accepting groove. The first terminals are accepted in the accepting grooves. A plurality of accepting holes are opened in the second housing. Each of the second terminals includes a welding portion and a base portion. The second terminal is arranged in the second housing. The welding portion projects out from the bottom of the second housing. The second housing is fixed on the bottom of the first housing. While the card connector is welded on a PCB, and the welding portion of the second terminal connects to the PCB, a space is formed between the card connector and the PCB. | 2009-05-07 |
20090117783 | Electrical connector assembly with magnetic retention device - An electrical connector assembly ( | 2009-05-07 |
20090117784 | Extension to electrical connector with improved housing structures - An electrical connector ( | 2009-05-07 |
20090117785 | EXTENSION TO ELECTRICAL CONNECTOR WITH IMPROVED CABLE TERMINATION - An electrical connector ( | 2009-05-07 |
20090117786 | ELECTRICAL CONNECTOR ASSEMBLY - The electrical connector assembly comprises first ( | 2009-05-07 |
20090117787 | ELECTRICAL CONTACT ASSEMBLY INCLUDING A SLEEVE MEMBER - A low cost crimpable and sealable contact assembly including a contact member and a tubular sleeve member. The contact member is capable of being manually continuity crimped to a tip of an electrically conductive core of an electrically insulated wire. The tubular sleeve member is then deformed to hermetically seal it to the insulation on the wire, and the contact member. The hermetic seal protects the core from corrosion. This hermetic seal is particularly important where the core comprises aluminum. Separating the crimping and sealing into separate operations permits them to be performed manually. The sleeve member may be comprised of polymeric material, or it may be metallic. The metallic embodiments may be mechanically or electromagnetically deformed. The polymeric sleeve members may, in addition, be heat shrunk. | 2009-05-07 |
20090117788 | MARINE VESSEL RUNNING CONTROLLING APPARATUS, AND MARINE VESSEL INCLUDING THE SAME - A marine vessel running controlling apparatus is applicable to a marine vessel which includes a propulsive force generating unit, a steering unit, and an operational unit to control a steering angle. The marine vessel running controlling apparatus includes a target characteristic storage unit arranged to store a target characteristic line which represents a target marine vessel maneuvering characteristic defining a relationship between a target turning behavior with respect to an operation amount of the operational unit and a traveling speed of the marine vessel, a target characteristic change inputting unit arranged to change a shape of the target characteristic line, and a target characteristic line updating unit arranged to update the target characteristic line according to an input from the target characteristic change inputting unit. The target characteristic change inputting unit includes an inflection point position change inputting unit arranged to change a position of an inflection point of the target characteristic line. | 2009-05-07 |
20090117789 | Engine for Driving a Watercraft Propelled by a Water Jet - A system for driving a water induction and discharge system of a watercraft propelled by a water jet includes a water impeller, an engine including a driven shaft and a first chamber for containing engine oil, a second chamber for containing engine oil, a pinion secured to the driven shaft and located in the second chamber, a gear located in the second chamber, engaged with the pinion and driveably connected to the water impeller, and a dam located in the second chamber for limiting oil flow across the dam into the oil contained in the second chamber. | 2009-05-07 |
20090117790 | WATER-JET PUMP, IMPELLER FOR THE SAME, AND BOAT INCLUDING THE SAME - A water-jet pump includes a cylindrical housing and an impeller. The impeller is disposed in the cylindrical housing and is configured to be rotated in a rotating direction. The impeller includes a shaft body and plural blades. The plural blades are provided on an outer circumference of the shaft body. A front portion of one of the plural blades overlaps a rear portion of another of the plural blades adjacent to one of the plural blades when viewed in an axial direction of the shaft body. When viewed in the axial direction, at least a part of a rear edge of the rear portion is formed obliquely with respect to a radial direction of the impeller towards the rotating direction. A cutaway portion is formed in each of the plural blades between at least a part of the rear edge and the outer circumference. | 2009-05-07 |
20090117791 | MOTOR LIFT ASSEMBLY - A motor lift assembly having a first side plate and a second side plate oppositely disposed from the first side plate. The motor lift assembly further includes a motor mount that is selectively moveable relative to the first and second side plates and a ladder assembly disposed on at least one of the first and second side plates. A method of extending a ladder assembly includes the step of pulling the ladder assembly from a motor lift assembly where the ladder assembly is engaged with the motor lift assembly. | 2009-05-07 |
20090117792 | Apparatus for Avoiding Tangling of a Surf Leash - An improved surf leash with a tangle resistant cord, fabrication methods thereof, and an apparatus operationally configured to resist tangling of existing surf leashes. | 2009-05-07 |