| 19th week of 2009 patent applcation highlights part 28 |
| Patent application number | Title | Published |
|---|
| 20090116292 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. The memory cell unit includes a plurality of memory cells connected in series. Each of the memory cells includes a charge accumulation layer and a control gate. The word lines are connected to the control gate. The driver circuit selects one of the word lines and applies voltages to a selected word line and unselected word lines. The voltage generator includes first and second charge pump circuits and outputs a voltage generated by the first and second charge pump circuits to the driver circuit. The first charge pump circuit is exclusively used to generate a voltage for a first word line. The first word line is one of the unselected word lines located adjacent to the selected word line. | 2009-05-07 |
| 20090116293 | Memory and method for charging a word line thereof - A memory and method for charging a word line thereof are disclosed. The memory includes a first word line driver, a first word line and a first switch. The first word line driver is connected to a first operational voltage for receiving a first control signal. The first word line comprises a start terminal connected to an output terminal of the first word line driver. The first switch is connected to a second operational voltage and an end terminal of the first word line. The second operational voltage is not smaller than the first operational voltage. When the first word line driver is controlled by the first control signal to start charging up the first word line, the first switch is simultaneously turned on to provide another charging path for the first word line until the first word line is charged to the first operational voltage. | 2009-05-07 |
| 20090116294 | METHOD OF PROGRAMMING CELL IN MEMORY AND MEMORY APPARATUS UTILIZING THE METHOD - A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/ID region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell. | 2009-05-07 |
| 20090116295 | METHOD OF OPERATING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE ONE-TIME - PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY - A programmable non-volatile device is operated using a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 2009-05-07 |
| 20090116296 | FLASH MEMORY DEVICE APPLYING ERASE VOLTAGE - A flash memory device includes; a plurality of layers, each one including memory cells arranged in a matrix of rows and columns, a layer decoder configured to select one of the plurality of layers to thereby define a selected layer and an unselected layer, a voltage generator configured to generate an erase voltage at a level higher than ground voltage, and an internal voltage, and a row select circuit configured to apply the erase voltage to the selected layer, and apply at least one of the erase voltage and the internal voltage to the unselected layer during an erase operation. | 2009-05-07 |
| 20090116297 | Redundancy program circuit and methods thereof - A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal. | 2009-05-07 |
| 20090116298 | APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION - A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified. | 2009-05-07 |
| 20090116299 | Semiconductor memory device and method for operating the same - A semiconductor memory device is capable of generating a desired output enable signal without increasing an initial count value and bit number and generating a desired final output enable signal, without unnecessary reset operations, by reflecting CAS latency information on an external clock count value. The semiconductor memory device includes a first output enable signal generating unit configured to compare a first count value, which is obtained by counting a delay locked loop (DLL) clock, with a second clock count value, which is obtained by counting an external clock until a read command is input, and output a first output enable signal, and a final output enable signal generating unit configured to output, as a final output enable signal, one of the first output enable signal and a plurality of output enable signals generated by shifting the first output enable signal, according to a column address strobe (CAS) latency. | 2009-05-07 |
| 20090116300 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the semiconductor memory device, when a test operation is activated. | 2009-05-07 |
| 20090116301 | INTERNAL DATA COMPARISON FOR MEMORY TESTING - Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data comparison test mode. The data comparison test mode systematically searches for addresses of defective columns by comparing a sensed data value to an expected data value at various levels of decoding. Upon detection of a defective column, the address value for each level of decoding is stored and can be used in redundancy selection to replace the defective columns with redundant columns. The comparison is internal to the memory device such that the test mode is independent of external testers and can be run after fabrication, even by an end user, thus allowing repair after fabrication and installation. The comparisons are facilitated by compare logic inserted into the data path. | 2009-05-07 |
| 20090116302 | Semiconductor memory device - A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from each other, a delay modeling unit configured to generate a plurality of delay clock signals by reflecting a delay time of an actual clock/data path to the plurality of clock signals, a selection signal generating unit configured to generate selection signals by comparing phases between the reference clock signal and the plurality of delay clock signals, and a phase multiplexing unit configured to output any one of the plurality of clock signals as a final clock signal in response to the selection signals. | 2009-05-07 |
| 20090116303 | Semiconductor memory device - A semiconductor memory device can generate an under_drive voltage that maintains a predetermined level stably even in case of a change in the operation mode of the semiconductor memory device or the level of an external power supply voltage. The semiconductor memory device, which includes an external power supply voltage detector configured to detect a level of an external power supply voltage to generate the external voltage detection signal, an under_drive voltage detector configured to detect a voltage level of an under_drive voltage to generate the under_drive voltage detection signal, and an under_drive voltage generator configured to generate the under_drive voltage in response to the under_drive voltage detection signal with a variable driving force in response to the external voltage detection signal. | 2009-05-07 |
| 20090116304 | Wordline driving circuit of semiconductor memory device - Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver. | 2009-05-07 |
| 20090116305 | WORD LINE DRIVER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A word line driver for use in a semiconductor memory device includes a boosted voltage generator, a sub word line driver and a main word line driver. The boosted voltage generator generates a boosted voltage by receiving an internal power supply voltage and pumping electric charge. The sub word line driver receives the internal power supply voltage and activates a boosted voltage control signal after supplying the internal power supply voltage to a boost node in a command operating mode. The main word line driver enables a word line by supplying the boosted voltage to the boost node in response to the boosted voltage control signal in a normal operating mode, and enables the word line with the boosted voltage after boosting the word line to the internal power supply voltage by changing the boost node from the internal power supply voltage to the boosted voltage in the command operating mode. | 2009-05-07 |
| 20090116306 | DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR DEVICE - A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals. | 2009-05-07 |
| 20090116307 | LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORMANCE - A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation. | 2009-05-07 |
| 20090116308 | Memory device and method of operating such a memory device - A memory device and method of operation is provided, the memory device having a plurality of memory cells arranged in at least one column, with each column having at least one bit line and a supply voltage line associated therewith. A capacitance exists between the supply voltage line and associated at least one bit line for each column. Control circuitry is used to control, for each column, connection of a voltage source to the associated supply voltage line. For a predetermined period during a memory access operation, the control circuitry disconnects the supply voltage line for at least the selected column from the voltage source, such that a voltage level on that supply voltage line changes in response to any change in voltage on the associated at least one bit line. This basic mechanism can be used to provide a variety of assist mechanisms, such as a write assist mechanism, a bit flip assist mechanism and a read assist mechanism. The technique of the present invention provides a particularly simple and power efficient technique for providing such assist mechanisms. | 2009-05-07 |
| 20090116309 | SEMICONDUCTOR DEVICE - A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD | 2009-05-07 |
| 20090116310 | METHOD AND APPARATUS FOR WRITE ENABLE AND INHIBIT FOR HIGH DENSITY SPIN TORQUE THREE DIMENSIONAL (3D) MEMORY ARRAYS - A method and apparatus for write enable and write inhibit for high density spin torque three dimensional ( | 2009-05-07 |
| 20090116311 | Semiconductor memory device - A semiconductor memory device includes data lines for transmitting one of data and a training data pattern, wherein the training data pattern is preset to a specific pattern, and training drivers for transmitting the training data pattern to the data lines in response to a training control signal which is produced by decoding a read training command. The semiconductor memory device according to the present invention can exactly measure a delay time, which is changed according to the surrounding environments between a semiconductor memory device and a data processing unit, through a data training and operation timing can be also adjusted based on the measured delay time. | 2009-05-07 |
| 20090116312 | Storage Array Including a Local Clock Buffer with Programmable Timing - A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaulate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation. | 2009-05-07 |
| 20090116313 | DATA OUTPUT CONTROL CIRCUIT - A data output control circuit includes a data output control circuit configured to compensate a delay amount of a system clock on a clock path when a delay locked loop (DLL) circuit is enabled in such a state that the semiconductor memory device exits a reset state in response to an active signal, and to determine an output timing of data corresponding to a read command by counting the system clock and a DLL clock outputted from the DLL circuit | 2009-05-07 |
| 20090116314 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device using system clock with a high frequency can maintain a constant margin of operation even with a changed operating environment including voltage level, temperature, and process. The semiconductor memory device includes a data output control circuit configured to control data outputted in synchronization with a falling edge of a system clock using a first output source signal corresponding to a rising edge of the system clock, and to control data outputted in synchronization with the rising edge of the system clock using a second output source signal corresponding to a falling edge of the system clock, and a data output circuit configured to output data, the data output circuit being controlled by the data output control circuit. | 2009-05-07 |
| 20090116315 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device has a DLL circuit capable of suppressing EMI without distorting a DLL clock required in high-speed operation. The semiconductor memory device includes a delay locked loop (DLL) circuit configured to be responsive to a system clock to output a DLL clock having a phase that is changed when electromagnetic interference (EMI) is detected, for the DLL clock to have frequencies within a delay locking range, and a data output circuit configured to output data in synchronization with the DLL clock. | 2009-05-07 |
| 20090116316 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-off units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal. | 2009-05-07 |
| 20090116317 | Block repair apparatus and method thereof - A block repair apparatus includes a plurality of cell blocks, a block repair fuse, a block isolation control unit, and a block repair selector. The block repair fuse outputs a repair signal of the plurality of cell blocks. The block isolation control unit outputs a control signal for activating the plurality of cell blocks or electrically isolating a defective cell block of the plurality of cell blocks, in response to the block repair signal. The block repair selector outputs a block repair selection signal for replacing the defective cell block with another cell block in response to a cell block address signal. | 2009-05-07 |
| 20090116318 | SEMICONDUCTOR STORAGE DEVICE - In a semiconductor storage device, such as a dynamic random access memory (DRAM), in which dynamic data is amplified and read on a bit line, a data line sense amplifier/write buffer connected to a data line of a memory array and a data line sense amplifier control signal generating logic circuit connected to a dummy data line of a dummy memory array are provided. A sense amplifier is activated in accordance with an output signal of the logic circuit. | 2009-05-07 |
| 20090116319 | Redundancy program circuit and methods thereof - A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal. | 2009-05-07 |
| 20090116320 | Methods and Apparatus for Screening Bit Line of a SRAM - Methods and apparatus provide for testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), by first and second transistors, respectively, the method comprising: preventing a write driver circuit from significantly pulling the BLT towards a supply voltage; preventing a pre-charge circuit from significantly pulling the BLT towards the supply voltage; preventing the first transistor from significantly pulling the BLT towards the voltage stored in the SRAM cell; and comparing the voltage of the BLT under the foregoing conditions to a threshold voltage. | 2009-05-07 |
| 20090116321 | Apparatus and method for detection of address decoder open faults - An apparatus and method are provided for performing a test sequence to detect address decoder open faults in a memory device. The apparatus comprises base address generation circuitry for generating a plurality of base addresses, and derived address generation circuitry, responsive to a base address portion of each base address, to generate an associated series of derived addresses. Each derived address is different to any other derived address in that associated series and has a derived address portion that differs from the corresponding base address portion by a single address bit value. Read/write sequence generator circuitry is then responsive to each base address in turn, to write in said memory device a first data value at the base address and a second data value at each derived address in the associated series of derived addresses. Further, the read/write sequence generator circuitry is arranged to read a data value stored at the base address each time the second data value is written to one of the derived addresses, and to detect an address decoder open fault if the read data value is the second data value. Such an apparatus can automatically perform the required test sequence for any configuration of memory device, hence providing a simple and efficient mechanism for detecting address decoder open faults. | 2009-05-07 |
| 20090116322 | Semiconductor memory device having wafer burn-in test mode - A semiconductor memory device includes an enable signal generator configured to generate an enable signal in response to a plurality of burn-in test signals; a test mode signal generator configured to generate a plurality of peripheral region test mode signals and a plurality of core region test mode signals corresponding to the burn-in test signals in response to the enable signal; a core region controller configured to control circuits in a core region in response to the core region test mode signals; and a peripheral region controller configured to control circuits in a peripheral region in response to the peripheral region test mode signals. | 2009-05-07 |
| 20090116323 | SCANNED MEMORY TESTING OF MULTI-PORT MEMORY ARRAYS - A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions. | 2009-05-07 |
| 20090116324 | Apparatus for Guaranteed Write Through in Domino Read SRAM'S - In a digital device for facilitating recovery of a precharged dot line, periodically precharged by a precharge signal, that has been prematurely discharged as a result of an early read condition, a data input signal can have a selected one of a first value and a second value. The first value is a value that would be reflected by the dot line being in a charged state. A logic device that is responsive to the data input signal causes charge to be applied to the dot line when the data signal has the first value. | 2009-05-07 |
| 20090116325 | ON-CHIP CHARACTERIZATION OF NOISE-MARGINS FOR MEMORY ARRAYS - A circuit, method, and computer readable medium for on-chip measuring of noise margins in a memory device memory device are disclosed. The on-chip method includes electrically coupling at least a first circuit to a memory cell. A voltage divider is electrically coupled to at least a first voltage and a second voltage. A multiplexer circuit is electrically coupled to the voltage divider. The multiplexer selects one of the first voltage and second voltage for producing a test voltage. A selecting line is electrically coupled to a force\measure network. A comparator is coupled to the force\measure network. The force-measure network supplies the test voltage to the comparator and a measured voltage to the comparator for determining when the measured voltage exceeds the test voltage. | 2009-05-07 |
| 20090116326 | Semiconductor memory device capable of performing per-bank refresh - A semiconductor memory device is provided that can support a per-bank refresh as well as an all-bank refresh and a self refresh. The semiconductor memory device includes an address counting unit for counting a bank address signal of a specific bank and row address signals of the specific bank in response to a control signal including refresh mode information when a per-bank refresh command is lo received, and for counting row address signals in response to the control signal when an all-bank refresh command or a self refresh command is received. | 2009-05-07 |
| 20090116327 | Redundancy program circuit and methods thereof - A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal. | 2009-05-07 |
| 20090116328 | POWER-OFF APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period. | 2009-05-07 |
| 20090116329 | INTERNAL-VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An internal-voltage generating circuit includes a plurality of generating units connected in cascade, out of the plurality of generating units, a generating unit of relatively lower level is activated by an output of a generating unit of relatively higher level. According to the present invention, because the plural voltage generating units are connected in cascade, the voltage generating unit of lower level is not activated unless the voltage generating unit of higher level is activated. Therefore, at least the voltage generating unit of the second level and the subsequent voltage generating units consume very small power during the standby time. Consequently, total power consumption of the internal-voltage generating circuit can be reduced. | 2009-05-07 |
| 20090116330 | Semiconductor memory device using bus inversion scheme - A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block. | 2009-05-07 |
| 20090116331 | Semiconductor memory device and method for operating the same - Semiconductor memory device and method for operating the same includes a phase detection unit configured to compare a phase of a first reference clock and a phase of a second divided reference clock to output a comparison result signal and a phase control and division unit configured to generate the second divided reference clock by dividing a second reference clock by a predetermined ratio according to the comparison result signal outputted from the phase detection unit and adjusting a phase of the second reference clock. | 2009-05-07 |
| 20090116332 | MULTI-FUNCTIONAL FUEL MIXING TANK - The present invention discloses a multi-functional fuel mixing tank, which comprises: a case, a condenser, a fan, a first sheet, and a second sheet; wherein, the case is configured with a first accommodation portion, a second accommodation portion, a third accommodation portion, a first channel, a second channel, a third channel, a fourth channel, a fuel inlet, an air inlet, a fuel outlet, and a product inlet. The fuel inlet, the air inlet, the fuel outlet and the product inlet are configured on the sidewall of the case. The second accommodation portion is used as a mixing tank. The first channel is connected with the fuel inlet and the second accommodation portion. The fourth channel is connected with the first accommodation portion and the second accommodation portion. The condenser is fixed with the first accommodation portion, and used to condense the steam from the air inlet into water, and the condensed water flows to the second accommodation portion through the third channel and the second channel. The fan is fixed with the third accommodation portion, and used to reduce the temperature of the condenser. The first sheet and the second sheet are tightly joined on the upper surface and the lower surface of the case. | 2009-05-07 |
| 20090116333 | Magnetic stirrer - A magnetic stirrer is disclosed. The magnetic stirrer is disposed with a gas entrance pipeline system and a liquid entrance pipeline system. The pipes of the gas entrance pipeline system and the liquid entrance pipeline system are connected with one another by one-touch fitting. A plurality of adjustment valves is arranged on the pipeline systems for adjusting gas flow and liquid flow. The magnetic stirrer is arranged with a heating plate so that the magnetic stirrer can perform heating and stirring processes at the same time. When not being used, the heating plate is disassembled. Therefore, the magnetic stirrer reduces time for constructing experiment equipments, increases convenience of use and further improves the efficiency of experiments. | 2009-05-07 |
| 20090116334 | METHOD FOR CONTROLLED MIXING OF FLUIDS VIA TEMPERATURE - Embodiments of the present invention provide a method for continuous flow production of mixed fluids. The mixed fluids can comprise a mixture of different fluids or a mixture of the same fluid having different input properties such as temperature. In general, two streams of fluid of varying temperature are supplied to a mixer. The flow rate of each of the input fluids can be regulated to produce a mixed fluid at a desired flow rate and temperature. As an example, mass flow controllers can regulate the flow rates of a hot and cold stream of de-ionized water to produce a stream of de-ionized water at a desired flow rate and temperature. | 2009-05-07 |
| 20090116335 | STIRRER UNIT - A stirrer unit includes a reaction vessel having an inlet port, a shaft stirrer having a stirrer blade and a stirrer shaft connected to the stirrer blade, and an adapter defining a passage. The adapter is configured to be inserted into the inlet port and releasably fastened to the inlet port using a fastening device so that, in a connected state, the stirrer blade and a part of the stirrer shaft is disposed inside the reaction vessel. Furthermore, in the connected state, an immersion depth to which the stirrer shaft extends into the reaction vessel is adjustable and securable using a locking device in at least two positions that are spaced apart from one another. | 2009-05-07 |
| 20090116336 | Determining Orientation For Seafloor Electromagnetic Receivers - Method for updating a velocity model ( | 2009-05-07 |
| 20090116337 | METHOD AND APPARATUS FOR MINIMIZING INTERFERENCE BETWEEN SEISMIC SYSTEMS - A method and apparatus for minimizing interference between seismic systems. The method may generally include: (a) actuating a plurality of first sources associated with a first seismic system to generate a first plurality of phase-encoded vibratory signals; (b) actuating a plurality of second sources associated with a second seismic system to generate a second plurality of phase-encoded vibratory signals that are at least partially frequency separated from the first plurality of phase-encoded vibratory signals generated in (a); and (c) detecting the first and second plurality of phase-encoded vibratory signals utilizing a first receiver positioned at a location remote from the first and second sources. | 2009-05-07 |
| 20090116338 | Identifying a stress anomaly in a subsurface region - A method for identifying a local stress anomaly in a subsurface region, which method comprises the steps of obtaining a model of the subsurface region, which model includes a salt layer in between adjacent layers; identifying a salt weld in the model; and attributing a stress anomaly to an area surrounding the salt weld. | 2009-05-07 |
| 20090116339 | METHOD FOR LOCATING AN IMPACT ON A SURFACE AND DEVICE FOR IMPLEMENTING SUCH A METHOD - Method for locating an impact on a surface ( | 2009-05-07 |
| 20090116340 | Surface Acoustic Wave Device and Communication Apparatus - To provide a surface elastic wave apparatus that suppresses occurrence of fine ripples within a pass band, improves insertion loss and enhances the degree of balance. First and second surface acoustic wave elements ( | 2009-05-07 |
| 20090116341 | Hybrid-drive multi-mode pipe projector - A hybrid drive (HD) multi-mode pipe projector (MMPP) for use in underwater acoustic applications is provided. The HD MMPP is formed with an inner magnetostrictive drive motor nested within an outer drive motor. The inner motor is surrounded by a magnetic field generating coil winding. Preferably the inner drive motor is a Terfenol-D motor and the outer drive motor is a radially-poled piezoceramic drive motor. This nested configuration provides increased bandwidth and low-frequency extension to the MMPP design. | 2009-05-07 |
| 20090116342 | Movable clock - A movable clock includes a control system ( | 2009-05-07 |
| 20090116343 | Balance spring, regulated balance wheel assembly and methods of manufacture thereof - A balance spring comprising a flat spiral coil and a non-elastic inner attachment part formed by laser beam cutting. The spring has an outer attachment plate in the plane of the coil formed with a channel which receives and protects the outer winding of the coil. The outer attachment plate has a curved attachment edge which allows the location of the oscillator dead point to be varied without affecting spring frequency. | 2009-05-07 |
| 20090116344 | INFORMATION RECORDING METHOD, INFORMATION RECORDING MEDIUM, AND INFORMATION RECORDING APPARATUS - An information recording method recording information on an information recording medium in the form of a recording mark having a time-length nT by irradiating optical beam pulses thereto according to a recording strategy, the recording strategy comprises the steps of forming the recording mark on the recording medium by controlling a power of the optical beam pulses to one of ternary values Pw, Pb and Pe (Pw>Pe>Pb) and irradiating a heating pulse having a power set to Pw, and a cooling pulse having a power set to Pb, upon the information recording medium alternately; and forming a space on the recording medium subsequent to the recording mark by irradiating the optical beam pulse with the power Pe, the recording strategy increasing the number of said heating pulses by one each time the time-length of the recording mark is increased by 2T, the recording strategy setting a heat pulse starting time sTtop and a heat pulse termination time eTtop for a first heating pulse, when forming a recording mark of a time-length of at least 2T, individually at least in the case of forming a space-length of 2T and the case in which there is formed a space-length of 3T or more, before or after the currently formed recording mark. | 2009-05-07 |
| 20090116345 | Objective Lens Actuator - An objective lens actuator in an optical pickup, having a semiconductor laser diode, electro-optic parts, such as a lens or the like, as well as, the objective lens actuator, etc., in a case, comprises: a holder, which mounts an objective lens and a coil thereon, as being a movable part; a magnetic circuit part, which is made up with a magnet for magnetically driving said holder and a yoke; a plural number of elastic support parts which elastically supports said holder; and a support part, which supports other ends of said elastic support parts, wherein said support part has a part, which is cut open in parallel with the elastic support parts, between said elastic support parts, and has a through hole, in which said elastic support part passes through for each of said elastic support parts, and thereby to provide the objective lens actuator for lowering the unwanted vibration mode of the objective lens, and also enabling a stable control thereof. | 2009-05-07 |
| 20090116346 | OPTICAL RECORDING/PLAYBACK DEVICE AND MEDIUM DIFFERENTIATION METHOD - There is provided a recording/playback device able to differentiate the type of an optical disc or another such optical recording medium with a high degree of precision while correcting wavefront aberrations. The recording/playback device has a detection part for sequentially detecting the surface of a cover layer and one or a plurality of signal recording surfaces of an object to be detected on the basis of an output signal of a photodetector, a medium differentiation part for differentiating the type of the detected object on the basis of the detection results, an aberration correction element, and an aberration control part for controlling the aberration correction state of the aberration correction element. When the focal point of the light beam moves toward the signal recording surface, the aberration control part sets the aberration correction state of the aberration correction element to a state between a first aberration correction state in which the wavefront aberrations are appropriately corrected in accordance with a surface of a cover layer of a predetermined optical recording medium, and a second aberration correction state in which the wavefront aberrations are appropriately corrected in accordance with a signal recording surface of the predetermined optical recording medium. | 2009-05-07 |
| 20090116347 | OPTICAL DISC APPARATUS AND SEEK PROCESSING METHOD - An optical disc apparatus of the present invention includes an optical head ( | 2009-05-07 |
| 20090116348 | OFF-TRACK DETECTION CIRCUIT - In a state where vibration is constantly detected, a protection function by a vibration detection circuit loses effectiveness, and thereby there may possibly arise a malfunction of an off-track detection circuit due to a pseudo-generated off-track signal. An off-track detection circuit which is capable of preventing malfunction due to a pseudo-generated off-track signal and of maintaining stable reproduction even when being under vibration, is provided by constructing the circuit not to judge as off-track when a reproduction synchronization signal is detected. | 2009-05-07 |
| 20090116349 | Information recording device and method, program storage medium, and program - The present invention relates to an information recording device and method, a program storage medium, and a program, wherein updated file system information can be recorded without changing a logical address. As shown to the upper side in FIG. | 2009-05-07 |
| 20090116350 | INFORMATION RECORDING APPARATUS AND METHOD AND COMPUTER PROGRAM - An information recording apparatus ( | 2009-05-07 |
| 20090116351 | WRITE-ONCE TYPE OPTICAL DISC, AND METHOD AND APPARATUS FOR MANAGING DEFECTIVE AREAS ON WRITE-ONCE TYPE OPTICAL DISC USING TDMA INFORMATION - A recording medium of writable once type, and a method and apparatus for managing a defective area on the recording medium are provided. The method includes detecting an existence of a defective area within a data area of the recording medium once data are written onto the data area in a data writing operation; writing data written in the defective area onto a spare area of the data area if the defective area is detected; writing temporary management information pertaining to the defective area, onto a temporary management area on the recording medium; and writing access information for accessing the temporary management information, onto a reserved area on the recording medium. | 2009-05-07 |
| 20090116352 | CLOCK GENERATING APPARATUS, MAGNETIC DISK APPARATUS, AND WRITE SYNCHRONIZATION METHOD - A recording apparatus detects a preamble, which is a series of patterns formed on a track, and generates a clock based on the preamble. The recording apparatus then detects a Sync mark, which is a predetermined pattern formed between the preamble and a Resync mark, calculates a predicted position of the next Resync, and switches PLL gain to a low level. The recording apparatus then detects the Resync mark, which is a pattern of equal to or more than one pulse, and corrects the generated clock. Specifically, upon detecting the Resync mark, the recording apparatus compares a timing of the predicted position of the Resync, and the timing at which the Resync mark is actually detected to correct a write clock. | 2009-05-07 |
| 20090116353 | Circuits, Architectures, Apparatuses, Systems, Algorithms and Methods and Software for Timing Calibration for Optical Disc Recording - The present disclosure relates to methods, software, and apparatuses for correcting reading and/or writing operations in an optical storage medium. The methods generally include reading a region of an optical storage medium to produce a readback signal, measuring timing offsets for a plurality of the data edges (including one or more non-guide edges), and storing an offset correction for at least one of the plurality of edges based on a measured offset of at least one of the plurality of edges relative to a predetermined offset. The disclosure advantageously enables precise measurement of timing offsets in optical storage media and correction of the measured offsets for timing offsets attributable to edge jitter, timing loop drift, or factors independent of variations in the medium and/or write operation characteristics. | 2009-05-07 |
| 20090116354 | Recording parameter setting device, program thereof, computer-readable recording medium containing the program, information recording medium, recording/reproducing device, and recording parameter setting method - A recording parameter setting device including a trial recording parameter setting section and a reproduced signal quality judging section. The reproduced signal quality judging section judges whether or not a reproduced signal obtained by reproduction of the trial recording carried out in accordance with the trial recording parameter satisfies a predetermined reproduced signal quality. If no, the recording parameters of the predetermined recording mark length or longer are further classified into detailed groups and trial recording is carried out again. If the reproduced signal satisfies the predetermined reproduced signal quality, the reproduced signal quality judging section sets the trial recording parameters as a recording parameter. This makes it possible to form a recording mark capable of surely providing a good reproduced signal quality while the number of recording parameters to be used is reduced. | 2009-05-07 |
| 20090116355 | METHOD AND APPARATUS FOR ACCESSING A DISC - A record carrier of rewritable type, such as a BD-RE, is operable to perform multiple write operations. Optionally, such a record carrier can nevertheless be treated as a one time recordable record carrier, opening new opportunities for the users, like for example offering a level of protection of user-data therein recorded against unintentional subsequent erasure. The apparatus and method according to the invention enable the logical formatting of the BD-RE disc as a BD Write Once disc. | 2009-05-07 |
| 20090116356 | METHOD FOR RECORDING A VISUALLY DETECTABLE PATTERN ON AN OPTICAL RECORD CARRIER, APPARATUS FOR RECORDING A VISUALLY DETECTABLE PATTERN ON A RECORD CARRIER AND INSTRUCTION TO BE EXECUTED BY THE APPARATUS - An apparatus is described for recording a visually detectable pattern on a record carrier ( | 2009-05-07 |
| 20090116357 | REPRODUCING APPARATUS - In a reproducing apparatus, a reading unit reads an information signal from a storage medium, and a converter converts the information signal reproduced by the reading unit into a first digital signal by sampling the information signal in accordance with a reference clock signal with a predetermined frequency higher than the frequency of the information signal. An oversampling unit generates a second digital signal by increasing the number of samples of the first digital signal output from the converter. A data detector selects two adjacent samples from the second digital signal on the basis of the frequency of the information signal reproduced by the reading unit and a phase change of the information signal. The data detector then generates read data using the selected samples of the digital signal. | 2009-05-07 |
| 20090116358 | INFORMATION RECORDING MEDIUM AND REPRODUCING APPARATUS THEREFOR - An environmental load information of an information recording medium is recorded on the information recording medium so as to recycle or dispose properly an information recording medium, which is not necessary any more. The information recording medium comprises a main information area ( | 2009-05-07 |
| 20090116359 | OPTICAL SCANNING DEVICE - An optical scanning device for scanning an information layer of a first optical record carrier having a first cover layer thickness and an information layer of a second optical record carrier having a second, different cover layer thickness. The device includes an objective lens system for converging a radiation beam on the information layers. The objective lens system includes a first lens element and a second lens element spaced apart along an optical axis. The objective lens system further includes a switchable optical element comprising a first fluid, and a chamber positioned between said first lens and said second lens. The objective lens system is switchable between a first configuration in which the first fluid occupies an optically active portion of the chamber such that the objective lens system has a first focal length for scanning the information layer of the first optical record carrier, and a second configuration in which the first fluid does not occupy the optically active portion of the chamber such that the objective lens system has a second, different focal length for scanning the information layer of the second optical record carrier. The objective lens system is arranged to satisfy the condition: Focal | 2009-05-07 |
| 20090116360 | OPTICAL RECORDING MEDIUM, OPTICAL RECORDING DEVICE, AND OPTICAL REPRODUCING DEVICE - An optical recording medium has a first recording layer, and a second recording layer contiguous to the first recording layer in a laminated direction. A recording operation is performed with respect to the first recording layer and the second recording layer in such a manner that frequency bands of reproducing signals are different from each other. | 2009-05-07 |
| 20090116361 | Recording Method, Recording and Reproducing Method, Reproducing Method, Recording Device, Recording and Reproducing Device, and Reproducing Device for Optical Information Recording and Reproducing Medium, and the Optical Information Recording and Reproducing Medium - Optical information recording and reproducing medium | 2009-05-07 |
| 20090116362 | OPTICAL RECORD CARRIER WITH A VISUALLY DETECTABLE PATTERN AS WELL AS AN APPARATUS AND A METHOD FOR RECORDING A VISUALLY DETECTABLE PATTERN ON AN OPTICAL RECORD CARRIER. - A system is described comprising an optical record carrier and an apparatus for recording the optical record carrier. The apparatus comprises a facility ( | 2009-05-07 |
| 20090116363 | INFORMATION STORAGE DEVICE AND STORAGE MEDIA - In an information memory apparatus having minute areas for storing information arranged in x, y and z directions three-dimensionally, parallel rays are irradiated to a memory area MA in a direction perpendicular to a z-axis to take projection images of the memory area MA while rotating the memory area MA around the z-axis little by little. The light rays irradiated at this time have a size which covers at least a direction of an x-y plane of the memory area. A computation unit PU finds data and addresses of minute areas distributed three-dimensionally by performing computation based upon the principle of computer tomography on the projection images. As for data writing, a change is given to optical transmissivity or light emission characteristics by irradiating laser light focused by a lens OL placed outside the memory area to a desired minute area and causing heat denaturation within the pertinent minute area. | 2009-05-07 |
| 20090116364 | OPTICAL PICKUP DEVICE - An optical pickup device according to the present invention includes: a first light source that outputs a first laser beam; a second light source that outputs a second laser beam; and an optical system that irradiates an information medium with the first and second laser beams. The information medium includes: an information layer on which user data is written; and a recording layer on which visible information, which is directly visible to a user, is recorded. The optical pickup device is characterized by outputting the first laser beam in writing the user data on the information layer but outputting the second laser beam in recording the visible information on the recording layer. | 2009-05-07 |
| 20090116365 | Optical Recording Medium and Optical Recording Method - An optical recording method to record information with a mark length recording method, where an amorphous mark and a crystal space are recorded only in the groove of a substrate having a guide groove, with the temporal length of the mark and the space of nT (T denotes a reference clock period; n denotes a natural number). The space is formed at least by an erase pulse of power P | 2009-05-07 |
| 20090116366 | Preload Modulation to Reduce Head Motion Hysteresis - An apparatus includes a data storage media and a plurality of heads, the data storage media and heads being structured and arranged for relative movement between the heads and storage media causing the heads to move along a scan path, and an actuator for changing a magnitude of head to media force as the heads move along the scan path. A method for reducing head motion hysteresis is also provided. | 2009-05-07 |
| 20090116367 | FERROELECTRIC RECORD CARRIER, ITS METHOD OF MANUFACTURE AND MICRO-TIP RECORDING SYSTEM INCORPORATING SAME - The present invention relates to a data record carrier of the type with ferroelectric memory layer, its method of manufacture and a micro-tip recording system incorporating same. The invention applies in particular to computer-based or multimedia applications requiring high memory capacities. A record carrier according to the invention comprises a substrate, a counter-electrode deposited on the substrate and intended to cooperate with an electrode of a data reading and/or writing device, and at least one ferroelectric memory layer which is able to store these data and which exhibits a first face in close contact with said counter-electrode. According to the invention, the counter-electrode is made of a substance comprising a carbonaceous material chosen from the group consisting of carbon in the form of graphite or amorphous diamond, the carbides of a metallic or non-metallic element with the exclusion of ionic carbides, and their mixtures. | 2009-05-07 |
| 20090116368 | METHOD AND SYSTEM FOR DETERMINING DISC FORMAT FOR RECOVERY OF DATA RECORDING - A method for determining a disc format is disclosed. Data from at least one address of the disc is retrieved, wherein the at least one address is selected from a plurality of predetermined addresses related to the disc format. The disc format is determined according to the retrieved data. | 2009-05-07 |
| 20090116369 | OPTICAL INFORMATION RECORDING MEDIUM - An optical information recording medium includes a disk-like substrate having a hole in a central portion thereof, and a light-reflective layer, a dye recording layer containing an organic dye, an intermediate layer composed of an inorganic substance, and a light-transmissive layer composed of a resin disposed in that order on one principal surface of the substrate, in which information is recorded/reproduced by irradiation of laser light from the light-transmissive layer side. In the optical information recording medium, the light-transmissive layer covers a surface of the intermediate layer from an inner peripheral edge of the intermediate layer to an outer peripheral edge of the intermediate layer, and a vicinity of an outer peripheral edge of the light-transmissive layer is in contact with the substrate in an annular region extending around an outer peripheral side of the substrate. | 2009-05-07 |
| 20090116370 | RECORDING MEDIUM HAVING A SUBSTRATE CONTAINING MICROSCOPIC PATTERN OF PARALLEL GROOVE AND LAND SECTIONS AND RECORDING/REPRODUCING EQUIPMENT THEREFOR - An information recording medium | 2009-05-07 |
| 20090116371 | RECORDING MEDIUM HAVING A SUBSTRATE CONTAINING MICROSCOPIC PATTERN OF PARALLEL GROOVE AND LAND SECTIONS AND RECORDING/REPRODUCING EQUIPMENT THEREFOR - An information recording medium | 2009-05-07 |
| 20090116372 | OPTICAL RECORDING MEDIUM - There is disclosed an optical recording medium having at least a recording layer provided on a light-transmissive substrate having grooves and lands with prepits, wherein said lands are generally rectangular or trapezoidal in cross section having a top surface and sidewalls, as well as a specified land height (h | 2009-05-07 |
| 20090116373 | SIGNAL PROCESSOR HAVING A SAMPLING ARRANGEMENT - In a signal processor, a sampling arrangement (SH | 2009-05-07 |
| 20090116374 | ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING SYNCHRONIZATION - Embodiments are directed to first and second OFDM pilot symbols. The first and second pilot symbols may have first and second sets, respectively, of allowed, forbidden, and active carrier frequencies. The second sets of carrier frequencies may be formed by frequency shifting the respective first sets by a predetermined frequency, such as the frequency difference between adjacent carriers. An embodiment is directed to frequency translating part of a first received pilot symbol by one carrier interval in a first direction, frequency translating part of a second received pilot symbol by one carrier interval in a second direction that is opposite from the first direction, and forming a correlation by multiplying the frequency translated parts of the first and second pilot symbols by complex conjugates of parts of the pilot symbols upon which frequency translation has not been performed, and summing the multiplication results. | 2009-05-07 |
| 20090116375 | METHOD AND APPARATUS FOR SPACE-TIME CODING AND DECODING - The present invention relates to methods for space-time coding and decoding in a wireless communication system with multiple antennas including: generating an orthogonal matrix according to signals to be transmitted; generating a coefficient matrix corresponding to the orthogonal matrix according to channel status information received; and generating a transmission matrix according to the orthogonal matrix and the coefficient matrix; performing a weight-combination for received signals according to channel status information in a receiver; and obtaining estimations of transmitted signals corresponding to the received signals by performing detection for the received signals. The present invention also provides apparatuses for space-time coding and decoding. By applying the present invention, the bit error rate of a system is reduced and bit error performance of the system is improved. And the transmission rate of the system is increased remarkably when there are more than one complex signals to be transmitted. | 2009-05-07 |
| 20090116376 | METHOD FOR COMMON TRANSMISSION OVER MULTIPLE LINE PAIRS, AND TRANSMITTING END AND RECEIVING END THEREFOR - The present disclosure discloses a method for common transmission over multiple line pairs, and a transmitting device and a receiving device therefor. The method for common transmission over multiple line pairs includes: modulating information to be sent; and sending a modulated signal to a receiving device over the multiple line pairs; wherein, a transmission spectrum of each transmitter in the multiple line pairs comprises two parts: a first part is a frequency segment that meets a bearer condition of a modulation method, and a second part is a frequency segment that does not meet the bearer condition of the modulation method. | 2009-05-07 |
| 20090116377 | Early service loss or failure indication in an unlicensed mobile access network - An Unlicensed Mobile Access Network Controller (UNC) and method for providing an early indication of service failure to a mobile station registered with the UNC. When the UNC detects a network failure that prevents service to the mobile station, the UNC prohibits new registrations by other mobile stations, starts a timer, and monitors the network failure to determine if the failure clears. If the failure clears before the timer expires, new registrations are accepted from other mobile stations. However, if the timer expires before the failure clears, the UNC continues to prohibit new registrations from other mobile stations, and deregisters the mobile station when a network Keep Alive timer expires for the mobile station. When a plurality of mobile stations are registered with the UNC, the UNC deregisters the plurality of mobile stations one at a time as the network Keep Alive timer expires for each mobile station. | 2009-05-07 |
| 20090116378 | Method for handling radio link failure in wireless communications system and related apparatus - After radio link failure is detected, a wireless communications system handles the radio link failure efficiently by utilizing at least two first timers in a first entity or at least two second timers in a second entity to perform radio link recovery or re-establishment to determine when to enter an idle mode or when to release radio resource. | 2009-05-07 |
| 20090116379 | Insufficient bandwidth notification for transmission of multimedia program - A network connection is established between a multimedia viewer at a viewer's premises and a service provider. The viewer requests presentation of a multimedia channel via the multimedia viewer. In response to the request, an available bandwidth of the network connection is determined, as is a bandwidth requirement of the requested multimedia channel. In response to determining the bandwidth requirement is inconsistent with the available bandwidth, the viewer is provided with an indicator that the first multimedia channel is unavailable for presentation by the multimedia receiver. In response to determining the bandwidth requirement is consistent with the available bandwidth, data representing the content of the requested multimedia channel is transmitted to the multimedia receiver for presentation to the viewer. | 2009-05-07 |
| 20090116380 | QUALITY OF SERVICE MANAGEMENT FOR MESSAGE FLOWS ACROSS MULTIPLE MIDDLEWARE ENVIRONMENTS - A method of managing information system resources to provide a message flow having a consistent level of quality of service (QoS) within and across a plurality of interconnected middleware domains is described. The method includes receiving a QoS message from a first QoS manager expressing at least one QoS requirement, translating the at least one QoS requirement to at least one parameter specific to a messaging service that communicatively couples multiple middleware domains, creating a client connection between a first middleware domain and the messaging service for receiving the message flow, transmitting the QoS message to a second middleware domain, and creating a client connection between the messaging service and the second middleware domain for transmitting the message flow. | 2009-05-07 |
| 20090116381 | METHOD AND SYSTEM FOR CONGESTION MANAGEMENT IN A FIBRE CHANNEL NETWORK - One embodiment of the present invention provides a system that facilitates congestion management in a Fibre Channel (FC) network. During operation, the system determines a threshold data rate on an outgoing link coupled to an FC switch. The system further determines the number of sources that send data to the outgoing link and an aggregate arrival rate of data for the outgoing link. Next, the system determines an injection data rate for a respective source based on the threshold data rate on the outgoing link, the number of sources transmitting data to the outgoing link, and the aggregate arrival data rate for the outgoing link. Subsequently, the system communicates the injection data rate to the source, thereby allowing the source to throttle its data injection in the FC network to prevent network congestion. | 2009-05-07 |
| 20090116382 | RESOURCE AND ADMISSION CONTROL SUBSYSTEM AND METHOD THEREOF IN NGN - A Resource and Admission Control Subsystem (RACS) in an NGN includes: a Resource Control Function in access network (A-RCF), an Access Admission Control Function (A-ACF), a Resource Control Function in core network (C-RCF), an Interconnection Admission Control Function (I-ACF), and corresponding interfaces. As a logically independent subsystem, RACS can support transport QoS requirements of multiple service subsystems (including IP multimedia service subsystem and PSTN/ISDN service emulation subsystem) simultaneously, implement QoS control for interconnecting links between different administrative domains, balance network load, prevent congestion (especially at bottle necks of network resources), support necessary measurement and protection mechanisms on the transport layer, and solve the problem of competition for transport resources among NGN traffics in the network administrative domains. | 2009-05-07 |
| 20090116383 | Providing Single Point-of-Presence Across Multiple Processors - A method for providing single point-of-presence for a network element includes receiving a packet at a network processor, determining if the packet is to be directed to a particular one of a plurality of traffic processors if a source address of the packet is associated with a subscriber terminal, and determining if the packet is to be directed to the particular one of the plurality of traffic processors if a destination address of the packet is associated with the subscriber terminal. The method further includes distributing the packet to the particular one of the plurality of traffic processors. | 2009-05-07 |
| 20090116384 | APPARATUS AND METHOD FOR CONNECTION ADMISSION CONTROL IN BROADBAND WIRELESS ACCESS SYSTEM - An apparatus and method for Connection Admission Control (CAC) in a Broadband Wireless Access (BWA) system are provided. In the method, a QoS class of a call requesting connection admission is detected and an application layer required bandwidth is determined using the QoS parameters of a service flow of the detected QoS class. A required bandwidth weight of the QoS class is determined in consideration of a packet header overhead. Per-slot available bandwidths of a reference QoS class and the QoS class are determined using the determined application layer required bandwidth, and a required bandwidth conversion ratio of a corresponding QoS class is determined using the determined per-slot available bandwidths. An equivalent MAC layer required bandwidth is determined using the determined application layer required bandwidth, the required bandwidth weight, and the required bandwidth conversion ratio. | 2009-05-07 |
| 20090116385 | BASE STATION CONTROL APPARATUS AND DOMAIN ACCESS REGULATING METHOD - Upon deciding to start domain access regulation, regulation controller ( | 2009-05-07 |
| 20090116386 | Overload Protection of a TMN System - To protect an overloading of a central controller OS of a TMN system, messages N received by network elements are assigned to different classes, thereby resulting in class specific loads. Those messages N which are assigned a class K with a class specific load overloading the controller are protected. | 2009-05-07 |
| 20090116387 | BANDWIDTH CONTROL CIRCUIT AND BANDWIDTH CONTROL METHOD USED FOR THE SAME | 2009-05-07 |
| 20090116388 | Vehicle Communication Method and Communication Device - In a vehicle communication method in which communication between a plurality of communication devices is performed and an amount of communication data sent from each communication device is changed, features are as follows. That is, if the amount of communication data sent from the first communication device is to be increased, the amount of communication data sent from the second communication device is decreased so that a total sum of the amounts of communication data sent from all the communication devices does not exceed a predetermined value. | 2009-05-07 |
| 20090116389 | RESOURCE SCALING IN WIRELESS COMMUNICATION SYSTEMS - Systems and methodologies are described that facilitate resource scaling for inter-access point fairness in a wireless communication system. As described herein, an offered load of an access point can be determined based on one or more loading metrics relating to associated terminals, throughput, data rate, quality of service (QoS), or the like. Based on the determined offered load of an access point, resources used by the access point and/or power utilized for communication over those resources can be scaled based on a comparison of the offered load of the access point to a nominal or default offered load. Centralized techniques for resource scaling are described herein, wherein one or more centralized controllers coordinate resource scaling with respective access points via backhaul messaging. In addition, distributed techniques for resource scaling are described herein, wherein neighboring access points communicate with each other via over-the-air messaging to determine a local optimal resource apportionment. | 2009-05-07 |
| 20090116390 | SCHEDULING BEST EFFORT FLOWS IN BROADBAND WIRELESS NETWORKS - Systems and methodologies are described that facilitate scheduling best effort flows in broadband or wideband wireless communication networks. The systems can include devices and/or component that effectuate associating utility functions to multiple disparate flows based on traffic conditions extant in the wireless system, ascertaining the average rate at which the flow has been serviced in the past, and utilizing the utility function associated with the flow or the average rate that the flow has been serviced in the past to optimally schedule the flow. | 2009-05-07 |
| 20090116391 | METHOD FOR DATA FLOW CONTROL IN A MOBILE COMMUNICATIONS SYSTEM - The invention relates to a method for controlling the flow of data between an RNC (R) and a base station (BS) of a UMTS mobile communications system with HSDPA capability via an lub interface (I | 2009-05-07 |
