| 19th week of 2009 patent applcation highlights part 15 |
| Patent application number | Title | Published |
|---|
| 20090114992 | Mixed gate CMOS with single poly deposition - A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation. In this latter case the oxidized protective material is incorporated into the metal gate stack, which incorporation results in a novel CMOS structure. | 2009-05-07 |
| 20090114993 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a silicon substrate; a P channel type field effect transistor including a first gate insulating film on the substrate, a first gate electrode on the first gate insulating film and a first source/drain region; and an N channel type field effect transistor including a second gate insulating film on the substrate, a second gate electrode on the second gate insulating film and a second source/drain region. The entire first gate electrode is made of a metal silicide, and at least in an upper portion including the upper surface of the second gate electrode, a silicide region of the same kind as the metal (M) is provided. The metal concentration in the silicide region is lower than that in the silicide of the first gate electrode. In an upper portion including the upper surface of the second gate electrode, there is a barrier layer region containing a metal diffusion suppressing element at a concentration higher than that in the lower portion. | 2009-05-07 |
| 20090114994 | STRUCTURE OF MTCMOS CELL AND METHOD FOR FABRICATING THE MTCMOS CELL - An architecture of the layout of the MTCMOS standard cell designed for low power consumption is supplemented so that the pick-up cells are included in the power line of the MTCMOS cell. Therefore, when the logic circuit is constructed using the library layout of the MTCMOS cell in which the related pick-up cells are not included, pick-up cells consisting of only the ends of the pick-up cells are not needed every 50 μm during the placement of the MTCMOS standard cell. The flexibility of the cell placement may thereby be improved. In addition, since additional space for the pick-up cells is not required, the size of the MTCMOS may be reduced, saving space on the semiconductor substrate. | 2009-05-07 |
| 20090114995 | COMPLEMENTARY SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film. | 2009-05-07 |
| 20090114996 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate having first and second regions on a surface thereof, a first conductivity type first MISFET formed in the first region and a second conductivity type second MISFET formed in the second region. The first MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate and a first insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film and which has a first element forming electric dipoles that reduce a threshold voltage of the first MISFET and the second MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate, and a second insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film formed on the surface of the substrate and which has a second element forming electric dipoles in a direction opposite to that in the first MISFET. | 2009-05-07 |
| 20090114997 | REDUCED METAL PIPE FORMATION IN METAL SILICIDE CONTACTS - Formation of metal pipes resulting from formation of metal silicide contacts are reduced or avoided. To reduce formation of metal pipes, an epitaxial layer is formed over the diffusion region on which the metal silicide contact is formed. The epitaxial layer reduces defects which enhances diffusion of metal atoms or molecules. | 2009-05-07 |
| 20090114998 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME - A first MIS transistor is formed in a low voltage transistor formation region and includes a gate insulating film and a first gate electrode composed of a metal film and a polycrystalline silicon film. A second MIS transistor is formed in a high voltage transistor formation region and includes a gate insulating film and a second gate electrode composed of a polycrystalline silicon film. An equivalent oxide thickness of the gate insulating film formed in the low voltage transistor formation region is thinner than an equivalent oxide thickness of the gate insulating film formed in the high voltage transistor formation region. A level of the surface of a semiconductor substrate in the low voltage transistor formation region is higher than a level of the surface of a semiconductor substrate in the high voltage transistor formation region. | 2009-05-07 |
| 20090114999 | TRANSISTORS OF SEMICONDUCTOR DEVICE HAVING CHANNEL REGION IN A CHANNEL-PORTION HOLE AND METHODS OF FORMING THE SAME - According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions. | 2009-05-07 |
| 20090115000 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same includes forming a poly-gate including a first poly-gate portion and a second poly-gate portion on and/or over a semiconductor substrate, forming a trench having a predetermined depth in the poly-gate, implanting dopant ions into the entire surface of the semiconductor substrate and the poly-gate including the trench, forming a contact barrier layer to cover a portion of the poly-gate including the trench while exposing an upper surface of the remaining portion of the poly-gate on which a contact will be formed, and forming a contact on the exposed upper surface of the poly-gate. | 2009-05-07 |
| 20090115001 | MOS DEVICES WITH MULTI-LAYER GATE STACK - An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor. | 2009-05-07 |
| 20090115002 | Semiconductor Device - There is provided a semiconductor device including: a first field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in a P channel forming region; and a second field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in an N channel forming region on a semiconductor substrate, wherein in the first and second field effect transistor regions, the gate electrodes are composed primarily of a silicide of metal M represented as M(x)Si(1−x)(0| 2009-05-07 | |
| 20090115003 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a stacked layer including a tungsten layer, forming a hard mask pattern over the stacked layer, and oxidizing a surface of the hard mask pattern to form a stress buffer layer. A portion of the stacked layer uncovered by the hard mask pattern is removed using the hard mask pattern and the stress buffer layer as an etch mask, thereby forming a first resultant structure. A capping layer is formed over the first resultant structure, the capping layer is etched to retain the capping layer on sidewalls of the first resultant structure, and the remaining portion of the stacked layer uncovered by the hard mask pattern is removed. | 2009-05-07 |
| 20090115004 | SURFACE ACOUSTIC WAVE SENSOR ASSEMBLIES - The invention is directed to a surface acoustic wave sensor assembly that makes use of a Z-axis conductive layer, such as a Z-axis conductive elastomer, or the like. In particular, a Z-axis conductive elastomer couples a circuit layer to a surface acoustic wave (SAW) sensor in order to form a SAW sensor assembly. For example, a plurality of electrical contacts of the circuit layer can be coupled to a plurality of electrodes of the SAW sensor via the Z-axis conductive elastomer. The Z-axis conductive elastomer provides electrical coupling between the electrical contacts and the electrodes, and also forms a hermetic barrier between the circuit layer and the SAW sensor. In addition, elastic properties of the Z-axis conductive elastomer may reduce pressure exerted on the SAW sensor during use. | 2009-05-07 |
| 20090115005 | Semiconductor IC and manufacturing method of the same - There are disclosed a semiconductor IC whose constitution can be miniaturized to facilitate manufacturing and improve a production efficiency, and a manufacturing method of the semiconductor IC. The manufacturing method of the semiconductor IC includes: forming a wiring line and a circuit element at a front surface of a silicon substrate; forming a concave portion to store a vibration element in a back surface of the silicon substrate by reactive ion etching; forming through holes which pass through the front surface of the silicon substrate and the concave portion in the back surface of the silicon substrate; forming electrode pads on the through holes on the side of the concave portion; storing the vibration element in the concave portion to connect the electrode pads to the vibration element by bump adhesion or adhesion using a conductive adhesive; and sealing the vibration element with a cover. | 2009-05-07 |
| 20090115006 | SOI substrate and semiconductor acceleration sensor using the same - According to the present invention, a SOI substrate includes a first silicon substrate having first and second surfaces; a second silicon substrate having first and second surfaces; and a first insulating layer formed between first surface of the first silicon substrate and the first surface of the second silicon substrates. The first surface of the first silicon substrate is partly depressed to form a thin-layer region thereat. The first insulating layer is formed at least in the thin-layer region. | 2009-05-07 |
| 20090115007 | MEMES PACKAGE STRUCTURE - A package structure including a chip, a lid, a substrate, a plurality of wires, an encapsulant, and a moisture resistive layer is provided. The chip has an active area where at least one MEMS device is disposed. The lid is covered on the chip, and the substrate is used to carry the chip and the lid. The plurality of wires is electrically connected between the substrate and the chip. The encapsulant is sealed around the lid and exposes an upper surface of the lid. The moisture resistive layer is covered on the encapsulant to enhance the airtightness and the moisture resistance of the encapsulant. | 2009-05-07 |
| 20090115008 | MANUFACTURING METHOD OF AN ELECTRONIC DEVICE INCLUDING OVERMOLDED MEMS DEVICES - A method manufactures an electronic device comprising a MEMS device overmolded in a protective casing. The MEMS device includes an active surface wherein a portion of the MEMS device is integrated, and is sensitive, through a membrane, to chemical/physical variations of a fluid. Prior to the molding step, at least one resin layer is formed on at least one region overlying the active surface in correspondence with the membrane. After, at least one portion of at least one resin layer is removed from at least one region, so that in the region an opening is formed, through which the MEMS device is activated from the outside of the protective casing. | 2009-05-07 |
| 20090115009 | Multibit electro-mechanical memory device and manufacturing method thereof - Provided are a multibit electro-mechanical memory device and a method of manufacturing the same. The device may include at least one bit line in a first direction on a substrate; at least one gate line and at least one lower word line in parallel by a given interval and in a second direction intersecting the first direction on the at least one bit line; at least one contact pad adjacent to the at least one gate line on the at least one bit line; and at least one cantilever electrode coupled to the at least one contact pad, configured to float with a void above and beneath the at least one cantilever electrode and configured to curve in a third direction vertical to the first and second directions. | 2009-05-07 |
| 20090115010 | PACKAGE FOR STRAIN SENSOR - The invention relates to a package for a strain sensor. The package includes a base part ( | 2009-05-07 |
| 20090115011 | Solid-state imaging device and production method thereof - A solid-state imaging device includes a plurality of photodiode regions arranged in an array, a non-transparent border region existing around each photodiode region, and a microlens array including a plurality of microlenses arranged in an array corresponding to the plurality of photodiode regions; wherein each microlens functions to converge incident light advancing straight toward the non-transparent border region around the corresponding photodiode region into that photodiode region, and the microlens array is formed using a transparent diamond-like carbon (DLC) film, the DLC film including a region where its refractive index is modulated corresponding to each microlens, and a light-converging effect being caused when light flux passes through the region where the refractive index was modulated. | 2009-05-07 |
| 20090115012 | DUAL IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - Embodiments relate to a dual image sensor which includes a first device including a first wafer having a first inclined step, a first reflective face on an inclined plane on the first inclined step, at least one first microlens over a lower end surface adjacent the first inclined step, and a first via-hole filled with metal on an upper end face adjacent the first inclined step. A second device in the dual image sensor includes a second wafer having a second inclined step, a second reflective face on an inclined plane on the second inclined step, and at least one second microlens over a first portion of an upper end face adjacent the second inclined step. A dual image sensor is formed by connecting the metal in the first via-hole and the metal in the second via-hole together. The dual image sensor is capable of imaging light incident from one or both sides as well as light incident in front or rear of the image sensor. | 2009-05-07 |
| 20090115013 | Image Sensor and Method for Manufacturing the Same - Disclosed is a method for manufacturing an image sensor capable of inhibiting bridge formation between microlenses and minimizing gaps between microlenses. A photodiode and circuitry can be formed on a substrate according to unit pixel. A color filter layer can be formed on the substrate with color filters corresponding to each photodiode. A planarization layer can be formed on the color filter layer, and a groove can be formed in the planarization layer at a boundary between pixels. In one embodiment, the groove can be formed by performing an ashing process with respect to a general photoresist pattern. In another embodiment, the groove can be formed by performing an ashing process with respect to the photoresist pattern for forming the microlens. A microlens can be formed on the planarization layer such that a region of the microlens fills the groove. | 2009-05-07 |
| 20090115014 | Image Sensor and Method for Manufacturing The Same - Provided is an image sensor and a method for manufacturing the same. The image sensor includes a substrate on which a circuitry including a first lower metal line and a second lower metal line is formed. A lower electrode is formed on the first lower metal line. A separation metal pattern surrounds the lower electrode and connected to the second lower metal line. An intrinsic layer is formed on the lower electrode. A second conductive type conduction layer is formed on the intrinsic layer. An upper electrode is formed on the second conductive type conduction layer. A bias can be applied to the second lower metal line such that the separation metal pattern can provide a Schottky Barrier, directing electrons to the lower electrode and inhibiting crosstalk between pixels. | 2009-05-07 |
| 20090115015 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor includes defining an active region in a substrate by forming a device isolating layer; and then sequentially forming a photodiode and a logic unit in the active region; and then forming a first passivation layer on the photodiode and the logic unit; and then forming a trench in the first passivation layer by selectively removing a portion of the first protective layer corresponding to an uppermost surface of the photodiode; and then forming a second passivation layer buried in the trench. Forming a thick second passivation layer in the trench which spatially corresponds to the photodiode can offset dangling bonds on the surface of the substrate in a subsequent annealing process while also reducing dark current and enhance photosensitivity of the photodiode. | 2009-05-07 |
| 20090115016 | OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optical semiconductor device is provided with an n-type epitaxial layer (second epitaxial layer) | 2009-05-07 |
| 20090115017 | SELECTIVE FORMATION OF TRENCHES IN WAFERS - A wafer substrate, such as a silicon wafer substrate, includes at least one selectively formed substrate trench that may be filled with an isolation material to form an isolation surface. The forming process includes converting at least one silicon wall etched into the wafer substrate into a silicon dioxide wall, which in turn creates a substantially larger substrate trench in the wafer substrate. The selectively formed and substantially larger substrate trench may be filled with an isolation material, such as silicon dioxide, through at least one or both of an oxidation growth process and an oxidation deposition process. | 2009-05-07 |
| 20090115018 | Transient voltage suppressor manufactured in silicon on oxide (SOI) layer - A transient voltage-suppressing (TVS) device supported on a semiconductor substrate is applied to protect an electronic device from a transient voltage. The TVS device includes a clamp diode functions with a high-side and a low side diodes for clamping a transient voltage disposed on a top layer of the semiconductor substrate insulated by a insulation layer constituting a TVS on silicon-on-insulator (SOI) device. In an exemplary embodiment, the insulator layer further includes a thick body oxide (BOX) layer having a thickness in the range of 250 Angstroms to 1 micrometer to sustain an application with a breakdown voltage higher than 25 volts. In another exemplary embodiment, the clamp diode further surrounded by a P-well and the P-well is formed on top of a P−/P+ substrate layer disposed above the insulator layer. | 2009-05-07 |
| 20090115019 | SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device having an air gap includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A metal line is formed to fill the metal line forming region of the insulation layer. An air gap is formed between the insulation layer and the metal line. | 2009-05-07 |
| 20090115020 | ELECTRICAL FUSE AND METHOD OF MAKING - A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material. | 2009-05-07 |
| 20090115021 | ANTIFUSE ELEMENT IN WHICH MORE THAN TWO VALUES OF INFORMATION CAN BE WRITTEN - An antifuse element includes a plurality of MOS transistors; a first electrode to which source electrodes of the plurality of MOS transistors are commonly connected; a second electrode to which gate electrodes of the plurality of MOS transistors are commonly connected; a third electrode to which at least one of drain electrodes of the plurality of MOS transistors is capable of being connected; and an insulation film provided between the drain electrodes of the plurality of MOS transistors and the third electrode, wherein the insulation on at least one position in said insulation film and that corresponds to one of the drain electrodes is broken down. | 2009-05-07 |
| 20090115022 | SEMICONDUCTOR DEVICE - A semiconductor device | 2009-05-07 |
| 20090115023 | CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A capacitor of a semiconductor device and a method for manufacturing the same. In one example embodiment, a capacitor of a semiconductor device includes a first electrode, first dielectric layer, second electrode, second dielectric layer, and third electrode sequentially formed on a semiconductor substrate. The capacitor also includes a first contact coupled to the first electrode and to the third electrode. The capacitor further includes a second contact coupled to the second electrode. | 2009-05-07 |
| 20090115024 | Seal ring structure with improved cracking protection and reduced problems - An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line. | 2009-05-07 |
| 20090115025 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device may include a chip including a chip including a silicon substrate having a semiconductor device area, a pad area and a scribe lane defining an outer contour of the chip. A semiconductor device may be formed in the semiconductor device area, and a pad electrically connected with the semiconductor device may be formed in the pad area. A crack prevention pattern may be formed on an outer contour of the chip, such that the crack prevention pattern extends from a lowest portion to a highest portion of the semiconductor device. A crack prevention pattern is manufactured such that chip cracking can be prevented during the sawing process. | 2009-05-07 |
| 20090115026 | SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIAS FOR HIGH CURRENT,HIGH FREQUENCY, AND HEAT DISSIPATION - An integrated circuit device ( | 2009-05-07 |
| 20090115027 | Method of Fabricating an Integrated Circuit - A method of fabricating an integrated circuit is disclosed. An etching process is performed in order to create a structure in a substrate. A material layer is generated during the etching process. The material layer is formed from at least one of the group of a Si/C/O composition and/or a Si/metal composition. | 2009-05-07 |
| 20090115028 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor substrate including a single crystal semiconductor layer with a buffer layer interposed therebetween is manufactured. A semiconductor substrate is doped with hydrogen to form a damaged layer containing a large amount of hydrogen. After the single crystal semiconductor substrate and a supporting substrate are bonded, the semiconductor substrate is heated so that the single crystal semiconductor substrate is separated along a separation plane. The single crystal semiconductor layer is irradiated with a laser beam from the single crystal semiconductor layer side to melt a region in the depth direction from the surface of the laser-irradiated region of the single crystal semiconductor layer. Recrystallization progresses based on the plane orientation of the single crystal semiconductor layer which is solid without being melted; therefore, crystallinity of the single crystal semiconductor layer is recovered and the surface of the single crystal semiconductor layer is planarized. | 2009-05-07 |
| 20090115029 | Semiconductor substrate and method for manufacturing the same, and method for manufacturing semiconductor device - A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved | 2009-05-07 |
| 20090115030 | N2 BASED PLASMA TREATMENT FOR ENHANCED SIDEWALL SMOOTHING AND PORE SEALING OF POROUS LOW-K DIELECTRIC FILMS - A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner. | 2009-05-07 |
| 20090115031 | SEMICONDUCTOR DEVICE INCLUDING A COUPLED DIELECTRIC LAYER AND METAL LAYER, METHOD OF FABRICATION THEREOF, AND PASSIVATING COUPLING MATERIAL COMPRISING MULTIPLE ORGANIC COMPONENTS FOR USE IN A SEMICONDUCTOR DEVICE - A material for passivating a dielectric layer in a semiconductor device has a molecular structure permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. The contemplated material may be constituted by multiple organic components. A semiconductor device including a layer of the passivating coupling material, and a method of manufacturing such a semiconductor device are also contemplated. | 2009-05-07 |
| 20090115032 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL CONNECTIVITY - An integrated circuit package system includes: forming a lead having a both top contact portion and a bottom contact portion; connecting an integrated circuit die and the lead; and forming a package encapsulation, having a top side and a bottom side, over the integrated circuit die. The forming the package encapsulation includes partially exposing the top contact portion at the top side, and partially exposing the bottom contact portion along the bottom side with the bottom contact portion extending beyond a nonhorizontal portion of the package encapsulation. | 2009-05-07 |
| 20090115033 | Reduction of package height in a stacked die configuration - A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material. | 2009-05-07 |
| 20090115034 | Semiconductor device - A semiconductor device according to the present invention includes a base tape (film carrier tape); a semiconductor chip mounted on the base tape; conducting leads formed on the base tape to be connected to the semiconductor chip; input terminals and output terminals connected to the conducting leads; and a protecting layer formed to cover the conducting leads completely. The base tape is provided at its side edges with roller-contact regions, where carrier rollers are to be in contact with. No holes and no unevenness area is formed on the roller-contact regions. | 2009-05-07 |
| 20090115035 | INTEGRATED CIRCUIT PACKAGE - Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material. | 2009-05-07 |
| 20090115036 | SEMICONDUCTOR CHIP PACKAGE HAVING METAL BUMP AND METHOD OF FABRICATING SAME - A semiconductor chip package having a metal bump and related method of fabrication are provided. The semiconductor chip package includes first and second bonding pads separated on a substrate, an insulating layer from on the substrate with first and second openings respectively exposing the first and second bonding pads, and an oxidation preventing pattern formed from a nickel layer and a silver layer and formed on the first and second bonding pads. | 2009-05-07 |
| 20090115037 | INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SINK - An IC package and methods for making the same are described. The IC package includes a die and a heat sink that is attached to the back surface of the die with a thermal interface material layer. The heat sink includes a base and a partition. The partition extends around the periphery of the base and is offset from the outer edge of the base such that a ledge region is formed that surrounds the periphery of the base. The inner surfaces of the partition define an inner region that includes heat dissipation structures. A molding material encapsulates at least portions of the die and the ledge region around the periphery of the heat sink while leaving the inner region of the heat sink unencapsulated by molding material and exposed. The molding material covering the ledge region provides a locking feature that secures the heat sink in the package. | 2009-05-07 |
| 20090115038 | Semiconductor Packages and Methods of Fabricating the Same - Provided are semiconductor packages and methods of fabricating the same. An exemplary semiconductor package includes a die pad including a dimple filled with an insulating material in an upper surface or a lower surface thereof. A semiconductor chip is mounted on the upper surface of the first die pad. A package body encapsulates the first die pad and the first semiconductor chip and includes a pinhole. A bottom surface of the pinhole terminates at the insulating material. | 2009-05-07 |
| 20090115039 | High Bond Line Thickness For Semiconductor Devices - Die attach methods used in making semiconductor devices and the semiconductor devices resulting from those methods are described. The methods include providing a leadframe with a die attach pad, using boundary features to define a perimeter on the die pad, depositing a conductive material (such as solder) within the perimeter, and then bonding a die containing an integrated circuit to the die pad by using the conductive material. The boundary features allow an increased thickness of conductive material to be used, resulting in an increased bond line thickness and increasing the durability and performance of the resulting semiconductor device. | 2009-05-07 |
| 20090115040 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ARRAY OF EXTERNAL INTERCONNECTS - An integrated circuit package system includes: forming an array of external interconnects with an intersecting region between the external interconnects; removing the intersecting region for forming an isolation hole between the external interconnects; mounting an integrated circuit die over the external interconnects; connecting an internal interconnect between the integrated circuit die and the external interconnects; and forming a package encapsulation over the integrated circuit die with the external interconnects partially exposed. | 2009-05-07 |
| 20090115041 | Semiconductor package and semiconductor device - A semiconductor package includes an insulating substrate configured to be provided for mounting a semiconductor chip which processes a signal with a frequency in a radio frequency band. The insulating substrate includes a first external connecting electrode, a second external connecting electrode, and a partial antenna wiring. The first external connecting electrode and the second external connecting electrode are connected with the partial antenna wiring. Each of the first external connecting electrode and the second external connecting electrode is an electrode to be connected with an external antenna pattern. | 2009-05-07 |
| 20090115042 | SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STACKED STRUCTURE AND METHOD OF FABRICATING THE SAME - A three-dimensional stacked structured semiconductor device comprising semiconductor circuit layers stacked on a support substrate, and a method of fabricating the device are provided. | 2009-05-07 |
| 20090115043 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING INTERCONNECTS - A mountable integrated circuit package system includes: mounting a first integrated circuit device over a carrier; mounting a substrate over the first integrated circuit device, the substrate having a mounting interconnect; connecting a first electrical interconnect between the carrier and the substrate; and forming a package encapsulation covering the carrier, the first integrated circuit device, the first electrical interconnect, and the substrate with the mounting interconnect partially exposed from and surrounded by the package encapsulation within a cavity of the package encapsulation. | 2009-05-07 |
| 20090115044 | STRUCTURES AND METHODS FOR STACK TYPE SEMICONDUCTOR PACKAGING - Methods and structures for stack type semiconductor packaging are disclosed. In one embodiment, a semiconductor device includes a semiconductor chip mounted onto a substrate, a first resin molding portion formed on the substrate for sealing the semiconductor chip, and a through metal mounted on the substrate so as to pierce the first resin molding portion around the semiconductor chip. The semiconductor device further comprises an upper metal electrically coupled with the through metal and mounted on the first resin molding portion to extend from the through metal toward the semiconductor chip along an upper surface of the first resin molding portion, where the through metal and the upper metal are formed into an integral structure. | 2009-05-07 |
| 20090115045 | Stacked package module and method for fabricating the same - The present invention relates to a stacked package module and a method for fabricating the same. The stacked package module comprises: a first package structure, a second package structure, a ceramic-surfaced aluminum plate, and a metal paste. Herein, the ceramic-surfaced aluminum plate has a plurality of through holes filled with the metal paste to correspond with and electrically connect the first conductive pads of the first package structure and the second conductive pads of the second package structure; and the ceramic-surfaced aluminum plate further has a first cavity to receive a chip. Besides, the present invention provides a stacked package module, which can avoid warpage, omit the process for soldering, favor the shrinkage of size and pitch of the conductive pads, and also can reduce the height of the package. | 2009-05-07 |
| 20090115046 | Micro-electro-mechanical system device and method for making same - According to the present invention, a method for making a micro-electro-mechanical system (MEMS) device comprises: providing a substrate with devices and interconnection formed thereon, the substrate having a to-be-etched region; depositing and patterning an etch stop layer; depositing and patterning metal and via layers to form an MEMS structure, the MEMS structure including an isolation region between MEMS parts, an isolation region exposed upwardly, and an isolation region exposed downwardly, wherein the isolation region exposed downwardly is in contact with the etch stop layer; masking the isolation region exposed upwardly, and removing the isolation region between MEMS parts; and removing the etch stop layer. | 2009-05-07 |
| 20090115047 | Robust multi-layer wiring elements and assemblies with embedded microelectronic elements - An interconnect element | 2009-05-07 |
| 20090115048 | Multipiece Apparatus for Thermal and Electromagnetic Interference (EMI) Shielding Enhancement in Die-Up Array Packages and Method of Making the Same - An integrated circuit (IC) device package is presented. A frame body has opposing first and second surfaces and a central opening that is open at the first and second surfaces. The second frame body surface is mounted to a first stiffener surface. An IC die is mounted to the first stiffener surface within the central opening through the frame body. A planar lid has opposing first and second surfaces. The second lid surface is coupled to the first frame body surface. A first substrate surface is coupled to a second stiffener surface. An array of electrically conductive terminals is coupled to a second substrate surface. The stiffener, frame body, and lid form an enclosure structure substantially enclosing the IC die. The die enclosure spreads heat from the IC die, and shields EMI emanating from and radiating toward the IC die. At least one tab protrudes from the second surface of the frame body. At least one receptacle formed in the first surface of the stiffener corresponding to the at least one tab. The at least one tab is coupled with the at least one corresponding receptacle, whereby structural coupling of said frame body to said stiffener is substantially improved. | 2009-05-07 |
| 20090115049 | SEMICONDUCTOR PACKAGE - A semiconductor package in which an electronic device chip is provided in a cavity of a silicon substrate stacked product constituted by stacking a plurality of silicon substrates. | 2009-05-07 |
| 20090115050 | Interposer And Semiconductor Device - An interposer and a semiconductor device including the interposer are provided, which can prevent thermal warpage of an insulative substrate thereof. The interposer is to be provided together with a semiconductor chip in a semiconductor device and, when the semiconductor device is mounted on a mount board, disposed between the semiconductor chip and the mount board. The interposer includes: an insulative substrate of an insulative resin; an island provided on one surface of the insulative substrate to be bonded to a rear surface of the semiconductor chip via a bonding agent; a thermal pad provided on the other surface of the insulative substrate opposite from the one surface in generally opposed relation to the island with the intervention of the insulative substrate; and a thermal via extending through the insulative substrate from the one surface to the other surface to connect the island to the thermal pad in a thermally conductive manner. | 2009-05-07 |
| 20090115051 | Electronic Circuit Package - An electronic circuit package has a thin-film circuit integrated with the ceramic substrate. The thin-film circuit includes at least two passive circuit elements joined by an integrated electrical interconnect. At least one active power electronic component mounted on the ceramic substrate and is electrically connected with the integrated thin-film circuit. | 2009-05-07 |
| 20090115052 | HYBRID SILICON/NON-SILICON ELECTRONIC DEVICE WITH HEAT SPREADER - A hybrid electronic device incorporating both Si and non-Si semiconductor components, utilizing SiC, diamond, or another highly thermally conductive material as an underlying heat spreader. The hybrid electronic device is comprised of some combination of components fabricated in: (1) the underlying heat spreader itself; (2) a thin Si layer attached to the heat spreader via wafer bonding; and/or (3) a discrete semiconductor electronics die soldered to the heat spreader. | 2009-05-07 |
| 20090115053 | Semiconductor Package Thermal Performance Enhancement and Method - A semiconductor device package and related method are disclosed for providing a semiconductor device encapsulated in a protective package body. The device has an exposed surface to which a thermal compound is applied for improving a thermal path for the egress of heat from the device. Preferred embodiments are disclosed in which a removable cover is attached to the thermal compound for further improved protection during handling. | 2009-05-07 |
| 20090115054 | ELECTRONIC COMPONENT - An electronic component includes: an active surface; a plurality of external connection terminals included in the active surface; a bump electrode disposed to the active surface, the bump electrode including: an internal resin formed on the active surface as a core; and a conductive film on a surface of the internal resin, the internal resin being formed in a nearly half-cylindrical shape having a transverse section of one of a nearly semicircular shape, a nearly semielliptical shape, and a nearly trapezoidal shape and extending orthogonal to the transverse section, the transverse section being orthogonal to the active surface; and a global wiring line disposed on the active surface and connecting between the plurality of external connection terminals, and at least one of the external connection terminals being electrically connected to the conductive film. | 2009-05-07 |
| 20090115055 | MOUNTING STRUCTURE OF ELECTRONIC COMPONENT - A mounting structure of an electronic component includes: a substrate having a terminal and the electronic component which is mounted on the substrate; and a bump electrode included in the electronic component. This bump electrode has an underlying resin provided on an active surface of the electronic component, and a conductive film covering part of a surface of the underlying resin and exposing the rest so as to be electrically continued to an electrode terminal. In this mounting structure, the conductive film of the bump electrode makes direct conductive contact with the terminal, and the underlying resin of the bump electrode elastically deforms so that at least part of an exposed area which is exposed without being covered by the conductive film directly adheres to the substrate. Further, the substrate and the electronic component retain a state of the bump electrode making conductive contact with the terminal by adhesivity of the exposed area of the underlying resin to the substrate. | 2009-05-07 |
| 20090115056 | DEVICE MOUNTING BOARD, SEMICONDUCTOR MODULE, AND MOBILE DEVICE - A device mounting board includes an insulating layer formed of an insulating resin, a glass cloth covering the surface of the insulating layer, and an electrode provided in a through hole extending through the glass cloth. The angle of contact with solder of the glass cloth is larger than that of the resin. Thus, solder bumps are formed on the electrode of the device mounting board | 2009-05-07 |
| 20090115057 | C4 JOINT RELIABILITY - In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump. | 2009-05-07 |
| 20090115058 | Back End Integrated WLCSP Structure without Aluminum Pads - An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line. | 2009-05-07 |
| 20090115059 | GOLD WIRE FOR SEMICONDUCTOR ELEMENT CONNECTION - A gold wire for semiconductor element connection having high strength and bondability. The connection has a limited amount of at least one element selected from calcium and rare earth elements, and a limited amount of at least one element selected from a group consisting of titanium, vanadium, chromium, hafnium, niobium, tungsten, and zirconium. The incorporation of a suitable amount of palladium or beryllium is preferred. The incorporation of calcium and rare earth element can improve the strength and young's modulus of a gold wire, and the incorporation of titanium and the like can reduce a deterioration in the roundness of press-bonded shape of press-bonded balls in the first bonding caused by the incorporation of calcium and rare earth elements. The bonding wire can simultaneously realize mechanical properties and bondability capable of meeting a demand for a size reduction in semiconductor and a reduction in electrode pad pitch. | 2009-05-07 |
| 20090115060 | INTEGRATED CIRCUIT DEVICE AND METHOD - An integrated circuit device includes a semiconductor chip with a metallization layer on the chip. A gas-phase deposited insulation layer is disposed on the metallization layer. | 2009-05-07 |
| 20090115061 | Solving Via-Misalignment Issues in Interconnect Structures Having Air-Gaps - An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer includes a conductive line; a low-k dielectric region adjacent and horizontally spaced apart from the conductive line by a space; and a filler dielectric material filling at least a portion of the space, wherein the filler dielectric material and the low-k dielectric region are formed of different materials. The integrated circuit structure further includes a capping layer over and adjoining the filler dielectric material and the low-k dielectric region. The filler dielectric material has a dielectric constant (k value) less than a k value of the capping layer. | 2009-05-07 |
| 20090115062 | Semiconductor device - A semiconductor device according to the present invention includes: a lower layer wiring made of a conductive material; an etching stopper film laminated on the lower layer wiring; an interlayer insulating film laminated on the etching stopper film; an intermediate film laminated on the interlayer insulating film and made of a material having an etching selectivity with respect to a material of the etching stopper film; an upper wiring layer laminated on the intermediate film; an upper layer wiring made of a metal material having Cu as a main component and embedded in an upper groove formed by digging in from a top surface of the upper wiring layer; and a via for electrically connecting the lower layer wiring and the upper layer wiring made of the same material as the material of the upper layer wiring and disposed in a via hole penetrating through the interlayer insulating film and the intermediate film. | 2009-05-07 |
| 20090115063 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily. | 2009-05-07 |
| 20090115064 | SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES - Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate. | 2009-05-07 |
| 20090115065 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Embodiments relate to a semiconductor device that may include a semiconductor substrate including a cell area and a pad area, a first insulating layer on and/or over the semiconductor substrate, and a first interconnection trench formed in the first insulating layer on and/or over a cell area having a first width. It may also include a first pad trench formed in the first insulating layer on and/or over the pad area and having a second width wider than the first width, and a first metal interconnection formed in the first interconnection trench and a first pad formed in the first pad trench. It may further include a second insulating layer on and/or over the first insulating layer, a second interconnection trench, exposing the first metal interconnection, and a second pad exposing the first pad and having a position and width substantially identical to that of the first pad trench. | 2009-05-07 |
| 20090115066 | Metal wiring layer and method of fabricating the same - A metal wiring layer and a method of fabricating the metal wiring layer are provided. The method includes forming a dielectric layer on a substrate, forming a plurality of dielectric layer patterns and holes therein on the substrate by etching part of the dielectric layer, with a cross sectional area of the holes in the dielectric layer patterns decreasing with increasing distance away from the substrate and the holes exposing the substrate, forming a trench by etching a portion of the substrate exposed through the holes in the dielectric layer patterns, and forming a metal layer which fills the trench and the holes in the dielectric layer patterns. Thus, it is possible to prevent the occurrence of an edge build-up phenomenon by forming a metal layer in a plurality of holes in the dielectric layer patterns having a cross sectional area decreasing with increasing distance away from the substrate. Therefore, it is possible to prevent the transmittance of a liquid crystal layer from decreasing due to a failure to properly fill liquid crystal molecules in the liquid crystal layer, and thus to increase the quality of display. | 2009-05-07 |
| 20090115067 | MODULE HAVING BUILT-IN ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING SUCH MODULE - An electronic component embedded module that can improve reliability of electric connection of inner vias, and a manufacturing method therefor are provided. A first electronic component ( | 2009-05-07 |
| 20090115068 | Semiconductor Device and Method of Manufacturing the Same - Provided are a semiconductor device and a method of manufacturing the same. In the method, a metal interconnection can be formed on a substrate. A dielectric can be formed on the metal interconnection. A photoresist pattern can be formed on the dielectric. The dielectric can be etched using the photoresist pattern as an etch mask to form a dense region of contact holes exposing the metal interconnection and dummy patterns surrounding the region of contact holes. In the semiconductor device, the dummy patterns are disposed around the dense contact holes to minimize a difference between etching rates of the contact holes, thereby inhibiting an etching defect such as an under-etch or over-etch defect. | 2009-05-07 |
| 20090115069 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip package having a molding layer is provided. The semiconductor chip package includes a semiconductor chip, a plurality of external connection terminals, and the molding layer. The semiconductor chip comprises a backside surface, side surfaces, and an active surface having a plurality of chip pads disposed thereon. The molding layer substantially covers the backside surface, the side surfaces, and the active surface of the semiconductor chip and defines at least one opening exposing a portion of the backside surface of the semiconductor chip. A multi-chip package including the semiconductor chip package and a method of manufacturing the semiconductor chip package are also provided. | 2009-05-07 |
| 20090115070 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device includes a semiconductor chip | 2009-05-07 |
| 20090115071 | FLIP CHIP MOUNTING METHOD AND METHOD FOR CONNECTING SUBSTRATES - A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a method for connecting substrates are provided. A circuit board 10 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 21 are disposed in mutually facing relation and a resin 13 containing conductive particles 12 and a gas bubble generating agent is supplied into the space therebetween. In this state, the resin 13 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 13. The resin 13 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof. The resin 13 pushed to the outside is self-assembled in the form of columns between the respective terminals of the circuit board 10 and the semiconductor chip 20. In this state, by pressing the semiconductor chip 20 against the circuit board 10, the conductive particles 12 contained in the resin 13 self-assembled between the facing terminals are brought into contact with each other to provide electrical connection between the terminals. | 2009-05-07 |
| 20090115072 | BGA Package with Traces for Plating Pads Under the Chip - A semiconductor flip-chip ball grid array package ( | 2009-05-07 |
| 20090115073 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a wiring substrate of a semiconductor device, a hollow portion is provided under a pad wiring portion including a connection pad, and thus a wiring layer has a cantilever structure in which the pad wiring portion is formed as an aerial wiring, and a semiconductor chip is flip-chip connected to the connection pad. The pad wiring portion including the connection pad is formed on a sacrifice layer which is filled in a recess portion in an interlayer insulating layer of the wiring substrate, then the semiconductor chip is flip-chip connected to the connection pad, and then the hollow portion is provided by removing the sacrifice layer. | 2009-05-07 |
| 20090115074 | Method of Processing a Contact Pad, Method of Manufacturing a Contact Pad, and Integrated Circuit Element - In a method of processing a contact pad, a passivation layer stack including at least one passivation layer is formed on at least an upper surface of a contact pad region. A first portion of the passivation layer stack is removed from above the contact pad region, wherein a second portion of the passivation layer remains on the contact pad region and covers the contact pad region. An adhesion layer is formed on the passivation layer stack. The adhesion layer is patterned, wherein the adhesion layer is removed from above the contact pad region. Furthermore, the second portion of the passivation layer stack is removed. | 2009-05-07 |
| 20090115075 | METHOD FOR MANUFACTURING THIN SUBSTRATE USING A LAMINATE BODY - Provided is a laminated body comprising a substrate to be ground and a support, where the substrate may be ground to a very small (thin) thickness and can then be separated from the support without damaging the substrate. One embodiment is a laminated body comprising a substrate to be ground, a curable silicone adhesive layer in contact with the substrate to be ground, a photothermal conversion layer comprising a light absorbing agent and a heat decomposable resin, and a light transmitting support. After grinding the substrate surface which is opposite that in contact with the adhesive layer, the laminated body is irradiated through the light transmitting layer and the photothermal conversion layer decomposes to separate the substrate and the light transmitting support. | 2009-05-07 |
| 20090115076 | Vortex Apparatus With Descending Flow Of Phases - The inventive vortex apparatus for carrying out physical-chemical processes is used for. absorption, desorption, dust and gas removal, drying, mixing and gas cooling. Said apparatus comprises a body, lid, bottom, phase delivery and discharging pipes, a vortex contact device having an upper base, tangential plates, a tray, a separator and liquid distributors which are provided with nozzles and arranged on the lid and on the upper base of the vortex contact device. Horizontal disklike partitions are positioned along the height of the tangential plates of the vortex contact device. Said horizontal disklike partitions and the upper base of the vortex contact device are provided with annular slots where the tangential plates are fixed. Annular beads are arranged on the outer and inner cuts of the disklike partitions and on the outer cut of said vortex device's upper base. | 2009-05-07 |
| 20090115077 | Packing elements for mass transfer applications - The invention provides novel ceramic mass transfer packing elements with physical characteristics that maximize efficiency of mass transfer and minimize pressure drop when randomly dumped in a chemical reactor. In some embodiments, the elements may have: a ratio of surface area of the interaction zone to surface area of the flow through zone between 1:0.5 and 1:3; and the interaction zone surface area occupies between 45% and 70% of the open face surface area. | 2009-05-07 |
| 20090115078 | Hollow Fiber System - Disclosed is a hollow fiber system for a humidifier, including hollow fibers that are permeable to steam. A first air flow can be conducted within the hollow fibers while a second air flow can be conducted outside the hollow fibers. The hollow fibers are located at least in part at a distance from each other via a device ( | 2009-05-07 |
| 20090115079 | Valve configuration that increases the capacity and improves the performance of cross-flow trays used in fractionation units of chemical, petrochemical and oil refining process plants - A mass or heat transfer device is provided in the form of a tray with at least one movable or fixed valve covering an opening to prevent liquid flowing in the design flow direction to pass through the opening. | 2009-05-07 |
| 20090115080 | CONVECTOR FOR COOLING OF A FLUID CIRCULATING IN A PIPE - The convector comprises at least one finned tube bundle ( | 2009-05-07 |
| 20090115081 | PRISMATIC MIRROR - A mirror assembly may include a middle portion having a first side, a second side, and a perimeter, where the first side comprises a reflective portion. A front portion may be substantially transparent and may be formed by injecting a first thermoplastic material into a mold on the first side of the middle portion. A back portion may be substantially opaque and may be formed by injecting a second thermoplastic material into the mold on the second side of the middle portion. The front portion and the back portion together may substantially encompass the perimeter of the middle portion. | 2009-05-07 |
| 20090115082 | Method of producing a lens - A method of producing a lens that includes shifting a first die relative to a second die, and pressing an optical material shaped in a preliminary form between the first die and the second die so as to form a lens having a configuration corresponding to a hollow portion formed by the first die and the second die while shifting the first die relative to the second die. The produced lens includes an effective optical surface configured to converge a light flux. The effective optical surface includes a light entrance side, a light exit side, and an optical axis. The effective optical surface is a convex surface shaped such that when a maximum normal line angle is defined as an angle formed between the optical axis and a normal line at the outermost circumference of the effective optical surface, the maximum normal angle is 60° to 90°. | 2009-05-07 |
| 20090115083 | METHOD OF MANUFACTURING PELLET AGGREGATE - A pellet aggregate preferably used in forming a film is obtained by a melt-film forming method. A raw material, which is formed of a cellulose acylate and an additive, is placed in a hopper. The pellet raw material is supplied from the hopper to an extruder, melted therein and extruded as a strand in a water vessel to cool the strand. The strand is then fed into a cutting unit. Washing water is supplied from a water supply unit to a cutting section of the cutting unit. The strand is cut into pellets by the cutting section and the generated powder is recovered by a powder separation unit. After the pellets are separated by a pellet/water separation unit, they are fed to a sieve unit to further remove powder by the sieve. The pellets from which the powder is removed is fed to a vessel and stored as a pellet aggregate. | 2009-05-07 |
| 20090115084 | Slip-casting method of fabricating zirconia blanks for milling into dental appliances - A process for fabricating pre-sintered zirconia blanks that are then computer machined and sintered to form dental appliances having highly advantageous features. The principal steps of a preferred embodiment of that process comprise a) preparing a ceramic slurry of binderless zirconia powder; b) subjecting the slurry to attrition milling; c) preparing a vacuum assisted slip casting mold and pouring the milled slurry into the slip-casting mold; d) after casting, excess slurry is poured from the mold and a consolidated zirconia blank is removed; e) drying the blank and pre-sintering it to form solid blanks ready for CAD/CAM machining and sintering to net shape. | 2009-05-07 |
| 20090115085 | SYSTEM AND METHOD FOR TWO-SHOT MOLDING CRASH PAD - A system and a method for two-shot molding a crash pad, in which a passenger side air bag (PAB) door region is more flexible than other regions is disclosed. The system includes a first resin supply unit, a second resin supply unit, a temperature sensor mounted on a predetermined position of a mold, adjacent to a target material interface, and a controller for controlling a time at which to supply the second resin into the passenger side air bag region based on a detection signal from the temperature sensor. This system is cost effective and can maintain a uniform interface between different types of materials. | 2009-05-07 |
| 20090115086 | Method of Molding System, Including Raising Temperature of Feedstock Responsive to a Calculated Amount of Thermal Energy - Disclosed is a molding-system method, including a temperature-changing operation, including changing temperature of a feedstock being positioned in a barrel assembly from an out-of-barrel temperature to substantially within a processing-temperature range, in response to supplying a calculated amount of thermal energy to the barrel assembly based on a melt throughput being associated with molding articles. | 2009-05-07 |
| 20090115087 | SYSTEM AND METHOD FOR MOULDING COLOURED SYNTHETIC PRODUCTS AND A DYE DISPENSING APPARATUS - The invention relates to a system for moulding coloured synthetic products, comprising at least one moulding apparatus for moulding synthetic products, a dye dispensing apparatus, and at least one collector to collect dispensed dyes comprising. The dye dispensing apparatus comprises a plurality of containers, each container configured to hold a liquid polymer dye, and a dispensing unit for dispensing one or more dyes from one or more of said plurality of containers. The moulding apparatus comprises a connection device configured to connect the collector to the moulding apparatus for introduction of the dispensed dyes in the moulding apparatus. | 2009-05-07 |
| 20090115088 | Process for Producing a Substantially Shell-Shaped Component - Disclosed is a process for producing a substantially shell-shaped component, from substantially carbon-fiber-reinforced synthetic material having at least one local reinforcing zone and at least one stiffening element, in particular a fuselage shell, a wing shell, a vertical stabilizer shell or horizontal stabilizer shell of an aircraft or the like. The process according to the invention comprises the following steps:
| 2009-05-07 |
| 20090115089 | METHOD FOR PRODUCING RESIN STRUCTURE - A macrocell structure | 2009-05-07 |
| 20090115090 | SYSTEM AND METHOD FOR OPTIMIZING TABLET FORMATION BY A ROTARY PRESS MACHINE - Rotary press machine including dies, pairs of upper and lower punches with a part of each lower punch being movable in a respective die to selectively enable formation of a cavity in the die, a feeding system for feeding powder material into the cavities, when present, in a feeding stage, a pressing system for pressing the upper and lower punches together in a pressing stage and a tablet ejection system for ejecting formed tablets from the dies in a tablet ejection stage. The upper and lower punches are rotated sequentially through the feeding stage, the pressing stage and the tablet ejection stage to thereby enable formation of tablets if powder material is feed into the cavities in the dies. To enable selective formation of tablets and thereby optimize production thereof, an adjustment mechanism is provided and enables selective formation of the cavities in the dies. | 2009-05-07 |
| 20090115091 | Method and Device for Granulating Plastics and/or Polymers - The present invention relates to a method for the pelletization of plastics and/or polymers, wherein a melt coming from a melt generator is supplied via a diverter valve having different operating positions to a plurality of pelletizing heads through which the melt is pelletized. The invention furthermore relates to a pelletizing apparatus for the pelletization of plastics and/or polymers having a diverter valve which has at least one melt generator connection, at least two pelletizer connections as well as a switching gate for selectively connecting the melt generator connection to at least one of the pelletizer connections, with a respective pelletizing head being connected to the at least two pelletizer connections and a melt generator having a variable melt volume flow being connected to the melt generator connection. Finally, the invention also relates to a diverter valve for such a pelletizing apparatus having a melt generator connection, a pelletizer connection as well as a melt passage for the connection of the melt generator connection to the pelletizer connection. The present invention therefore starts from the idea of using a plurality of pelletizing heads with different passage capacities and of hereby enlarging the throughput window to be able to work largely continuously without intermediate interruptions and to shorten unavoidable start-up processes by switching in pelletizing heads having small throughput capacities or to minimize them with respect to the start-up products which occur. In accordance with an aspect of the present invention, a plurality of pelletizing heads having different throughput capacities are used sequentially for the start-up of the pelletizing process, with the melt first being supplied to a first pelletizing head having a smaller throughput capacity and then the melt volume flow being increased and the diverter valve being switched over such that the melt is diverted by the diverter valve to a second pelletizing head having a larger throughput capacity. The time and thus the amount of the start-up product until the melt generator reaches the lower throughput limit of the pelletizing head and the pelletizing process can be started are cut by the use of initially one pelletizing head having a throughput capacity which is as low as possible. No further start-up product is incurred from the start onwards of the pelletizing process at the lower throughput limit of the said first pelletizing head. The melt volume flow is increased quantitatively for so long until the diverter valve can be switched to the second pelletizing head having the larger throughput capacity with no start-up product being incurred during this time period. Moreover, the throughput window is enlarged in total so that the number of unavoidable start-up procedures with start-up product arising therein is reduced since it is possible, on a ramping down of the melting performance below the lower throughput limit of the larger pelletizing head which may become necessary for various reasons, to switch back to the first pelletizing head. | 2009-05-07 |
