18th week of 2021 patent applcation highlights part 75 |
Patent application number | Title | Published |
20210134952 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures vertically stacked and separated from one another. The semiconductor structure also includes a gate stack wrapping around the plurality of nanostructures. The semiconductor structure also includes a source/drain feature adjacent to the plurality of nanostructures. The semiconductor structure also includes a semiconductor inner spacer layer interposing between the gate stack and the source/drain feature and interposing between the plurality of nanostructures and the source/drain feature. | 2021-05-06 |
20210134953 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate, a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate, and a third semiconductor stack having a third threshold voltage and comprising a third insulating stack positioned on the substrate. The first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other, a thickness of the first insulating stack is different from a thickness of the second insulating stack and a thickness of the third insulating stack, and the thickness of the second insulating stack is different from the thickness of the third insulating stack. | 2021-05-06 |
20210134954 | SEMICONDUCTOR DEVICE WITH SEPARATE ACTIVE REGION AND METHOD OF FABRICATING THE SAME - The disclosure provides a semiconductor device having a separate active region and a method of fabricating the same. The semiconductor device includes a substrate, a plurality of isolation islands, a source region, and a drain region. The substrate includes a first active region, a second active region, and a plurality of separate active regions. The separate active regions are connected to the first active region and the second active region. The separate active regions and the isolation islands are alternately disposed. The gate structure includes a body portion and a plurality of extensions. The body portion disposed on a portion of the first active region. The extensions are coupled to the body portion and extend from the body portion to the isolation islands. The source region and the drain region are respectively located in the substrate in the first active region and the second active region. | 2021-05-06 |
20210134955 | Methods of Forming Epitaxial Source/Drain Features in Semiconductor Devices - A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature. | 2021-05-06 |
20210134956 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a stack including alternately stacked conductive films and insulating films, wherein the stack includes an opening penetrating the conductive films and the insulating films, and wherein the stack includes a rounded corner that is exposed to the opening. The semiconductor device also includes a first channel film formed in the opening and including a first curved surface surrounding the rounded corner. The semiconductor device further includes a conductive pad formed in the opening, and a second channel film interposed between the first curved surface of the first channel film and the conductive pad. | 2021-05-06 |
20210134957 | SEMICONDUCTOR DEVICE WITH STRAIN RELAXED LAYER - A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride. | 2021-05-06 |
20210134958 | SEMICONDUCTOR DEVICES - A semiconductor device including an active structure on a substrate, the active structure including silicon germanium patterns and silicon patterns alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on sidewalls of the active structure that face in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source/drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction that is perpendicular to the first direction, wherein the silicon germanium patterns are silicon rich-silicon germanium. | 2021-05-06 |
20210134959 | STRUCTURES WITH DOPED SEMICONDUCTOR LAYERS AND METHODS AND SYSTEMS FOR FORMING SAME - Methods and systems for depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, forming a first doped semiconductor layer overlying the substrate, and forming a second doped semiconductor layer overlying the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and wherein the second doped semiconductor layer comprises the first dopant. Structures and devices formed using the methods and systems for performing the methods are also disclosed. | 2021-05-06 |
20210134960 | Silicon Carbide Device with Trench Gate Structure and Method of Manufacturing - A silicon carbide device includes a silicon carbide body having a hexagonal crystal lattice with a c-plane and with further main planes. The further main planes include a-planes and m-planes. A mean surface plane of the silicon carbide body is tilted to the c-plane by an off-axis angle. The silicon carbide body includes a columnar portion with column sidewalls. At least three of the column sidewalls are oriented along a respective one of the further main planes. A trench gate structure is in contact with the at least three of the column sidewalls. | 2021-05-06 |
20210134961 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - After trench etching, trench corner portions are rounded by hydrogen annealing at a temperature of at least 1500 degrees C. Next, n-type regions that cause leak current and are formed in inner walls of the trenches by the hydrogen annealing are removed by a heat treatment (hydrogen etching) under a hydrogen atmosphere of a temperature less than 1500 degrees C. and the inner walls are planarized. Next, the inner walls are nitrided by introducing nitrogen into the heat treatment furnace while the temperature of the hydrogen-etching heat treatment decreases, thereby forming a SiN film along the inner walls. Next, an HTO film is formed, as gate insulating films, on the SiN film along the inner walls of the trenches. Thereafter, by PDA, an oxygen amount of an interface section of a SiO | 2021-05-06 |
20210134962 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a substrate; and an n-type layer including a nitride semiconductor formed on the surface of the substrate. In the n-type layer, the concentration of donor impurities (excluding O) is 1×10 | 2021-05-06 |
20210134963 | BIDIRECTIONAL SWITCH ELEMENT - A bidirectional switch element includes: a substrate; an Al | 2021-05-06 |
20210134964 | FIELD PLATE STRUCTURE TO ENHANCE TRANSISTOR BREAKDOWN VOLTAGE - Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate electrode overlies a substrate between a source region and a drain region. A drift region is arranged laterally between the gate electrode and the drain region. A plurality of inter-level dielectric (ILD) layers overlie the substrate. The plurality of ILD layers includes a first ILD layer underlying a second ILD layer. A plurality of conductive interconnect layers is disposed within the plurality of ILD layers. The field plate extends from a top surface of the first ILD layer to a point that is vertically separated from the drift region by the first ILD layer. The field plate is laterally offset the gate electrode by a non-zero distance in a direction toward the drain region. The field plate includes a same material as at least one of the plurality of conductive interconnect layers. | 2021-05-06 |
20210134965 | FIELD EFFECT TRANSISTOR HAVING FIELD PLATE - A field effect transistor having a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure having: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and electric charge disposed in portions of the dielectric layer, a portion of such charge being disposed in the dielectric layer over an upper surface of the gate and another portion of the change extending from the upper surface of the gate into the region between gate and the drain; and wherein the electric charge solely produces the electric field. | 2021-05-06 |
20210134966 | HIGH ELECTRON MOBILITY TRANSISTORS HAVING IMPROVED DRAIN CURRENT DRIFT AND/OR LEAKAGE CURRENT PERFORMANCE - A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses. | 2021-05-06 |
20210134967 | STRUCTURE OF FLASH MEMORY CELL AND METHOD FOR FABRICATING THE SAME - A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure. | 2021-05-06 |
20210134968 | Semiconductor Device and Inverter - In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain. | 2021-05-06 |
20210134969 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME - A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material. | 2021-05-06 |
20210134970 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, and a second nanostructure. The method includes forming an isolation layer over the base. The method includes forming a gate dielectric layer over the first nanostructure, the second nanostructure, the fin, and the isolation layer. The method includes forming a gate electrode layer over the first part. The method includes forming a spacer layer. The method includes removing the second part of the gate dielectric layer and the first upper portion of the isolation layer to form a space between the fin and the spacer layer. The method includes forming a source/drain structure in the space and over the first nanostructure and the second nanostructure. | 2021-05-06 |
20210134971 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer. | 2021-05-06 |
20210134972 | PMOS High-K Metal Gates - Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiment comprise MoN as a PMOS work function material. Some embodiments comprise TiSiN as a high-κ capping layer. Some embodiments provide improved PMOS bandedge performance. Some embodiments provide improved PMOS bandedge performance with reduced EOT penalty. | 2021-05-06 |
20210134973 | Air Spacers Around Contact Plugs and Method Forming Same - A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer. | 2021-05-06 |
20210134974 | Transistors with Reduced Defect and Methods Forming Same - A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer. | 2021-05-06 |
20210134975 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D | 2021-05-06 |
20210134976 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME - Semiconductor structure and fabrication method are provided. The method includes providing a substrate including a first region and a second region; forming a plurality of fins on the first region of the substrate; forming a first isolation structure on the first region and the second region of the substrate; forming a gate structure and a dummy gate structure each across fins and the first isolation structure at the first region; forming an epitaxial layer in each fin on two sides of the gate structure; forming a first opening by etching a portion of each of the first isolation structure and the substrate that are at the second region; filling the first opening with a conductive material layer; removing the dummy gate structure and a portion of the conductive material layer in the first opening to form a power rail; and forming a second isolation structure in a second opening. | 2021-05-06 |
20210134977 | SEMICONDUCTOR DEVICE INCLUDING A TRANSISTOR WITH ONE OR MORE BARRIER REGIONS - A semiconductor device includes a transistor having a drift region of a first conductivity type in a semiconductor substrate having a first main surface, a body region of a second conductivity type between the drift region and first main surface, and trenches in the first main surface which pattern the substrate into mesas. The trenches include an active trench and first and second source trenches. A source region of the first conductivity type is in a first mesa arranged adjacent to the active trench. A second mesa between the first and second source trenches is in contact with at least one source trench. A barrier region of the first conductivity type at a higher doping concentration than the drift region is arranged between the body and drift regions in the second mesa. A vertical size of the barrier region is at least twice a width of the second mesa. | 2021-05-06 |
20210134978 | HIGH-ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF - A high-electron mobility transistor includes a substrate; a buffer layer on the substrate; a AlGaN layer on the buffer layer; a passivation layer on the AlGaN layer; a source region and a drain region on the AlGaN layer; a source layer and a drain layer on the AlGaN layer within the source region and the drain region, respectively; a gate on the AlGaN layer between the source region and a drain region; and a field plate on the gate and the passivation layer. The field plate includes an extension portion that laterally extends to an area between the gate and the drain region. The extension portion has a wave-shaped bottom surface. | 2021-05-06 |
20210134979 | METHOD FOR FABRICATING GATE STRUCTURES - A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer. | 2021-05-06 |
20210134980 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode. | 2021-05-06 |
20210134981 | METHOD OF FABRICATING METAL GATE TRANSISTOR - A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench. | 2021-05-06 |
20210134982 | FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate. | 2021-05-06 |
20210134983 | Non-Conformal Capping Layer and Method Forming Same - A method includes forming a protruding structure, and forming a non-conformal film on the protruding structure using an Atomic Layer Deposition (ALD) process. The non-conformal film includes a top portion directly over the protruding structure, and a sidewall portion on a sidewall of the protruding structure. The top portion has a first thickness, and the sidewall portion has a second thickness smaller than the first thickness. | 2021-05-06 |
20210134984 | Semiconductor Device and Method - A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate. | 2021-05-06 |
20210134985 | Conformal Transfer Doping Method for Fin-Like Field Effect Transistor - Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer. | 2021-05-06 |
20210134986 | CAP OXIDATION FOR FINFET FORMATION - Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material. | 2021-05-06 |
20210134987 | GATE CONTROLLED LATERAL BIPOLAR JUNCTION/HETEROJUNCTION TRANSISTORS - The present disclosure relates to semiconductor structures and, more particularly, to gate controlled transistors and methods of manufacture. The structure includes: an emitter region; a collector region; base regions on opposing sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, the body region being located between the base regions on opposing sides of the emitter region and the collector region, and the leg regions isolating the base regions from both the emitter region and the collector region. | 2021-05-06 |
20210134988 | BIPOLAR JUNCTION TRANSISTOR (BJT) COMPRISING A MULTILAYER BASE DIELECTRIC FILM - Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure. | 2021-05-06 |
20210134989 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - An Enhanced Planar MOS cell based on a simple and self-aligned process provides a structure where the lateral distance between the edge of the gate electrode opening and the end of the P-well region is less than 70% from the vertical distance between the surface of the substrate and the depth of the P-well region. Usually, for previous designs, this ratio was 70-80% or more. A spacer can be introduced at the edge of the polysilicon gate electrode openings after the diffusion of an enhancement layer. Using the spacer, a P-type implant is made, resulting in a shorter lateral MOS channel, while the vertical depth of the P-well remains unchanged. The design results in much lower on-state losses without affecting the voltage blocking capability of the device. This design offers advantages both in terms of performance and processability and can be applied to both IGBTs and MOSFETs. | 2021-05-06 |
20210134990 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the present invention includes a semiconductor substrate including at least a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type provided in the upper layer of the third semiconductor layer; a first gate trench extending in the thickness direction through the fourth, third, and second semiconductor layers to the inside of the first semiconductor layer; an interlayer insulating film; a first main electrode provided in contact with the fourth semiconductor layer; and a second main electrode provided on the side opposite the first main electrode. The first gate trench includes a first gate electrode on the lower side and a second gate electrode on the upper side. | 2021-05-06 |
20210134991 | METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE - A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage. | 2021-05-06 |
20210134992 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals. | 2021-05-06 |
20210134993 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess. | 2021-05-06 |
20210134994 | HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) - A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top. | 2021-05-06 |
20210134995 | VERTICAL CHANNEL DEVICE - The disclosed technology relates generally to semiconductor devices, and more particularly to a vertical channel device and a method of forming a vertical channel device. In one aspect, a method of forming a vertical channel transistor structure comprises the steps of: (a) forming a bottom source/drain region on a substrate surface and depositing a spacer oxide layer over the bottom source/drain region; (b) forming vertically extending portions and depositing a gate material on the deposited spacer oxide layer such that the gate material is arranged over the bottom source/drain region and over the deposited spacer oxide layer, wherein the vertically extending portions are arranged around and extend above the gate material; and (c) depositing a spacer material at sidewalls of the vertically extending portions, thereby defining a horizontal gap between the vertically extending portions, the gap being positioned vertically over the gate material and the bottom source/drain portion. The method further comprises the steps of: (d) forming a vertical opening through the gate material extending from the horizontal gap down to the bottom source/drain region; (e) depositing an oxide at sidewalls of the gate material in the vertical opening; (f) performing an epitaxial deposition process of a semiconductor material on the bottom source/drain portion to form a vertical channel structure above the gate material, wherein a width (w | 2021-05-06 |
20210134996 | SILICON CARBIDE POWER DEVICES - An embodiment relates to a device comprising a unit cell on a SiC substrate, the unit cell comprising a gate insulator film, a trench in the well region, and a first sinker region of a second conduction type, wherein the first sinker region has a depth that is equal to or greater than a depth of a well region; wherein the device has an on-resistance of less than 3 milliohm-cm | 2021-05-06 |
20210134997 | POWER DEVICE WITH GRADED CHANNEL - A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration. | 2021-05-06 |
20210134998 | SILICON CARBIDE POWER DEVICES - An embodiment relates to a device comprising a unit cell on a SiC substrate, the unit cell comprising a gate insulator film, a trench in the well region, and a first sinker region of a second conduction type, wherein the first sinker region has a depth that is equal to or greater than a depth of a well region; wherein the device has an on-resistance of less than 3 milliohm-cm | 2021-05-06 |
20210134999 | METHODS FOR LDMOS AND OTHER MOS TRANSISTORS WITH HYBRID CONTACT - A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region. | 2021-05-06 |
20210135000 | Semiconductor Device and Method - A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope. | 2021-05-06 |
20210135001 | SEMICONDUCTOR DEVICE - A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern. | 2021-05-06 |
20210135002 | SEMICONDUCTOR DEVICE AND POWER CONVERTER - A silicon carbide semiconductor device includes a diffusion protective layer provided below a gate insulating film, a gate line provided on an insulation film on the bottom face of a terminal trench and electrically connected to a gate electrode, the terminal trench being located more toward the outer side than the gate trench, a gate pad joined to the gate line in the terminal trench, a terminal protective layer provided below the insulation film on the bottom face of the terminal trench, and a source electrode electrically connected to a source region, the diffusion protective layer, and the terminal protective layer. The diffusion protective layer has first extensions that extend toward the terminal protective layer and that are separated from the terminal protective layer. This configuration inhibits an excessive electric field from being applied to the gate insulating film provided on the bottom face of the gate trench. | 2021-05-06 |
20210135003 | SINGLE-CHIP CONTAINING POROUS-WAFER BATTERY AND DEVICE AND METHOD OF MAKING THE SAME - A chip comprises a porous wafer battery and a device. The chip further comprises a wafer containing the device and at least a portion of the porous wafer battery. The wafer comprises a silicon substrate. The silicon substrate comprises a first region and a second region. The first region comprises a plurality of pores of the porous wafer battery. The second region | 2021-05-06 |
20210135004 | SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a first dielectric layer, a work function layer, and a gate electrode sequentially stacked over the substrate, the first dielectric layer is between the work function layer and the substrate, the work function layer is between the first dielectric layer and the gate electrode, the first dielectric layer has a thin portion and a thick portion, the thin portion is thinner than the thick portion and surrounds the thick portion. The semiconductor device structure includes. The semiconductor device structure includes an insulating layer over the substrate and wrapping around the gate stack. The thin portion is between the thick portion and the insulating layer. | 2021-05-06 |
20210135005 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*10 | 2021-05-06 |
20210135006 | LATERAL DOUBLE-DIFFUSED METAL-OXIDE-SEMICONDUCTOR (LDMOS) FIN FIELD EFFECT TRANSISTOR WITH ENHANCED CAPABILITIES - A fin-shaped field-effect transistor (finFET) device is provided. The finFET device includes a substrate material with a first surface and a bottom surface. The finFET device also includes a well region formed in the substrate material. The well region may include a first type of dopant. The finFET device also includes a fin structure disposed on the first surface of the substrate material. A portion of the fin structure may include the first type of dopant. The finFET device also includes an oxide material disposed on the first surface of the substrate material and adjacent to the portion of the fin structure. The finFET device also includes a first epitaxial material disposed over a portion of the fin structure. The first epitaxial material may include a second type of dopant. | 2021-05-06 |
20210135007 | METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL - A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process. | 2021-05-06 |
20210135008 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH STRESSOR - A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the stressor structure. | 2021-05-06 |
20210135009 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer. | 2021-05-06 |
20210135010 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor. | 2021-05-06 |
20210135011 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH STRESSOR - A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure. | 2021-05-06 |
20210135012 | THIN FILM TRANSISTOR, FABRICATING METHOD THEREOF, AND DISPLAY APPARATUS - The present disclosure is related to a thin film transistor. The thin film transistor may include an active layer; a gate insulating layer on the active layer; and a gate and a plurality of metal films on the gate insulating layer. The plurality of metal films may be spaced apart from the gate, and insulated from the gate and the active layer. | 2021-05-06 |
20210135013 | SEMICONDUCTOR DEVICE PROVIDED WITH OXIDE SEMICONDUCTOR TFT - A semiconductor device includes a substrate and an oxide semiconductor TFT supported by the substrate. The oxide semiconductor TFT includes an oxide semiconductor layer containing In, Ga, and Zn, a gate electrode, a gate insulating layer formed between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode that are in contact with the oxide semiconductor layer. The oxide semiconductor layer has a layered structure that includes a first layer, a second layer, and an intermediate transition layer disposed between the first layer and the second layer, and the first layer is disposed closer to the gate insulating layer side than the second layer. The first layer and the second layer have different compositions, and the intermediate transition layer has a continuously changing composition from the first layer side toward the second layer side. | 2021-05-06 |
20210135014 | THIN FILM TRANSISTOR, GATE DRIVER INCLUDING THE SAME, AND DISPLAY DEVICE INCLUDING THE SAME - Disclosed are a thin film transistor having an oxide semiconductor layer which is applicable to a flat display device requiring high-speed driving due to ultra-high definition, a gate driver including the same, and a display device including the same. The thin film transistor includes a first oxide semiconductor layer formed of iron-indium-zinc oxide (FIZO) and a second oxide semiconductor layer formed of indium-gallium-zinc oxide (IGZO), thus being capable of exhibiting effects, such as high reliability and high electron mobility. | 2021-05-06 |
20210135015 | FIELD-EFFECT TRANSISTORS WITH CHANNEL REGIONS THAT INCLUDE A TWO-DIMENSIONAL MATERIAL ON A MANDREL - Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A gate electrode has a section that is wrapped about a first side surface and a second side surface of a mandrel that is composed of a dielectric material. A channel layer has a channel region that is positioned in part between the first side surface of the mandrel and the section of the gate electrode. The channel layer is composed of a two-dimensional material. | 2021-05-06 |
20210135016 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack. | 2021-05-06 |
20210135017 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V | 2021-05-06 |
20210135018 | SEMICONDUCTOR DEVICE - In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode. | 2021-05-06 |
20210135019 | TERMINATION STRUCTURE FOR INSULATED GATE SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench. | 2021-05-06 |
20210135020 | DETECTION PANEL, MANUFACTURING METHOD THEREOF AND DETECTION DEVICE - A detection panel, a manufacturing method thereof, and a detection device are provided. The detection panel includes base substrate; a detection circuit on the base substrate; a photoelectric conversion structure on the detection circuit and electrically connected to the detection circuit; and a bias voltage layer on the photoelectric conversion structure and electrically connected to the photoelectric conversion structure; wherein the bias voltage layer has a grid-like structure. | 2021-05-06 |
20210135021 | LIGHT RECEIVING ELEMENT AND RANGING MODULE - The present technology relates to a light receiving element and a ranging module that can improve characteristics._A light receiving element includes: light receiving regions each including a first voltage application unit to which a first voltage is applied, a first charge detection unit provided around the first voltage application unit, a second voltage application unit to which a second voltage different from the first voltage is applied, and a second charge detection unit provided around the second voltage application unit; and an isolation portion that is arranged at a boundary between the light receiving regions adjacent to each other, and isolates the light receiving regions from each other. The present technology can be applied to a light receiving element. | 2021-05-06 |
20210135022 | LIGHT RECEPTION DEVICE AND DISTANCE MEASUREMENT MODULE - The present technology relates to a light reception device and a distance measurement module whose characteristic can be improved. The light reception device includes an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer. The semiconductor layer includes a first tap having a first voltage application portion and a first charge detection portion arranged around the first voltage application portion, and a second tap having a second voltage application portion and a second charge detection portion arranged around the second voltage application portion. Furthermore, the light reception device is configured such that a phase difference is detected using signals detected by the first tap and the second tap. The present technology can be applied, for example, to a light reception device that generates distance information, for example, by a ToF method, and so forth. | 2021-05-06 |
20210135023 | SEMICONDUCTOR DEVICE AND METHOD FOR TIME-OF-FLIGHT MEASUREMENTS - The semiconductor device comprises an emitter of electromagnetic radiation, a photodetector enabling a detection of electromagnetic radiation of a specific wavelength, a filter having a passband including the specific wavelength, the filter being arranged on the photodetector, the emitter and/or the filter being electrically tunable to the specific wavelength, and a circuit configured to determine a time elapsed between emission and reception of a signal that is emitted by the emitter and then received by the photodetector. | 2021-05-06 |
20210135024 | SEMICONDUCTOR DEVICE COMPRISING A PHOTODETECTOR WITH REDUCED DARK CURRENT - Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector. | 2021-05-06 |
20210135025 | METHOD AND OPTOELECTRONIC STRUCTURE PROVIDING POLYSILICON PHOTONIC DEVICES WITH DIFFERENT OPTICAL PROPERTIES IN DIFFERENT REGIONS - Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure. | 2021-05-06 |
20210135026 | COMPOUND FOR USE IN AN OPTOELECTRONIC DEVICE INCLUDING A HETEROJUNCTION - The present invention relates to a compound for use in an optoelectronic device including a heterojunction. The heterojunction includes a metal-organic framework optimized for operation as an electron transport layer in an optoelectronic device. | 2021-05-06 |
20210135027 | SOLAR CELL AND PRODUCTION METHOD THEREFOR, AND SOLAR CELL MODULE - A solar cell includes a semiconductor substrate, a first conductive layer, a second conductive layer, a first electrode, a second electrode, and an island-shaped conductive layer. The first conductive layer and the second conductive layer are disposed on one principal surface of the semiconductor substrate. The first electrode is disposed on the first conductive layer and the second electrode is disposed on the second conductive layer. The first electrode and the second electrode are electrically separated, and the island-shaped conductive layer is disposed between the first electrode and the second electrode. | 2021-05-06 |
20210135028 | Adamantine Semiconductor and Uses Thereof - Disclosed is an adamantine semiconductor. The semiconductor comprises a first element being from one of the following groups: | 2021-05-06 |
20210135029 | MANUFACTURING METHOD OF FLEXIBLE THIN FILM SOLAR CELL MODULE AND THE FLEXIBLE THIN FILM SOLAR CELL MODULE USING THE SAME - Provided is a method of manufacturing a high efficiency flexible thin film solar cell module including a see-thru pattern. The method of manufacturing a flexible thin film solar cell module includes: sequentially forming a light-absorbing layer, a first buffer layer, and a first transparent electrode layer on the release layer; forming a second buffer layer on the exposed bottom surface of the light-absorbing layer; forming a P2 scribing pattern by removing at least one portion of each of the first buffer layer, the light-absorbing layer, and the second buffer layer; forming a second transparent electrode layer on the second buffer layer and the first transparent electrode layer exposed by the P2 scribing pattern; and forming a P4 see-thru pattern by selectively removing at least one portion of the first buffer layer, the light-absorbing layer, the second buffer layer, and the second transparent electrode layer. | 2021-05-06 |
20210135030 | A PHOTOVOLTAIC DEVICE HAVING A LIGHT ABSORBING LAYER INCLUDING A PLURALITY OF GRAINS OF A DOPED SEMICONDUCTING MATERIAL - The present invention relates to a photovoltaic device ( | 2021-05-06 |
20210135031 | SOLAR CELL MODULE - The present invention relates to a solar cell module and, more specifically, to a solar cell module in which solar cells are disposed to partially overlap each other so as to increase a space occupancy ratio of the solar cells and which is capable of solving safety and structural problems caused by the solar cells being disposed to overlap each other. In the solar cell module according to the present invention, the solar cells are disposed to partially overlap each other, thereby reducing a reactive power region and concurrently increasing a space occupancy ratio of the solar cells to increase power generation efficiency. In addition, a gap between portions at which the solar cells overlap each other is reduced to considerably reduce an incidence rate of cracks and damage, thereby improving stability and structural performance | 2021-05-06 |
20210135032 | SHINGLED PHOTOVOLTAIC MODULE WITH BYPASS DIODES - A shingled photovoltaic module with bypass diodes, includes four regions. Each region includes a plurality of cell strings consisting of crystalline silicon cells or crystalline silicon slice cells; the cell strings in the each region are connected in parallel with each other, and circuits between the regions are connected in series with each other; a first region and a second region are protected by one bypass diode, and a third region and a fourth region are protected by another bypass diode; the bypass diodes are positioned in a central part of the module; and positive electrode and negative electrode cables of the module are led out from a junction box which is located on a back side of the module and is close to an edge of the module. | 2021-05-06 |
20210135033 | INTERCONNECTION OF NEIGHBORING SOLAR CELLS ON A FLEXIBLE SUPPORTING FILM - A method of fabricating a solar cell assembly comprising a plurality of solar cells mounted on a flexible support, the support comprising a conductive layer on the top surface thereof divided into two electrically isolated portions—a first conductive portion and a second conductive portion. Each solar cell comprises a front surface, a rear surface, and a first contact on the rear surface and a second contact on the front surface. Each one of the plurality of solar cells is placed on the first conductive portion with the first contact electrically connected to the first conductive portion so that the solar cells are connected through the first conductive portion. A second contact of each solar cell is then connected to the second conductive portion by an interconnect. The two conductive portions serve as bus bars representing contacts of two different polarities of the solar cell assembly. | 2021-05-06 |
20210135034 | LIGHT CONVERTING SYSTEMS EMPLOYING THIN LIGHT ABSORBING AND LIGHT TRAPPING STRUCTURES WITH LENS ARRAYS - A light converting optical system employing a planar light trapping optical structure illuminated by a source of monochromatic light. The light trapping optical structure includes a photoabsorptive layer including quantum dots. The photoabsorptive layer is configured at a relatively low thickness and located between a broad-area optically transmissive surface configured to reflect light using a total internal reflection and an opposing broad-area reflective surface formed by a thin sheet of material configured to diffusely reflect light. The opposing surfaces confine and redistribute light within the light trapping structure, causing multiple transverse propagation of light through the photoabsorptive layer and enhanced absorption and light conversion. The light trapping optical structure may further incorporate an array of lenses or other optical elements located on a light path between the light source and the photoabsorptive layer. | 2021-05-06 |
20210135035 | HYBRID MOCVD/MBE EPITAXIAL GROWTH OF HIGH-EFFICIENCY LATTICE-MATCHED MULTIJUNCTION SOLAR CELLS - Semiconductor devices and methods of fabricating semiconductor devices having a dilute nitride layer and at least one semiconductor material overlying the dilute nitride layer are disclosed. Hybrid epitaxial growth and the use of aluminum barrier layers to minimize hydrogen diffusion into the dilute nitride layer are used to fabricate high-efficiency multijunction solar cells. | 2021-05-06 |
20210135036 | PHOTOSENSITIVE DEVICE, X-RAY DETECTOR AND DISPLAY DEVICE - The present disclosure provides a photosensitive device, including: a photosensitive layer ( | 2021-05-06 |
20210135037 | AUTOMATICALLY LIMITING POWER CONSUMPTION BY DEVICES USING INFRARED OR RADIO COMMUNICATIONS - Methods, apparatus, and processor-readable storage media for automatically limiting power consumption by devices using infrared or radio communications are provided herein. An example computer-implemented method includes detecting, via at least one photodiode of an emitting sensor, one or more signals output by a user device within a predetermined proximity; automatically transitioning, via utilizing at least one transistor connected to the photodiode, and in response to detecting the one or more signals, the emitting sensor from a first power-consumption state to a second power-consumption state; transmitting one or more signals in response to transitioning from the first power-consumption state to the second power-consumption state; and subsequent to transmitting, automatically transitioning, via utilizing the at least one transistor, the emitting sensor from the second power-consumption state to the first power-consumption state after a predetermined amount of time has elapsed during which no signals were detected. | 2021-05-06 |
20210135038 | OPTOELECTRONIC DEVICE - An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip. | 2021-05-06 |
20210135039 | METHOD OF MANUFACTURING PHOTO SENSOR - A method of manufacturing a photo sensor includes forming a first conductive layer on a substrate, the first conductive layer including a metal layer and a transparent conductive oxide layer formed on the metal layer, forming a photoconductive layer on the first conductive layer, forming a second conductive layer on the photoconductive layer, forming a first photoresist pattern on the second conductive layer, etching the second conductive layer using the first photoresist pattern as an etch mask to form a second electrode, deforming the first photoresist pattern to form a second photoresist pattern, and etching the photoconductive layer and the first conductive layer using the second photoresist pattern to form a photoconductive pattern and a first electrode, respectively. | 2021-05-06 |
20210135040 | TILED SOLAR CELL LASER PROCESS - In an example, the present invention provides a method of separating a photovoltaic strip from a solar cell. The method includes providing a solar cell, placing the front side of the solar cell on a platen such that the backside is facing a laser source, initiating a laser source to output a laser beam having a wavelength from 200 to 600 nanometers and a spot size of 18 to 30 microns, subjecting a portion of the backside to the laser beam at a power level ranging from about 20 Watts to about 35 Watts to cause an ablation to form a scribe region having a depth, width, and a length, the depth being from 40% to 60% of a thickness of the solar cell, the width being between 16 and 35 microns to create a plurality of scribe regions spatially disposed on the backside of the solar cell. | 2021-05-06 |
20210135041 | METHOD OF FABRICATING SEE-THROUGH THIN FILM SOLAR CELL - Provided is a method of fabricating a see-through thin film solar cell, the method including preparing a substrate including a molybdenum (Mo) layer on one surface, forming see-through patterns by selectively removing at least parts of the Mo layer, sequentially depositing a chalcogenide absorber layer, a buffer layer, and a transparent electrode layer on the substrate and the Mo layer including the see-through patterns, and forming a see-through array according to a shape of the see-through patterns by removing the chalcogenide absorber layer, the buffer layer, and the transparent electrode layer deposited on the see-through patterns, by irradiating a laser beam from under the substrate toward the transparent electrode layer. | 2021-05-06 |
20210135042 | METHOD FOR TRANSFERRING MICRO LIGHT-EMITTING DIODES AND TRANSFERRING DEVICE - The present application provides a method for transferring micro light emitting diodes and a transferring device. The device includes: a first substrate, having at least one surface arranged with a plurality of first adhesive region for a plurality of micro light emitting diodes to adhere thereon; and a transferring substrate, having at least one surface arranged with a plurality of second adhesive regions for at least a portion of the micro light emitting diodes to adhere on and being configured to transfer the at least a portion of the micro light emitting diodes to a driving back plate. | 2021-05-06 |
20210135043 | LIGHT-EMITTING METAL-OXIDE-SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS - Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light. | 2021-05-06 |
20210135044 | MICRO-LED ARRAY TRANSFER METHOD, MANUFACTURING METHOD AND DISPLAY DEVICE - It is disclosed a micro-LED transfer method, manufacturing method and display device. The method for transferring a micro-LED array comprises: patterning conductive resist on a receiving substrate to cover electrodes for the micro-LED array to be transferred; bonding the micro-LED array on a first substrate with the receiving substrate through the conductive resist, wherein the first substrate is laser transparent; irradiating laser onto the micro-LED array from a side of the first substrate to lift-off the micro-LED array from the first substrate. According to an embodiment, the performance of a micro-LED device may be improved. | 2021-05-06 |
20210135045 | METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE - A method of manufacturing a light-emitting device includes providing a structure body including a silicon substrate having a first portion, a second portion, and a third portion between the first portion and the second portion, and a first semiconductor layered body including a first light-emitting layer, the first semiconductor layered body being disposed on or above the silicon substrate. The method includes forming a first resin layer covering a lateral side of the silicon substrate and a lateral side of the first semiconductor layered body. The method includes a removal step of removing the first portion to expose a first surface of the first semiconductor layered body, removing the second portion to expose a second surface of the first semiconductor layered body, and leaving the third portion. The method includes forming a first wavelength conversion member on or above the first surface exposed by the removal of the first portion. | 2021-05-06 |
20210135046 | COMPONENT HAVING METAL CARRIER LAYER AND REDUCED OVERALL HEIGHT - A component includes a carrier and a semiconductor body arranged on the carrier, wherein the semiconductor body includes a semiconductor layer facing away from the carrier, a further semiconductor layer facing the carrier and an optically active layer located therebetween, the carrier has a metallic carrier layer that is contiguous and mechanically stabilizes the component, the carrier includes a mirror layer disposed between the semiconductor body and the metallic carrier layer, the carrier has a compensating layer directly adjacent to the metallic carrier layer and is configured to compensate for internal mechanical strains in the component, and the compensating layer is arranged between the semiconductor body and the metallic carrier layer. | 2021-05-06 |
20210135047 | DISPLAY DEVICE, SUBSTRATE FOR DISPLAY DEVICE AND METHOD FOR REPAIRING DISPLAY DEVICE - A substrate for displays including a base, a plurality of first interconnects disposed on the base, a plurality of second interconnects disposed on the base to intersect with the first interconnects, and a plurality of sub-pixels disposed on the base and including one or more of the first and second interconnects, each of the sub-pixels including at least one interconnect extension protruding from at least one side of the second interconnect, first and second mounting portions formed between the at least one interconnect extension and the first interconnect, and a light emitting diode mounted on the first mounting portion, in which the second mounting portion is configured to mount another light emitting diode thereon. | 2021-05-06 |
20210135048 | MICRO LIGHT-EMITTING DIODE (LED) ELEMENTS AND DISPLAY - Micro light-emitting diode (LED) displays and assembly apparatuses are described. In an example, a pixel element for a micro-light emitting diode (LED) display panel includes a first color nanowire LED, a second color nanowire LED, the second color different than the first color, and a pair of third color nanowire LEDs, the third color different than the first and second colors. A continuous insulating material layer ius laterally surrounding the first color nanowire LED, the second color nanowire LED, and the pair of third color nanowire LEDs. | 2021-05-06 |
20210135049 | LIGHT-EMITTING DEVICE - A light-emitting device includes a substrate including a top surface; a semiconductor stack including a first semiconductor layer, an active layer and a second semiconductor layer formed on the substrate, wherein a portion of the top surface is exposed; a distributed Bragg reflector (DBR) formed on the semiconductor stack and contacting the portion of the top surface of the substrate; a metal layer formed on the distributed Bragg reflector (DBR), contacting the portion of the top surface of the substrate and being insulated with the semiconductor stack; and an insulation layer formed on the metal layer and contacting the portion of the top surface of the substrate. | 2021-05-06 |
20210135050 | TEMPLATE SUBSTRATE, ELECTRONIC DEVICE, LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING TEMPLATE SUBSTRATE, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - A template substrate including: a first layer that includes Al | 2021-05-06 |
20210135051 | SEMICONDUCTOR STRUCTURE - The embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate. The semiconductor structure also includes a first buffer layer disposed on the substrate. The semiconductor structure further includes a second buffer layer disposed on the first buffer layer. The semiconductor structure includes a semiconductor-based layer disposed on the second buffer layer. The second buffer layer includes aluminum, and the aluminum content of the second buffer layer gradually increases in the direction away from the substrate. | 2021-05-06 |