| 18th week of 2021 patent applcation highlights part 72 |
| Patent application number | Title | Published |
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| 20210134652 | SUBSTRATE HOLDING APPARATUS AND SUBSTRATE PROCESSING APPARATUS - A substrate holding apparatus is used for a substrate processing apparatus for supplying the processing liquid to a substrate. The substrate holding apparatus includes a holding member, a ring member, and a rotation mechanism. The holding member holds the substrate in a horizontal attitude. The ring member is in a shape of a ring surrounding a peripheral edge of the substrate held by the holding member, and has an upper surface level with or positioned below a front surface of the substrate. The rotation mechanism rotates the holding member and the ring member about a rotation axis at rotation speeds different from each other and/or in rotational directions different from each other, the rotation axis being a vertical axis passing through the substrate held by the holding member. | 2021-05-06 |
| 20210134653 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer. | 2021-05-06 |
| 20210134654 | MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH WAVEGUIDES - A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an electromagnetic waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds. | 2021-05-06 |
| 20210134655 | PROFILE OF DEEP TRENCH ISOLATION STRUCTURE FOR ISOLATION OF HIGH-VOLTAGE DEVICES - In some embodiments, the present disclosure relates to an integrated chip that includes a silicon-on-insulator (SOI) substrate having an insulator layer between an active layer and a base layer. A semiconductor device and a shallow trench isolation (SIT) structure are disposed on a frontside of the SOI substrate. A semiconductor core structure continuously surrounds the semiconductor device and extends through the STI structure and towards a backside of the SOI substrate. A first insulator liner portion and a second insulator liner portion surround a first outermost sidewall and a second outermost sidewall of the semiconductor core structure. The first and second insulator liner portions respectively have a first protrusion and a second protrusion. The first and second protrusions are arranged between the STI structure and the insulator layer of the SOI substrate. | 2021-05-06 |
| 20210134656 | Patterning Methods for Semiconductor Devices - Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask. | 2021-05-06 |
| 20210134657 | Method of Forming a Semiconductor Device - A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer. | 2021-05-06 |
| 20210134658 | GAP FILL VOID AND CONNECTION STRUCTURES - The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively. | 2021-05-06 |
| 20210134659 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF - A semiconductor structure and a forming method thereof are provided. The forming method includes: providing a base, where a mask material layer is formed on the base, a plurality of first trenches disposed at intervals are formed in the mask material layer, an extension direction of the first trenches is a first direction, the plurality of first trenches are arranged in parallel along a second direction, and the second direction is perpendicular to the first direction; forming a first side wall covering layer and a barrier layer, where the first side wall covering layer is located on a side wall of the first trench, the barrier layer is located in at least one of the first trenches, the barrier layer divides the first trench in the first direction, and the first side wall covering layer exposes side walls of the barrier layer on two sides in the first direction; forming a second side wall covering layer on the side walls of the barrier layer exposed by the first side wall covering layer; and etching the mask material layer between the adjacent first trenches by using the first side wall covering layer, the second side wall covering layer and the barrier layer as a mask to form a second trench, where the second trench is isolated from the first trench by the first side wall covering layer. According to the present disclosure, the barrier layer is protected by the second side wall covering layer, thereby improving the accuracy of pattern transfer. | 2021-05-06 |
| 20210134660 | Semiconductor Device and Method of Manufacture - Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device. | 2021-05-06 |
| 20210134661 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Semiconductor devices and methods of forming the same are provided. The methods may include forming a stacked structure that may include a stacking area and a stepped area and may include first layers and second layers alternately stacked. The second layers may have a stepped shape in the stepped area, and the stepped area may include at least one flat area and at least one inclined stepped area. The methods may also include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a lower level than the first upper surface. The methods may further include patterning the capping insulating layer to form protrusions at least one of which overlaps the stepped area and then planarizing the capping insulating layer. | 2021-05-06 |
| 20210134662 | Wet Cleaning with Tunable Metal Recess for Via Plugs - In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug. | 2021-05-06 |
| 20210134663 | MULTI-WAFER CAPPING LAYER FOR METAL ARCING PROTECTION - The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process. | 2021-05-06 |
| 20210134664 | TOP VIA WITH HYBRID METALLIZATION - Embodiments of the present invention are directed to fabrication methods and resulting structures for subtractively forming a top via using a hybrid metallization scheme. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a topmost surface of a first liner layer. The first liner layer can be positioned between the conductive line and a dielectric layer. A top via layer is formed on the recessed surface of the conductive line and a hard mask is formed over a first portion of the top via layer. A second portion of the top via layer is removed. The remaining first portion of the top via layer defines the top via. The conductive line can include copper while the top via layers can include ruthenium or cobalt. | 2021-05-06 |
| 20210134665 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH PROTECTION LAYER AND METHOD FOR FORMING THE SAME - A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure formed over the fin structure and adjacent to the gate structure, and an S/D contact structure formed over the S/D structure and adjacent to the gate structure. The FinFET device structure also includes a protection layer formed on the S/D contact structure, and the protection layer and the S/D contact structure are made of different materials. The protection layer has a bottommost surface in direct contact with a topmost surface of the S/D contact structure. | 2021-05-06 |
| 20210134666 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide. | 2021-05-06 |
| 20210134667 | Semiconductor Device and Method - A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron. | 2021-05-06 |
| 20210134668 | ETCH STOP LAYER FOR MEMORY DEVICE FORMATION - The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process. | 2021-05-06 |
| 20210134669 | ISOLATION STRUCTURE FOR METAL INTERCONNECT - The present disclosure describes a method for forming an interconnect structure. The method can include forming a first layer of insulating material on a substrate, forming a via recess within the layer of insulating material, filling the via recess with a layer of conductive material, selectively growing a second layer of insulating material over the first layer of insulating material, and opening the second layer of insulating material to the layer of conductive material while growing the second layer of insulating material. | 2021-05-06 |
| 20210134670 | ENCAPSULATED SOLDER TSV INSERTION INTERCONNECT - A method of coupling a first semiconductor device to a second semiconductor device can include encapsulating solder balls on a first surface of a first substrate of the first semiconductor device with an encapsulant material. In some embodiments, the method includes removing a portion of the encapsulant material and a portion the solder balls to form a mating surface. The method can include reflowing the solder balls. In some embodiments, the method includes inserting exposed conductive pillars of the second semiconductor device into the reflowed solder balls. | 2021-05-06 |
| 20210134671 | Partial Self-Aligned Contact for MOL - Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided. | 2021-05-06 |
| 20210134672 | SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS - A semiconductor device includes a first conductive structure. The semiconductor device includes a first dielectric structure. The semiconductor device includes a second conductive structure. The first dielectric structure is positioned between a first surface of the first conductive structure and a surface of the second conductive structure. The semiconductor device includes an etch stop layer overlaying the first conductive structure. The semiconductor device includes a first spacer structure overlaying the first dielectric structure. The semiconductor device includes a second dielectric structure overlaying the first spacer structure and the etch stop layer. | 2021-05-06 |
| 20210134673 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 2021-05-06 |
| 20210134674 | SEMICONDUCTOR COMPONENTS HAVING CONDUCTIVE VIAS WITH ALIGNED BACK SIDE CONDUCTORS - A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another. | 2021-05-06 |
| 20210134675 | HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES - An integrated circuit apparatus includes a silicon-on-insulator (SOI) substrate comprising a silicon layer overlying an insulator layer; a first silicon fin region formed in a first region of the silicon layer, the first silicon fin region comprising a first source region, a first drain region, and a first channel region; a second silicon fin region formed in a second region of the silicon layer, the second silicon fin region comprising a second source region, a second drain region, and a second channel region; a gate dielectric layer formed on the first, second, and third surface regions of the first silicon fin region, and on the third and fourth surface regions of the second silicon fin region; a dual-gate FinFET, comprising the second drain, source and channel regions in the second silicon fin region; and a tri-gate FinFET, comprising the first drain, source and channel regions. | 2021-05-06 |
| 20210134676 | WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width. | 2021-05-06 |
| 20210134677 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack. | 2021-05-06 |
| 20210134678 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess. | 2021-05-06 |
| 20210134679 | GATE OXIDE FORMING PROCESS - A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area. | 2021-05-06 |
| 20210134680 | Method and Structure for FinFET Isolation - A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer. | 2021-05-06 |
| 20210134681 | Semiconductor Device and Method - A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer. | 2021-05-06 |
| 20210134682 | SECURE INSPECTION AND MARKING OF SEMICONDUCTOR WAFERS FOR TRUSTED MANUFACTURING THEREOF - A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised. | 2021-05-06 |
| 20210134683 | Method of Manufacturing Semiconductor Device, Non-transitory Computer-readable Recording Medium and Substrate Processing Apparatus - Described herein is a technique capable of stabilizing conditions in a furnace at the start of a film-forming process. According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: pre-processing of preparing a process environment in a process furnace of a substrate processing apparatus; film-forming by processing a substrate; and post-processing, wherein the pre-processing comprises (a1) determining whether to execute a maintenance recipe for a target object in the substrate processing apparatus, wherein (a1) is performed first in the pre-processing. | 2021-05-06 |
| 20210134684 | Apparatus and Method - A white light illumination source can illuminate a region of a substrate to be plasma etched with an incident light beam. A camera takes successive images of the region being illuminated during a plasma etch process. Image processing techniques can be applied to the images so as to identify a location of at least one feature on the substrate and to measure a reflectivity signal at the location. The plasma etch process can be modified in response to the measured reflectivity signal at the location. | 2021-05-06 |
| 20210134685 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A method includes the following steps. A semiconductor wafer including integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings is provided. A first wafer saw process is performed at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including a testing structure among the testing structures. When performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance. | 2021-05-06 |
| 20210134686 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes: a power semiconductor element; a control circuit that controls the power semiconductor element; a control substrate having the control circuit mounted thereon; a lid arranged to overlap with at least a portion of the control substrate in a first direction; and at least one external connection terminal having a first portion connected with the control substrate, a second portion to be connected with an external apparatus, and a third portion located between the first portion and the second portion and fixed to the lid, the first portion being constituted as a press-fit portion. | 2021-05-06 |
| 20210134687 | ELECTRONIC COMPONENT MOUNTING PACKAGE AND ELECTRONIC DEVICE - An electronic component mounting package and an electronic device provide improved reliability. An electronic component mounting package includes a heat sink having a mount area in its middle, on which an electronic component is mountable, a frame installed on the heat sink to surround the mount area, a bond joining the heat sink and the frame together, and lead terminals installed on the upper surface of the frame to extend outward from the frame. The heat sink includes a metal, and includes a first portion having the mount area and a second portion thinner than the first portion. The second portion has a metallic crystal with a crystal grain size smaller than a crystal grain size of a metallic crystal of the first portion in a heat-sink thickness direction. | 2021-05-06 |
| 20210134688 | PRESSURE SENSORS ON FLEXIBLE SUBSTRATES FOR STRESS DECOUPLING - A semiconductor device includes a semiconductor chip including a substrate and a MEMS element, wherein the substrate includes a surface, and wherein the MEMS element is disposed at the surface of the substrate and the MEMS element includes a sensitive area; a first electrical interconnect structure electrically connected to the surface of the substrate; a carrier electrically connected to the first electrical interconnect structure; and a first stress relieve spring entrenched in the carrier, wherein the first stress relieve spring is a single integral channel that comprises two parallel channels that join together at a periphery of the first electrical interconnect structure to form the single integral channel that wraps around a portion of the periphery of the first electrical interconnect structure, wherein the two parallel channels extend outward, in parallel, from the periphery of the first electrical interconnect structure to a first termination region of the carrier. | 2021-05-06 |
| 20210134689 | CAVITY PACKAGES - An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure. | 2021-05-06 |
| 20210134690 | SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device package includes a substrate and an interposer. A bottom surface of the interposer is attached to a top surface of the substrate by a conductive adhesive layer including a spacer. | 2021-05-06 |
| 20210134691 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - To prevent deterioration of light incident/emission environment in a semiconductor device in which a transmissive material is laminated on an optical element forming surface via an adhesive. The semiconductor device includes a semiconductor element manufactured by chip size packaging, a transmissive material which is bonded with an adhesive to cover an optical element forming surface of the semiconductor element, and a side surface protective resin which covers an entire side surface where a layer structure of the semiconductor element and the transmissive material is exposed. | 2021-05-06 |
| 20210134692 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME - A semiconductor package includes a semiconductor die having a first surface and a second surface opposite to the first surface, a conductive wiring layer stacked with the semiconductor die and proximal to the first surface, an encapsulant encapsulating the semiconductor die and stacked with the conductive wiring layer, and a replacement structure exposing from the encapsulant and being free of fillers. A method for manufacturing the semiconductor package is also disclosed in the present disclosure. | 2021-05-06 |
| 20210134693 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate having a first surface, at least one memory chip including a first memory chip provided on the first surface, a controller chip configured to control the first memory chip, and provided on the first surface to be spaced apart from the first memory chip, a sealing member sealing the first memory chip and the controller chip, and a first member covering at least part of the controller chip and has a lower thermal conductivity than that of the sealing member. | 2021-05-06 |
| 20210134694 | TRIM WALL PROTECTION METHOD FOR MULTI-WAFER STACKING - The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process. | 2021-05-06 |
| 20210134695 | INTERPOSER BOARD HAVING HEATING FUNCTION AND ELECTRONIC DEVICE USING THE SAME - A non-conductive film having heating function and an electronic device using the same are provided. The electronic device includes a circuit substrate, an interposer board disposed on the circuit substrate, at least one electronic chip carried by the interposer board, a first non-conductive film disposed between the interposer board and the circuit substrate, and a second non-conductive film disposed between the at least one electronic chip and the interposer board, the at least one electronic chip being electrically connected to the circuit substrate through the interposer board. One of the first non-conductive film and the second non-conductive film is a type of non-conductive film having heating function, and the non-conductive film with heating function includes a non-conductive body and a plurality of micro heaters. The shape of the non-conductive body is changeable by heating, and the micro heaters are disposed on or in the non-conductive body. | 2021-05-06 |
| 20210134696 | SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device package includes a substrate, an electronic component disposed on the substrate, a supporting structure disposed on the substrate and surrounding the electronic component, and a heat spreading structure disposed on the supporting structure. A length of the supporting structure and a length of the heat spreading structure are greater than a length of the substrate. | 2021-05-06 |
| 20210134697 | Double Sided Semiconductor Package - A semiconductor package includes an encapsulant body; an upper electrically conductive element having an outwardly exposed metal surface; a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the upper electrically conductive element and the upper electrically conductive layer; a power semiconductor chip between the upper electrically conductive element and the upper electrically conductive layer; and a second electrically conductive spacer between the upper electrically conductive element and the power semiconductor chip, a first carrier region of the upper electrically conductive layer is connected to a first power terminal, a second carrier region of the upper electrically conductive layer is alongside the first carrier region and is connected to a phase terminal, a first region of the upper electrically conductive element is connected to a second power terminal. | 2021-05-06 |
| 20210134698 | THERMAL INTERFACE STRUCTURES FOR INTEGRATED CIRCUIT PACKAGES - A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device. | 2021-05-06 |
| 20210134699 | RF DEVICES WITH NANOTUBE PARTICLES FOR ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME - The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound with nanotube particles. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The nanotube particles are dispersed throughout a bottom portion of the first mold compound, and have a higher thermal conductivity than the first mold compound alone. The bottom portion of the first mold compound resides over the active layer and top surfaces of the isolation sections. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die. | 2021-05-06 |
| 20210134700 | APPARATUSES AND METHODS FOR IMPLEMENTING A SLIDING THERMAL INTERFACE BETWEEN SUBSTRATES WITH VARYING COEFFICIENTS OF THERMAL EXPANSION - Systems and methods include an integrated circuit assembly that includes a semiconductor substrate; a heat transfer element; and an ambulatory thermal interface arranged between the semiconductor substrate and the heat transfer element, the ambulatory thermal interface comprising: a thermally conductive material, and a friction reduction material, wherein: the thermally conductive material is arranged along a surface of the heat transfer element, the friction reduction material is arranged along a surface of the semiconductor substrate, opposing surfaces of the thermally conductive material and the friction reduction material define a slidable interface when placed in contact. | 2021-05-06 |
| 20210134701 | APPARATUS HAVING COOLING LINE FOR COLLECTING BY-PRODUCT IN SEMICONDUCTOR MANUFACTURING PROCESS - Disclosed is an apparatus having a cooling line for collecting a by-product in a semiconductor manufacturing process. The apparatus includes: a housing cooling channel ( | 2021-05-06 |
| 20210134702 | ELECTRONIC DEVICE HAVING A CHIP PACKAGE MODULE - An electronic device includes a chip package module which includes a chip carrier substrate, a chip, a thermal conductive unit, and an encapsulant laver. The chip is electrically connected to the chip carrier substrate. The thermal conductive unit has a first thermal conductive surface connected to the chip, and a second thermal conductive surface opposite to the first thermal conductive surface. The thermal conductive unit has a thermal conductivity greater than that of the chip. The encapsulant layer covers the chip and partially covers the thermal conductive unit in such a manner that the second thermal conductive surface is exposed from the encapsulant layer. | 2021-05-06 |
| 20210134703 | Thermal Management Of RF Devices Using Embedded Microjet Arrays - The present invention generally relates to a microjet array for use as a thermal management system for a heat generating device, such as an RF device. The microjet array is formed in a jet plate, which is attached directly to the substrate containing the heat generating device. Additional enhancing features are used to further improve the heat transfer coefficient above that inherently achieved by the array. Some of these enhancements may also have other functions, such as adding mechanical structure, electrical connectivity or pathways for waveguides. This technology enables higher duty cycles, higher power levels, increased component lifetime, and/or improved SWaP for RF devices operating in airborne, naval (surface and undersea), ground, and space environments. This technology serves as a replacement for existing RF device thermal management solutions, such as high-SWaP finned heat sinks and cold plates. | 2021-05-06 |
| 20210134704 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die. | 2021-05-06 |
| 20210134705 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a through via structure and a pad pattern. The first semiconductor substrate may include a first surface and a second surface opposite to the first surface, and the second surface may include a recess. The through via structure may pass through the first semiconductor substrate from the first surface to a bottom of the recess of the second surface. An upper surface of the through via structure may protrude from the bottom of the recess. The pad pattern may be electrically connected to the upper surface of the through via structure, and the pad pattern may include a first recess having a concave shape thereon. The second semiconductor chip may include a bump pattern bonded on an inside of the first recess of the pad pattern. | 2021-05-06 |
| 20210134706 | POWER MODULE SEMICONDUCTOR DEVICE AND INVERTER EQUIPMENT, AND FABRICATION METHOD OF THE POWER MODULE SEMICONDUCTOR DEVICE, AND METALLIC MOLD - The power module semiconductor device ( | 2021-05-06 |
| 20210134707 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes a die attach pad; a plurality of lead terminals disposed around the die attach pad; a semiconductor die mounted on the die attach pad; a molding compound encapsulating the plurality of lead terminals, the semiconductor die, and the die attach pad; and a step cut sawn into the molding compound along a perimeter of a bottom surface of the semiconductor package. The step cut penetrates through an entire thickness of each of the plurality of lead terminals, whereby each of the plurality of lead terminals has at least an exposed outer end at the step cut. | 2021-05-06 |
| 20210134708 | Semiconductor Package and Method for Fabricating a Semiconductor Package - A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase. | 2021-05-06 |
| 20210134709 | SEMICONDUCTOR MODULE - A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region an an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad. | 2021-05-06 |
| 20210134710 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device, including a semiconductor module and a conducting board. The semiconductor module includes a semiconductor chip and an external connecting terminal which has a first end electrically connected to the semiconductor chip and a second end extending from the semiconductor chip. The conducting board has a terminal hole penetrating therethrough, an inlet and an outlet of the terminal hole being respectively on two opposite surfaces of the conducting board. The conducting board is electrically connected to the external connecting terminal, of which the second end fits into the terminal hole from the inlet toward the outlet, and is fixed therein by solder. At least one of the terminal hole and the second end of the external connecting terminal has a lock part. The second end of the external connecting terminal, inserted into the terminal hole, is locked by the lock part and thereby remains in the terminal hole. | 2021-05-06 |
| 20210134711 | PACKAGE STRUCTURE, ASSEMBLY STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A package structure includes at least one electronic device, a protection layer and an encapsulant. The electronic device has a first surface and includes a plurality of bumps disposed adjacent to the first surface thereof. Each of the bumps has a first surface. The protection layer covers the bumps and the first surface of the electronic device, and has a first surface. The encapsulant covers the protection layer and at least a portion of the electronic device, and has a first surface. The first surfaces of the bumps, the first surface of the protection layer and the first surface of the encapsulant are substantially coplanar with each other. | 2021-05-06 |
| 20210134712 | SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device package includes a substrate, a redistribution structure, a conductive pad, a conductive element, and a conductive via. The redistribution structure is disposed over the substrate and includes a first dielectric layer and a first conductive layer. The conductive pad is disposed on a first surface of the first dielectric layer. The conductive element is disposed in the first dielectric layer and is electrically connected to the conductive pad. The conductive via extends from the conductive pad toward the substrate through the conductive element and the first dielectric layer. The first conductive layer is separated from the conductive via. | 2021-05-06 |
| 20210134713 | SEMICONDUCTOR DEVICE - A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as R | 2021-05-06 |
| 20210134714 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen. | 2021-05-06 |
| 20210134715 | Memory Device Interconnects and Method of Manufacture - An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend tit rough the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes. | 2021-05-06 |
| 20210134716 | TIGHT PITCH WIRINGS AND CAPACITOR(S) - The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material. | 2021-05-06 |
| 20210134717 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate of the present disclosure includes a substrate, a first conductive layer, a first insulating layer, and a second conductive layer. The substrate has an insulating surface. The first conductive layer is disposed on the substrate and includes a first part and a second part. The first part has a first thickness. The second part has a second thickness thinner than the first thickness and is adjacent to the first part. The first insulating layer is disposed on the first part and apart from the second part. The first insulating layer is disposed between the second conducting layer and the first part. | 2021-05-06 |
| 20210134718 | CONDUCTIVE RAIL STRUCTURE FOR SEMICONDUCTOR DEVICES - The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures. | 2021-05-06 |
| 20210134719 | LAYOUT STRUCTURES WITH MULTIPLE FINGERS OF MULTIPLE LENGTHS - Back-end-of-line layout structures and methods of forming a back-end-of-line layout structure. A metallization level includes a plurality of interconnects positioned over a plurality of active device regions. The plurality of interconnects have a triangular-shaped layout and a plurality of lengths within the triangular-shaped layout. | 2021-05-06 |
| 20210134720 | SEMICONDUCTOR DEVICE, AND ASSOCIATED METHOD AND SYSTEM - A semiconductor device, including: a substrate, a transistor layer, a dielectric layer, and a power grid structure. The transistor layer is formed on a first side of the substrate and includes a plurality of active regions for forming transistors. The dielectric layer is formed on the transistor layer and includes a conductive strip disposed on a first active region and extending toward a second active region for signal connection. The power grid structure is formed on a second side of the substrate opposite to the first side and arranged to direct a power source to the transistor layer. | 2021-05-06 |
| 20210134721 | Backside Power Rail Structure and Methods of Forming Same - Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail. | 2021-05-06 |
| 20210134722 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME - Semiconductor structure and fabrication method are provided. The method includes providing a substrate including a first region and a second region; forming a plurality of fins on the first region of the substrate; forming an isolation structure on the first region and the second region of the substrate; forming a gate structure across the plurality of fins and on the isolation structure at the first region; etching the isolation structure and the substrate at the second region to form a first opening; filling the first opening with a conductive material layer; and etching the gate structure till exposing the isolation structure to form a second opening in the gate structure and removing a portion of the conductive material layer in the first opening to form a power rail. | 2021-05-06 |
| 20210134723 | A Die Interconnect Substrate, an Electrical Device and a Method for Forming a Die Interconnect Substrate - A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material. | 2021-05-06 |
| 20210134724 | MULTI-CHIP PACKAGE STRUCTURES FORMED WITH INTERCONNECT BRIDGE DEVICES AND CHIP PACKAGES WITH DISCRETE REDISTRIBUTION LAYERS - Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages. | 2021-05-06 |
| 20210134725 | HIGH DENSITY PILLAR INTERCONNECT CONVERSION WITH STACK TO SUBSTRATE CONNECTION - A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area. | 2021-05-06 |
| 20210134726 | MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME - A multi-chip package includes a substrate ( | 2021-05-06 |
| 20210134727 | PACKAGE ARCHITECTURE UTILIZING PHOTOIMAGEABLE DIELECTRIC (PID) FOR REDUCED BUMP PITCH - An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process. | 2021-05-06 |
| 20210134728 | MULTI-CHIP PACKAGE STRUCTURES HAVING EMBEDDED CHIP INTERCONNECT BRIDGES AND FAN-OUT REDISTRIBUTION LAYERS - A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top-side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top-side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top-side of the chip interconnect bridge and the first and second integrated circuit chips. | 2021-05-06 |
| 20210134729 | FRAME DESIGN IN EMBEDDED DIE PACKAGE - In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit. | 2021-05-06 |
| 20210134730 | Semiconductor Structures and Methods of Forming the Same - A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies. | 2021-05-06 |
| 20210134731 | EMBEDDED DIE ON INTERPOSER PACKAGES - Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias. | 2021-05-06 |
| 20210134732 | FAN-OUT PACKAGING STRUCTURE AND METHOD OF MAKING SAME - A fan-out packaging structure includes a redistribution layer and a positioning sheet formed on the redistribution layer. The positioning sheet defines at least one opening penetrating opposite sides of the positioning sheet. At least one chip is mounted in the at least one opening. The redistribution layer comprises at least one conductive circuit. The at least one chip is electrically coupled to a corresponding one conductive circuit. | 2021-05-06 |
| 20210134733 | MICROWAVE DEVICE AND ANTENNA - A microwave device includes: a multilayer resin substrate being a first multilayer resin substrate; an IC being a radio frequency circuit provided on the multilayer resin substrate and electrically connected to the multilayer resin substrate; a heat spreader provided on a side opposite to the multilayer resin substrate across the IC, and in contact with the IC; a mold resin covering the periphery of the IC and the heat spreader; and a conductive film covering the mold resin and the heat spreader, where an inner side of the conductive film is in contact with the heat spreader, and the conductive film is electrically connected to a ground via hole of the multilayer resin substrate. | 2021-05-06 |
| 20210134734 | Semiconductor Device with Shield for Electromagnetic Interference - A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side. | 2021-05-06 |
| 20210134735 | STRESS MITIGATION STRUCTURE - A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut. | 2021-05-06 |
| 20210134736 | MICROELECTRONIC DEVICES WITH POLYSILICON FILL MATERIAL BETWEEN OPPOSING STAIRCASE STRUCTURES, AND RELATED DEVICES, SYSTEMS, AND METHODS - Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts. | 2021-05-06 |
| 20210134737 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a substrate. The semiconductor structure also includes a buffer layer disposed on the substrate. The semiconductor structure further includes a first semiconductor layer disposed on the buffer layer. The buffer layer includes a first buffer structure and a second buffer structure partially disposed on the first buffer structure. The material of the first buffer structure is different from the material of the second buffer structure. | 2021-05-06 |
| 20210134738 | CHIP - A chip is provided. The chip is provided with a circuit block. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel. The first sub-transistors and the second sub-transistors are disposed in a first row and a second row of the circuit block in a staggered manner. The first transistors disposed in the first row and the second row respectively receive a first input signal through different signal lines. The second transistors disposed in the first row and the second row respectively receive a second input signal through different signal lines. | 2021-05-06 |
| 20210134739 | SEMICONDUCTOR DEVICE - A semiconductor device including a base, a buffer member, a frame, a lid, and a semiconductor element, is disclosed. The ceramic frame is mounted on the copper base with the molybdenum buffer member interposed therebetween. The semiconductor element is sealed in a space within the frame defined by the lid. The frame includes a top portion, a lower stage portion that is disposed below the top portion and is provided with an input electrode and an output electrode, and an upper stage portion. The upper stage portion is formed in an arrangement direction of the input electrode and the output electrode, and is formed below the top portion and above the lower stage portion. The upper stage portion includes an upper stage connection portion formed on the periphery of the lower stage portion in a direction intersecting the arrangement direction of the input electrode and the output electrode. | 2021-05-06 |
| 20210134740 | CONFIGURABLE CAPACITOR - A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration. | 2021-05-06 |
| 20210134741 | SEMICONDUCTOR DEVICE - An object of the s int invention is to provide a semiconductor device suppressing a ringing. A semiconductor device in an embodiment 1 includes an IGBT, an SBD connected to the IGBT in series, a PND connected to the IGBT in series and parallelly connected to the SBD, and an output electrode connected between the IGBT and the SBD and between the IGBT and the PND. An anode electrode of the PND is connected to the output electrode by the wiring via an anode electrode of the SBD. | 2021-05-06 |
| 20210134742 | BOND PADS OF SEMICONDUCTOR DEVICES - A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad. | 2021-05-06 |
| 20210134743 | SEMICONDUCTOR DEVICE WITH SPACER OVER BONDING PAD - The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad | 2021-05-06 |
| 20210134744 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a pad structure positioned above the substrate, and a top groove positioned on a top surface of the pad structure. The method for fabricating the semiconductor device includes forming a pad structure over a substrate and forming a top groove on a top surface of the pad structure. | 2021-05-06 |
| 20210134745 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part. | 2021-05-06 |
| 20210134746 | BUMP STRUCTURE AND METHOD OF MANUFACTURING BUMP STRUCTURE - A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring. | 2021-05-06 |
| 20210134747 | BONDED SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure is disclosed, including a substrate, an insulating layer on the substrate, a barrier layer on the insulating layer, a bonding dielectric layer on the barrier layer, and a bonding pad extending through the insulating layer, the barrier layer and the bonding dielectric layer. A top surface of the bonding pad exposed from the bonding dielectric layer for bonding to another bonding pad on another substrate. A liner on a bottom surface of the bonding pad directly contacts the substrate. | 2021-05-06 |
| 20210134748 | SEMICONDUCTOR DEVICES HAVING ADJOINED VIA STRUCTURES FORMED BY BONDING AND METHODS FOR FORMING THE SAME - Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding layer having a plurality of first bonding contacts, and a first via structure extending vertically through the first bonding layer and into the first semiconductor structure. The second semiconductor structure includes a second bonding layer having a plurality of second bonding contacts, and a second via structure extending vertically through the second bonding layer and into the second semiconductor structure. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, the first via structure is in contact with the second via structure, and sidewalls of the first via structure and the second via structures have a staggered profile at the bonding interface. | 2021-05-06 |
| 20210134749 | Integrated Circuit Package and Method - In an embodiment, a device includes: a semiconductor substrate; a contact pad on the semiconductor substrate; a passivation layer on the contact pad and the semiconductor substrate; a die connector extending through the passivation layer, the die connector being physically and electrically coupled to the contact pad, the die connector including a first conductive material, the first conductive material being a Lewis acid having a first acid hardness/softness index; a dielectric layer on the die connector and the passivation layer; and a protective layer disposed between the dielectric layer and the die connector, the protective layer surrounding the die connector, the protective layer including a coordination complex of the first conductive material and an azole, the azole being a Lewis base having a first ligand hardness/softness index, where a product of the first acid hardness/softness index and the first ligand hardness/softness index is positive. | 2021-05-06 |
| 20210134750 | CONDUCTIVE MEMBERS FOR DIE ATTACH IN FLIP CHIP PACKAGES - In examples, a semiconductor package comprises a semiconductor die having an active surface; a conductive layer coupled to the active surface; and a polyimide layer coupled to the conductive layer. The package also comprises a conductive pillar coupled to the conductive layer and to the polyimide layer; a flux adhesive material coupled to the conductive pillar; and a solder layer coupled to the flux adhesive material. The package further includes a conductive terminal coupled to the solder layer and exposed to a surface of the package, the active surface of the semiconductor die facing the conductive terminal. | 2021-05-06 |
| 20210134751 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die. | 2021-05-06 |
