| 18th week of 2010 patent applcation highlights part 79 |
| Patent application number | Title | Published |
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| 20100115228 | Unified address space architecture - A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space. | 2010-05-06 |
| 20100115229 | System And Method For On-the-fly TLB Coalescing - An apparatus and method for coalescing TLB entries on-the-fly at virtual address translation time is disclosed. A search is made for a requested virtual address translation in the VHPT. Further searching is performed for additional VHPT entries meeting certain coalescing and compatibility criteria. The compatible VHPT entries are coalesced and stored in the TLB into a single combined TLB entry. | 2010-05-06 |
| 20100115230 | HASH FUNCTIONS USING RECURRENCY AND ARITHMETIC - Aspects relate to systems and methods for implementing a hash function using a stochastic and recurrent process, and performing arithmetic operations during the recurrence on portions of a message being hashed. In an example method, the stochastic process is a Galton-Watson process, the message is decomposed into blocks, and the method involves looping for a number of blocks in the message. In each loop, a current hash value is determined based on arithmetic performed on a previous hash value and some aspect of a current block. The arithmetic performed can involve modular arithmetic, such as modular addition and exponentiation. The algorithm can be adjusted to achieve qualities including a variable length output, or to perform fewer or more computations for a given hash. Also, randomizing elements can be introduced into the arithmetic, avoiding a modular reduction until final hash output production. | 2010-05-06 |
| 20100115231 | PSEUDO-RANDOM NUMBER GENERATION DEVICE, PSEUDO-RANDOM NUMBER GENERATION PROGRAM, AND MEDIUM CONTAINING PSEUDO-RANDOM NUMBER GENERATION PROGRAM - [Problems] To provide a highly efficient pseudo-random number generation device which can be used in a small-scale computer and a mobile terminal. | 2010-05-06 |
| 20100115232 | LARGE INTEGER SUPPORT IN VECTOR OPERATIONS - A vector processor or vector processing computer has a first vector register operable to store two or more vector elements that together comprise a single first large integer and a second vector register operable to store two or more vector elements that together comprise a single second large integer. An adder having a carry-in bit is operable to add the large integer in the first vector register to the large integer in the second vector register by using the carry-in bit to add sequential elements of the vector registers. | 2010-05-06 |
| 20100115233 | DYNAMICALLY-SELECTABLE VECTOR REGISTER PARTITIONING - The present invention is directed generally to dynamically-selectable vector register partitioning, and more specifically to a processor infrastructure (e.g., co-processor infrastructure in a multi-processor system) that supports dynamic setting of vector register partitioning to any of a plurality of different vector partitioning modes. Thus, rather than being restricted to a fixed vector register partitioning mode, embodiments of the present invention enable a processor to be dynamically set to any of a plurality of different vector partitioning modes. Thus, for instance, different vector register partitioning modes may be employed for different applications being executed by the processor, and/or different vector register partitioning modes may even be employed for use in processing different vector oriented operations within a given applications being executed by the processor, in accordance with certain embodiments of the present invention. | 2010-05-06 |
| 20100115234 | CONFIGURABLE VECTOR LENGTH COMPUTER PROCESSOR - A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core. | 2010-05-06 |
| 20100115235 | Eliminating Synchronous Grace Period Detection For Non-Preemptible Read-Copy Update On Uniprocessor Systems - A technique for optimizing grace period detection in a uniprocessor environment. An update operation is performed on a data element that is shared with non-preemptible readers of the data element. A call is issued to a synchronous grace period detection method. The synchronous grace period detection method performs synchronous grace period detection and returns from the call if the data processing system implements a multi-processor environment at the time of the call. The synchronous grace period detection determines the end of a grace period in which the readers have passed through a quiescent state and cannot be maintaining references to the pre-update view of the shared data. The synchronous grace period detection method returns from the call without performing grace period detection if the data processing system implements a uniprocessor environment at the time of the call. | 2010-05-06 |
| 20100115236 | HIERARCHICAL SHARED SEMAPHORE REGISTERS - A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores. | 2010-05-06 |
| 20100115237 | CO-PROCESSOR INFRASTRUCTURE SUPPORTING DYNAMICALLY-MODIFIABLE PERSONALITIES - A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities. | 2010-05-06 |
| 20100115238 | STREAM PROCESSING SYSTEM HAVING A RECONFIGURABLE MEMORY MODULE - A stream processing system includes a stream processing module coupled to a memory module and operable so as to fetch stream elements from the memory module, to process the stream elements fetched thereby, and to store processed stream elements in the memory module. The stream processing module includes a number (N) of stream processing units, and the memory module is configured with a number (N) of memory bank units each corresponding to a respective one of the stream processing units. The memory module is reconfigurable based on a desired inter-level configuration so that each of the memory bank units is configured to have a memory size sufficient to meet processing requirement of the respective one of the stream processing units. | 2010-05-06 |
| 20100115239 | VARIABLE INSTRUCTION WIDTH DIGITAL SIGNAL PROCESSOR - A DSP architecture achieves high code density and performance by using 16 bit encoding/decoding of three-register instructions and including orthogonal 64 register selection fields within a 32-bit instruction. A 64 entry register file allows high performance, while the 16-bit instruction size provides excellent code density in control type applications. | 2010-05-06 |
| 20100115240 | Optimizing performance of instructions based on sequence detection or information associated with the instructions - In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed. | 2010-05-06 |
| 20100115241 | KERNEL FUNCTION GENERATING METHOD AND DEVICE AND DATA CLASSIFICATION DEVICE - Kernel functions, the number of which is set in advance, are linearly coupled to generate the most suitable Kernel function for a data classification. An element Kernel generating unit | 2010-05-06 |
| 20100115242 | ENGINE/PROCESSOR COOPERATION SYSTEM AND COOPERATION METHOD - To provide an engine software cooperation mechanism which avoids stopping the operation of a high-speed engine during timer monitoring processing. This system checks occurrence of a timeout event by directly accessing the content of a session data memory without regard to the locking state of a session. If detecting the state of timeout, the system requests execution of timeout processing via a timer transmission circuit. By timeout processing, the time of timeout and the present time are checked again to confirm whether a timer is not cancelled. | 2010-05-06 |
| 20100115243 | Apparatus, Method and Instruction for Initiation of Concurrent Instruction Streams in a Multithreading Microprocessor - A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by allocating context for the new thread, copying the first operand to a program counter of the new thread context, copying the second operand to a register of the new thread context, and scheduling the new thread for execution. If no new thread context is free for allocation, the microprocessor raises an exception to the fork instruction. The fork instruction is efficient because it does not copy the parent thread general purpose registers to the new thread. The second operand is typically used as a pointer to a data structure in memory containing initial general purpose register set values for the new thread. | 2010-05-06 |
| 20100115244 | MULTITHREADING MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR INCREASING PIPELINE UTILIZATION EFFICIENCY - A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline. One or more instructions in the pipeline of the thread context associated with the thread context flush signal can be flushed or nullified. | 2010-05-06 |
| 20100115245 | DETECTING AND RECOVERING FROM TIMING VIOLATIONS OF A PROCESSOR - A system for detecting and correcting invalid calculation results due to a timing violation. A processor compares results of an instruction simultaneously executed by a first arithmetic pipeline and a second arithmetic pipeline of the processor. In the second arithmetic pipeline, the critical stage of the first arithmetic pipeline is divided to multiple stages. A first result calculated by the first arithmetic pipeline is speculatively executed within the processor. The second arithmetic pipeline calculates a second result. The processor compares the second result to the first result. When the results are identical, the first result is assigned as the final result with a complete status. When the results do not match, the processor replaces the first result with the second result. The processor may then cancel the speculatively executed instruction and issue the second result as a final result. The processor may then restart subsequent instructions using the second result. | 2010-05-06 |
| 20100115246 | SYSTEM AND METHOD OF DATA PARTITIONING FOR PARALLEL PROCESSING OF DYNAMICALLY GENERATED APPLICATION DATA - An improved system and method of data partitioning for parallel processing of dynamically generated application data is provided. An application may send a request to partition the application data specified by a data partitioning policy and to process each of the data partitions according to processing instructions. The data partitioning policy may be flexibly defined by an application for partitioning data any number of ways, including balancing the data volume across each of the partitions or partitioning the data by data type. Asynchronous data partition processors may be instantiated to perform parallel processing of the partitioned data. The data may be partitioned according to the data partitioning policy and processed according to the processing instructions. And the results may be returned to the application. | 2010-05-06 |
| 20100115247 | REPLACEMENT POLICY FOR HOT CODE DETECTION - Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed. | 2010-05-06 |
| 20100115248 | Technique for promoting efficient instruction fusion - A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction. | 2010-05-06 |
| 20100115249 | Support of a Plurality of Graphic Processing Units - Included are systems and methods for supporting a plurality of Graphics Processing Units (GPUs). At least one embodiment of a system includes a context status register configured to send data related to a status of at least one context and a context switch configuration register configured to send instructions related to at least one event for the at least one context. At least one embodiment of a system includes a context status management component coupled to the context status register and the context switch configuration register. | 2010-05-06 |
| 20100115250 | CONTEXT SWITCHING AND SYNCHRONIZATION - A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread. | 2010-05-06 |
| 20100115251 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR OPTIMIZING RUNTIME BRANCH SELECTION IN A FLOW PROCESS - A method, system, and computer program product for optimizing runtime branch selection in a flow process are provided. The method includes gathering performance metrics of flow branch behavior for executed flows in a runtime system over time and using aggregated performance metrics for the behavior to determine an optimal ordering of branches for a currently running flow. The optimal ordering is determined by identifying one or more branch points in the flow, generating ordering permutations for at least a portion of the branches in the branch point for the flow to identify any permutations that have not been executed, gathering metrics for permutation(s) of the branch point in the flow, comparing the metrics to performance metrics of executed flows having substantially similar flow branch behavior, and identifying optimal branch ordering for the permutation(s) based upon the comparison. The method also includes executing the flow according to the optimal branch ordering. | 2010-05-06 |
| 20100115252 | AUTOMATED FIRMWARE RECOVERY - According to one embodiment, a corrupted network hardware device may be automatically inspected and repaired. A default boot sequence may be suspended, and an external recovery device may inspect and repair the corrupted code by selectively repairing files and configuration settings in a minimally invasive manner, to preserve as many user settings as practicable. The network hardware device may then be re-booted from the repaired firmware. | 2010-05-06 |
| 20100115253 | METHOD AND SYSTEM FOR SECURELY DISTRIBUTING CONTENT - A system for securely distributing content is provided. A distribution system includes a content server that distributes content to content clients via a communications link or a tangible medium. The distribution system uses passwords to encrypt and decrypt content and to control access to sensitive information stored on the content clients. The distribution system initially receives various passwords from a user and encrypts each password. Some of the encrypted passwords are “identification passwords” and others are “encryption passwords.” The identification passwords are used to control access to sensitive information stored on the content clients, and the encryption passwords are used to encrypt and decrypt content that is distributed to the content clients. The distribution system configures each content client to contain the identification passwords and encryption passwords in a secure folder. | 2010-05-06 |
| 20100115254 | Synchronization in Multiple Environments - A method and apparatus for synchronizing different environments in response to a change in one of the environments. The term environment encompasses operating systems, virtual machines, and states. The synchronization functions when one environment controls a master file or the environments access a shared folder. The synchronization is one-way or two-ways. The synchronization applies to digital photos, personal information management data, shared maps and directions, documents, configuration data, network settings, browser data sync, account information for accessing the client, and local and web applications. | 2010-05-06 |
| 20100115255 | System and Method of Dynamically Building a Behavior Model on a Hardware System - A control system is dynamically built directly on a target hardware system. A host application on a host computer provides an interface to download configuration building blocks for the control system directly onto the target hardware. The host application is used to define building block type and connectivity. Microprocessor execution control of the system as well as block priority can likewise by defined by the host application. | 2010-05-06 |
| 20100115256 | METHOD, APPARATUS, AND SYSTEM FOR QUIESCING A BOOT ENVIRONMENT - An apparatus, system, and method are disclosed for quiescing a boot environment. A reservation module reserves a portion of a first storage device. A store module stores an update boot image to the reserved portion. A detection module detects the update boot image stored on the first storage device when the computer boots and executes the update boot image in place of a standard boot image in response to detecting the update boot image. The update boot image places a computer in a known quiescent state. | 2010-05-06 |
| 20100115257 | Systems and Methods to Provide Failover Support for Booting Embedded Hypervisor From an Internal Non-Volatile Memory Card - The present disclosure further relates to information handling systems with failover support for booting an embedded hypervisor, the information handling system. For example, an information handling system with failover support may comprise a processor; one or more applications configured to be executed, at least in part, by the processor; a memory communicatively coupled to the processor and comprising a basic input/output system (BIOS), the BIOS comprising a BIOS universal serial bus (USB) driver, the BIOS USB driver comprising a mass storage device driver; a primary internal embedded hypervisor non-volatile memory (NVM) card communicatively coupled to the memory, the first NVM card comprising a first bootable hypervisor image; and a back up internal embedded hypervisor NVM card communicatively coupled to the memory, the second NVM card comprising a second bootable hypervisor image. | 2010-05-06 |
| 20100115258 | IMAGE PROCESSING APPARATUS AND CONTROL METHOD THEREOF - Disclosed are an image processing apparatus and a control method of the image processing apparatus. The image processing apparatus includes: a storing unit in which booting data for system booting is stored; a random access memory (RAM) in which the booting data is loaded; a central processing unit which loads the booting data in the RAM if system power supply is turned off, and refers to the booting data loaded in the RAM to perform the system booting if the system power supply is turned on; and a control unit which cuts off power supply to the central processing unit, and controls the RAM to operate in a low power mode in which power is supplied to the RAM to maintain the booting data loaded in the RAM while the system power supply is turned off | 2010-05-06 |
| 20100115259 | Methods, Apparatuses, and Computer Program Products for Reducing Power Consumption in Computing Devices - A method, apparatus, and computer program product are provided for reducing power consumption in computing devices. An apparatus may include a processor configured to provide a user interface allowing a user to select a device power profile from a plurality of available device power profiles. The processor may be further configured to receive an indication of a selection of a device power profile. The processor may additionally be configured to implement the selected device power profile based at least in part upon the received indication. The processor may also be configured to measure power consumed by the device and calculate power consumption statistics based at least in part upon the measured power consumed. The processor may further be configured to send the calculated power consumption statistics to a community power savings portal. Corresponding methods and computer program products are also provided. | 2010-05-06 |
| 20100115260 | UNIVERSAL SECURE TOKEN FOR OBFUSCATION AND TAMPER RESISTANCE - Program obfuscation is accomplished with tamper proof token including an embedded oracle. A public obfuscation function can be applied to any program/circuit to produce a new obfuscated program/circuit that makes calls to the corresponding oracle to facilitate program execution. A universal circuit representation can be employ with respect to obfuscation to hide circuit wiring and allow the whole circuit to be public. Furthermore, the token or embedded oracle can be universal and stateless to enable a single token to be employed with respect to many programs. | 2010-05-06 |
| 20100115261 | EXTENSIBLE SEAL MANAGEMENT FOR ENCRYPTED DATA - Embodiments of the present invention address deficiencies of the art in respect to seal list management in decrypting encrypted data and provide a method, system and computer program product for extensible seal management for encrypted data. In an embodiment of the invention, a method for extensible seal management for encrypted data can include identifying multiple different seal hints of different seal hint formats for different seals in a seal list associated with encrypted data and selecting from amongst the multiple different seal hints, seal hints of a recognizable seal hint format. The method also can include filtering the seals in the seal list according to the selected seal hints and attempting decryption of the filtered seals with a decryption key specified by the selected seal hints to decrypt one of the filtered seals in order to reveal a bulk key. Finally, the method can include decrypting the encrypted data with the bulk key. | 2010-05-06 |
| 20100115262 | Wireless Network System and Wireless Communicaton Method - A wireless network system includes a user device, a client and an access point. In the wireless network system, a wireless network mode of the client is started in an AdHoc mode in response to specific operation, a wireless network mode of the user device is switched to an AdHoc mode when it is detected that the wireless network mode of the client is started in the AdHoc mode. Then, infrastructure network information including a network name and an encryption key for setting the wireless network communication in the infrastructure mode is transmitted from the user device to the client, and the wireless network mode of the client is switched to the infrastructure mode on the basis of the infrastructure network information. | 2010-05-06 |
| 20100115263 | TRACKING ELECTRONIC CONTENT - A method of tracking electronic content includes producing a file of electronic content and executable instructions that collect notification information and attempt to transmit the notification information to an address when triggered by an event. The executable instructions deny access to the electronic content until the notification information is transmitted successfully. | 2010-05-06 |
| 20100115264 | System and Method for Processing Encoded Messages for Exchange with a Mobile Data Communication Device - A system and method are provided for pre-processing encrypted and/or signed messages at a host system before the message is transmitted to a wireless mobile communication device. The message is received at the host system from a message sender. There is a determination as to whether any of the message receivers has a corresponding wireless mobile communication device. For each message receiver that has a corresponding wireless mobile communication device, the message is processed so as to modify the message with respect to one or more encryption and/or authentication aspects. The processed message is transmitted to a wireless mobile communication device that corresponds to the first message receiver. The system and method may include post-processing messages sent from a wireless mobile communications device to a host system. Authentication and/or encryption message processing is performed upon the message. The processed message may then be sent through the host system to one or more receivers. | 2010-05-06 |
| 20100115265 | System And Method For Enhanced Network Entrance Into A Wireless Network - In one embodiment, a method for wireless communication includes providing, at a base station, access to a network to a preferred endpoint. The method includes sending, at the base station, at least one cryptographic parameter to the preferred endpoint. In addition, the method includes receiving, at the base station, a plurality of ranging codes from the preferred endpoint. The plurality of ranging codes are received after the base station has ceased providing the preferred endpoint access to the network. Also, the method includes determining, at the base station, that the plurality of received ranging codes correspond to a plurality of ranging codes of a predetermined set of ranging codes. The predetermined set of ranging codes is determined utilizing the at least one cryptographic parameter. Further, the method includes providing, at the base station, an entrance to the network to the preferred endpoint in response to determining that the plurality of received ranging codes correspond to the plurality of ranging codes of the predetermined set of ranging codes. | 2010-05-06 |
| 20100115266 | METHOD AND DEVICE FOR ENABLING A TRUST RELATIONSHIP USING AN UNEXPIRED PUBLIC KEY INFRASTRUCTURE (PKI) CERTIFICATE - A method and device are useful for enabling a trust relationship using an unexpired public key infrastructure (PKI) certificate, where a current status of the PKI certificate is unavailable. The method includes determining at a relying party that a certificate status update for the PKI certificate is unavailable (step | 2010-05-06 |
| 20100115267 | METHOD AND DEVICE FOR ENABLING A TRUST RELATIONSHIP USING AN EXPIRED PUBLIC KEY INFRASTRUCTURE (PKI) CERTIFICATE - A method and device are useful for enabling a trust relationship using an expired public key infrastructure (PKI) certificate. The method includes determining at a relying party a maximum permissible grace period during which the PKI certificate can be conditionally granted a valid status (step | 2010-05-06 |
| 20100115268 | Network Device and Computer Readable Medium Therefor - A network device, connectable with a service providing server and an authentication sever via a network, includes an acquisition information storage storing acquisition information for acquiring a certificate corresponding to each of services the service providing server provides, a certificate storage storing certificates acquired from the authentication server, a determining unit that, in response to acceptance of a request for utilizing a service, determines whether a certificate necessary for utilizing the requested service is stored in the certificate storage, and a controller that, when the necessary certificate is not stored, reads out acquisition information for the necessary certificate from the acquisition information storage, makes a certificate acquiring unit acquire the necessary certificate from the authentication server using the acquisition information, and stores the necessary certificate into the certificate storage. When the necessary certificate is stored, the controller makes the certificate acquiring unit acquire the necessary certificate from the certificate storage. | 2010-05-06 |
| 20100115269 | Revoking Malware in a Computing Device - A computing device is operated in a manner which provides improved checking to determine whether or not an authentication certificate for a software application being loaded onto the device has been revoked. In the case of trusted certificate chains that contain no revocation information, the device checks using an AuthorityInfoAccess extension (AIA) as selected by the device. In the case of untrusted certificate chains, notably including self-signed certificates, the device is controlled so that it ignores any authentication revocation information provided with the software application and always uses information stored on the device. | 2010-05-06 |
| 20100115270 | Authentication of a Consumable - A method authenticating a consumable is disclosed. The consumable includes a first integrated circuit operative to receive data and return the data encrypted. The method receives a random number from a trusted second integrated circuit. The random number is communicated to the first integrated circuit, and in response a first message containing the random number encrypted by the first integrated circuit is received from the first integrated circuit. Also, a second message containing the random number encrypted by the trusted integrated circuit is received from the trusted second integrated circuit. By comparing the first and second messages it is determined that the consumable is authentic when the first and second messages are the same. | 2010-05-06 |
| 20100115271 | Method of Automatically Establishing a Security Link for a Wireless Communication System and Related Communication Device - A method for a access point device having first network identity information to automatically establish a security link with a peer access point device in a wireless communication system includes searching and receiving a beacon corresponding to the peer access point device by radio frequency scan, obtaining second network identity information corresponding to the peer access point device from the beacon, determining a primary-secondary relationship for the access point device and the peer access point device according to the first and second network identity information, generating or receiving security data according to the primary-secondary relationship, and then establishing the security link with the peer access point device according to the security data. | 2010-05-06 |
| 20100115272 | COMMUNICATING A PACKET FROM A MESH-ENABLED ACCESS POINT TO A MESH PORTAL IN A MULTI-HOP MESH NETWORK - Methods are provided for processing a packet received by a mesh-enabled access point (MAP). When a first MAP receives a packet it can determine whether the packet is destined for a mesh portal based on the destination address. If so, the first MAP can retrieve an encryption key corresponding to the mesh portal, use the encryption key to encrypt the packet and set a mesh forwarding flag in the packet to indicate that the packet is destined for a mesh portal, and is encrypted with an encryption key corresponding to the mesh portal, and then forward the packet to the next hop MAP towards the a mesh portal. The mesh forwarding flag indicates that the packet is destined for a mesh portal, is encrypted with an encryption key corresponding to the mesh portal, and is to be forwarded to the next hop MAP without performing decryption/re-encryption processing on the packet. When a MAP receives a packet, the first MAP it determines whether a mesh forwarding flag is set in the packet. When the mesh forwarding flag is set in the packet, the first MAP skips decryption/re-encryption processing of the packet, and forwards the packet to the next hop MAP towards the mesh portal. When the mesh forwarding flag is not set in the packet, the first MAP retrieves an encryption key corresponding to the mesh portal, encrypts the packet using the encryption key, sets a mesh forwarding flag in the packet and forwards the packet to the next hop MAP. | 2010-05-06 |
| 20100115273 | SYSTEM AND METHOD FOR FINDING KERNEL MEMORY LEAKS - The invention provides a system and method for tracking memory information associated with dynamically loaded kernel modules with the help of a tracking system. The tracking system defines its own kernel memory allocation functions. Whenever, a dynamic kernel module is loaded/unloaded into/from the kernel space, these newly defined functions are called in response to kernel memory allocation/de-allocation requests from the kernel module. The newly defined functions are responsible for allocating and de-allocating kernel memory, as well as, keeping track of information relating to the kernel memory allocations/de-allocations. The tracked information may be used to identify the source of kernel memory leaks. | 2010-05-06 |
| 20100115274 | Conditional access system and method - The present invention relates to methods of and systems for providing conditional access to electronic content. Electronic content is provided to a user along with authorization information. The electronic content may be transmitted to the user, and the user may use the authorization information to access the electronic content. An authorization code may be provided to the user such that the user may be granted access to the content based on a comparison of the provided authorization code and a second authorization code transmitted with the electronic content, and transmission of the second authorization code may be controlled by a content provider to control access by the user. | 2010-05-06 |
| 20100115275 | SECURITY SYSTEM AND METHOD FOR WIRELESS COMMUNICATION SYSTEM - A security system processing method of a User Equipment (UE) and a security system for a wireless communication system are provided. The security processing method of the UE includes transmitting a Layer 3 message including a UE security capability to a Mobility Management Entity (MME) and the eNB, receiving a Access Stratum Security Mode Command (AS SMC) including a AS security algorithm selected by the eNB, as a result of verification of the UE security capability and information received from the MME, and a AS Message Authentication Code (MAC), transmitting a AS security mode complete message including the AS SMC to the eNB after verification of integrity of the AS SMC using the AS MAC, and transmitting, when receiving a Non Access Stratum (NAS) SMC including the UE security capability, a NAS security mode complete message to the MME after verification of integrity of the NAS SMC. | 2010-05-06 |
| 20100115276 | SYSTEM AND METHOD FOR DERIVATING DETERMINISTIC BINARY VALUES - Disclosed herein are systems, computer-implemented methods, and computer-readable media for deriving a deterministic binary value. The method consists of generating a graph from multiple inputs, formalizing the graph, calculating paths between starting and ending nodes in the graph using a shortest path algorithm and performing a digest operation based on the derived paths to generate a deterministic binary value. In another aspect of this disclosure, authentication is performed utilizing deterministic binary values and a graph-merging function. This method allows for diversity in complexity, thus maintaining security on different computer platforms. | 2010-05-06 |
| 20100115277 | METHOD AND DEVICE FOR MUTUAL AUTHENTICATION - A method of authenticating communication between a first and second party (or node) over an insecure, high bandwidth communications network, in which the first party (C) authenticates the second party (M) using a communications protocol comprising a first communications phase through a first communications channel over the insecure, high bandwidth communications network to establish a secure mode of communications between the first and second party, followed by a second communications phase of receiving information from the second party over a second communications channel, such as an empirical channel, and enabling a user to make a human comparison of the information received from the second party with information generated by the first party thereby enabling the user to authenticate the second party in the event of the information from both parties agrees. | 2010-05-06 |
| 20100115278 | SUPPORT OF MULTIPLE PRE-SHARED KEYS IN ACCESS POINT - A method of operating an access point (AP) configured to support multiple pre-shared keys at a given time to authenticate its associated client devices. Each client device associated with the AP is provisioned with a key. To authenticate the client device tat attempts to connect to the AP, the AP determines which pre-shared key (PSK) of the multiple supported pre-shared keys (PSKs). if any, matches information including the key received from the client device. When the information matches, the client device is allowed to connect to the AP. Provisioning the AP with multiple PSKs allows selectively disconnecting associated client devices from the AP. The AP may be configured to support PSKs of different lifetime and complexity. Removing a PSK of the multiple PSKs supported by the AP and disconnecting a client device that uses this PSK does not disconnect other client devices using different keys to access the AP. | 2010-05-06 |
| 20100115279 | Method for pairing and authenticating one or more medical devices and one or more remote electronic devices - A method for authenticating a medical device and a remote electronic device may include generating a PIN code by one device, capturing the generated PIN code with the other device, checking authentication of the PIN code, which is based at least in part on the captured PIN code, by the one device, generating a strong key by the one device, sending the strong key encrypted to the other device, checking authentication of the sent strong key by the one device, and upon successful authentication, storing the strong key in a memory of the one device and the other device. The roles of the medical device and the remote electronic device may be reversed in the authenticating method. The authenticating method may be preceded by a pairing process and/or followed by a binding process. | 2010-05-06 |
| 20100115280 | METHOD OF COMMUNICATIONS AND COMMUNICATION NETWORK INTRUSION PROTECTION METHODS AND INTRUSION ATTEMPT DETECTION SYSTEM - A method, system and computer readable medium for protecting a communications device connected to a communications system against an unauthorized intrusion, including providing a variable identifier to the communications device and entities authorized access thereto. The variable identifier is provided to a user address book and assigned with a permanent identifier and the permanent identifier, but not the variable identifier, is available to a user. The presence or absence of the correct variable identifier is sensed during an attempt to access the communications device for granting or denying access to the communications device. A new variable identifier is periodically provided to the communications device and to the authorized entities and to the user address book and assigned with the permanent identifier, wherein the permanent identifier, but not the new variable identifier, is available to the user. | 2010-05-06 |
| 20100115281 | ATTRIBUTES IN CRYPTOGRAPHIC CREDENTIALS - Method and apparatus for generating cryptographic credentials certifying user attributes and making cryptographic proofs about attributes encoded in such credentials. Attributes are encoded as prime numbers E in accordance with a predetermined mapping and a cryptographic credential is generated encoding E. To prove that an attribute encoded in a cryptographic credential associated with a proving module of the system is a member of a predetermined set of user attributes, without revealing the attribute in question, the proving module determines the product Q of respective prime numbers corresponding to the attributes in the set in accordance with the predetermined mapping of attributes to prime numbers. The proving module demonstrates to the receiving module possession of a cryptographic credential encoding a secret value that is the prime number E, and then whether this secret value divides the product value Q. | 2010-05-06 |
| 20100115282 | METHOD FOR WATERMARK HIDING IN DESIGNATED APPLICATIONS - A method, service, and product for hiding a watermark existing in a digital media within a software application, comprising creating a set pattern of pixels represented by coordinates which represent a red, a green, a blue, and an alpha level of color, where the set pattern of pixels covers a set of original pixels within the digital media. The method including determining whether the transparency level of color should be removed from the set pattern of pixels based on a known pixel transparency removal parameter; and modifying the set pattern of pixels to remove the transparency level of color coordinates, wherein an original pixel color can be seen because the set pattern of pixels are made transparent; or not modifying the set of pixels to remove the transparency level of color coordinates, wherein the original pixel color cannot be seen because the set of original pixels is made transparent. | 2010-05-06 |
| 20100115283 | SYSTEMS AND METHODS FOR USING CRYPTOGRAPHY TO PROTECT SECURE AND INSECURE COMPUTING ENVIRONMENTS - Computation environments are protected from bogus or rogue load modules, executables, and other data elements through use of digital signatures, seals, and certificates issued by a verifying authority. A verifying authority—which may be a trusted independent third party—tests the load modules and/or other items to verify that their corresponding specifications are accurate and complete, and then digitally signs them based on a tamper resistance work factor classification. Secure computation environments with different tamper resistance work factors use different digital signature authentication techniques (e.g., different signature algorithms and/or signature verification keys), allowing one tamper resistance work factor environment to protect itself against load modules from another tamper resistance work factor environment. The verifying authority can provide an application intended for insecure environments with a credential having multiple elements covering different parts of the application. To verify the application, a trusted element can issue challenges based on different parts of the authenticated credential that the trusted element selects in an unpredictable (e.g., random) way, and deny service (or take other appropriate action) if the responses do not match the authenticated credential. | 2010-05-06 |
| 20100115284 | SUPPORT OF TAMPER DETECTION FOR A LOG OF RECORDS - Tamper detection of audit records comprises configuring a proxy for adding tamper evidence information to audit information by obtaining audit records from at least one audit record generating source, grouping obtained audit records into subsets of audit records and providing tamper evidence processing to the subsets utilizing a cryptographic mechanism to calculate a signature over each subset of audit records. The proxy groups the subsets such that each subset contains at least one designated carryover audit record that overlaps into a next subset so that each carryover audit record is associated with at least two signatures. As such, the proxy creates an overlapping chain of digitally signed audit records subsets. The proxy further forwards the tamper evident audit records from the tamper evidence adding proxy to a corresponding audit log storage subsystem for storage, storing the calculated signatures. | 2010-05-06 |
| 20100115285 | MIX-NET SYSTEM - Each participant apparatus ( | 2010-05-06 |
| 20100115286 | LOW LATENCY BLOCK CIPHER - A block cipher is provided that secures data by encrypting it based on the memory address where it is to be stored. When encrypting data for storage in the memory address, the memory address is encrypted in a first plurality of block cipher rounds. Data round keys are generated using information from the first plurality of block cipher rounds. Data to be stored is combined with the encrypted memory address and encrypted in a second plurality of block cipher rounds using the data round keys. The encrypted data is then stored in the memory location. When decrypting data, the memory address is again encrypted as before while the encrypted stored data is decrypted in a second plurality of the block cipher rounds using the data round keys to obtain a partially decrypted data. The partially decrypted data is combined with the encrypted memory address to obtain fully decrypted data. | 2010-05-06 |
| 20100115287 | SYSTEM AND METHOD FOR OBFUSCATING CONSTANTS IN A COMPUTER PROGRAM - Disclosed herein are systems, computer-implemented methods, and tangible computer-readable media for obfuscating constants in a binary. The method includes generating a table of constants, allocating an array in source code, compiling the source code to a binary, transforming the table of constants to match Pcode entries in an indirection table so that each constant in the table of constants can be fetched by an entry in the indirection table. A Pcode is a data representation of a set of instructions populating the indirection table with offsets toward the table of constants storing the indirection table in the allocated array in the compiled binary. The method further includes populating the indirection table with offsets equivalent to the table of constants, and storing the indirection table in the allocated array in the compiled binary. Constants can be of any data type. Constants can be one byte each or more than one byte each. In one aspect, the method further includes splitting constants into two or more segments, treating each segment as a separate constant when transforming the table of constants, and generating a function to retrieve and reconstruct the split constants. | 2010-05-06 |
| 20100115288 | SYSTEM AND METHOD OF ENCRYPTION FOR DICOM VOLUMES - Digital image storage and management systems capable of producing encrypted DICOM volumes on different types of media (e.g., Blu-ray, CD, DVD, memory stick, USB flash drive, etc.), with or without the automatic generation of labels, systems and mechanisms to generate and manage passwords for the encrypted volumes, and systems and mechanisms to manage access to encrypted data on such volumes are disclosed. Generated encrypted DICOM volumes, which can comprise confidential patient data, can be securely interchanged, archived, and distributed to users. The disclosed systems and methods can permit authorized users to access encrypted data, even if the users do not have access to the original encryption mechanism. Encrypted data stored on the volume can be easily and securely accessed by a variety of authorized users. | 2010-05-06 |
| 20100115289 | Method and apparatus for encrypting user data - A mobile terminal is capable of performing message encryption. The mobile terminal includes a display unit that can display contents of a message and an input unit that can receive a selection input for a portion of the displayed content. A portion of the displayed content can be selected for encryption. The selected portion of the displayed content is encrypted. The mobile terminal can store the message containing the encrypted content and information regarding the password. | 2010-05-06 |
| 20100115290 | KEYBOARD AND METHOD FOR SECURE TRANSMISSION OF DATA - A keyboard, in particular a POS (point of sale, point of service) keyboard, bank keyboard, keyboard for secure data entry, and a method for secure transmission of data that is entered through various data entry modules such as, e.g., magnetic card readers, chip card readers, key switches, or a keypad, to an external device connected to the keyboard, for example a computer. The keyboard comprises at least one data entry module for entering data and a keyboard control device with at least one receiving device for receiving the entered data, an encryption device for encrypting the received data by means of an encryption algorithm, wherein the encryption algorithm is present in the form of program code, and a transmission device for transmitting the data encrypted by the encryption means to the external device connected to the keyboard control device, wherein the encryption algorithm can be selected by the user from multiple predefined encryption algorithms and associated with the data entry module. | 2010-05-06 |
| 20100115291 | Secure Virtual Machine Manager - Secure processing systems providing host-isolated security are provided. An exemplary secure processing system includes a host processor and a virtual machine instantiated on the host processor. A virtual unified security hub (USH) is instantiated on the virtual machine to provide security services to applications executing on the host processor. The virtual USH may further include an application programming interface (API) operable to expose the security services to the applications. A further exemplary secure processing system includes a host processor running a windows operating system for example, a low power host processor, and a USH processor configured to provide secure services to both the host processor and the low power host processor isolating the secure services from the host processor and the low power processor. The USH processor may also include an API to expose the security services to applications executing on the host processor and/or the low power host processor. | 2010-05-06 |
| 20100115292 | MULTI-VOLTAGE POWER SUPPLY - A multi-voltage power supply includes a transformer connecting to an AC power source to regulate voltage and deliver voltage-transformed electric power, a rectification output circuit connecting to the transformer to rectify the voltage-transformed electric power and output first DC power, and at least one voltage regulation circuit to receive the first DC power from a first DC power output line and regulate to become second DC power. The first DC power on the first DC power output line reaches a first potential after a voltage boosting period. The rectification output circuit has a rear end installing a hysteresis unit which adds a delay time in the voltage boosting period to defer the time of the first DC power reaching the first potential. Thereby the time difference between delivering DC power output of the first DC power and the second DC power can be regulated to avoid abnormal start of computers. | 2010-05-06 |
| 20100115293 | DETERMINISTIC MANAGEMENT OF DYNAMIC THERMAL RESPONSE OF PROCESSORS - Methods and apparatus relating to deterministic management of dynamic thermal response of processors are described. In one embodiment, available thermal headroom may be used to extract the performance potential in a deterministic way, e.g., such that it reduces or even eliminates the product-to-product variations. Other embodiments are also disclosed and claimed. | 2010-05-06 |
| 20100115294 | Delayed shutdown system for auxiliary power supply device of personal computer - Disclosed is a delayed shutdown system applicable to a computer system including two power supply devices and a slave power supply interface card. A secondary power supply device of the delayed shutdown system serves as an auxiliary power supply to the computer system. The slave power supply interface card includes a delayed shutdown circuit, which delays the shutdown of the auxiliary power supply when the computer system is shut down, so that after the computer system is shut down, the secondary power supply device is maintained in operation for a given period of time. Thus, even the peripheral devices connected to the slave power supply interface card are set in a signal silent condition after the computer is shut down, they can maintain in operation with the electrical power supplied from the auxiliary power supply during the given period of time and thus they are provided with sufficient time complete a smooth shutdown operation by returning to a home position/an original condition and sufficiently dissipating heat therefrom. | 2010-05-06 |
| 20100115295 | Method And System For Energy Efficient Communication Among One Or More Interfaces In A Communication Path - Network devices coupled via serial and/or parallel interfaces may determine a power level mode of operation according to an energy efficient network communication control policy and may configure one or more of the interfaces for the lower power mode. The network devices may comprise a PHY, a MAC and/or higher layer devices. The interfaces may comprise a XGMII extender, a XAUI and/or a XFI device. The interfaces may comprise a backplane PHY, for example, a 10 GBASE-KR, a 10 GBASE-KX4 and/or a 1 GBASE-KX PHY which may perform FEC. The interfaces may comprise direct attach copper such as SFP+ and/or InfiniBand and/or 10 GBASE-CX4 PHYs. The interfaces may comprise a pluggable transceiver module. Energy efficient network control data may be communicated to and/or from the network devices which may enter and/or exit a lower power mode of operation. | 2010-05-06 |
| 20100115296 | INFORMATION PROCESSOR - According to one embodiment, an information processor, which is capable of supplying power to an external device, includes a connector, a storage module, and a power supply control module. The connector connects the external device to the information processor. The storage module stores a plurality of power supply modes each defining conditions of respective modules of the information processor to make the external device connected to the connector chargeable. The power supply control module selects a power supply mode effective for the external device from the power supply modes when the external device is connected to the connector, and sets the respective modules of the information processor according to the conditions corresponding to the power supply mode selected. | 2010-05-06 |
| 20100115297 | CIRCUIT, METHOD FOR OPERATING A CIRCUIT, AND USE - Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch. | 2010-05-06 |
| 20100115298 | APPARATUS AND METHOD FOR ADAPTIVELY CHANGING CONSTANT POWER LEVEL OF SYSTEM IN COMPLIANCE WITH SYSTEM SPECIFICATION - An apparatus and method for adaptively changing a constant power level of a system in compliance with a current system specification can improve safety issues such as overheating, due to excess charging capacity. After purchase/after market add-ons to the system made by a customer can change the load such that the present invention adaptively changes the constant power level supplied to match the after initial purchase add-ons. The method includes acquiring system specification information, searching for a constant power level corresponding to the acquired system specification information, and changing a constant power level according to the searched constant power level. | 2010-05-06 |
| 20100115299 | COMPENSATION FOR HIGH POWERED MIDSPAN POWER SOURCING EQUIPMENT - A midspan unit arranged to supply power to a powered device over data communication cabling constituted of a signal conditioner exhibiting a transfer function with a gain of not less than −0.4 dB as compared with: (K | 2010-05-06 |
| 20100115300 | METHOD AND DEVICE FOR ADJUSTING CLOCK FREQUENCY AND OPERATING VOLTAGE OF COMPUTER SYSTEM - A frequency and voltage adjusting method is provided for adjusting a clock frequency or an operating voltage of a first component of a computer system. Firstly, a control function of a computer keyboard is enabled. Then, an initiating signal is generated by the computer keyboard. After the initiating signal is received, a control key of the computer keyboard is depressed to generate a frequency-increasing signal, a frequency-decreasing signal, a voltage-increasing signal or a voltage-decreasing signal. The clock frequency is increased according to the frequency-increasing signal. The clock frequency is decreased according to the frequency-decreasing signal. The operating voltage is increased according to the voltage-increasing signal. The operating voltage is decreased according to the voltage-decreasing signal. | 2010-05-06 |
| 20100115301 | CPU POWER DELIVERY SYSTEM - A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout. | 2010-05-06 |
| 20100115302 | LOW POWER ZIGBEE DEVICE AND LOW POWER WAKE-UP METHOD - Provided is a low-power ZigBee device provided with a sleeping mode and an active mode including a power supplying unit for supplying a power; a Medium Access Control (MAC) processing unit for receiving a wake-up packet and for controlling a modem unit and an Radio Frequency (RF) unit; and a Central Processing Unit (CPU) for receiving and processing a data packet, wherein the MAC processing unit makes the power supplying unit apply a power to the CPU based on a result of checking an identification (ID) of the wake-up packet. | 2010-05-06 |
| 20100115303 | SYSTEM AND METHOD OF UTILIZING RESOURCES WITHIN AN INFORMATION HANDLING SYSTEM - A system and method of utilizing resources within an information handling system are disclosed. In a particular form, a method of utilizing an information handling system can include detecting an operating state controllable by a state controller configured to enable a plurality of operating environments including a host environment and a reduced power environment. The method can also include detecting an event operable to alter the operating state to enable an operating environment of the plurality of operating environments. According to an aspect, the operating environment can be used separate from a host system operable to enable the host environment. | 2010-05-06 |
| 20100115304 | POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES - Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed. | 2010-05-06 |
| 20100115305 | Methods and Apparatus to Provision Power-Saving Storage System - A power-saving computer system comprises a plurality of storage areas provided by one or more storage systems, including at least one first storage area which is always powered on and at least one second storage area which is periodically powered on and off according to a power control schedule. The at least one first storage area provides primary and secondary volumes of a first backup set that is scheduled as always paired. For a second backup set that is scheduled as normally suspended and resynchronized according to a backup schedule, a primary volume of the second backup set is included in the at least one first storage area and a secondary volume of the second backup set is included in the at least one second storage area. The at least one second storage area is powered on during every backup time for resynchronizing the second backup set according to the backup schedule. | 2010-05-06 |
| 20100115306 | METHOD AND SYSTEM FOR CONTROL OF ENERGY EFFICIENCY AND ASSOCIATED POLICIES IN A PHYSICAL LAYER DEVICE - Aspects of a method and system for physical layer control of energy efficiency and associated policies in a physical layer device. In this regard, operation of a PHY device may be controlled based on one or more energy efficient networking (EEN) control policies executed from within the PHY device. The one or more control policies may enable management of power consumption associated with communication of data via the PHY device. A mode of operation of the PHY device may be selected based on the control policy. One or more components of the PHY device may be reconfigured based on the selected mode of operation. The selected mode of operation may comprise a low power idle (LPI) mode of operation or a subset PHY mode of operation. The control policy may be executed within the PHY device utilizing hardware, software, and/or firmware within the PHY device. | 2010-05-06 |
| 20100115307 | METHOD AND SYSTEM FOR ENERGY EFFICIENT NETWORKING VIA PACKET INSPECTION - Aspects of a method and system for energy efficient networking via packet inspection are provided. In various embodiments of the invention, a network device may include one or more circuits operable to inspect one or both of ingress and/or egress packets in the network device. The one or more processors may be operable to predict traffic in the network device based on the inspection. The one or more processors may be operable to, based on the predicted traffic, control a mode of operation of the network device to manage power consumption in the network device. A downlink path within the network device may be configured based on inspection of packets conveyed along a corresponding uplink path. An uplink path within the network device may be configured based on inspection of packets conveyed along a corresponding downlink path. | 2010-05-06 |
| 20100115308 | COMMUNICATION DEVICE AND POWER SUPPLY METHOD - Provided is a communication device capable of efficiently performing a power supply control when reducing power consumption by reducing the time during which the power is supplied. In the device, a CPU power saving control unit ( | 2010-05-06 |
| 20100115309 | ANTICIPATION OF POWER ON OF A MOBILE DEVICE - A method of managing the power up of a device that has power down state; and at least two power up states, wherein the method includes the following steps:
| 2010-05-06 |
| 20100115310 | DISK ARRAY APPARATUS - A disk array apparatus includes: a plurality of storage units for storing data redundantly, the data of the at least one of the storage units being recoverable by the rest of the storage units; and a controller for controlling the storage units to have write data written into redundantly in response to a write command from the exterior, and controlling at least one of the storage units to assume an inactive state under a power saving mode and controlling the rest of the storage units to produce read out data in response to a read command from the exterior during the power saving mode. | 2010-05-06 |
| 20100115311 | PCI Express System and Method of Transiting Link State Thereof - A PCI Express system and a method of transitioning link state thereof. The PCI Express system includes an upstream component, a downstream component and a link. The upstream component and the downstream component transmit data to each other via the link. When at least one of the upstream component and the downstream component stops data transmission under a normal working state and if the system idle time period reaches a threshold idle time, then transiting the link into a second link state | 2010-05-06 |
| 20100115312 | TECHNIQUES FOR ENTERING A LOW-POWER LINK STATE - Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state. | 2010-05-06 |
| 20100115313 | INFORMATION HANDLING SYSTEM WITH INTEGRATED LOW-POWER PROCESSING RESOURCES - An information handling system employs low-power processing. In a particular form, an information handling system can include a processing system configured operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system. The information handling system can also include a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system. The operation of the low-power processing system can be separate from the operation of the processing system. The information handling system can also include a chipset including a processor of the processing system and operable to be enabled during operation of the processing system. The processor can be configured to be disabled during operation of the low-power processing system. | 2010-05-06 |
| 20100115314 | POWER CONTROL FOR INFORMATION HANDLING SYSTEM HAVING SHARED RESOURCES - An information handling system includes at least two processing systems that share system resources. In response to detecting a designated event, a power control module of the information handling system can select one of a plurality of available power profiles. The power profile can be selected based on the event and state information indicative of a state of the processing systems. Based on the selected profile, the power control module can set an operational power mode of one or more of the shared system resources. | 2010-05-06 |
| 20100115315 | ESTABLISHING POWER SAVE MODE IN HYPERVISOR SYSTEM - A hypervisor intercepts a reduced power mode call from a guest operating system (GOS) and executes reduced power scripts, prior to passing control back to BIOS for entry into the reduced power mode. | 2010-05-06 |
| 20100115316 | METHOD AND SYSTEM FOR MANAGING ENERGY EFFICIENCY OF A NETWORK LINK VIA PLUGGABLE TRANSCEIVER MODULES IN AN ENERGY EFFICIENT NETWORK DEVICE - An Ethernet network may comprise link partners that may be coupled via an Ethernet link. The link partners may comprise pluggable PHY devices. The pluggable PHY devices and/or other link partner devices may determine energy efficient network (EEN) control policies, may select a power level mode and may configure the link partners to operate in the power level mode. Some components may be reconfigured prior to sending an energy efficient network control signal to a link partner and configuring remaining components. Hardware, software and/or firmware may execute the pluggable PHY energy efficient network control policies. Packet data pending delivery may be buffered in the pluggable PHY. The pluggable PHY devices may comprise a MAC and/or a SERDES device. Exemplary form factors for the pluggable PHYs may comprise a SFP, a SFP+, a XENPAK, a X2, a XFP and/or a XPAK. Low power idle mode and/or sub-rate mode may be utilized. | 2010-05-06 |
| 20100115317 | GENERATION OF AN IDLE MODE SIGNAL FOR AN ELECTRICAL CONTROL DEVICE - A method for generating a low-voltage power supply for an electrical control device, the method includes switching a first power supply unit to one of an active mode and an idle mode by inputting an activation/deactivation input to the first power supply unit, wherein the activation/deactivation input is input by one of connecting a low-voltage switching signal to the first power supply unit and disconnecting the low-voltage switching signal from the first power supply unit, wherein the low-voltage switching signal is generated at an output end by an additional power supply unit, at least in the idle mode of the first power supply unit, and wherein the low-voltage signal is one of connected and disconnected from the activation/deactivation input of the power supply unit using a low-voltage switch. The invention further relates to a low-voltage power supply circuit of an electrical control device for carrying out such a method. | 2010-05-06 |
| 20100115318 | DATA PROCESSING DEVICE AND POWER CONTROL METHOD - A data processing device comprising: a receiving unit operable to receive a control signal from a display device externally connected; a signal processing unit for operable to generate video data and/or audio data; a drive unit operable to store the data generated by the signal processing unit to a recording medium; a signal output unit operable to output a video signal and/or audio signal; and a control unit operable to control operation of the signal processing unit, the drive unit, and the signal output unit; the data processing device further comprising: a power control unit operable to control electric power supplied to the signal processing unit, the drive unit, the signal output unit, and the control unit, wherein the power control unit can control supplying of the electric power in three power states including at least a power-off state, a recording standby state, a power-on state, and wherein the power control unit stops the supplying of the electric power to at least the drive unit in the power-off state, supplies the electric power to at least the drive unit and the control unit in the recording standby state, and supplies the electric power to the signal processing unit, the drive unit, the signal output unit, and the control unit in the power-on state, and wherein the signal output unit stops outputting of the video signal and/or audio signal in the power-off state and the recording standby state, and outputs the video signal and/or audio signal in the power-on state, and wherein the power control unit switches the power state from the power-off state to the recording standby state when the receiving unit receives a signal indicating that the display device is turned on, in the power-off state, and wherein the power control unit switches the power state from the recording standby state to the power-on state when the receiving unit receives a signal instructing start of a recording operation or a power state confirmation signal inquiring the power state of the data processing device from the display device, in the recording standby state. | 2010-05-06 |
| 20100115319 | STORING DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - A storing device includes a number of first storing unit, a second storing unit, and a control unit. The first storing units are capable of storing files therein. The second storing unit is capable of storing address information corresponding to the files stored in the first storing units. The control unit is electrically connected to each first storing unit and the second storing unit respectively. The control unit includes a data interface for communicating data with each first storing unit and a power port. The control unit is capable of selectively providing power for the first storing unit. | 2010-05-06 |
| 20100115320 | MOBILE SYSTEM ON CHIP (SoC) AND A MOBILE TERMINAL INCLUDING THE MOBILE SoC - A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled separately from a power mode of the mobile SoC so that the audio out module operates when the mobile SoC is in a power down mode. | 2010-05-06 |
| 20100115321 | Disk Array Control Apparatus and Information Processing Apparatus - According to one embodiment, a disk array control apparatus includes a volatile memory configured to temporarily store data sent or received by a disk array controller, a first power supply generation circuit configured to generate second power to drive the volatile memory from first power, a second power supply generation circuit configured to generate fourth power to drive the volatile memory from power having a higher voltage selected from the first power and third power supplied from a battery, a first switch configured to interpose in a path flowing the second power, a second switch configured to interpose in a path through which flowing the fourth power, and a power supply switching control unit includes a logic circuit which controls on/off switching of the first switch and the second switch based on a state of a initialization signal. | 2010-05-06 |
| 20100115322 | SYNCHRONOUS OPERATION OF A SYSTEM WITH ASYNCHRONOUS CLOCK DOMAINS - A system may be employed for allowing the synchronous operation of an asynchronous system. The system may be a system that may include multiple clusters. The clusters may include asynchronous clock domains and may also receive a global clock signal through a global clock grid that may overlay the system. Furthermore, a method may be employed for synchronizing asynchronous clock domains within a cluster. The method of synchronizing may include providing a global clock that corresponds to a global clock grid to each cluster. Additionally, the method of synchronizing may include accounting for the mismatch between the asynchronous clock domains by employing logic in a block. | 2010-05-06 |
| 20100115323 | DATA STORE SYSTEM, DATA RESTORATION SYSTEM, DATA STORE METHOD, AND DATA RESTORATION METHOD - A data store system and a data restoration system that can decrease power consumed in data store-processing or data restoration are provided. | 2010-05-06 |
| 20100115324 | Memory interface and operating method of memory interface - A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data strobe buffer configured to receive a data strobe signal supplied from the memory; a system clock synchronizing circuit configured to supply a data read from the memory to a logic circuit in synchronization with the system clock signal; and a delay detecting circuit provided at a front stage to the system clock synchronizing circuit and configured to detect a transmission delay from the clock signal supply buffer to the data strobe buffer. The delay detecting circuit generates a phase difference data indicating the transmission delay based on a difference between a phase of the system clock signal and a phase of the data strobe signal outputted from the data strobe buffer, and supplies the phase difference data to the system clock synchronizing circuit. The system clock synchronizing circuit generates a read clock signal by shifting the system clock signal based on the phase difference data, and controls a supply timing at which the data is supplied to the logic circuit, based on the read clock signal. | 2010-05-06 |
| 20100115325 | METHOD FOR ACCESSING A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for accessing a Flash memory including a plurality of blocks includes: selectively programming a page in a first block of the blocks; when a status of the Flash memory is abnormal, determining whether a number of error bits is less than a predetermined value; and when the number of error bits is not less than the predetermined value, moving the first block. An associated memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. In addition, when the number of error bits is not less than the predetermined value, the controller that executes the program code by utilizing the microprocessor moves the first block. | 2010-05-06 |
| 20100115326 | FAULT-TOLERANT SYSTEM FOR DATA TRANSMISSION IN A PASSENGER AIRCRAFT - The invention relates to a transmission system for the transmission of communications data from at least one data source ( | 2010-05-06 |
| 20100115327 | CONGESTION CONTROL METHOD FOR SESSION BASED NETWORK TRAFFIC - A method includes establishing an expected traffic load for a plurality of servers, wherein each server has a respective actual capacity. The method further includes limiting the actual capacity of each server to respective available capacities, wherein a combined available capacity that is based on the available capacities corresponds to the expected traffic load. The method also includes dynamically altering the respective available capacity of the servers based on the failure of at least one server. | 2010-05-06 |
