| 18th week of 2010 patent applcation highlights part 25 |
| Patent application number | Title | Published |
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| 20100109697 | PROBE CARD, NEEDLES OF PROBE CARD, AND METHOD OF MANUFACTURING THE NEEDLES OF PROBE CARD - A probe card for use in the test of the semiconductor devices, a needle of the probe card, and a method of manufacturing the needle are disclosed. This invention is to strengthen the beam portion of the needle, to reduce the contact area between a probing portion and a pad of a wafer die, and to prevent the test apparatus from malfunctioning. The needle of a probe card includes: a probing portion for contacting a pad of a wafer die at a certain pin pressure; a soldered portion soldered to a circuit board of the probe card, for transmitting an electrical signal to the probing portion; and a beam portion integrally connecting the probing portion and the soldered portion and having elasticity to exhibit a certain pin pressure by which the probing portion | 2010-05-06 |
| 20100109698 | PROBE ASSEMBLY ARRANGEMENT - A probe array is assembled on a probe card platform. Each of the probes in the probe array has a probe base that includes a gripping handle. The probe bases have two or more different shapes. The probe bases of different shapes are interleaved such that any two adjacent probes on the platform have probe bases of different shapes. The arrangement of the probes increases effective spacing between the probes to facilitate the maneuvering of a handling tool. | 2010-05-06 |
| 20100109699 | METHODS, APPARATUS AND ARTICLES OF MANUFACTURE FOR TESTING A PLURALITY OF SINGULATED DIE - In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors. | 2010-05-06 |
| 20100109700 | ON-CHIP DETECTION OF POWER SUPPLY VULNERABILITIES - On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies. | 2010-05-06 |
| 20100109701 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode. | 2010-05-06 |
| 20100109702 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 2010-05-06 |
| 20100109703 | OUTPUT CONTROL CIRCUIT - To provide an output control circuit having a small circuit scale that still operates stably at high speed, an output control circuit includes a first inverter and a second inverter, connected in series for outputting signals at an inverted voltage level of an input signal, a first output unit, for which output is controlled based on a voltage level of a signal output by the second inverter, a third inverter, an output of which is connected to an output of the first inverter, for outputting a signal at an inverted voltage level of a signal output by the second inverter, and a second output unit for which output is controlled based on a voltage level of a signal output by the first inverter and a voltage level of a signal output by the third inverter. | 2010-05-06 |
| 20100109704 | DIFFERENTIAL ON-LINE TERMINATION - Memory devices and systems incorporate on-die termination for signal lines. A memory device comprises an integrated circuit die. The integrated circuit die comprises a pair of input signal pins that supply a pair of input signals, and an on-die termination circuit coupled between the pair of input signal pins that differentially terminates the pair of input signals. | 2010-05-06 |
| 20100109705 | LEVEL SHIFTER - A device for shifting voltage levels includes an input stage, an output stage and multiple cascode sets connected between the input stage and the output stage. The input stage includes input transistors connected to a first voltage and an input for receiving an input signal. The output stage includes output transistors connected to a second voltage and an output for outputting an output signal having a voltage level different from a corresponding voltage level of the input signal. Each cascode set includes corresponding cascode transistors gated to a third voltage, which is between the first voltage and the second voltage, preventing excessive voltage across terminals of the input transistors and the output transistors. | 2010-05-06 |
| 20100109706 | USB 2.0 HS Voltage-Mode Transmitter With Tuned Termination Resistance - A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D− signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45Ω±10%) in the USB transceiver. | 2010-05-06 |
| 20100109707 | LOW POWER, SELF-GATED, PULSE TRIGGERED CLOCK GATING CELL - A clock gating cell for gating clock signals includes a latch circuit, a comparison logic circuit, a first logic circuit, and a second logic circuit. An input signal is provided to the latch circuit. An input clock signal is provided to the first logic circuit. The first logic circuit switches the input clock signal based on a comparison signal generated by the comparison logic circuit, thereby generating a latch clock signal. The latch clock signal switches between a first state and a second state only when the input signal switches between the first state and the second state, thereby preventing power loss of the clock gating cell. | 2010-05-06 |
| 20100109708 | LOGIC CIRCUIT - An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor | 2010-05-06 |
| 20100109709 | CIRCUIT ARRANGEMENT FOR IDENTIFYING NETWORK ZERO CROSSINGS - A circuit arrangement for identifying network zero crossings of a network voltage of an alternating current network is provided. A measurement current generated by the network voltage is supplied to a zero crossing detector in order to produce a network zero crossing signal. A current sink is arranged between a live conductor and a neutral conductor of the alternating current network, the current sink allowing the path of a current value of the measurement current generated by the network voltage to be defined. | 2010-05-06 |
| 20100109710 | SAMPLER BLOCKER PROTECTED AGAINST SWITCHING PARASITES - The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase. | 2010-05-06 |
| 20100109711 | LOW NOISE CORRELATED DOUBLE SAMPLING AMPLIFIER FOR 4T TECHNOLOGY - A correlated double sampling circuit and method for providing the same are disclosed. The circuit may include an amplifier, a plurality of capacitors, and a switch matrix. The amplifier provides a reset voltage replica and a signal voltage replica. The switch matrix controls a plurality of switches to perform correlated double sampling over at least three phases. The first phase for sampling the reset voltage replica on a first and second capacitors. The second phase for sampling the reset voltage replica and the kTC noise on a third capacitor. The first phase producing a thermal kTC noise from the first and second capacitors. The third phase for subtracting a charge representing the signal voltage replica, the kTC noise and the reset voltage replica, combined, from the charge sampled in the second phase to provide an output voltage. The method for providing low noise correlated double sampling includes controlling the plurality of switches to provide the at least three phases. | 2010-05-06 |
| 20100109712 | Nanodevices for Spintronics and Methods of Using Same - Graphene magnet multilayers (GMMs) are employed to facilitate development of spintronic devices. The GMMs can include a sheet of monolayer (ML) or few-layer (FL) graphene in contact with a magnetic material, such as a ferromagnetic (FM) or an antiferromagnetic material. Electrode terminals can be disposed on the GMMs to be in electrical contact with the graphene. A magnetic field effect is induced in the graphene sheet based on an exchange magnetic field resulting from a magnetization of the magnetic material which is in contact with graphene. Electrical characteristics of the graphene can be manipulated based on the magnetization of the magnetic material in the GMM. | 2010-05-06 |
| 20100109713 | CURRENT BALANCING CIRCUIT AND METHOD - A multi-phase power converter and a method for balancing a plurality of currents in the multi-phase power converter. The multi-phase power converter that includes a pulse width modulator coupled to an oscillator. A plurality of currents are generated in response to output signals from the pulse width modulator. The levels of the currents are sensed and a sense signal is transmitted to the pulse width modulator. Switching circuitry within the pulse width modulator switches signals from the oscillator in accordance with the current levels, the levels of the signals from the oscillator, and whether at least one of the signals from the oscillator is either rising or falling. | 2010-05-06 |
| 20100109714 | Frequency synthesizer having a plurality of independent output tones - Described is an apparatus that includes a frequency source and a plurality of time domain direct digital synthesizers each having an input connected to an output of the frequency source and an output providing an output frequency signal. A particular time domain direct digital synthesizer includes a sigma-delta modulator that functions as a second order multi-stage noise shaping sigma-delta modulator. In one exemplary embodiment sigma-delta modulator outputs provide a unitary-weighted word used to switch certain unit capacitors that comprise part of a delay modulator to produce a time-varying delay having a time-averaged value that directly corresponds to a binary value appearing on a plurality of phase accumulator outputs. | 2010-05-06 |
| 20100109715 | Method For Use in a Digital Frequency Synthesizer - A method for use in a digital frequency synthesizer, the method comprising phase to amplitude conversion of an output value of a phase accumulator in said synthesizer, said conversion being carried out as an approximation (y) of a phase value (x) which corresponds to said output amplitude value, the method being characterized in that the approximation comprises a combination of a linear interpolation value and a second order sinusoidal value, the second order sinusoidal value being used as an error term to correct for errors in the linear interpolation value. | 2010-05-06 |
| 20100109716 | SEMICONDUCTOR DEVICE - A semiconductor device is provided which has a driving circuit operable to drive a circuit that has a delay, the semiconductor device including: an auxiliary driving circuit operable to accelerate drive of the driving circuit, which receives a drive signal of the driving circuit as an input signal. | 2010-05-06 |
| 20100109717 | Pixel Circuit - A pixel circuit includes an LED having an anode that receives a driving current and a cathode that receives a scan signal, and a driving circuit including: a switch unit operable according to a voltage signal, and adapted for permitting transfer of a data signal when operating in an on state; a capacitor having a first end coupled to the switch unit, and a second end; a first transistor having a first terminal that is coupled to the second end of the capacitor, a second terminal that is coupled to the anode of the LED, and a control terminal that is coupled to the first end of the capacitor; and a second transistor having a first terminal that is adapted for coupling to the voltage source, a second terminal that is coupled to the first terminal of the first transistor, and a control terminal that is adapted for receiving a reference voltage. | 2010-05-06 |
| 20100109718 | Driving Circuit, and a Pixel Circuit Incorporating the Same - A driving circuit includes: a switch unit permitting transfer of a data signal when operating in an on state; a capacitor having a first end coupled to the switch unit, and a second end; a first transistor having a first terminal for coupling to a second voltage source, a second terminal coupled to the second end of the capacitor and to a load, and a control terminal coupled to the first end of the capacitor; and a second transistor having a first terminal coupled to the second end of the capacitor, a second terminal receiving a bias voltage, and a control terminal coupled to the first terminal of the second transistor. | 2010-05-06 |
| 20100109719 | PRESCALING STAGE FOR HIGH FREQUENCY APPLICATIONS - A prescaling stage includes bistable circuit in turn including respective master and slave portions inserted between a first and a second voltage reference and feedback connected to each other. Each portion is provided with at least one differential stage supplied by the first voltage reference and connected, by a transistor stage, to the second voltage reference, as well as a differential pair of cross-coupled transistors, supplied by output terminals of the differential stage and connected, by the transistor stage, to the second voltage reference. Advantageously, each master and slave portion includes a degeneration capacitance inserted in correspondence with respective terminals of the transistors of the differential pair. | 2010-05-06 |
| 20100109720 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD OF THE SAME - A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes a power-on-reset circuit that outputs a reset signal based on a detect signal representing that power is applied to the semiconductor integrated circuit; an initialization object circuit for which an initialization is performed based on the reset signal; and a power-on-reset monitor circuit that generates and outputs a power-on-reset monitor signal representing whether or not the initialization is performed normally, based on the reset signal output from the power-on-reset circuit and an output signal of the initialization object circuit for which the initialization is performed. | 2010-05-06 |
| 20100109721 | SYSTEM FOR DETECTING A RESET CONDITION IN AN ELECTRONIC CIRCUIT - There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted. | 2010-05-06 |
| 20100109722 | INTIALIZATION CIRCUIT FOR DELAY LOCKED LOOP - An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line. | 2010-05-06 |
| 20100109723 | POWER-UP SIGNAL GENERATING CIRCUIT AND INTEGRATED CIRCUIT USING THE SAME - A power-up signal generating circuit includes a detecting unit configured to output a bias signal having a voltage level corresponding to an external power voltage in response to an internal voltage and a deep power down (DPD) signal; and a signal generating unit configured to generate a power-up signal having a logic level corresponding to the voltage level of the external power voltage in response to the DPD signal and the bias signal, wherein the internal voltage increases during an activation time of the power-up signal to reach a predetermined voltage level after a predetermined time, and maintains a ground voltage level during an inactivation period of the power-up signal. | 2010-05-06 |
| 20100109724 | SUBMILLIMETER-WAVE SIGNAL GENERATION BY LINEAR SUPERIMPOSITION OF PHASE-SHIFTED FUNDAMENTAL TONE SIGNALS - Generation of Terahertz range (300 GHz to 3 THz) frequencies is increasingly important for communication, imaging and spectroscopic systems, including concealed object detection. Apparatus and methods describe generating multiple phase signals which are phase-locked at a fundamental frequency, which are then interleaved into an output which is a multiple of the fundamental frequency. By way of example phase generators comprise cross-coupling transistors (e.g., NMOS) and twist coupling transistors (NMOS) for generating a desired number of phase-locked output phases. A rectifying interleaver comprising a transconductance stage and Class B amplifiers provides superimposition of the phases into an output signal. The invention allows frequency output to exceed the maximum frequency of oscillation of a given device technology, such as CMOS in which a 324 GHz VCO in 90 nm digital CMOS with 4 GHz tuning was realized. | 2010-05-06 |
| 20100109725 | DLL CIRCUIT HAVING DUTY CYCLE CORRECTION AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes a duty cycle correcting unit configured to correct a duty cycle of a reference clock signal in response to a duty cycle correction signal and generate a correction clock signal. A feedback loop of the DLL circuit performs a delay lock operation on the correction clock signal and generates an output clock signal. A first duty cycle detecting unit detects a duty cycle of the correction clock signal and generates a first detection signal and a second duty cycle detecting unit detects a duty cycle of the output clock signal and generates a second detection signal. Finally, a duty cycle control unit generates the duty cycle correction signal in response to the first detection signal and the second detection signal to perform the duty cycle correction. | 2010-05-06 |
| 20100109726 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING OUTPUT ENABLE SIGNAL - A semiconductor memory device includes a DLL for detecting a phase difference between an external clock signal and a feedback clock signal to generate a delay control signal corresponding to the phase difference, and delaying the external clock signal by a delay amount corresponding to the delay control signal to generate a DLL clock signal; a clock counter reset signal generator for synchronizing an output enable reset signal with the external clock signal, delaying the synchronized signal by a delay amount corresponding to the delay control signal, and latching the delayed signal in response to the DLL clock signal to output a clock counter reset signal; and an output enable signal generator, reset in response to the clock counter reset signal, for counting the external clock signal and the DLL clock signal to generate an output enable signal corresponding to a read command and a CAS latency. | 2010-05-06 |
| 20100109727 | SEMICONDUCTOR DEVICE - A semiconductor device for providing a reliable data valid window includes a drive control unit configured to output a driving power control signal in response to an internal clock and a command signal; a sub-drive voltage supply unit configured to supply sub-drive voltages; a main drive unit configured to generate a delay-locked loop (DLL) clock by driving the internal clock with a main drive voltage; a sub-drive unit configured to drive the internal clock with the sub-drive voltage in response to the driving power control signal; and a data output driver configured to drive and output a data signal in sync with the DLL clock, wherein the main drive unit and the sub-drive unit share their output terminal. | 2010-05-06 |
| 20100109728 | ELECTRONIC DEVICE AND METHOD OF CORRECTING CLOCK SIGNAL DEVIATIONS IN AN ELECTRONIC DEVICE - A digital electronic device is provided which comprises a digital clock deviation detecting means and a digital clock correcting means. The clock deviation detecting means is used to detect a deviation of a first clock signal of the electronic device and/or the duty cycle of the first clock signal. The clock correcting means is used to correct the first clock signal and/or the duty cycle of the first clock signal if the clock deviation detecting means has detected a deviation of the first clock signal and/or the duty cycle of the first clock signal. The clock correcting means comprises at least a first and second compensation path (P | 2010-05-06 |
| 20100109729 | DUTY DETECTING CIRCUIT AND DUTY CYCLE CORRECTOR INCLUDING THE SAME - A duty cycle corrector includes a duty adjusting unit configured to adjust a duty cycle of an input clock in response to a duty correction code and generate an output clock, a duty detecting unit configured to measure a difference between a high pulse width and a low pulse width of the output clock and output a difference value, and an accumulating unit configured to accumulate the difference value to generate the duty correction code. | 2010-05-06 |
| 20100109730 | PWM CONTROL CIRCUIT HAVING ADJUSTABLE MINIMUM DUTY CYCLE - A pulse width modulated (PWM) controller includes a triangle wave generation circuit generating a triangle wave signal to oscillate between an upper limit voltage and a lower limit voltage. The upper limit voltage and the lower limit voltage are adjustable in response to changes in the power supply voltage. A pulse generation circuit is coupled to the triangle wave generation circuit and a minimum duty cycle setting voltage, and is configured to generate a PWM pulse signal with a minimum duty cycle determined by the relative magnitude of the triangle wave signal and the minimum duty cycle reference voltage. In an embodiment, the minimum duty cycle is increased when the power supply voltage is lower than a predetermined reference voltage. | 2010-05-06 |
| 20100109731 | APPARATUS AND METHOD FOR DUTY CYCLE CORRECTION - There is provided an apparatus for duty cycle correction. The apparatus for duty cycle correction comprises a moving sum unit performing a moving sum calculation with respect to the square-wave signal and outputting the moving sum signal subjected to moving sum calculation, a comparison unit comparing the moving sum signal with a predetermined threshold voltage, outputting a high signal or low signal, a mean value calculation unit calculating the mean value of an output signal outputted from the comparison unit, the output signal being included in a section having a period integer times greater than that of the square-wave signal, and a threshold voltage control unit comparing the mean value with a middle value, increasing the threshold voltage when the mean value is greater than the middle value, and decreasing the threshold voltage when the mean value is less than the middle value. | 2010-05-06 |
| 20100109732 | INTEGRATED CIRCUIT, CONTROL METHOD, AND USE OF A CIRCUIT FOR A SLEEP MODE AND AN OPERATING MODE - A circuit, control method, and use of a circuit for a sleep mode and an operating mode with a digital CMOS circuit with NMOS field-effect transistors and with PMOS field-effect transistors, with a first load device, whereby source terminals of the NMOS field-effect transistors of the digital CMOS circuit are connected via the first load device to a first supply voltage, and with a second load device, whereby source terminals of the PMOS field-effect transistors of the digital CMOS circuit are connected via the second load device to a second supply voltage, wherein the body terminals of the NMOS field-effect transistors of the digital CMOS circuit are connected directly to the first supply voltage, and the body terminals of the PMOS field-effect transistors of the digital CMOS circuit are connected directly to the second supply voltage. | 2010-05-06 |
| 20100109733 | Analog Comparators in a Control System - An apparatus is disclosed that includes first and second circuits coupled together via a bus, an input pin configured to receive an analog input signal, a digital-to-analog (DAC) convertor configured to convert a multibit reference signal into an analog reference signal, a comparator circuit coupled to the bus, an output of the DAC and to the input pin. The comparator circuit is configured to receive the analog reference signal from the DAC and the analog input signal, and configured to generate a first digital signal set to a first state if the analog reference signal is greater in magnitude than the analog input signal, or set to a second state if analog reference signal is lower in magnitude than the analog input signal. The comparator circuit is also configured to transmit the first digital signal to the first circuit via the bus. The first circuit in turn is configured to receive the first digital signal. In response to receiving the first digital signal, the first circuit is configured to generate a second digital signal set to the first or second state depending on whether the received first digital signal is set to the first or second state. The second circuit is configured to receive the second digital signal from the first circuit via the bus. | 2010-05-06 |
| 20100109734 | CURRENT-MODE PHASE ROTATOR WITH PARTIAL PHASE SWITCHING - In one illustrative embodiment, an apparatus for a current-mode phase rotator with partial input phase switching comprises a mixer, wherein the mixer is a four quadrant current-mode mixer comprised of four interpolation buffers, wherein each interpolation buffer receives as input a clock phase from a set of four equidistant clock phases, and a set of two-output current-steering digital to analog converters that supply tail currents to the mixer wherein a first digital to analog converter has additional switches to connect each of two outputs to one of two polarities of a given clock while each remaining digital to analog converter has no additional switches and has two outputs supplying current only to two different polarities of a same clock phase wherein steering the current during incremental rotation about a phase circle defines an octagonal shaped phase envelope. | 2010-05-06 |
| 20100109735 | Control signal generation circuit and sense amplifier circuit using the same - A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals. | 2010-05-06 |
| 20100109736 | ELECTRONIC DEVICE AND SQUARE WAVE GENERATOR THEREOF - A square wave generator includes a sawtooth wave generator and a convertor. The sawtooth wave generator generates a sawtooth wave. The convertor generates a square wave based on the sawtooth wave. The sawtooth wave generator includes a capacitor and a switching unit connected parallel to each other. A first terminal of the capacitor is electrically coupled to a power source and the convertor, and a second terminal of the capacitor is grounded. When a voltage drop on the capacitor equals to or is greater than a first threshold voltage, the switching unit closes and grounds the first terminal of the capacitor, so that the capacitor discharges rapidly. | 2010-05-06 |
| 20100109737 | Clock pulse generating circuit - A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator. | 2010-05-06 |
| 20100109738 | Gate driver and method for making same - A gate driver for use in a liquid crystal display has a plurality of shift registers connected in series. Each of the shift registers is used to provide a gate-line pulse to a row of pixels in the liquid crystal display. The gate-line pulse has a front pulse and a rear pulse and the shift register has a front-pulse generating part and a rear-pulse generating part for generating to corresponding pulse. Each of the pulse generating parts has a first pull-up circuit to generate a voltage level to keep a switching element in a second pull-up circuit conducting so as to generate a front or rear pulse, in response to a corresponding clock signal, and two pull-down circuits, in response to the voltage level, to allow the front or rear pulse to be generated only at a pull-down period. | 2010-05-06 |
| 20100109739 | ACTIVE GUARDING FOR REDUCTION OF RESISTIVE AND CAPACITIVE SIGNAL LOADING WITH ADJUSTABLE CONTROL OF COMPENSATION LEVEL - In various embodiments, applicants' teachings are related to an active guarding circuit and method for reducing parasitic impedance signal loading on a signal-transmission channel that is shunted by a parasitic impedance. The presence of an electrical signal on the signal-transmission channel causes a leakage current to flow through the parasitic impedance. In various embodiments, the circuit comprises an amplifier and an impedance, one terminal of the impedance is coupled to the signal-transmission channel. The input of the amplifier is coupled to the signal-transmission channel and the output is coupled to the other terminal of the impedance so as to cause a compensation current to flow through the impedance. The gain of the amplifier and the value of the impedance are selected so that the compensation current has a magnitude substantially equal to the leakage current magnitude. | 2010-05-06 |
| 20100109740 | Clamp networks to insure operation of integrated circuit chips - Clamp networks are provided to insure successful operation of a variety of electronic circuits that are realized in the form of integrated circuit chips. These networks are especially suited for use in chips in which on-chip circuits generate a voltage to bias the chip substrate relative to the chip ground. The clamp networks are configured to drive a current between the chip ground and the chip substrate whenever the chip substrate begins to rise above the chip ground during turn on of the chip input voltage. The clamp networks thus insure that the chip substrate is properly biased when the input voltage has been established and that the chip, therefore, functions as intended. | 2010-05-06 |
| 20100109741 | METHOD AND APPARATUS FOR ROBUST MODE SELECTION WITH LOW POWER CONSUMPTION - A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary a current limit out of the selector terminal in response to a voltage on the selector terminal. The circuit also includes a second current limiting circuit coupled between the selector terminal and a second voltage bus. The second current limiting circuit adapted to vary a current limit into the selector terminal in response to the voltage on the selector terminal. | 2010-05-06 |
| 20100109742 | Level shift circuit - A level shift circuit includes a first resistor with one end connected to GND, a first transistor with a drain and a gate connected to the other end of the first resistor, and a source connected to a first power supply, a second transistor with a source connected to the first power supply, and a gate connected to the drain and the gate of the first transistor, a second resistor with one end connected to a drain of the second transistor, a third transistor with a source connected to the other end of the second resistor, and a gate connected to an input terminal, a first current source connected between a second power supply and a drain of the third transistor; and a fourth transistor connected between an output terminal and the first power supply with a gate connected to the drain of the second transistor. | 2010-05-06 |
| 20100109743 | LEVEL SHIFTER HAVING NATIVE TRANSISTORS - A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS | 2010-05-06 |
| 20100109744 | LEVEL SHIFTER HAVING A CASCODE CIRCUIT AND DYNAMIC GATE CONTROL - A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS | 2010-05-06 |
| 20100109745 | LEVEL CONVERSION CIRCUIT FOR CONVERTING VOLTAGE AMPLITUDE OF SIGNAL - In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable. | 2010-05-06 |
| 20100109746 | SAMPLING MIXER, FILTER DEVICE, AND RADIO DEVICE - A sampling mixer includes TAs (transconductance amplifiers), an in-phase mixer section connected to the TA and the TA, an opposite-phase mixer section connected in parallel with the in-phase mixer section, and a signal generator for generating a control signal for the in-phase mixer section and the opposite-phase mixer section respectively. The IIR filter using signals that underwent a current conversion by using the different transconductances is constructed, so that the filter characteristic can be designed by a weighting of the transconductance in addition to a capacitance ratio. As a result, the wide-band filter characteristic and the band-pass filter characteristic can be obtained, and deterioration of the receiving sensitivity can be suppressed by designing the filter characteristic suitable for the radio communication system. | 2010-05-06 |
| 20100109747 | Systems and Methods Using Improved Clock Gating Cells - A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge or discharge of the output logic circuit input node by the pull-up and/or the pull-down circuit when the clock gating cell is enabled. | 2010-05-06 |
| 20100109748 | APPLIANCE CONTROL SYSTEM WITH A ZERO CROSSING DETECTING CIRCUIT - A control system includes a zero crossing detecting circuit for detecting a zero crossing of an AC signal. The circuit includes a transformer having a primary portion and a secondary portion. The primary portion receives the AC signal. The secondary portion comprises first and second terminals. The first terminal is biased at a first DC voltage level. An output switch is operatively connected to the second terminal and has an on state and an off state. The output switch selectively activates an output signal of the zero crossing detecting circuit according to an activation voltage level sensed by the output switch and corresponding to the zero crossing. While in the off state, the output switch is biased at a second DC voltage level. A voltage difference between the first and second DC voltage levels substantially equals the activation voltage level. A controller monitors the output signal and controls an operation based on the output signal. | 2010-05-06 |
| 20100109749 | SIGNAL TRANSMISSION PATH SELECTION CIRCUIT AND METHOD, AND ELECTRONIC DEVICE EMPLOYING THE CIRCUIT - An electronic device includes a central processing unit, a USB connector, a USB switch, and an audio path selector. The USB switch has a data transmission path and an audio signal transmission path for signal transmission between the central processing unit and the USB connector. The USB switch selects the data transmission path for data transmission according to a first selection signal from the central processing unit, and selects the audio signal transmission path for audio signal transmission according to a second selection signal from the central processing unit. The audio path selector interconnects the central processing unit and the USB switch, and has a first audio path for output of audio signals from the central processing unit to the audio signal transmission path, and a second audio path for output of audio signals from the audio signal transmission path to the central processing unit. | 2010-05-06 |
| 20100109750 | Boost Mechanism Using Driver Current Adjustment for Switching Phase Improvement - System and method for providing a boost current to a switching transistor gate is disclosed. A boost capacitor precharged to a voltage level above a gate-source voltage is coupled to a switching transistor gate at the beginning of a switch-on phase. The boost capacitor is decoupled from the switching transistor gate when a boost capacitor voltage falls below the gate-source voltage and is again precharged to the voltage level above the gate-source voltage. A second-phase resistance is coupled between a supply voltage and the switching transistor gate. The second-phase resistance value is selected based upon a current peak detected in the switching transistor. A switch-off capacitor precharged to a voltage level below the gate-source voltage may be coupled to the switching transistor gate at the beginning of a switch-of phase. | 2010-05-06 |
| 20100109751 | HIGH-PERFORMANCE ANALOG SWITCH - Techniques for designing a high performance analog switch for use in electronic circuit applications. In one aspect, a variable bulk voltage generation module is provided to vary the bulk voltage of a transistor in the switch, such that the threshold voltage of the transistor is reduced during the on state. In another aspect, a pulling transistor is provided to pull a middle node of the switch to a DC voltage during the off state to further increase the isolation provided by the switch. | 2010-05-06 |
| 20100109752 | Semiconductor Device, and Power Source and Processor Provided with the Same - A semiconductor device includes: a transistor having a first electrode coupled to a first power source node to which a first power source voltage is supplied, and a second electrode, and supplying a reference current to a temperature detection element; a diffused resistor including a first semiconductor region having a potential-fixing node coupled to the first power source node, and a second semiconductor region having a first resistor node coupled to the second electrode of the transistor and a second resistor node coupled to a second power source node to which a second power source voltage is supplied, and formed at a surface of the first semiconductor region; and a leakage current correction circuit for allowing a current having approximately the same magnitude and the same direction as a magnitude and a direction of a current flowing via the potential-fixing node and the second resistor node, to flow not via the diffused resistor but via the transistor. | 2010-05-06 |
| 20100109753 | METHOD OF OUTPUTTING TEMPERATURE DATA IN SEMICONDUCTOR DEVICE AND TEMPERATURE DATA OUTPUT CIRCUIT THEREFOR - A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation. | 2010-05-06 |
| 20100109754 | Bias circuit for a switching power supply - A bias circuit for a switching power supply includes a rectifier that is connected to an AC power source and outputs a full wave rectified voltage Vs; a voltage divider, a diode, a first transistor, and a second transistor connected in parallel between Vs and ground; a capacitor connected between a first terminal of the second transistor and ground; and a node between the capacitor and the first terminal of the second transistor providing an output bias voltage Vcc from the bias circuit. A voltage from the voltage divider is provided to a gate of the first transistor, and the diode and a first terminal of the first transistor are connected to a gate of the second transistor. | 2010-05-06 |
| 20100109755 | SEMICONDUCTOR DEVICE - A semiconductor device capable of improving the breakdown voltage in the overall device is provided. The semiconductor device includes: a semiconductor substrate; a p-MOS formed on a surface layer portion of the semiconductor substrate; an n-MOS formed on the surface layer portion of the semiconductor substrate and serially connected with the p-MOS between a power source and a ground; and a substrate potential control circuit for controlling the potential of the back surface of the semiconductor substrate to an intermediate potential higher than the ground potential and lower than the potential of the power source. | 2010-05-06 |
| 20100109756 | SEMICONDUCTOR DEVICE - A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip. | 2010-05-06 |
| 20100109757 | COMPENSATION OF OPERATING TIME-RELATED DEGRADATION OF OPERATING SPEED BY A CONSTANT TOTAL DIE POWER MODE - By maintaining a substantially constant total die power during the entire lifetime of sophisticated integrated circuits, the performance degradation may be reduced. Consequently, greatly reduced guard bands for parts classification may be used compared to conventional strategies in which significant performance degradation may occur when the integrated circuits are operated on the basis of a constant supply voltage. | 2010-05-06 |
| 20100109758 | FEEDBACK-CONTROLLED BODY-BIAS VOLTAGE SOURCE - A body-bias voltage source having an output monitor, charge pump, and shunt. a shunt circuit having on/off control is coupled to the output monitor and to the output of the charge pump. Upon sensing that the output voltage of the charge pump is above a desired value, the output monitor may disable the charge pump circuit and may enable the shunt circuit to reduce the voltage at the output of the charge pump. When the voltage output of the charge pump is below the desired value, the output monitor may disable the shunt circuit and may enable the charge pump circuit. A shunt circuit having proportional control may be substituted for the shunt circuit with on/off control. | 2010-05-06 |
| 20100109759 | SOLAR CELL DEVICE HAVING A CHARGE PUMP - A solar cell device includes a solar cell section configured to output a first voltage upon receiving light. A charge pump circuit includes a first charge pump. The first charge pump includes a first terminal and a second terminal. The first terminal is configured to receive the first voltage from the solar cell section, and the second terminal is configured to output a second voltage that is higher than the first voltage. An output section is configured to receive an output voltage output by the charge pump circuit. The charge pump circuit is formed on a single semiconductor substrate. | 2010-05-06 |
| 20100109760 | VOLTAGE BOOSTING CIRCUIT AND SEMICONDUCTOR DEVICE - A voltage boosting circuit includes a first voltage boosting circuit configured to receive an external power supply voltage, and pump the external power supply voltage to a second boosting voltage higher than the external supply voltage in a single pumping stage, and a second voltage boosting circuit configured to receive the second boosting voltage and pump the second boosting voltage to a first boosting voltage higher than the second boosting voltage in two pumping stages. | 2010-05-06 |
| 20100109761 | SEMICONDUCTOR DEVICE INCLUDING INTERNAL VOLTAGE GENERATION CIRCUIT - A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented. | 2010-05-06 |
| 20100109762 | INTERNAL VOLTAGE GENERATOR - An internal voltage generating circuit includes an internal voltage generating unit configured to generate an internal voltage that corresponds to a target voltage level by driving an internal voltage terminal with an external power supply voltage, and current sinking unit configured to adjust leakage current introduced to the internal voltage terminal in response to the external power supply voltage. | 2010-05-06 |
| 20100109763 | STANDARD VOLTAGE GENERATION CIRCUIT - A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state. | 2010-05-06 |
| 20100109764 | CIRCUIT, AN ADJUSTING METHOD, AND USE OF A CONTROL LOOP - A circuit, an adjusting method, and use of a control loop for adjusting a data retention voltage and/or a leakage current of a CMOS circuit for a sleep mode, wherein the CMOS circuit is operated to control in a measuring mode, whereby in the measuring mode a leakage current exclusively flows through the CMOS circuit, the control loop in the measuring mode adjusts the data retention voltage and/or the leakage current, and the adjustments of the control loop for the sleep mode are stored. | 2010-05-06 |
| 20100109765 | REDUCING CURRENT LEAKAGE AND IMPROVING SHELF LIFE TIME OF BATTERY-BASED-DEVICES - An electronic device includes a rechargeable battery, an electrical circuit, a battery safety circuit, and a power down mode circuit. The electrical circuit is configured to generate a power mode control signal. The power down mode circuit receives the power mode control signal. If the power mode control signal has a first value, the power down mode circuit is configured to force a voltage at a first port of the battery safety circuit to a voltage value that is less than an under voltage lock out (UVLO) threshold value of the battery safety circuit to transition the electronic device from a normal operating mode to a low current power down mode. The electronic device may further include a wake up mode circuit. | 2010-05-06 |
| 20100109766 | Method and Device for Demodulation of Signals - A method and device are provided for demodulation of an output signal from a transducer ( | 2010-05-06 |
| 20100109767 | DIGITAL PULSE WIDTH MODULATION FOR HALF BRIDGE AMPLIFIERS - A switching amplifier drives a load or audio transducer. A digital integral noise shaping circuit converts a digital input such as audio content to an output digital pulse width modulated signal using an integrator. The integrator integrates the digital input, a variable frequency reference pulse width modulated signal and an inverse of the output digital pulse width modulated signal. A half bridge amplifier receives the output digital pulse width modulated signal and drives the load or audio transducer. A variable frequency generator generates the variable frequency reference pulse width modulated signal with an approximately equal duty ratio or alternatively varies the variable frequency pulse width modulated signal above and below about a fifty percent duty ratio. | 2010-05-06 |
| 20100109768 | METHOD AND APPARATUS FOR HIGH PERFORMANCE CLASS D AUDIO AMPLIFIERS - The present disclosure provides a method and apparatus for high performance class D audio amplifier circuit that includes: a modulator circuit for receiving a PWM input signal and generating a control signal, a driver control circuit, a switching circuit, and a feedback circuit. The driver control circuit is adapted to generate a drive signal for the switching circuit. The driving signal provides compensation for noise and distortions in a PWM output signal at each cycle by selecting either a first pulse signal or a second pulse signal based on the information of the control signal. | 2010-05-06 |
| 20100109769 | POWER AMPLIFIER - A power amplifier is provided with a signal generating circuit, a plurality of control signal amplifiers and an RF amplifier. The signal generating circuit outputs the amplitude modulation components of an input signal by dividing the components into a plurality of control signals, and outputs a modulation wave signal or the phase modulation components of the modulation wave signal. The control signal amplifier is provided with a pulse modulator, which performs pulse modulation of a control signal; a switching amplifier, which performs current amplification of a rectangular wave signal outputted from the pulse modulator; and a low-pass filter, which removes spurious components from the signal outputted from the switching amplifier. The RF amplifier amplifies the inputted signal, performs amplitude modulation with the signal outputted from the low-pass filter and outputs the amplitude-modulated signal. | 2010-05-06 |
| 20100109770 | RECONFIGURABLE POWER AMPLIFIER AND USE OF SUCH AMPLIFIER FOR MAKING A MULTI-STANDARD AMPLIFICATION STAGE FOR MOBILE PHONE COMMUNICATIONS - A reconfigurable power amplifier includes at least one amplification circuit (E | 2010-05-06 |
| 20100109771 | REPEATING SYSTEM AND METHOD FOR CANCELLATION OF FEEDBACK INTERFERENCE SIGNAL WITH PRE-DISTORTION FUNCTION - There is provided a repeating system for cancellation of a feedback interference signal, including: a PA (Power Amplifier) for power-amplifying an output signal; a feedback ICS (Interference Cancellation System) for canceling a feedback interference signal and detecting a residual error; a pre-distorter for compensating for an error of the PA by applying pre-distortion and compensating for the residual error by using information on the residual error detected by the feedback ICS to linearize the characteristic of the PA; and a control unit for controlling the feedback ICS and the pre-distorter. | 2010-05-06 |
| 20100109772 | SIGMA DELTA CLASS D POWER AMPLIFIER AND METHOD THEREOF - A sigma delta class D power amplifier includes a loop filter, a quantizer, and an output stage. The quantizer is coupled to the loop filter and quantifies an error signal according to levels of two reference signals to output a pair of mean signals, wherein different logic combinations of the mean signals belong to one of three quantum states. The output stage is coupled to the quantizer and outputs a corresponding output signal according to the different quantum states to drive a load, wherein a driving current of the output signal belongs to one of the three driving states which include at least a steady state with no current of a power amplifier. | 2010-05-06 |
| 20100109773 | Class-D Amplifier - A class-D power amplifier according to the present invention includes: a pulse width modulation circuit which modulates an analog signal into low-level and high-level binary signals; and a detection circuit which turns off operation of a circuit connected with a back stage of the pulse modulation circuit if the high level or the low level of the binary signal output from the pulse width modulation circuit is maintained for a predetermined time. | 2010-05-06 |
| 20100109774 | Operational amplifier - An operational amplifier includes an input stage amplifier that receives an input signal, an output stage amplifier that amplifies a signal output from the input stage amplifier and outputs the signal, a capacitor that is connected between an input node and an output node of the output stage amplifier, and a charge and discharge control circuit that controls a charge and discharge current of the capacitor. | 2010-05-06 |
| 20100109775 | SEMICONDUCTOR DEVICE HAVING RESISTORS WITH A BIASED SUBSTRATE VOLTAGE - To eliminate the substrate voltage dependences of the respective resistance values of resistor elements, in the resistor elements coupled in series to each other over respective substrate regions, the ends of the resistor elements are coupled to the corresponding substrate regions by respective bias wires such that respective average potentials between the substrate regions of the resistor elements and the corresponding resistor elements have opposite polarities, and equal magnitudes. | 2010-05-06 |
| 20100109776 | Millimeter Wave Monolithic Integrated Circuits - A millimeter wave amplifier constructed on a substrate and configured for use at a frequency of 75 GHz or higher, may include four amplifier stages. A first inter-stage filter, resonant at an operating frequency of the amplifier, may couple the output of the first stage to the input of the second stage. A second inter-stage filter, resonant at the operating frequency, may couple the output of the second stage to the input of the third stage. A third inter-stage filter, resonant at the operating frequency, may couple the output of the third stage to the input of the fourth stage. A plurality of bias supply leads that couple a gate bias voltage and a drain bias voltage to each of the amplifier stages. A plurality of bias line filters, resonant at the operating frequency, may be connected from at least some of the bias supply leads to a ground plane. | 2010-05-06 |
| 20100109777 | Amplifying Circuit - An amplifying circuit includes amplifying unit comprising a first transistor unit having a gate width that is controllable and is controlled based on a first control signal. | 2010-05-06 |
| 20100109778 | BROADBAND RF LINEAR AMPLIFIER - A broad-band linear amplifier circuit includes a driver amplifier to produce a first amplified radio frequency (RF) signal in a first single RF band in response to a first input RF signal and to produce a second amplified RF signal in a second single RF band in response to a second input RF signal. The first single RF band and the second single RF band reside in a broad band that has a bandwidth more than two times a bandwidth of the first single RF band or the second single RF band. A sensing circuit can sense a power, a gain, or a phase of the first output RF signal and the second output RF signal, and to produce a sensing signal. A gain control circuit controls gain variation of the driver amplifier in response to the sensing signal. | 2010-05-06 |
| 20100109779 | HYBRID CLASS AB SUPER FOLLOWER - Various embodiments of a hybrid class AB super follower circuit are provided. One embodiment is a follower circuit comprising: an input node for receiving an input voltage signal; an output node for driving a capacitive load based on the input voltage signal; a transistor M | 2010-05-06 |
| 20100109780 | Flexible Dynamic Range Amplifier - An amplifying device ( | 2010-05-06 |
| 20100109781 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: an amplifier circuit which respectively has one or more input terminals and one or more output terminals; a replica circuit which has the same DC characteristics as those of the amplifier circuit; a reference voltage generation circuit which is connected to a bias terminal of the replica circuit, and which generates a predetermined reference voltage at the bias terminal; and a feedback circuit which takes a difference between the reference voltage generated at the bias terminal of the replica circuit and the voltage generated at a bias terminal of the amplifier circuit, and which performs feedback control by providing negative feedback of the difference to the bias terminal of the amplifier circuit so that the voltage generated at the bias terminal of the amplifier circuit is made equal to the reference voltage generated at the bias terminal of the replica circuit. | 2010-05-06 |
| 20100109782 | FET BIAS CIRCUIT - A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class. | 2010-05-06 |
| 20100109783 | Reconfigurable Amplifier and Filter Using Time-Varying Circuits - A reconfigurable system is used for amplifying, filtering, and sampling analog signals. Unlike conventional analog filters and amplifiers based on linear time-invariant systems and classical filter responses such as Butterworth or Chebyshev filters, the system described here uses parallel branches comprising time-varying circuits. An input voltage or current is communicated to a number of parallel branches and each branch processes a segment of the input signal using time-varying circuits such as analog multipliers and/or super-regenerative amplifiers. The time-window of the input signal processed by each branch is equal in length, but offset in time from all other branches. The output of each branch is a series of filtered and amplified samples of the input signal. The output samples of all branches are then time-interleaved in the analog domain, or digitized using separate analog-to-digital converters and then time-interleaved digitally. By using time-varying circuits, sharper filters and greater amplification is achieved while consuming less integrated-circuit area and power. The time-varying circuits in each branch are controlled by synthesized signals that determine the filter response and gain of the overall system. As a result, better flexibility and reconfigurability are achieved compared with classical filters and amplifiers. | 2010-05-06 |
| 20100109784 | MILLIMETER WAVE MONOLITHIC INTEGRATED CIRCUITS AND METHODS OF FORMING SUCH INTEGRATED CIRCUITS - A description is provided of a high-frequency, multi-stage, millimeter wave amplifier integrated circuit, and of a method for designing and constructing the circuit. The methods and structures have been created to enable the construction of an amplifier offering substantial gain at a relatively high power and high frequency, but occupying minimal area of an integrated circuit die. Various structures and methodologies are described which each contribute to the practical feasibility of constructing an amplifier with such performance in a relatively compact space. | 2010-05-06 |
| 20100109785 | AMPLIFIER CIRCUIT - An amplifier circuit includes a first amplifying section for amplifying a signal, and a second amplifying section for amplifying the signal amplified by the first amplifying section. A capacitive element connects the output of the first amplifying section to the input of the second amplifying section. When power is applied to the amplifier circuit, a bypass circuit causes the electric current flowing from a first power supply toward the input of the second amplifying section through the first amplifying section and the capacitive element to be bypassed to a second power supply. | 2010-05-06 |
| 20100109786 | POWER SUPPLY VOLTAGE OUTPUT CIRCUIT - a power supply voltage output circuit includes: a power supply voltage generation unit generating a power supply voltage to be supplied into a ring oscillator; a reference clock oscillator oscillating a reference clock with respect to a clock oscillated by the ring oscillator; a phase difference detection unit detecting a phase difference between the clock from the ring oscillator and the reference clock from the reference clock oscillator; a filter unit smoothing an output of the phase difference detection unit; and a PWM signal generation unit generating a PWM signal based on an output of the filter unit such that the phase difference approaches zero. | 2010-05-06 |
| 20100109787 | METHOD AND APPARATUS FOR OSCILLATOR STABILITY VERIFICATION - A technique for oscillator stability and accuracy verification involves analysis of parameters from a plurality of phase locked loops (PLLs). During testing, each PLL receives a stable reference clock to identify variations in its clock oscillator. Mathematical calculations on the data extracted from each PLL permit identification of clock oscillators having undesirable timing characteristics. Remedial measures may then be implemented to correct problems with any faulty oscillators. | 2010-05-06 |
| 20100109788 | Driver circuit - In a driver circuit | 2010-05-06 |
| 20100109789 | Radio frequency amplifier with digital amplitude modulation and method for controlling the delivering of power - A digital amplitude modulator is configured to modulate the amplitude of an input carrier signal based on input digital data and generate a corresponding output signal. The digital amplitude modulator includes a first variable gain amplifier for receiving the input carrier signal and generating a corresponding first amplified carrier signal, a second variable gain amplifier for receiving the input digital data and generating corresponding digital amplitude control data and a plurality of selectively activatable amplifier stages. Each amplifier stage receives a replica of the first amplified carrier signal and generates a corresponding second amplified carrier signal when activated. The output signal corresponds to a combination of the second amplified carrier signals generated by the activated amplifier stages. The digital amplitude modulator further includes a driving circuit configured to receive the digital amplitude control data and activate a corresponding set of selected amplifier stages based on the digital amplitude control data, and a power controller unit configured to adjust the power delivered by the digital amplitude modulator by setting a first amplifying gain of the first variable gain amplifier and a second amplifying gain of the second variable gain amplifier. | 2010-05-06 |
| 20100109790 | Multilayer Complementary-conducting-strip Transmission Line Structure - A multilayer complementary-conducting-strip transmission line (CCS TL) structure is disclosed herein. The multilayer CCS TL structure includes a substrate, and n signal transmission lines being parallel and interlacing with n-1 mesh ground plane(s), therein a plurality of inter-media-dielectric (IMD) layers are correspondingly stacked with among the n signal transmission lines and the n-1 mesh ground plane(s) to form a stack structure on the substrate, therein n≧2 and n is a natural number. Whereby, a multilayer CCS TL with independent of each layer and complete effect on signal shield is formed to provide more flexible for circuit design, reduce the circuit area and also diminish the transmission loss. | 2010-05-06 |
| 20100109791 | CIRCULATOR/ISOLATOR WITH AN ASYMMETRIC RESONATOR - The present invention is directed to a circulator device that includes a housing defining an interior three-dimensional volume. The housing includes a plurality of port openings disposed therein. A gyromagnetic resonator stack is disposed in the housing. The gyromagnetic resonator stack includes a circuit disposed between a first ferrite disk and a second ferrite disk. The first ferrite disk and the second ferrite disks form a pair of ferrite disks having a ferrite disk centroid and a ferrite disk perimeter. The circuit including an asymmetric center resonator having a eccentric region characterized by a predetermined resonator geometry. The circuit further including an impedance matching transmission line structure coupled to an edge of the eccentric region proximate the ferrite disk perimeter and at least one 50 Ohm transmission line structure coupled to a non-eccentric portion of the asymmetric center resonator. Each of the impedance matching transmission line structure and the at least one 50 Ohm transmission line structure extending through corresponding port openings of the plurality of port openings. The impedance matching transmission line structure is characterized by a section geometry and a predetermined matching impedance. The predetermined matching impedance is a function of the section geometry and at least one performance parameter of the device is a function of the predetermined resonator geometry. | 2010-05-06 |
| 20100109792 | Thin film balun - The present invention provides a thin film balun includes: an unbalanced transmission line | 2010-05-06 |
| 20100109793 | Thin film balun - To provide a thin film balun that can improve balance characteristics while maintaining miniaturization. In a thin film balun to which an embodiment relates, an auxiliary coil portion is disposed at a predetermined position so as to face any one of an unbalanced transmission line and a balanced transmission line. | 2010-05-06 |
| 20100109794 | Circuit and method for driving at least one differential line - In the case of a circuit arrangement which can be supplied by way of at least one voltage source, in particular a driver output stage, for driving at least one differential line which can be connected to at least one first output connection as well as to at least one second output connection for the purpose of, in particular digital, data transmission, wherein the circuit arrangement has at least two paths which are arranged in a mirror-image fashion relative to one another and which connect the voltage source to at least one reference potential, in particular earth potential or ground potential or zero potential, as well as in the case of a method for driving at least one differential line using at least one such circuit arrangement, an increased output impedance is avoided during the switching phase, and this ensures high signal quality. | 2010-05-06 |
| 20100109795 | TRANSMISSION OF ALTERNATIVE CONTENT OVER STANDARD DEVICE CONNECTORS - Transmission of alternative content over standard device connectors. An embodiment of a method includes connecting a first device to a second device utilizing a standard connector, the connector including multiple pins, and detecting whether the second device is operating in a standard mode or an alternative mode. If the second device is operating in the alternative mode, then switching one or more pins of the standard connector for the alternative mode and transmitting or receiving signals for the alternative mode via the plurality of pins of the standard connector. | 2010-05-06 |
| 20100109796 | Multi-Band Transmit-Receive Switch for Wireless Transceiver - A transmit-receive switch has a transmit port, an antenna port, and a receive port. A first switch couples the transmit port to the antenna port when a signal TxON is asserted. A LOW_BAND signal indicates the selection of a lower band of frequencies. A tuning structure is formed by a second and third switch in series which couple the antenna port to ground through a first capacitor when TxON and LOW_BAND are both asserted, and LOW_BAND may be provided to one or more such tuning structures for multi-band frequency operation. A second capacitor couples the antenna port to ground when a fourth switch is enabled. An inductor couples the antenna port to the receive port. A third capacitor is placed across the receive port and ground. A fifth switch is closed when TxON is asserted. The first through fifth switches can be a CMOS FET with an isolated substrate coupled to ground through an associated resistor. | 2010-05-06 |
