| 18th week of 2010 patent applcation highlights part 19 |
| Patent application number | Title | Published |
|---|
| 20100109097 | INTEGRATED CIRCUIT SYSTEM EMPLOYING AN ELEVATED DRAIN - A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region. | 2010-05-06 |
| 20100109098 | GATE STRUCTURE INCLUDING MODIFIED HIGH-K GATE DIELECTRIC AND METAL GATE INTERFACE - A method of fabricating a gate of a semiconductor device is provided. In an embodiment, the method includes forming a gate dielectric layer on a semiconductor substrate. An interface layer is formed on the gate dielectric layer. In an embodiment, the gate dielectric layer includes HfO | 2010-05-06 |
| 20100109099 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×10 | 2010-05-06 |
| 20100109100 | MICRO-FLUIDIC STRUCTURE - A microfabricated structure that includes a first layer of material on a substrate, and a second layer of material over the first layer that forms an encapsulated cavity, and a structural support layer added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout. | 2010-05-06 |
| 20100109101 | Method of Positioning Catalyst Nanoparticle and Nanowire-Based Device Employing Same - A method of positioning a catalyst nanoparticle that facilitates nanowire growth for nanowire-based device fabrication employs a structure having a vertical sidewall formed on a substrate. The methods include forming the structure, forming a targeted region in a surface of either the structure or the substrate, and forming a catalyst nanoparticle in the targeted region using one of a variety of techniques. The techniques control the position of the catalyst nanoparticle for subsequent nanowire growth. A resonant sensor system includes a nanowire-based resonant sensor and means for accessing the nanowire. The sensor includes an electrode and a nanowire resonator. The electrode is electrically isolated from the substrate. One or more of the substrate is electrically conductive, the nanowire resonator is electrically conductive, and the sensor further comprises another electrode. The nanowire resonator responds to an environmental change by displaying a change in oscillatory behavior. | 2010-05-06 |
| 20100109102 | Method and structure for forming a gyroscope and accelerometer - A method for fabricating a micro electromechanical device includes providing a first substrate including control circuitry. The first substrate has a top surface and a bottom surface. The method also includes forming an insulating layer on the top surface of the first substrate, removing a first portion of the insulating layer so as to form a plurality of standoff structures, and bonding a second substrate to the first substrate. The method further includes thinning the second substrate to a predetermined thickness and forming a plurality of trenches in the second substrate. Each of the plurality of trenches extends to the top surface of the first substrate. Moreover, the method includes filling at least a portion of each of the plurality of trenches with a conductive material, forming the micro electromechanical device in the second substrate, and bonding a third substrate to the second substrate. | 2010-05-06 |
| 20100109103 | MEMS PACKAGE - The invention provides a MEMS package including: a MEMS chip including a first surface, a second surface, a first cavity, and a sensing device, the sensing device defining a first end of the first cavity; a leadframe including a second cavity and being electrically connected to the first surface of the MEMS chip, the second cavity being adjacent to the sensing device of the MEMS chip; a conductive layer disposed on the second surface of the MEMS chip to define a second end of the first cavity and grounded via the leadframe that is electrically connected to the conductive layer so as to provide electromagnetic shielding to the MEMS chip; and an encapsulant covering the MEMS chip, the leadframe, and the conductive layer to define an shape of the MEMS package and allowing outer surfaces of the leadframe to emerge from the MEMS package. | 2010-05-06 |
| 20100109104 | PRESSURE SENSOR AND WIRE GUIDE ASSEMBLY - A pressure sensor chip is described. The pressure sensor chip include a substrate, a polycrystalline silicon layer, at least one silicon layer, and a diaphragm movement element. The polycrystalline silicon layer is formed on the substrate and has a cavity recess formed therein. The at least one silicon layer is formed on the polycrystalline silicon layer and covers the cavity recess thereby forming a reference chamber with a diaphragm. The diaphragm movement element is configured to sense movement of the diaphragm. An assembly incorporating the pressure sensor chip and a method of forming the pressure sensor chip are also described. | 2010-05-06 |
| 20100109105 | COMPONENT AND METHOD FOR ITS MANUFACTURE - A method for reducing microcrack formation and crack growth in the glass carrier of a component having a micromechanical sensor element that is bonded to the glass carrier. The upper side of the glass carrier acts as a bonding surface for the sensor element. The rear side of the glass carrier, situated opposite the upper side, acts as a mounting surface for the component, and the glass carrier has side surfaces that connect the upper side and the rear side. In particular, the glass carrier is formed by a segment of a glass wafer into which at least the contours of the glass carrier have been stamped, so that at least the areas produced in this way of the side surfaces of the glass carrier and the rear side of the glass carrier form a surface that is largely closed and free of microcracks. | 2010-05-06 |
| 20100109106 | High density spin-transfer torque MRAM process - A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden. | 2010-05-06 |
| 20100109107 | MAGNETIC STACK DESIGN WITH DECREASED SUBSTRATE STRESS - A magnetic element and a method for making a magnetic element. The method includes patterning a first electrode material to form a first electrode on a substrate and depositing filler material on the substrate around the first electrode. The method further includes polishing to form a planar surface of filler and the first electrode. A magnetic cell is formed on the planar surface and a second electrode is formed on the magnetic cell. In some embodiments, the first electrode has an area that is at least 2:1 to the area of the magnetic cell. | 2010-05-06 |
| 20100109108 | STRAM WITH COMPOSITE FREE MAGNETIC ELEMENT - Spin-transfer torque memory includes a composite free magnetic element, a reference magnetic element having a magnetization orientation that is pinned in a reference direction, and an electrically insulating and non-magnetic tunneling barrier layer separating the composite free magnetic element from the magnetic reference element. The free magnetic element includes a hard magnetic layer exchanged coupled to a soft magnetic layer. The composite free magnetic element has a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit. | 2010-05-06 |
| 20100109109 | MAGNETIC MEMORY ELEMENT UTILIZING SPIN TRANSFER SWITCHING - A magnetic memory element utilizing spin transfer switching includes a pinned layer, a tunneling barrier layer and a free layer structure. The tunneling barrier layer is disposed on the pinned layer. The free layer structure includes a composite free layer. The composite free layer includes a first free layer, an insert layer and a second free layer. The first free layer is disposed on the tunneling barrier layer and has a first spin polarization factor and a first saturation magnetization. The insert layer is disposed on the first free layer. The second free layer is disposed on the insert layer and has a second spin polarization factor smaller than the first spin polarization factor and a second saturation magnetization smaller than the first saturation magnetization. Magnetization vectors of the first free layer and the second free layer are arranged as parallel-coupled. | 2010-05-06 |
| 20100109110 | ST-RAM Cells with Perpendicular Anisotropy - Magnetic spin-torque memory cells, often referred to as magnetic tunnel junction cells, which have magnetic anisotropies (i.e., magnetization orientation at zero field and zero current) of the associated ferromagnetic layers aligned perpendicular to the wafer plane, or “out-of-plane”. A memory cell may have a ferromagnetic free layer, a first pinned reference layer and a second pinned reference layer, each having a magnetic anisotropy perpendicular to the substrate. The free layer has a magnetization orientation perpendicular to the substrate that is switchable by spin torque from a first orientation to an opposite second orientation. | 2010-05-06 |
| 20100109111 | MAGNETIC TUNNEL JUNCTION STRUCTURE HAVING FREE LAYER WITH OBLIQUE MAGNETIZATION - The present invention provides a magnetic tunnel junction structure, including a first magnetic layer having a fixed magnetization direction; a second magnetic layer having a reversible magnetization direction; a non-magnetic layer formed between the first magnetic layer and the second magnetic layer; a third magnetic layer allowing the magnetization direction of the second magnetic layer to be inclined with respect to a plane of the second magnetic layer by a magnetic coupling to the second magnetic layer, and having a perpendicular magnetic anisotropic energy thereof larger than an in-plane magnetic anisotropic energy thereof; and a crystal-structure separation layer formed between the second magnetic layer and the third magnetic layer for separating a crystallographic structure between the second and the third magnetic layers. | 2010-05-06 |
| 20100109112 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor and a method for manufacturing the same are disclosed. The image sensor can include a semiconductor substrate that includes photodiodes arranged for each unit pixel; an interlayer dielectric layer and metal wirings disposed on the semiconductor substrate; and a photorefractive unit that is formed on the periphery of an optical path incident on the photodiodes. The photorefractive unit has a lower refractive index than the interlayer dielectric layer. The slantly incident light can be incident on the photodiodes, while maintaining the slanted optical path as it is. The light sensitivity of the photodiodes can be improved, thereby improving image quality. | 2010-05-06 |
| 20100109113 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a semiconductor substrate formed on a first surface thereof with a readout circuitry and a photodiode area; a metal interconnection layer formed on the first surface; a connection via metal extending from the first surface to a second surface of the semiconductor substrate, the connection via metal having a projection part projecting from the second surface; an insulating layer formed on the first surface of the semiconductor substrate to expose the projection part while surrounding a portion of a lateral side of the projection part; and a metal pad formed on the insulating layer such that the metal pad covers the projection part, thereby shortening an optical path to reduce light loss and improve image sensitivity. | 2010-05-06 |
| 20100109114 | Semiconductor device and manufacturing method thereof - A semiconductor device manufacturing method includes etching a silicon on insulator (SOI) from its surface (i.e., semiconductor substrate layer) to form a first trench and a second trench. The first trench extends through the SOI substrate and reaches an electrode pad. The second trench terminates in the semiconductor substrate layer. The manufacturing method also includes forming an insulation film that covers the surface of the semiconductor substrate layer as well as the side walls and bottoms of the first and second trenches. The manufacturing method also includes removing the insulation film from the bottoms of the first and second trenches to expose the electrode pad from the first trench bottom and to expose the semiconductor substrate layer from the second trench bottom. The manufacturing method also includes forming a conductive film that covers the semiconductor substrate layer and the side walls and the bottoms of the first and second trenches to form a through via electrically connected to the electrode pad at the first trench bottom and to form a contact part electrically connected to the semiconductor substrate layer at the second trench bottom. The manufacturing method also includes patterning the conductive film on the semiconductor substrate layer to form the external electrodes and to form a potential fixing external electrode electrically connected to the contact part. | 2010-05-06 |
| 20100109115 | Virtual IC wafers and bonding of constitutent IC films - Integrated circuits are made by bonding to a substrate one or more slices of material, and forming circuits using the slices of material. | 2010-05-06 |
| 20100109116 | PHOTOELECTRIC CONVERSION FILM, PHOTOELECTRIC CONVERSION DEVICE AND COLOR IMAGE SENSOR HAVING THE PHOTOELECTRIC CONVERSION DEVICE - A blue color photoelectric conversion film includes: a p-type layer formed by depositing tetracene; a p,n-type layer formed by co-depositing tetracene and naphthalene-tetracarboxylic-dianhydride (“NTCDA”) on the p-type layer; and an n-type layer formed by depositing NTCDA on the p,n-type layer. | 2010-05-06 |
| 20100109117 | IMAGE SENSOR PHOTODIODES USING A MULTI-LAYER SUBSTRATE AND CONTACT METHOD AND STRUCTURE THEREOF - The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection. | 2010-05-06 |
| 20100109118 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor layer, a low withstand voltage transistor, and a high withstand voltage transistor. In the low withstand voltage transistor, a first high concentration collector region and a first base region contact with a first low concentration collector region provided in the semiconductor layer. In the high withstand voltage transistor, a second high concentration collector region and a second base region contact a second low concentration collector region provided in the semiconductor layer. Further, the second high concentration collector region and the second base region are configured such that the distance between the second high concentration collector region and the second base region in a parallel direction to a main surface of the semiconductor layer is longer than the distance between the first high concentration collector region and the first base region. | 2010-05-06 |
| 20100109119 | METHOD OF FORMING A GUARD RING OR CONTACT TO AN SOI SUBSTRATE - Embodiments of the present invention provide a microelectronic structure including a conductive element contacting a bulk semiconductor region of a substrate, the bulk semiconductor region being separated from a semiconductor-on-insulator (“SOI”) layer of the substrate by a buried dielectric layer. The microelectronic structure includes a trench isolation region overlying the buried dielectric layer, the trench isolation region sharing an edge with the SOI layer; a conformal layer overlying the trench isolation region, the conformal layer having a top surface and an opening defining a wall extending from the top surface towards the trench isolation region, the top surface including a lip portion adjacent to the wall; a dielectric layer overlying the top surface of the conformal layer; and a conductive element in conductive communication with the bulk semiconductor region, the conductive element consisting essentially of at least one of a semiconductor, a metal, and a conductive compound of a metal, and extending through the dielectric layer, the opening in the conformal layer, the trench isolation region, and the buried dielectric layer, and the conductive element contacting the lip portion. | 2010-05-06 |
| 20100109120 | SINGLE CRYSTAL SILICON STRUCTURES - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created. | 2010-05-06 |
| 20100109121 | MICROELECTROMECHANICAL SYSTEM - A micro electromechanical system and a fabrication method thereof, which has trenches formed on a substrate to prevent circuits from interfering each other, and to prevent over-etching of the substrate when releasing a microstructure. | 2010-05-06 |
| 20100109122 | METHOD TO REDUCE METAL FUSE THICKNESS WITHOUT EXTRA MASK - Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided. | 2010-05-06 |
| 20100109123 | Method of Constructing Inductors and Transformers - An embodiment of the invention relates to an apparatus including a magnetic device and a related method. A multilayer substrate is constructed with a winding formed in a metallic layer, an electrically insulating layer above the metallic layer, and a via formed in the electrically insulating layer to couple the winding to a circuit element positioned on the multilayer substrate. A depression is formed in the multilayer substrate, and a polymer solution, preferably an epoxy, containing a ferromagnetic component such as nanocrystaline nickel zinc ferrite is deposited within a mold positioned on a surface of the multilayer substrate above the winding and in the depression. An integrated circuit electrically coupled to the winding may be located on the multilayer substrate. The multilayer substrate may be a semiconductor substrate or a printed wiring board, and the circuit element may be an integrated circuit formed on the multilayer substrate. | 2010-05-06 |
| 20100109124 | METHOD OF FORMING A METAL-INSULATOR-METAL CAPACITOR - A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer. | 2010-05-06 |
| 20100109125 | SEMICONDUCTOR DEVICE - The semiconductor device includes a resistor cell that includes a diffused layer resistor, a P-well contact and an N-well contact. The diffused layer resistor is arranged on a semiconductor substrate and is formed by a diffused layer. The P-well contact surrounds an outer rim of the diffused layer resistor and is formed by another diffused layer. The N-well contact is arranged surrounding the outer rim of the P-well contact and is formed by a further diffused layer. Both the P-well and N-well contacts are partitioned into contact portions. Control electrode layer portions are arranged between neighboring contact sections of the P-well contact so the contact sections of the P-well contact and the control electrode layer portions alternate. Control electrode layer portions are arranged between neighboring contact sections of the N-well contact so that the contact sections of the N-well contact and the control electrode layer portions alternate with one another. | 2010-05-06 |
| 20100109126 | METHODS OF FORMING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN, SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING SAME - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure. | 2010-05-06 |
| 20100109127 | Semiconductor Constructions - Some embodiments include methods of reflecting ions off of vertical regions of photoresist mask sidewalls such that the ions impact foot regions along the bottom of the photoresist mask sidewalls and remove at least the majority of the foot regions. In some embodiments, trenches may be formed adjacent the photoresist mask sidewalls in a material that is beneath the photoresist mask. Another material may be formed to have projections extending into the trenches. Such projections may assist in anchoring said other material to the material that is beneath the photoresist mask. In some embodiments, the photoresist mask is utilized for patterning flash memory structures. Some embodiments include semiconductor constructions having materials anchored to underlying materials through fang-like projections. | 2010-05-06 |
| 20100109128 | Crack Deflector Structure for Improving Semiconductor Device Robustness Against Saw-Induced Damage - An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal. | 2010-05-06 |
| 20100109129 | WAFER LEVEL BUCK CONVERTER - A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front side of the LS die, the LS die having source, drain, and gate bonding pads located on a front side of a second section separate from the first section, the drain bonding pad electrically connected to the back side of the LS die in the second section. The HS die and the LS die are bonded together such that the source bonding pad of the HS die is electrically connected to the back side of the LS die, and each of the drain and gate bonding pads are electrically connected to separate TSVs in the LS die. | 2010-05-06 |
| 20100109130 | METHOD OF FORMING AN OXIDE THIN FILM - A thin oxide film is formed by atomic layer deposition (ALD) onto a substrate by exposing the substrate to a first precursor comprising a metal organic alkoxide or amide or heteroleptic derivatives thereof and subsequently exposing the substrate to a second precursor comprising an ALD compatible carboxylic acid or carboxyl acid derivative compound. The sequential exposure to the first and second precursors may be repeated until a sufficient film thickness of an oxide of the metal has been deposited on the substrate. This process allows growth of an oxide thin film or nanostructure, on any suitable substrate. It permits formation of a high-κ dielectric oxide thin film on the substrate with similar dielectric properties to a much thinner SiO | 2010-05-06 |
| 20100109131 | REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN THE METALLIZATION SYSTEM - In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools. | 2010-05-06 |
| 20100109132 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure. | 2010-05-06 |
| 20100109133 | SEMICONDUCTOR DEVICE - A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip. | 2010-05-06 |
| 20100109134 | PRE-MOLDED, CLIP-BONDED MULTI-DIE SEMICONDUCTOR PACKAGE - Semiconductor packages that contain multiple dies and methods for making such packages are described. The semiconductor packages contain a leadframe with multiple dies and also contain a single premolded clip that connects the dies. The premolded clip connects the solderable pads of the source die and gate die to the source and gate of the leadframe via standoffs. The solderable pads on the dies and on the standoffs provide a substantially planar surface to which the premolded clip is attached. Such a configuration increases the cross-sectional area of the interconnection when compared to wirebonded connections, thereby improving the electrical (RDS | 2010-05-06 |
| 20100109135 | SEMICONDUCTOR DIE PACKAGE INCLUDING LEAD WITH END PORTION - A semiconductor die package, and methods of making the same. The package includes a leadframe and a clip structure. The clip structure is formed, such that a portion of the clip structure points towards the semiconductor die and is coplanar with the leadframe. The semiconductor die package further includes a housing material covering at least a portion of the leadframe, the semiconductor die, and the clip structure. The housing material has an external recess that holds a portion of the clip structure. | 2010-05-06 |
| 20100109136 | Semiconductor device including semiconductor chip mounted on lead frame - A semiconductor device includes a lead frame, a semiconductor chip, a substrate, a plurality of chip parts, a plurality of wires, and a resin member. The lead frame includes a chip mounted section and a plurality of lead sections. The semiconductor chip is mounted on the chip mounted section. The substrate is mounted on the chip mounted section. The chip parts are mounted on the substrate. Each of the chip parts has a first end portion and a second end portion in one direction, and each of the chip parts has a first electrode at the first end portion and a second electrode at the second end portion. Each of the wires couples the second electrode of one of the chip parts and one of the lead sections. The resin member covers the lead frame, the semiconductor chip, the substrate, the chip parts, and the wires. | 2010-05-06 |
| 20100109137 | Layered chip package with heat sink - A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions. | 2010-05-06 |
| 20100109138 | WAFER-LEVEL CHIP-ON-CHIP PACKAGE, PACKAGE ON PACKAGE, AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a multi-chip package in which a plurality of semiconductor chips are mounted on a single package using a chip-on-chip technique reduces warping due to a difference in coefficients of thermal expansion (CTEs) between a printed circuit board (PCB) and a stacked semiconductor chip. A package on package is manufactured by vertically stacking packages to operate a memory semiconductor chip package and a logic semiconductor chip package in a single system. To improve a non-wet defect of solder balls used to connect packages and minimize the mounting height of the package on package, a protection member formed of an epoxy mold compound (EMC) is formed on the memory semiconductor chip package to only partially expose the solder balls, and the exposed portions of the solder balls are connected to vias formed in a rear surface of the logic semiconductor chip package using a solder ball attaching process. | 2010-05-06 |
| 20100109139 | STACK PACKAGE MADE OF CHIP SCALE PACKAGES - A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages. | 2010-05-06 |
| 20100109140 | FLEXIBLE SEMICONDUCTOR PACKAGE APPARATUS HAVING A RESPONSIVE BENDABLE CONDUCTIVE WIRE MEMBER AND A MANUFACTURING THE SAME - A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted. | 2010-05-06 |
| 20100109141 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY CARD - A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region. | 2010-05-06 |
| 20100109142 | INTERPOSER FOR SEMICONDUCTOR PACKAGE - An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact. | 2010-05-06 |
| 20100109143 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package includes forming a protection layer on a support plate, stacking substrates on the protection layer, electrically connecting the substrates to each other, forming a molding layer on the support plate, and removing the support plate while the protection layer remains on the substrates. The stacked substrates are offset from adjacent substrates. | 2010-05-06 |
| 20100109144 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate; and an interconnect electrically connected to the electrode and formed to extend over the resin protrusion. The interconnect includes a first portion formed on a top surface of the resin protrusion and a second portion formed on a side of a lower portion of the resin protrusion. The second portion has a width smaller than a width of the first portion. | 2010-05-06 |
| 20100109145 | SEALED BALL GRID ARRAY PACKAGE - According to an aspect of the invention, there is provided an electrical package device comprising: a first substrate and a second substrate enclosing a first electric component; the second substrate supporting a second electric component, a plurality of connectors for mechanically connecting said first and second substrates in a stacked arrangement; and a seal provided between said first and second substrates at a distance from said first electric component; wherein said first electric component is electrically connected to said second electric component by connecting circuitry comprising said connectors; and wherein said connectors are provided in said seal. Preferably, said seal comprises a no flow resin material. | 2010-05-06 |
| 20100109146 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; and a chip formed on the substrate and electrically connected to the substrate by a wire. The chip includes a wiring layer electrically connected to the wire; and a protective layer formed on the wiring layer. The wiring layer includes a wiring portion having the protective layer formed in an upper layer thereof and being electrically connected to another layer at a lower layer thereof; a bonding portion connected to one end of the wire at an exposed surface thereof, the exposed surface not having the protective layer formed in an upper layer thereof; and a connecting portion configured to join the wiring portion and the bonding portion. The connecting portion includes an etched portion formed by digging out the wiring layer. | 2010-05-06 |
| 20100109147 | Less expensive high power plastic surface mount package - A high power surface mount package including a thick bond line of solder interposed between the die and a heatsink, and between the die and a lead frame, wherein the lead frame has the same coefficient of thermal expansion as the heatsink. In one preferred embodiment, the heatsink and the lead frame are comprised of the same material. The package can be assembled using standard automated equipment, and does not require a weight or clip to force the parts close together, which force typically reduces the solder bond line thickness. Advantageously, the thermal stresses on each side of the die are effectively balanced, allowing for a large surface area die to be packaged with conventional and less expensive materials. One type of die that benefits from the present invention can include a transient voltage suppressor, but could include other dies generating a significant amount of heat, such as those in excess of 0.200 inches square. | 2010-05-06 |
| 20100109148 | SEMICONDUCTOR DEVICE - When a second semiconductor chip is mounted onto a first semiconductor chip, collision of the first semiconductor chip with a lead frame is to be prevented. The lead frame has a die pad and suspending leads for supporting the die pad. A joining portion is provided over the lead frame. The first semiconductor chip is provided over the lead frame through the joining portion. The second semiconductor chip is provided over the first semiconductor chip. A resin member covers the die pad and the first and second semiconductor chips. The joining portion is positioned over each of the die pad and the suspending leads. | 2010-05-06 |
| 20100109149 | FLIP CHIP WITH INTERPOSER, AND METHODS OF MAKING SAME - A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material. | 2010-05-06 |
| 20100109150 | METHOD OF ASSEMBLY OF A SEMICONDUCTOR PACKAGE FOR THE IMPROVEMENT OF THE ELECTRICAL TESTING YIELD ON THE PACKAGES SO OBTAINED - A method of assembly of a semiconductor package includes treating the electrical contacts thereof by the application on the electrical contacts of a chemical composition comprising at least one ionic polar surfactant. A semiconductor package has a coating on the electrical contacts thereof, the coating comprising at least one ionic polar surfactant. A device includes a semiconductor package with electrical contacts on a circuit board, the electrical contacts having a coating that includes an ionic surfactant. | 2010-05-06 |
| 20100109151 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a semiconductor chip having a first electrode on one face; a circuit board having a second electrode on a mounting face; a warp suppressing layer to suppress a warp of at least the semiconductor chip; and a stress relaxing layer to relax stress arising between the semiconductor chip and the warp suppressing layer. The semiconductor chip is mounted on the circuit board so as to electrically connect the first electrode with the second electrode of the circuit board and to oppose the one face to the mounting face: the stress relaxing layer is provided on a back face of the one face in the semiconductor chip; the warp suppressing layer is laminated on the semiconductor chip via the stress relaxing layer; the stress relaxing layer has a spacer to maintain a predetermined gap between the semiconductor chip and the warp suppressing layer; the stress relaxing layer has a Young's modulus lower than that of the warp suppressing layer; and the stress relaxing layer and the warp suppressing layer have coefficients of linear expansion greater than that of the semiconductor chip. | 2010-05-06 |
| 20100109152 | Electronic device and lid - The present invention can prevent a lid from tilting when the lid is attached to a substrate. An electronic device | 2010-05-06 |
| 20100109153 | HIGH BANDWIDTH PACKAGE - Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies. | 2010-05-06 |
| 20100109154 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - At least a part of a heat radiation member ( | 2010-05-06 |
| 20100109155 | RELIABLE INTERCONNECT INTEGRATION - A semiconductor device includes a dielectric layer in which an upper portion is densified. An interconnection is disposed in the dielectric layer. The densified portion reduces undercut during subsequent processing, improving reliability of the interconnection. | 2010-05-06 |
| 20100109156 | BACK SIDE PROTECTIVE STRUCTURE FOR A SEMICONDUCTOR PACKAGE - The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; a conductive layer formed upon the back surface of the die; and a protection substrate formed on the conductive layer. An adhesive layer is formed between the conductive layer and the protective layer, if necessary. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming a conductive layer upon the back surface of the die; forming protection substrates on the conductive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation by exerting external force on the substrate. An adhesive layer is formed between the conductive layer and the protective layer, if necessary. | 2010-05-06 |
| 20100109157 | CHIP STRUCTURE AND CHIP PACKAGE STRUCTURE - A chip structure and a chip package structure are disclosed herein. The chip structure includes a chip and a bump. The chip includes at least one pad. The bump is disposed on a bounding region of the pad. The shape of the bump is triangular pillar or trapezoidal pillar. A surface area of connection between the bump and the pad is less than or equal to the bounding region. Therefore, the material usage and the cost of the bump can be reduced. In addition, such shape of the bump has directional characteristic so that it is easy to perform the chip testing via the identifiable pads, and perform the package process of bonding the chip to a circuit board or any carriers. | 2010-05-06 |
| 20100109158 | SEMICONDUCTOR DEVICE INCLUDING A REDUCED STRESS CONFIGURATION FOR METAL PILLARS - In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar. | 2010-05-06 |
| 20100109159 | BUMPED CHIP WITH DISPLACEMENT OF GOLD BUMPS - A bumped chip is revealed, including a chip, a UBM layer, an Ag bump, and a creeping-resist layer. The chip has a bonding pad and a passivation layer covering one surface of the chip and exposing the bonding pad. The UBM layer is disposed on the bonding pad and covers the passivation layer at the peripheries of the opening. The Ag bump is disposed on the UBM layer to form as a pillar bump having a top surface and a pillar sidewall. The creeping-resist layer is formed at least on the pillar sidewall to fully encapsulate the Ag bump. Therefore, the disclosed bumped chip will have no Ag-creeping due to exerting stresses nor changing of joint heights under high temperature environment to meet the bumping requirements of lead-free, high reliability, and lower cost. | 2010-05-06 |
| 20100109160 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes the steps of preparing a semiconductor wafer having a connection pad, forming an insulating dam layer in which an opening portion is provided in an area including the connection pad, on the semiconductor wafer, and forming a bump electrode by mounting a conductive ball on the connection pad in the opening portion of the insulating dam layer. | 2010-05-06 |
| 20100109161 | REDUCING METAL VOIDS IN A METALLIZATION LAYER STACK OF A SEMICONDUCTOR DEVICE BY PROVIDING A DIELECTRIC BARRIER LAYER - Metallization systems on the basis of copper and low-k dielectric materials may be efficiently formed by providing an additional dielectric material of enhanced surface conditions after the patterning of the low-k dielectric material. Consequently, defects such as isolated copper voids and the like may be reduced without significantly affecting overall performance of the metallization system. | 2010-05-06 |
| 20100109162 | High Integrated Semiconductor Memory Device - Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array. | 2010-05-06 |
| 20100109163 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device comprising a first layer that is provided on a semiconductor substrate and includes a first wiring pattern planarized by CMP and a plurality of first dummy patterns made of a same material as the first wiring pattern and a second layer that is provided above the semiconductor substrate and includes a second wiring pattern planarized by CMP and a plurality of second dummy patterns made of a same material as the second wiring pattern. A central axis of each of the second dummy patterns coincides with that of a corresponding one of the first dummy patterns in a direction perpendicular to the semiconductor substrate. | 2010-05-06 |
| 20100109164 | STACKED INTEGRATED CIRCUIT PACKAGE FABRICATION METHODS THAT USE VIAS FORMED AND FILLED AFTER STACKING, AND RELATED STACKED INTEGRATED CIRCUIT PACKAGE STRUCTURES - Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages arc also described. | 2010-05-06 |
| 20100109165 | SEMICONDUCTOR DEVICE - A semiconductor device having a GaAsFET and input and output matching circuits connected to the FET is provided. In the semiconductor device, a line, including a wire connection portion connected to the input or output matching circuit and a lead connection portion connected to an input or output lead which is connected to an external circuit, is formed in such a manner that a line width at the wire connection portion is wider than that at the lead connection portion. With the semiconductor device, the number of wires connecting the input or output matching circuits with the wire connection portion can be increased. | 2010-05-06 |
| 20100109166 | DEVICE WITH CHIPLETS AND ADAPTABLE INTERCONNECTIONS - An active-matrix device includes a device substrate including a plurality of pixels formed thereon, each pixel having a separate control electrode, a plurality of chiplets having at least first and second corresponding chiplets disposed at different locations over the device substrate, a plurality of wires formed over the device substrate, each wire being connected to a connection pad and to a different pixel control electrode, and wherein the shape of at least one of the wires connecting a connection pad for the first chiplet is different from the shape of at least one of the wires connecting a corresponding connection pad for the second chiplet. | 2010-05-06 |
| 20100109167 | CONDUCTIVE PATHS FOR TRANSMITTING AN ELECTRICAL SIGNAL THROUGH AN ELECTRICAL CONNECTOR - The claimed invention relates to structures suitable for improving the performance and reliability of electrical connectors. One embodiment of the claimed invention includes an integrated circuit die having an electrical contact coupled with electrically conductive paths that share a common electrical source. The conductive paths are configured to transmit the same electrical signal to the electrical contact, which supports an electrical connector, such as a solder bump. The electrical connector couples the die with an outside component, such as a circuit board. Each of the conductive paths connect to the electrical contact at different interface locations. When the electrical signal passes through the interface locations, the paths are configured to have non-zero current densities at those locations. The electrical resistance of the conductive paths may be substantially similar. Thus, instead of being concentrated at a single point, current is more evenly distributed along the junction between the die and solder bump, which may reduce voiding and localized heating. | 2010-05-06 |
| 20100109168 | CONNECTING MICROSIZED DEVICES USING ABLATIVE FILMS - A method of providing connectivity to a microsized device, the method includes the steps of providing an ablative base material having at least a top surface; providing a die having a first and second surface and having bonding pads at least upon the first surface; placing the die with the at least first surface of the die contacting the at least first surface of the ablative base material; and ablating a channel in the ablative material proximate to the die. | 2010-05-06 |
| 20100109169 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME - A stiffener is provided for use in making semiconductor devices. The stiffener and method of use provided prevent or reduce warpage of a semiconductor package during the assembly process. More particularly, the stiffener functions to prevent or reduce warpage during molding of an assembly of wafers and/or dies. The stiffener may be positioned above the backside or non-active side of an assembly of wafer and/or dies during molding. The presence of the stiffener prevents or reduces warpage caused by CTE mismatch between the mold material and the wafer and/or under the high temperatures encountered in the process of molding. After molding, the stiffener may continue to provide support to the assembly. | 2010-05-06 |
| 20100109170 | MULTI-DIRECTIONAL SUBMERSIBLE FLOATING AERATOR - A multi-direction submersible floating aerator has a gas-ring compressor ( | 2010-05-06 |
| 20100109171 | TOWER/FRAME STRUCTURE AND COMPONENTS FOR SAME - A tower/frame structure of interconnected columns and beams (which may be used in a cooling tower) and novel columns, beams, connection mechanisms and other components are provided. In one embodiment, a column and a beam are constructed of pultruded composite fiber-reinforced plastic (FRP) materials. The beam includes two sidewall extensions or flanges (each having one or more attachment apertures) at one end and which are integral with the beam for connection to the column (having one or more corresponding attachment apertures). The dimension/spacing between the inner walls of the two flanges substantially equals or is slightly larger than the outer dimension of the column. The attachment holes are aligned and a fastener is inserted through the extensions and column for attaching the column and beam. The C-shaped end of the beam substantially conforms to the cross-sectional shape and dimensions of the column. Additional plastic components, such as a firewall and toe/trim member, for use in a cooling tower are also provided. | 2010-05-06 |
| 20100109172 | MOLD FOR MAKING LENS ARRAY AND METHOD FOR MAKING LENSES - An exemplary mold for molding a lens array includes a first mold core having a first molding surface and a second mold core having a second molding surface. The first and second molding surfaces each include spaced first and third molding portions arranged in an array and second and fourth molding portions, respectively. The first molding portions are interconnected by the second molding portions. The third molding portions are interconnected by the fourth molding portions. When the first mold core and the second mold core are in a ready position, a chamber is defined between the first molding surface and the second molding surface by having a space being maintained between each the first molding portion and the third molding portion and having a space being maintained between each the second molding portion and the fourth molding portion. | 2010-05-06 |
| 20100109173 | METHOD OF MANUFACTURING OPTICAL WAVEGUIDE - An optical waveguide is cut by moving a heated knife blade across the optical waveguide with the knife blade maintained at a predetermined angle. At that time, by maintaining the temperature of the knife blade at a temperature not lower than the glass transition point of the optical waveguide, a portion, in contact with a bevel plane of the knife blade, of the optical waveguide softens to be planarized along the bevel plane. In this way, an optical path conversion mirror constituted of a planarized cut plane is formed in a region through which the bevel plane has passed. | 2010-05-06 |
| 20100109174 | Method for drop cable having an oval cavity - A method of forming a low-cost drop cable ( | 2010-05-06 |
| 20100109175 | PROCESSOR CONTROLLED OPHTHALMIC DEVICE - This invention discloses methods and apparatus for providing a media insert with a Data Processor into an ophthalmic lens. An energy source is capable of powering the Data Processor included within the ophthalmic lens. In some embodiments, an ophthalmic lens is cast molded from a silicone hydrogel. | 2010-05-06 |
| 20100109176 | MACHINED LENS MOLDS AND METHODS FOR MAKING AND USING SAME - Molds for making ophthalmic lenses are generally discussed herein with particular discussions extended to plastic injection molded ophthalmic lens molds that are subsequently machined to have customized optical quality lens-defining surfaces for producing customized ophthalmic lenses, including contact lenses. The present molds can be used to form multifocal zones, ballast zones, diagnostic marks and the like on the ophthalmic lenses without the need tor making post-cure modifications to the lenses. | 2010-05-06 |
| 20100109177 | APPARATUS AND METHOD FOR THE PRODUCTION OF PLASTIC GRANULATE - The invention relates to a method and a device for producing plastic granulate, having a granulator which breaks up essentially continuously conveyed plastic mass flow into granulate particles, the granulator ( | 2010-05-06 |
| 20100109178 | EMBOLIZATION - Embolization, as well as related particles and methods, are described. | 2010-05-06 |
| 20100109179 | Orally Therapeutic Plastics and Devices Formed Therefrom - The present invention provides methods whereby a thermally formable plastic is compounded with releasable active ingredients. The compounded plastic is then formed into a desired dental delivery device such as an anatomical membrane, tray or strip. The dental device is then placed in the oral environment where it will release or leach active ingredients. The dental device is intended to treat, alter, improve, or aid in various conditions that are often present in the oral environment. | 2010-05-06 |
| 20100109180 | PROCESS FOR COOLING FLAT PLASTIC PRODUCTS - Method for cooling flat plastic products, in which plasticized plastic compound is fed to a calender via a slot nozzle by means of an extruder and is rolled and calibrated to the desired shape in this calender between at least two smoothing rolls, after which the film or sheet produced in this way is fed to a chill section comprising a plurality of adjustable rolls and passes through this section until it is sufficiently cool and dimensionally stable, at least both the gap width between the rolls and the speed of the rolls being controllable by open- and/or closed-loop control. | 2010-05-06 |
| 20100109181 | CONTROLLING DELIVERY OF POLYMER MATERIAL IN A SEQUENTIAL INJECTION MOLDING PROCESS - Method and apparatus for controlling the delivery of polymer material in a sequential injection molding process. In one embodiment, the method provides: delivering a first shot of a first material simultaneously to a plurality of mold cavities; independently sensing for each cavity a property that is indicative of a volume or flow of material that is delivered to the corresponding cavity during the step of delivering the first shot; independently stopping the step of delivering the first shot to one or more cavities according to a program that uses as a variable a signal indicative of the property sensed for the corresponding cavity during delivery of the first shot; and delivering a second shot of a second material simultaneously to the cavities subsequent to the step of stopping the step of delivering the first shot. | 2010-05-06 |
| 20100109182 | METHOD OF SETTING MOLD CLAMPING FORCE OF INJECTION MOLDING MACHINE - When test molding is performed by sequentially clamping a mold with a mold clamping force (100%, 80%, 70%, ...) obtained by sequentially lowering a mold clamping force by a predetermined amount from the maximum mold clamping force (100%), a mold clamping pressure Pc in an injection process is detected and a plurality of different monitored elements (Pc, Pcd and Per) corresponding to the variation of the mold clamping pressure Pc are monitored, and thus it is detected that at least one of the monitored elements is varied to exceed a predetermined threshold, a mold clamping force obtained by increasing a mold clamping force at the time of the production of the variation by a predetermined amount is set as a proper mold clamping force Fs. | 2010-05-06 |
| 20100109183 | METHOD OF SETTING MOLD CLAMPING FORCE OF INJECTION MOLDING MACHINE - Test molding is performed by sequentially clamping a mold | 2010-05-06 |
| 20100109184 | METHOD FOR THE MANUFACTURE OF AN ENGINE SHAFT - For the manufacture of a tubular low-pressure turbine shaft made of a fiber-composite material with metallic driven/driving protrusions ( | 2010-05-06 |
| 20100109185 | METHOD AND APPARATUS FOR MANUFACTURING UNEVEN THICKNESS RESIN SHEET - A method according to the invention comprises an extruding step of extruding molten resin from a die in a belt shape, a molding/cooling step of cooling and solidifying the extruded resin sheet while molding the same in uneven thickness by nipping the same between a mold roller and a nip roller, and a slow cooling step of slowly cooling the resin sheet peeled off the mold roller, and at least the former part of the slow cooling step has a substep of slowly cooling the resin sheet while holding the resin sheet in the original warp-free uneven thickness shape while so applying an external force to the resin sheet as not to obstruct the carriage of the resin sheet. | 2010-05-06 |
| 20100109186 | PRODUCTION OF BACKING COMPONENT FOR CARPET PRODUCTS - Disclosed are plastic compositions for a carpet backing having from about 5 to about 25% by weight PVC resin, from about 5 to about 25% by weight plasticizer, and from about 50 to about 90% by weight filler. In a preferred embodiment, the plastic composition is about 15% by weight Geon-138, about 15% by weight di-isononyl phthalate, and about 70% by weight fly ash. Also disclosed are methods for forming backings for floorcoverings using the disclosed plastic compositions. In preferred embodiments, a plastic composition is applied through a slot-die directly to the underside of a carpet or alternatively onto a conveyor belt on top of which the carpet or floorcovering may be subsequently positioned. | 2010-05-06 |
| 20100109187 | METHOD FOR PREPARING POLYURETHANE UREA-CONTAINING FILMS - Described is a method of preparing a cured, non-elastomeric polyurethane-containing film, the method including:
| 2010-05-06 |
| 20100109188 | METHOD FOR PREPARING POLYURETHANE UREA-CONTAINING FILMS - A method of preparing a polyurethane-containing film including:
| 2010-05-06 |
| 20100109189 | CONTINUOUS FLEXIBLE SUPPORT STRUCTURE ASSEMBLY - A surface support structure is provided with at least one cell having a plurality of upright walls. A first wall of the plurality of upright walls has a recessed portion forming at least a portion to allow extension and contraction in multiple directions of the at least one cell. The plurality of upright walls of the at least one cell define a perimeter such that the recessed portion extends towards a second wall of the plurality of upright walls and is within the perimeter. | 2010-05-06 |
| 20100109190 | PROCESS FOR PRODUCING THERMOPLASTIC RESIN MOLDING - A method for producing a thermoplastic resin molded article having a thermoplastic resin foam substrate and a functional member joined by welding to the foam substrate is provided. | 2010-05-06 |
| 20100109191 | METHOD FOR MAKING MULTI-LAYERED MOLDED ARTICLES - A method of forming a multi-layered molded article is described. The method includes applying a soft material to a substrate, thereby forming a substrate with a soft layer thereon. | 2010-05-06 |
| 20100109192 | METHOD FOR SEALING A COMPLEX SHAPE ELECTRONIC SENSOR BY LOW-PRESSURE INJECTION OF REACTIVE RESIN - A method of sealing, by low-pressure injection of reactive resin, an electronic sensor placed in a housing consisting of at least two attached elements, includes the following steps:
| 2010-05-06 |
| 20100109193 | PROCESS FOR PREPARING AN ELASTIC NONWOVEN WEB - A process of preparing an elastic thermally bonded nonwoven web, whereby the process is characterized by the following steps:
| 2010-05-06 |
| 20100109194 | Master Template Replication - Systems and methods for providing multiple replicas from a master template are described. Replicas may be formed having a mesa. In one embodiment, a dummy fill region may be included on master template and/or replicas. | 2010-05-06 |
| 20100109195 | RELEASE AGENT PARTITION CONTROL IN IMPRINT LITHOGRAPHY - Release agents with increased affinity toward nano-imprint lithography template surfaces interact strongly with the template during separation of the template from the solidified resist in a nano-imprint lithography process. The strong interaction between the surfactant and the template surface reduces the amount of surfactant pulled off the template surface during separation of a patterned layer from the template in an imprint lithography cycle. Maintaining more surfactant associated with the surface of the template after the separation of the patterned layer from the template may reduce the amount of surfactant needed in a liquid resist to achieve suitable release of the solidified resist from the template during an imprint lithography process. Strong association of the release agent with the surface of the template facilitates the formation of ultra-thin residual layers and dense fine features in nano-imprint lithography. | 2010-05-06 |
| 20100109196 | SYSTEM AND METHOD FOR PROCESSING MATERIAL - A system for processing materials includes handling and cutting stations positioned at appropriate positions along first and second conveying portions. A crust cutting station is positioned along the first conveyor portion. A crust removal station is positioned to span across the first and second conveying portions. Similarly, a stacking station is also positioned to span across the first and second conveying portions. Further, a first (vertical) cross cutting station is position along the second conveyor portion. Similarly, a second (horizontal) cross cutting station is located along the second conveyor portion. The process of using the disclosed system eliminates the need for specially designed stacking frames or trays and support rods, and improves cutting capacity and reduces processing time by only stacking the materials to be processed once, without de-stacking and restacking steps. | 2010-05-06 |
