| 18th week of 2010 patent applcation highlights part 18 |
| Patent application number | Title | Published |
|---|
| 20100108997 | Novel organic electroluminescent compounds and organic electroluminescent device using the same - Provided are novel organic electroluminescent compounds, and organic electroluminescent devices comprising the same as electroluminescent material. Specifically, the organic electroluminescent compounds according to the present invention are represented by Chemical Formula (1): | 2010-05-06 |
| 20100108998 | LIGHT EMITTING DEVICE - The invention relates to a light emitting device ( | 2010-05-06 |
| 20100108999 | PROCESS FOR PREPARING AN ELECTRONIC DEVICE - The invention relates to a process for preparing an electronic device using a protection layer, and to improved electronic devices prepared by this process, in particular organic field effect transistors (OFETs). | 2010-05-06 |
| 20100109000 | CHARGE INJECTION AND TRANSPORT LAYERS - Compositions for use in hole transporting layers (HTLs) or hole injection layers (HILs) are provided, as well as methods of making the compositions and devices fabricated from the compositions. OLED devices can be made. The compositions comprise at least one conductive conjugated polymer, at least one semiconducting matrix component that is different from the conductive conjugated polymer, and an optional dopant, and are substantially free of an insulating matrix component. | 2010-05-06 |
| 20100109001 | ORGANIC ELECTROLUMINESCENCE ELEMENT - In an organic electroluminescence device having a pair of electrodes and an organic medium which has a light emitting layer or a plurality of layers including the light emitting layer, contains a light emitting material formed with an organometallic complex compound having a heavy metal and is disposed between the pair of electrodes, the organic medium contains an amine derivative having a specific structure. The organic electroluminescence device exhibits a high efficiency of light emission even at a high luminance of several thousand cd/m | 2010-05-06 |
| 20100109002 | OXYNITRIDE SEMICONDUCTOR - Provided is an oxynitride semiconductor comprising a metal oxynitride. The metal oxynitride contains Zn and at least one element selected from the group consisting of In, Ga, Sn, Mg, Si, Ge, Y, Ti, Mo, W, and Al. The metal oxynitride has an atomic composition ratio of N, N/(N+O), of 7 atomic percent or more to 80 atomic percent or less. | 2010-05-06 |
| 20100109003 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed. | 2010-05-06 |
| 20100109004 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE - The present invention provides a thin film transistor substrate realizing reduced interlayer short-circuit defects in a capacitor, and a display device having the thin film transistor substrate. The thin film transistor substrate includes: a substrate; a thin film transistor having, over the substrate, a gate electrode, a gate insulating film, an oxide semiconductor layer, and a source-drain electrode in order; and a capacitor having, over the substrate, a bottom electrode, a capacitor insulating film, and a top electrode made of oxide semiconductor in order. | 2010-05-06 |
| 20100109005 | SEMICONDUCTOR DEVICE COMPRISING A DISTRIBUTED INTERCONNECTED SENSOR STRUCTURE FOR DIE INTERNAL MONITORING PURPOSES - In a semiconductor device, electrical measurement data may be obtained with enhanced spatial resolution, for instance from within the entire die region, by providing a distributed sensor structure, each of which may be individually accessed by an appropriate interconnect structure, while nevertheless maintaining the required number of terminals and test signals at a low level. | 2010-05-06 |
| 20100109006 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor device layer, a multilayered wiring section formed of a plurality of wiring layers and a plurality of interlayer insulating films on one surface of the semiconductor device layer, an external connection electrode formed on one of the plurality of wiring layers, and an opening formed in a concave shape extending from the semiconductor device layer to the multilayered wiring section so as to expose a surface of the external connection electrode; the opening has a larger opening diameter at an end farther from the external connection electrode than at the other end closer to the external connection electrode. | 2010-05-06 |
| 20100109007 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a thin film transistor array panel and a manufacturing method thereof. The method comprises: forming a thin film transistor on a substrate; forming a color filter adjacent to the thin film transistor and over the same substrate; depositing a first passivation layer on the color filter; coating a photosensitive film on the first passivation layer and exposing the photosensitive film to light using a first photomask to form a first photosensitive film pattern that comprises a first portion and a second portion that is thicker than the first portion, the first photosensitive film pattern exposing the first passivation layer around a circumference of the second portion; removing the exposed first passivation layer using the first photosensitive film pattern as an etch mask; blanket etching a whole surface of the first photosensitive film pattern until the first portion is removed to form a second photosensitive film pattern; depositing a conductive layer on the second photosensitive film pattern; and removing the second photosensitive film pattern to thereby selectively lift off portions of the conductive layer where a left behind portion forms a pixel electrode. | 2010-05-06 |
| 20100109008 | THIN-FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME - A thin-film transistor (“TFT”) substrate includes an insulating substrate, a gate line and a data line which are insulated from each other, disposed on the insulating substrate and are arranged in a lattice, and a pixel electrode which is electrically connected to the gate line and the data line by a switching device. The data line includes a lower layer which is formed of a transparent electrode, and an upper layer which is disposed directly on the lower layer. | 2010-05-06 |
| 20100109009 | DISPLAY DEVICE - Provided is a display device capable of suppressing generation of optical leakage current as well as increase in capacitance in a case where a plurality of thin film transistors (TFTs) including a gate electrode film on a light source side are formed in series. Relative areas of opposing regions between a semiconductor film and the gate electrode film with respect to channel regions are different in at least a part of the plurality of TFTs, to thereby provide a flat panel display having a structure for suppressing increase in capacitance while suppressing generation of optical leakage current. | 2010-05-06 |
| 20100109010 | DISPLAY DEVICE - A display device having thin film transistors which can efficiently suppress an OFF-leak current while suppressing the decrease of an ON current is provided. The display device includes an insulation substrate, and thin film transistors which are formed on the insulation substrate. Each thin film transistor includes a conductive layer on which a gate electrode is formed, a first insulation layer which is formed on the conductive layer, a semiconductor layer which is formed on the first insulation layer and has a first semiconductor film thereof formed above the gate electrode, the first semiconductor film having a first region and a second region which are spaced apart from each other on an upper surface thereof, a first electrode which is connected to the upper surface of the first semiconductor film via the first region, and a second electrode which is connected to the upper surface of the first semiconductor film via the second region. A portion of the gate electrode which is covered with the first semiconductor film is arranged closer to the first region than the second region. | 2010-05-06 |
| 20100109011 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME - A plurality of gate lines having gate electrodes are formed on a substrate and a semiconductor layer is formed on a gate insulating layer covering the gate lines. A plurality of data lines intersecting the gate lines are formed on the gate insulating layer and a plurality of drain electrodes are formed extending parallel with and adjacent to the data lines. Furthermore, a plurality of storage capacitor conductors are formed to be connected to the drain electrodes and to overlap an adjacent gate line. A passivation layer made of an organic material is formed on the above structure and has a contact hole. Furthermore, a plurality of pixel electrodes are formed to be electrically connected to the drain electrodes through the contact hole. | 2010-05-06 |
| 20100109012 | STRESS TRANSFER ENHANCEMENT IN TRANSISTORS BY A LATE GATE RE-CRYSTALLIZATION - A gate electrode structure of a transistor may be formed so as to exhibit a high crystalline quality at the interface formed with a gate dielectric material, while upper portions of the gate electrode may have an inferior crystalline quality. In a later manufacturing stage after implementing one or more strain-inducing mechanisms, the gate electrode may be re-crystallized, thereby providing increased stress transfer efficiency, which in turn results in an enhanced transistor performance. | 2010-05-06 |
| 20100109013 | Thin film transistor, method of manufacturing the same, and organic light emitting diode display device including the same - A thin film transistor for an organic light emitting diode includes a substrate including a pixel portion and an interconnection portion, a buffer layer on the substrate, a gate electrode and a gate interconnection on the buffer layer, wherein the gate electrode is located at the pixel portion and the gate interconnection is located at the interconnection portion, a gate insulating layer on the substrate, a semiconductor layer on the gate electrode, source and drain electrodes electrically connected to the semiconductor layer, and a metal pattern on the gate interconnection. | 2010-05-06 |
| 20100109014 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes: a conductive layer on which gate electrodes are formed; a first insulation layer which is formed on the conductive layer; a semiconductor layer which is formed on the first insulation layer and is provided for forming semiconductor films which contain poly-crystalline silicon above the gate electrodes; and a second insulation layer which is formed on the semiconductor layer. Here, the semiconductor film includes a channel region which overlaps with the gate electrode as viewed in a plan view. In the channel region, a portion of the semiconductor film which is in contact with the second insulation layer exhibits higher impurity concentration than a portion of the semiconductor film which is in contact with the first insulation layer. | 2010-05-06 |
| 20100109015 | GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer. In this manner, there are provided a gallium nitride semiconductor device which can be used under a high temperature environment while reduction in total circuit size can be attained, and a method for producing the gallium nitride semiconductor device. | 2010-05-06 |
| 20100109016 | POWER SEMICONDUCTOR MODULE - Provided is a power semiconductor module in which two components are bonded by a Bi based solder material. A Cu layer is provided on the surfaces thereof to be bonded by the Bi based solder material on the two-component. Two components, i.e., the components to be bonded, are a combination of a semiconductor element and an insulating part, or a combination of an insulating part and a radiator plate. The insulating part is composed of a Cu/SiNx/Cu laminated body. | 2010-05-06 |
| 20100109017 | GaN-BASED COMPOUND SEMICONDUCTOR DEVICE - A gallium nitride (GaN)-based compound semiconductor device having a structure improving a surface characteristic of a thin film growing on a substrate is provided. The GaN-based compound semiconductor device includes an Al | 2010-05-06 |
| 20100109018 | METHOD OF FABRICATING SEMI-INSULATING GALLIUM NITRIDE USING AN ALUMINUM GALLIUM NITRIDE BLOCKING LAYER - A method for fabricating a single crystal, high quality, semi-insulating (SI) gallium nitride (GaN) layer using an Al | 2010-05-06 |
| 20100109019 | FORMING METHOD OF GALLIUM NITRIDE SYSTEM COMPOUND SEMICONDUCTOR LAYER, TRANSFER METHOD OF THE SAME, AND SUBSTRATE STRUCTURE WITH THE SAME BONDED THERETO - A method includes: forming a first layer containing silicon oxide on a first substrate; partially removing the first layer to form an exposure portion on the first substrate; depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion; evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate; forming an epitaxial layer of the semiconductor on the first substrate through increase in a size of the core, combination of the cores, crystal growth, formation of facets, bending of dislocation lines, transverse crystal growth onto the first layer, collision between adjoining crystal grains, combination of the transversely grown crystals, formation of dislocation networks, and formation of a flat surface of the semiconductor; and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove. | 2010-05-06 |
| 20100109020 | Diode having vertical structure and method of manufacturing the same - A light emitting diode includes a conductive layer, an n-GaN layer on the conductive layer, an active layer on the n-GaN layer, a p-GaN layer on the active layer, and a p-electrode on the p-GaN layer. The conductive layer is an n-electrode. | 2010-05-06 |
| 20100109021 | REFLECTION -TYPE PHOTOINTERRUPTER - A reflection-type photointerrupter of the present invention includes a substrate, a light emitting element and a light receiving element. The substrate includes a first surface, a second surface opposite the first surface, and a first and a second recesses that are open in the first surface side. The light emitting element is arranged in the first recess, while the light receiving element is arranged in the second recess. The light emitting element is capable of emitting light. The light receiving element is capable of receiving the light emitted from the light emitting element and reflected by an object to be detected. | 2010-05-06 |
| 20100109022 | Light emitting device and fabricating method thereof - In a light emitting device and a fabricating method thereof are provide, wherein the light emitting device includes a light converting element, and a light emitting element positioned on the light converting element and including a first electrode, a light emitting structure and a second electrode, the first electrode formed on the light emitting element and having a first opening, the light emitting structure having a first conductive pattern of a first conductivity type, a light emitting pattern, and a second conductive pattern of a second conductivity type, which are sequentially stacked, and the second electrode formed on the second conductive pattern, wherein the light generated from the light emitting structure reaches the light converting element through the first opening. | 2010-05-06 |
| 20100109023 | TRANSFER METHOD OF FUNCTIONAL REGION, LED ARRAY, LED PRINTER HEAD, AND LED PRINTER - A method includes placing a first bonding layer on at least one of a first functional region bonded on a release layer with a light releasable adhesive layer on a first substrate, and a transfer region on a second substrate; bonding the first functional region to the second substrate by the first bonding layer; irradiating the release layer with light with a light blocking member being provided to separate the first substrate from the first functional region at the release layer; placing a second bonding layer on at least one of a second functional region on the first substrate, and a transfer region on the release layer or a transfer region on a third substrate; bonding the second functional region to the second substrate or the third substrate by the second bonding layer; and separating the first substrate from the second functional region at the release layer. | 2010-05-06 |
| 20100109024 | TRANSFER METHOD OF FUNCTIONAL REGION, LED ARRAY, LED PRINTER HEAD, AND LED PRINTER - A method includes arranging a bonding layer of a predetermined thickness on at least one of a first functional region bonded on a release layer, which is capable of falling into a releasable condition when subjected to a process, on a first substrate, and a region, to which the first functional region is to be transferred, on a second substrate; bonding the first functional region to the second substrate through the bonding layer; and separating the first substrate from the first functional region at the release layer. | 2010-05-06 |
| 20100109025 | OVER THE MOLD PHOSPHOR LENS FOR AN LED - Rectangular LED dice are mounted on a submount wafer. A first mold has rectangular indentations in it generally corresponding to the positions of the LED dice on the submount wafer. The indentations are filled with silicone, which when cured forms a clear first lens over each LED. Since the wafer is precisely aligned with the mold, the top surfaces of the first lenses are all within a single reference plane irrespective of any x, y, and z misalignments of the LEDs on the wafer. A second mold has rectangular indentations filled with a phosphor-infused silicone so as to form a precisely defined phosphor layer over the clear first lens, whose inner and outer surfaces are completely independent of any misalignments of the LEDs. A third mold forms an outer silicone lens. The resulting PC-LEDs have high chromaticity uniformity from PC-LED to PC LED within a submount wafer and from wafer to wafer, and high color uniformity over a wide viewing angle. | 2010-05-06 |
| 20100109026 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a light emitting device and a method of manufacturing the same. The light emitting device includes each of first and second semiconductor stacked structures including first and second conductive type semiconductor layers and an active layer, first and second contacts on tops and bottoms of the first and second semiconductor stacked structures to be connected to the first and second conductive type semiconductor layers, a substrate structure including first and second sides, a first insulation layer on an area where no second contact is formed among a surface of the first and second semiconductor stacked layers, first and second conductive layers connected to the second contacts of the first and second semiconductor stacked structures, first and second wiring layers on the first side of the substrate structure, and first and second external connection terminals connected to the first and second contacts of the first semiconductor stacked structure. | 2010-05-06 |
| 20100109027 | LIGHT EMITTING DIODE PACKAGE - Provided is an LED package. It is easy to control luminance according to the luminance and an angle applicable. Since heat is efficiently emitted, the LED package is easily applicable to a high luminance LED. The manufacturing process is convenient and the cost is reduced. The LED package includes a substrate, an electrode, an LED, and a heatsink hole. The electrode is formed on the substrate. The LED is mounted in a side of the substrate and is electrically connected to the electrode. The heatsink hole is formed to pass through the substrate, for emitting out heat generated from the LED. | 2010-05-06 |
| 20100109028 | Vertical ACLED structure - This application related to an opto-electrical device, comprising a first ACLED having a first n-type semiconductor layer, a first light emitting layer, a first p-type semiconductor layer, a first p-type electrode and a first n-type electrode; a second ACLED having a second n-type semiconductor layer, a second light emitting layer, a second p-type semiconductor layer, a second p-type electrode and a second n-type electrode, wherein each of the first ACLED and the second ACLED are vertical stack structure and is connected in anti-parallel manner. | 2010-05-06 |
| 20100109029 | Semiconductor Light Emitting Device Packages Including Submounts - A submount for a solid state lighting package includes a support member having upper and lower surfaces, a first side surface, and a second side surface opposite the first side surface, a first electrical bondpad on the upper surface of the support member and having a first bonding region proximate the first side surface of the support member and a second bonding region extending toward the second side surface of the support member, and a second electrical bondpad on the upper surface of the support member having a die mounting region proximate the first side surface of the support member and an extension region extending toward the second side surface of the support member. The die mounting region of the second electrical bondpad may be configured to receive an electronic device. The submount further includes a third electrical bondpad on the upper surface of the support member and positioned between the second side surface of the support member and the die mounting region of the second electrical bondpad. | 2010-05-06 |
| 20100109030 | SERIES CONNECTED FLIP CHIP LEDS WITH GROWTH SUBSTRATE REMOVED - LED layers are grown over a sapphire substrate. Individual flip chip LEDs are formed by trenching or masked ion implantation. Modules containing a plurality of LEDs are diced and mounted on a submount wafer. A submount metal pattern or a metal pattern formed on the LEDs connects the LEDs in a module in series. The growth substrate is then removed, such as by laser lift-off. A semi-insulating layer is formed, prior to or after mounting, that mechanically connects the LEDs together. The semi-insulating layer may be formed by ion implantation of a layer between the substrate and the LED layers. PEC etching of the semi-insulating layer, exposed after substrate removal, may be performed by biasing the semi-insulating layer. The submount is then diced to create LED modules containing series-connected LEDs. | 2010-05-06 |
| 20100109031 | LIGHT EMITTING ELEMENT WITH A PLURALITY OF CELLS BONDED, METHOD OF MANUFACTURING THE SAME, AND LIGHT EMITTING DEVICE USING THE SAME - The present invention relates to a light emitting element with arrayed cells, a method of manufacturing the same, and a light emitting device using the same. The present invention provides a light emitting element including a light emitting cell block with a plurality of light emitting cells connected in series or parallel on a single substrate, and a method of manufacturing the same, wherein each of the plurality of light emitting cells includes an N-type semiconductor layer and a P-type semiconductor layer, and the N-type semiconductor layer of one light emitting cell is electrically connected to the P-type semiconductor layer of another adjacent light emitting cell. Further, the present invention provides a light emitting device including a light emitting element with a plurality of light emitting cells connected in series. Accordingly, it is possible to simplify a manufacturing process of a light emitting device for illumination capable of being used with a household AC power source, to decrease a fraction defective occurring in manufacturing a light emitting device for illumination, and to mass-produce the light emitting device for illumination. Further, there is an advantage in that DC driving efficiency can be enhanced in an AC operation by installing a predetermined rectifying circuit outside the light emitting element. | 2010-05-06 |
| 20100109032 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed are a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a pad under the plurality of compound semiconductor layers; an electrode layer on the plurality of compound semiconductor layers; and a shock supporting member disposed on the plurality of compound semiconductor layers and corresponding to the pad. | 2010-05-06 |
| 20100109033 | Cavity Glass for Light-Emissive Devices and a Method of Manufacturing the Same - A method of manufacturing a transparent encapsulating sheet for a light-emissive device, the method comprising the steps: forming a plurality of cavities in one side of a transparent sheet of material for receiving light-emissive structures therein, said forming step producing a frosted surface comprising micro cracks in the cavities; coating said frosted surface with a low viscosity material whereby the micro cracks in the frosted surface are filled with the low viscosity material in order to form the transparent encapsulating sheet. | 2010-05-06 |
| 20100109034 | LED WITH MOLDED BI-DIRECTIONAL OPTICS - A double-molded lens for an LED includes an outer lens molded around the periphery of an LED die and a collimating inner lens molded over the top surface of the LED die and partially defined by a central opening in the outer lens. The outer lens is formed using silicone having a relatively low index of refraction such as n=1.33-1.47, and the inner lens is formed of a higher index silicone, such as n=1.54-1.76, to cause TIR within the inner lens. Light not internally reflected by the inner lens is transmitted into the outer lens. The shape of the outer lens determines the side emission pattern of the light. The front and side emission patterns separately created by the two lenses may be tailored for a particular backlight or automotive application. | 2010-05-06 |
| 20100109035 | COMPOUND SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a compound semiconductor light emitting device including: an Si—Al substrate; protection layers formed on top and bottom surfaces of the Si—Al substrate; and a p-type semiconductor layer, an active layer, and an n-type semiconductor layer which are sequentially stacked on the protection layer formed on the top surface of the Si—Al substrate, and a method for manufacturing the same. | 2010-05-06 |
| 20100109036 | LIGHT EMITTING UNIT - A light emitting unit includes a substrate, a first reflecting element, a light-emitting diode (LED), and a second reflecting element. At least one part of the substrate is light permeable. The LED is disposed between the substrate and the first reflecting element, and the first and second reflecting elements are disposed on two opposite sides of the substrate, respectively. | 2010-05-06 |
| 20100109037 | FLUORESCER SOLUTION, LIGHT-EMITTING DEVICE, AND METHOD FOR MANUFACTURING SAME - In a fluorescer solution, a plurality of types of fluorescent particles are contained in a resin liquid. Average particle sizes of these fluorescent particles decrease as densities of the types increase. In other words, average settling rates v | 2010-05-06 |
| 20100109038 | LIGHT EMITTING DIODE WITH INTEGRAL PARABOLIC REFLECTOR - The dielectric casing of a light emitting diode (LED) incorporates an integral parabolic reflector system which redirects light in a collimated pattern deflected at significant angles relative to the axis of symmetry of the LED. | 2010-05-06 |
| 20100109039 | LIGHT EMITTING DIODE PACKAGE - Provided is an LED package. It is easy to control luminance according to the luminance and an angle applicable. Since heat is efficiently emitted, the LED package is easily applicable to a high luminance LED. The manufacturing process is convenient and the cost is reduced. The LED package includes a substrate, an electrode, an LED, and a heatsink hole. The electrode is formed on the substrate. The LED is mounted in a side of the substrate and is electrically connected to the electrode. The heatsink hole is formed to pass through the substrate, for emitting out heat generated from the LED. | 2010-05-06 |
| 20100109040 | CHIP COATED LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - A chip coated LED package and a manufacturing method thereof. The chip coated LED package includes a light emitting chip composed of a chip die-attached on a submount and a resin layer uniformly covering an outer surface of the chip die. The chip coated LED package also includes an electrode part electrically connected by metal wires with at least one bump ball exposed through an upper surface of the resin layer. The chip coated LED package further includes a package body having the electrode part and the light emitting chip mounted thereon. The invention improves light efficiency by preventing difference in color temperature according to irradiation angles, increases a yield, miniaturizes the package, and accommodates mass production. | 2010-05-06 |
| 20100109041 | HIGH EFFICIENCY LED STRUCTURE - A high efficiency light-emitting diode (LED) structure is provided, which mainly includes a die cup. The die cup is respectively provided with an anode and a cathode at two sides there below, and is mounted on a substrate. A plurality of dies is disposed above the die cup. The dies are connected in series via a gold wire and meanwhile sealed with a molding compound. Pins of the dies are connected to the anode and the cathode. A drive current that is lower than one half of a maximum rated current value is applied to the LED structure, thereby improving the luminescent efficiency. | 2010-05-06 |
| 20100109042 | LIGHT EMITTING DEVICE - To provide a low-profile light emitting device which can be manufactured with good productivity without worsening mold releasability and which can prevent bending an end terminal of a lead electrode during handling of the light emitting device. A light emitting device comprising: a light emitting element; and a package having lead electrodes to be connected to the light emitting element and an opening in front thereof for emitting a light emitted from the light emitting element in which parts of the lead electrodes project out of the package and are bent so that end portions thereof are located on side surfaces of the package, wherein side surfaces have a first face adjacent to a rear surface of the package, on which the end portions are located, a second face having a plane direction different from the first face, and a third face adjacent to a front surface of the package, having a plane direction different from the second face. | 2010-05-06 |
| 20100109043 | METHODS AND STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event. | 2010-05-06 |
| 20100109044 | Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer - A semiconductor process and apparatus includes forming PMOS transistors ( | 2010-05-06 |
| 20100109045 | INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED LAYERS - An integrated circuit system that includes: providing a substrate including an active device; forming a trench within the substrate adjacent the active device; forming a first layer with a first lattice constant within the trench; and forming a second layer with a second lattice constant over the first layer, the second lattice constant differing from the first lattice constant. | 2010-05-06 |
| 20100109046 | Methods of forming low interface resistance contacts and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide. | 2010-05-06 |
| 20100109047 | Multijunction rare earth solar cell - Examples of device structures utilizing layers of rare earth oxides to perform the tasks of strain engineering in transitioning between semiconductor layers of different composition and/or lattice orientation and size are given. A structure comprising a plurality of semiconductor layers separated by transition layer(s) comprising two or more rare earth compounds operable as a sink for structural defects is disclosed. | 2010-05-06 |
| 20100109048 | METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES - A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device. | 2010-05-06 |
| 20100109049 | PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE - A device that includes a pattern of strained material and relaxed material on a substrate, a strained device in the strained material, and a non-strained device in the relaxed material. The strained material may be silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. Carbon-doped silicon or germanium-doped silicon may be used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon. | 2010-05-06 |
| 20100109050 | FIELD EFFECT TRANSISTOR WITH INDEPENDENTLY BIASED GATES - A field effect transistor (FET) having at least two independently biased gates can provide uniform electric field in the channel region of the FET. The same AC voltage may be applied to each gate for modulating the FET. One of the gates is positioned closer to the channel region than the other gate. Such a FET allows tailoring the electric field in the channel region of the FET so that it is substantially uniform. The FET exhibits desirable performance characteristics, including having a constant transconductance. | 2010-05-06 |
| 20100109051 | HIGH VOLTAGE GAN TRANSISTORS - A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm | 2010-05-06 |
| 20100109052 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer. | 2010-05-06 |
| 20100109053 | SEMICONDUCTOR DEVICE HAVING INTEGRATED CIRCUIT WITH PADS COUPLED BY EXTERNAL CONNECTING COMPONENT AND METHOD FOR MODIFYING INTEGRATED CIRCUIT - The present invention discloses a semiconductor device. The semiconductor device includes an integrated circuit and a connecting component. The integrated circuit includes a first pad; a second pad; a first current guiding circuit, coupled to the first pad and a first reference voltage, for selectively guiding a first specific electrical signal received from the first pad to the first reference voltage; and a second current guiding circuit, coupled to the second pad and a second reference voltage, for selectively guiding a second specific electrical signal received from the second pad to the second reference voltage; and the connecting component is external to the integrated circuit for coupling the first pad and the second pad. | 2010-05-06 |
| 20100109054 | PATTERN FORMATION IN SEMICONDUCTOR FABRICATION - Provided is a semiconductor device. The device includes a substrate having a photo acid generator (PAG) layer on the substrate. The PAG layer is exposed to radiation. A photoresist layer is formed on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element. | 2010-05-06 |
| 20100109055 | MOS transistors having optimized channel plane orientation, semiconductor devices including the same, and methods of fabricating the same - MOS transistors having an optimized channel plane orientation are provided. The MOS transistors include a semiconductor substrate having a main surface of a ( | 2010-05-06 |
| 20100109056 | METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS - Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching. | 2010-05-06 |
| 20100109057 | Fin field effect transistor and method of fabricating the same - A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode. | 2010-05-06 |
| 20100109058 | CONDUCTIVE OXYNITRIDE AND METHOD FOR MANUFACTURING CONDUCTIVE OXYNITRIDE FILM - An electrode formed using a transparent conductive oxide is likely to be crystallized by heat treatment performed in the manufacturing process of a semiconductor device. In the case of a thin film element using an electrode having a significantly uneven surface due to crystallization, a short circuit is likely to occur and thus reliability of the element is degraded. An object is to provide a light-transmitting conductive oxynitride which is not crystallized even if subjected to heat treatment and a manufacturing method thereof. It is found that an oxynitride containing indium, gallium, and zinc, to which hydrogen atoms are added as impurities, is a light-transmitting conductive film which is not crystallized even if heated at 350° C. and the object is achieved. | 2010-05-06 |
| 20100109059 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME, AND SOLID-STATE IMAGE PICKUP DEVICE USING THE SAME - Disclosed herein is a semiconductor device, including: a gate electrode formed on a semiconductor substrate through a gate insulating film; an extension region formed in the semiconductor substrate on a source side of the gate electrode; a source region formed in the semiconductor substrate on the source side of the gate electrode through the extension region; an LDD region formed in the semiconductor substrate on a drain side of the gate electrode; and a drain region formed in the semiconductor substrate on the drain side of the gate electrode through the LDD region; wherein the extension region is formed at a higher concentration than that of the LDD region so as to be shallower than the LDD region. | 2010-05-06 |
| 20100109060 | IMAGE SENSOR WITH BACKSIDE PHOTODIODE IMPLANT - An array of pixels is formed using a substrate. Each pixel can be formed on the substrate, which has a backside and a frontside that includes metalization layers. A photodiode is formed in the substrate and frontside P-wells are formed using frontside processing that are adjacent to the photosensitive region. A first N-type region is formed in the substrate below the photodiode. A second N-type region is formed in a region of the substrate below the first N-type region and is formed using backside processing. | 2010-05-06 |
| 20100109061 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A channel layer is deposited on a first impurity layer, a second impurity layer is deposited on the channel layer, a gate electrode is placed to surround a circumference of the channel layer with a gate insulating film interposed therebetween, a spin-injection magnetization-reversal element is deposited on the second impurity layer, a bit line is placed on the spin-injection magnetization-reversal element, and a word line is placed on the bit line to be electrically connected to the gate electrode. | 2010-05-06 |
| 20100109062 | SEMICONDUCTOR DEVICE - A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction. | 2010-05-06 |
| 20100109063 | Semiconductor device having MOS gate capacitor - To provide a PMOS transistor that is arranged within an N-well formed in a P-type semiconductor substrate and that is connected to an external terminal; and an MOS gate capacitor that is positioned adjacent to the PMOS transistor and of which one end and the other end are supplied with a power supply potential and a ground potential, respectively. An N-type diffusion layer that becomes a cathode of a PNPN parasitic thyristor configured by the PMOS transistor and the MOS gate capacitor is fixed to the power supply potential. This structure does not permit turning on of the PNPN parasitic thyristor, and thus a problem that a device is broken by a latch-up phenomenon is eliminated. | 2010-05-06 |
| 20100109064 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof. | 2010-05-06 |
| 20100109065 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES HAVING SUB-DIVIDED ACTIVE BARS AND METHODS OF MANUFACTURING SUCH DEVICES - Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar. | 2010-05-06 |
| 20100109066 | COMMON DRAIN NON-VOLATILE MULTIPLE-TIME PROGRAMMABLE MEMORY - An array of programmable non-volatile devices use a floating gate that functions as a FET gate that overlaps a portion of a common source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 2010-05-06 |
| 20100109067 | SiH4 soak for low hydrogen SiN deposition to improve flash memory device performance - Prior to deposition of a silicon nitride (SiN) layer on a structure, a non-plasma enhanced operation is undertaken wherein the structure is exposed to silane (SiH | 2010-05-06 |
| 20100109068 | Lanthanide dielectric with controlled interfaces - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film. | 2010-05-06 |
| 20100109069 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOF - A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer. | 2010-05-06 |
| 20100109070 | FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS - A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer. | 2010-05-06 |
| 20100109071 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer. The stacked body in a memory cell array region including a plurality of memory strings is divided into a plurality of blocks by slits with an interlayer dielectric film buried therein, the memory string including as many memory cells series-connected in the stacking direction as the conductive layers, the memory cell including the conductive layer, the semiconductor layer, and the charge storage layer provided between the conductive layer and the semiconductor layer, and each of the block is surrounded by the slits formed in a closed pattern. | 2010-05-06 |
| 20100109072 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes a first stacked body on a silicon substrate, and a second stacked body is provided thereon. The first stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a first portion of a through-hole extending in a stacking direction is formed. The second stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a second portion of the through-hole is formed. A memory film is formed on an inner face of the through-hole, and a silicon pillar is buried in an interior of the through-hole. A central axis of the second portion of the through-hole is shifted from a central axis of the first portion, and a lower end of the second portion is positioned lower than an upper portion of the first portion. | 2010-05-06 |
| 20100109073 | FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A flash memory device includes a semiconductor substrate having a trench formed therein, the trench including a device isolation film, an oxide film formed over the semiconductor substrate including the trench, a nitride film pattern inserted into the oxide film and formed at a sidewall of the trench, and a polysilicon pattern formed over the oxide film including the nitride film pattern. A method for manufacturing a flash memory device includes forming a first oxide film over the semiconductor substrate including the trench, forming the nitride film pattern at the sidewall of the trench provided with the first oxide film and forming a second oxide film over the semiconductor substrate including the nitride film pattern, forming an oxide film pattern at a contact surface between the nitride film pattern and the semiconductor substrate and a side of the nitride film pattern by partially removing the first oxide film and the second oxide film formed over the bottom of the trench and the semiconductor substrate, and forming a third oxide film over the semiconductor substrate including the oxide film pattern to form the oxide cover film into which the nitride film pattern is inserted. | 2010-05-06 |
| 20100109074 | Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same - A gate structure using nanodots as a trap site, a semiconductor device having the gate structure and methods of fabricating the same are provided. The gate structure may include a tunneling layer, a plurality of nanodots on the tunneling layer, and a control insulating layer including a high-k dielectric layer on the tunneling layer and the nanodots. A semiconductor memory device may further include a semiconductor substrate, the gate structure according to example embodiments on the semiconductor substrate and a first impurity region and a second impurity region in the semiconductor substrate, wherein the gate structure is in contact with the first and second impurity regions. | 2010-05-06 |
| 20100109075 | SEMICONDUCTOR DEVICE HAVING AN EXPANDED STORAGE NODE CONTACT AND METHOD FOR FABRICATING THE SAME - A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a yield, and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having an active region including a gate, a storage node contact region, and an isolation region that defines the active region. A passing gate and an isolation structure surrounding the passing gate are formed in the isolation region. A silicon epitaxial layer is selectively formed over an upper portion of the passing gate to expand the storage node contact region. | 2010-05-06 |
| 20100109076 | STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A first doped region of the first conductivity type and a second doped region of the second conductivity type are located in the second well region. A first transistor includes the first doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event. | 2010-05-06 |
| 20100109077 | High-voltage vertical transistor with a multi-gradient drain doping profile - A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2010-05-06 |
| 20100109078 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer. The first region and second region are driven into the semiconductor layer so as to form a pre-control region of the first conductivity type extending into the semiconductor layer from the surface and under a portion of the control region and a graded body region of the second conductivity type extending into the semiconductor layer under the pre-control region. A body region is formed by providing semiconductor material of the second conductivity type to the outlined first portion. The body region extends into the pre-control region. A current electrode region is formed in the body region. | 2010-05-06 |
| 20100109079 | Vertical type semiconductor device - A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns. | 2010-05-06 |
| 20100109080 | PSEUDO-DRAIN MOS TRANSISTOR - A pseudo-drain MOS transistor is disclosed. The transistor includes a semiconductor substrate; a gate structure disposed on the semiconductor substrate; a source, a pseudo-drain, a drain, and a shallow trench isolation disposed in the semiconductor substrate, a p-well disposed in the semiconductor substrate and under the source and the gate structure; and an n-well disposed under the drain. The source and the pseudo-drain are disposed adjacent to two sides of the gate structure and the shallow trench isolation is disposed between the pseudo-drain and the drain, and the n-well is extended toward the pseudo-drain while not reaching the area below the gate structure. | 2010-05-06 |
| 20100109081 | SEMICONDUCTOR DEVICE AND IC CHIP - A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region. | 2010-05-06 |
| 20100109082 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the region, implanting first impurities into the substrate using the gate electrode and the drain electrode as a mask, forming an insulating film to fill the space between the gate electrode and the drain electrode, and implanting second impurities into the substrate to form a source region using the gate electrode, the drain electrode and the insulating film as a mask. | 2010-05-06 |
| 20100109083 | Semiconductor Device and Method for Manufacturing the Same - Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes at least two of first and second conductive-type high-voltage transistors and first and second conductive-type low-voltage transistors. The first conductive-type high-voltage transistor include a first conductive-type well in a semiconductor substrate, a device isolation film in the first conductive-type well, a gate pattern on the first conductive-type well, second conductive-type drift regions in the semiconductor substrate at opposite sides of the gate pattern, second conductive-type source and drain regions in the second conductive-type drift region, a pick-up region to receive a bias voltage, and a first latch-up inhibiting region under the pick-up region. Accordingly, it is possible to reduce and prevent latchup without using a double guard ring and to eliminate an additional process to form first and second latch-up inhibiting regions. | 2010-05-06 |
| 20100109084 | Semiconductor Device and Method for Fabricating the Same - Disclosed herein is a semiconductor device having an enhanced floating body and a fabrication method for increasing operational stability of the device. The method includes depositing a fin structure on a silicon-on-insulator, forming a gate pattern covering the fin structure, and forming conductive regions in the silicon-on-insulator exposed at both sides of the gate pattern to compartmentalize a floating body of each transistor. | 2010-05-06 |
| 20100109085 | MEMORY DEVICE DESIGN - Memory elements and methods for making memory elements. One method of making a memory element includes forming a first electrode, forming an electrically conductive current densifying element and a memory cell on the first electrode, the memory cell and the current densifying element adjacent to each other. A second electrode is formed over the current densifying element and the memory cell. The memory elements may be resistance random access memory elements. | 2010-05-06 |
| 20100109086 | Method of Fabricating A Fin Field Effect Transistor (FinFET) Device - A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width. | 2010-05-06 |
| 20100109087 | Multichannel Metal Oxide Semiconductor (MOS) Transistors - Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided. | 2010-05-06 |
| 20100109088 | BALANCE STEP-HEIGHT SELECTIVE BI-CHANNEL STRUCTURE ON HKMG DEVICES - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 2010-05-06 |
| 20100109089 | MOS DEVICE AND PROCESS HAVING LOW RESISTANCE SILICIDE INTERFACE USING ADDITIONAL SOURCE/DRAIN IMPLANT - An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×10 | 2010-05-06 |
| 20100109090 | CMOS LATCH-UP IMMUNITY - Latch-up of CMOS devices ( | 2010-05-06 |
| 20100109091 | RECESSED DRAIN AND SOURCE AREAS IN COMBINATION WITH ADVANCED SILICIDE FORMATION IN TRANSISTORS - During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency. | 2010-05-06 |
| 20100109092 | MONOLITHICALLY INTEGRATED CIRCUIT - A monolithically integrated circuit, particularly an integrated circuit for radio frequency power applications, may include a transistor and a spiral inductor. The spiral inductor is arranged above the transistor. An electromagnetic coupling is created between the transistor and the inductor. The transistor may have a finger type layout to prevent any significant eddy currents caused by the electromagnetic coupling from occurring. The chip area needed for the circuit may be reduced by such arrangement. | 2010-05-06 |
| 20100109093 | Semiconductor memory devices and methods of fabricating the same - Semiconductor memory devices and methods of fabricating the semiconductor memory devices are provided, the semiconductor memory devices may include a one-time-programmable (OTP) cell and an electrically erasable programmable read-only memory (EEPROM). The OTP cell includes a memory transistor and a program transistor. The program transistor may include a fuse electrode and may be spaced apart from the memory transistor. The EEPROM cell includes a memory transistor including a first gate and a selection transistor including a second gate. The OTP cell includes a first high-density impurity region which overlaps with the fuse electrode. | 2010-05-06 |
| 20100109094 | METHOD FOR FORMING SILICIDE CONTACTS - Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes. | 2010-05-06 |
| 20100109095 | METHOD FOR FABRICATING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND THE DEVICE MADE THEREOF - A method for manufacturing a dual work function semiconductor device and the device made thereof are disclosed. In one aspect, a method includes providing a gate dielectric layer over a semiconductor substrate. The method further includes forming a metal layer over the gate dielectric layer. The method further includes forming a layer of gate filling material over the metal layer. The method further includes patterning the gate dielectric layer, the metal layer and the gate filling layer to form a first and a second gate stack. The method further includes removing the gate filling material only from the second gate stack thereby exposing the underlying metal layer. The method further includes converting the exposed metal layer into an metal oxide layer. The method further includes reforming the second gate stack with another gate filling material. | 2010-05-06 |
| 20100109096 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device capable of achieving improvement of I/O processing performance, reduction of power consumption, and reduction of cost is provided. Provided is a semiconductor integrated circuit device including, for example, a plurality of semiconductor chips stacked and mounted, the chips having data transceiving terminals bus-connected via through-vias, and data transmission and reception are performed via the bus with using the lowest source voltage among source voltages of internal core circuits of the chips. In accordance with that, a source voltage terminal of an n-th chip to be at the lowest source voltage is connected with source voltage terminals for data transceiving circuits of the other semiconductor chips via through-vias. | 2010-05-06 |
