18th week of 2022 patent applcation highlights part 74 |
Patent application number | Title | Published |
20220140034 | DISPLAY DEVICE - A display device includes: a substrate including a curved portion and a flat portion; an insulating layer disposed on the substrate; a first organic light emitting diode disposed on the insulating layer and having a first projection; and a second organic light emitting diode having a second projection, wherein a light emission portion is disposed in the curved portion and the flat portion, the first projection overlaps the light emission portion disposed in the curved portion and is asymmetric in the light emission portion, and the second projection overlaps the light emission portion in the flat portion and is symmetric in the light emission portion. | 2022-05-05 |
20220140035 | FLEXIBLE DISPLAY - A flexible display is provided. Each of a unit driving circuit of the flexible display includes a driving transistor and a reset capacitor. The reset capacitor includes a first reset electrode and a second reset electrode. The first reset electrode is arranged on a side of a gate of the driving transistor facing a source and a drain, and the second reset electrode is the gate or is electrically connected to the gate. The flexible display includes a metal interconnection layer formed around a transparent portion, and the metal interconnection layer is electrically connected to the first reset electrode. | 2022-05-05 |
20220140036 | DISPLAY DEVICE - A display device includes a substrate including pixels including a first pixel and a second pixel, a driver of the first pixel disposed on the substrate, a driver of the second pixel disposed on the substrate, a first pixel electrode overlapping the driver of the first pixel and electrically connected to the driver of the first pixel, a second pixel electrode overlapping the driver of the first pixel and the driver of the second pixel and electrically connected to the driver of the second pixel, an emission layer disposed on the first pixel electrode and the second pixel electrode, and a common electrode disposed on the emission layer, wherein the second pixel electrode includes a first opening overlapping the driver of the first pixel. | 2022-05-05 |
20220140037 | DISPLAY APPARATUS - A display apparatus, which may prevent a defect of a pixel due to external electrostatic discharge, includes: a first pixel including a first node; a second pixel neighboring the first pixel and including a second node; and an always-off thin-film transistor including a first electrode, a second electrode, and a gate electrode, the first electrode being connected to the first node of the first pixel, the second electrode being connected to the second node of the second pixel, in which a turn-off voltage is applied to the gate electrode. | 2022-05-05 |
20220140038 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer. | 2022-05-05 |
20220140039 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate and a display device are provided. The display substrate includes sub-pixels and a light emitting control signal line. The sub-pixel includes an organic light emitting element and a pixel circuit, the organic light emitting element includes a second electrode, the pixel circuit includes a driving transistor and a first light emitting control transistor, and the pixel circuit further includes a connection structure. In the second color sub-pixel, a first electrode of the first light emitting control transistor is electrically connected with the connection structure through a first connection hole, and the connection structure is electrically connected with the second electrode through a second connection hole, the first connection hole and the second connection hole are located on both sides of the light emitting control signal line. In the third color sub-pixel, the second electrode does not overlap with a channel of the driving transistor. | 2022-05-05 |
20220140040 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - A display panel, a manufacturing method thereof and a display device are disclosed. The display panel includes a display array layer, a first optical structural layer, and a first light shielding pattern. The display array layer includes a first sub-display area and a second sub-display area at least partially surrounded by the first sub-display area, the second sub-display area is configured to be able to transmit ambient light; the first optical structural layer is located at a display side of the display array layer; and the first light shielding pattern is located at a side of the first optical structural layer facing the display array layer, and the first light shielding pattern at least partially surrounds the second sub-display area and exposes at least a part of the second sub-display area. | 2022-05-05 |
20220140041 | DISPLAY DEVICE - A display device includes a substrate including a first display area and a second display area, a first sub-pixel in the first display area, a second sub-pixel in the second display area, and a light-shielding layer having a first hole overlapping the first sub-pixel and a second hole overlapping the second sub-pixel, where a ratio of a width of the first hole to a width of the first sub-pixel is greater than a ratio of a width of the second hole to a width of the second sub-pixel. | 2022-05-05 |
20220140042 | DISPLAY APPARATUS - A display apparatus in which an area of a peripheral area may be reduced while having a simple structure, the display apparatus includes a substrate, a bottom metal layer on the substrate and including a first extension line extending from the peripheral area outside a display area into the display area, a semiconductor layer on the bottom metal layer, a gate layer on the semiconductor layer, a first metal layer on the gate layer, and a second metal layer on the first metal layer and including a first data line extending from the peripheral area into the display area and electrically coupled to the first extension line in the peripheral area. | 2022-05-05 |
20220140043 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel includes a substrate, a driving circuit, and a first light blocking layer. The driving circuit includes an oxide transistor and a silicon transistor disposed at the substrate. The oxide transistor includes a first active layer. An orthographic projection of the first light blocking layer on the substrate at least overlaps an orthographic projection of the first active layer on the substrate. | 2022-05-05 |
20220140044 | FLEXIBLE DISPLAY PANEL AND DISPLAY DEVICE - A flexible display panel and a display device are provided. The flexible display panel includes a non-bending zone and at least one bending zone. A shape of the non-bending zone is a first rectangle, and a shape of the at least one bending zone is a second rectangle. The bending zone is arranged around the non-bending zone and is connected to the non-bending zone. A side of the second rectangle is connected to a straight side of the first rectangle. At least one of two rounded corners corresponding to the straight side of the non-bending zone connected to the at least one bending zone includes a concave wave shape. | 2022-05-05 |
20220140045 | DISPLAY PANEL, DISPLAY MODULE, AND ELECTRONIC DEVICE - A display panel, a display module, and an electronic device are provided. The display panel includes a third metal layer including a signal line, and a conductive layer including a connection portion. The connection portion is connected to the signal line. A pixel definition layer is disposed on the conductive layer, and the pixel definition layer includes a first opening region and a second opening region. A cathode is disposed in the second opening region and disposed on the pixel definition layer. The cathode is connected to the connection portion. | 2022-05-05 |
20220140046 | DISPLAY PANEL AND FABRICATION METHOD THEREOF - The present application provides a display panel and a fabrication method thereof. In the display panel, a bonding module covers a display area and an extension area, and a bonding conductive layer of the bonding module is electrically connected to an external driving chip. A display module covers the display area and the extension area, the display module comprises a thin film transistor array structure, and the thin film transistor array structure comprises a source-drain conductive layer. A portion of the source-drain conductive layer in the extension area is electrically connected to the bonding conductive layer by a through hole. | 2022-05-05 |
20220140047 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes a drive backplane, a transparent insulating layer and a light-emitting device layer. The drive backplane includes a driving circuit layer, a metal wiring layer, a first insulating layer and a reflective electrode layer. The first insulating layer has first via holes filled with first metal connectors. The reflective electrode layer includes first reflective electrodes respectively connected with the metal wiring layer through the first metal connectors. The light-emitting device layer includes a pixel electrode layer, an organic light-emitting layer and a common electrode layer. The pixel electrode layer includes first pixel electrodes respectively connected with the first reflective electrodes through the connection via holes. A distance between an orthographic projection of the connection via hole on the pixel electrode layer and an edge of the first pixel electrode is not less than a first threshold value. | 2022-05-05 |
20220140048 | DISPLAY PANEL, METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE - The present disclosure provides a display panel, including: a base substrate, a plurality of metal lead layers located on the base substrate, an insulating layer covering the plurality of metal lead layers, a driving transistor embedded on the base substrate, and a first electrode layer located on a surface of the insulating layer away from the base substrate, a binding area of the display panel including a first via hole exposing a first metal lead layer in the plurality of metal lead layers, a display area of the display panel including a second via hole penetrating the insulating layer, the first electrode layer being electrically connected to a first electrode of the driving transistor through the second via hole, and a slope angle of a sidewall of the first via hole being less than a slope angle of a sidewall of the second via hole. | 2022-05-05 |
20220140049 | DISPLAY AND DISPLAY DEVICE - A display includes a circuit board structure including a first circuit board and a second circuit board. The first circuit board has a carrying region and an electrical connection region on which a first pad is disposed. The second circuit board has a first region and a second region, the first region is arranged on the electrical connection region and is electrically connected to the first pad, and the second region is electrically connected to the driving terminal. The rigidity of the second circuit board is less than that of the first circuit board. The display substrate is in the carrying region and includes a silicon substrate in which a driving circuit is partially embedded, and a second pad electrically connected to the driving circuit. The driving circuit includes a transistor having a semiconductor layer which is inside the silicon substrate. The second pad is electrically connected to the first pad. | 2022-05-05 |
20220140050 | DISPLAY SUBSTRATE, FABRICATING METHOD THEREOF AND DISPLAY PANEL - Provided is display substrate, including driving circuit board, and first electrode layer, insulating layer, second electrode layer, isolation layer, transparent conductive layer sequentially stacked thereon. Driving circuit board includes pixel and bonding regions. First electrode layer includes first sub-portion in bonding region and second sub-portion in pixel region. Insulating and isolation layers are partially cover bonding and pixel regions. Insulating layer has first via hole in area corresponding to first sub-portion. Isolation layer has second via hole in the area. Axes of first and second via holes coincide, first sub-portion is exposed at first and second via holes. Second electrode layer is in pixel region, coupled to second sub-portion through third via hole in area corresponding to second sub-portion. Isolation layer has fourth via hole in area corresponding to second electrode layer. Transparent conductive layer is in pixel region, coupled to second electrode layer through fourth via hole. | 2022-05-05 |
20220140051 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes: a silicon-based substrate, a driving layer, a first electrode layer, an organic light emitting layer, a second electrode layer and a plurality of pads. The display signal access pad is configured to access the display signal during a display phase, the test signal access pad at least includes a first group of test phase access pads, and the first group of test phase access pads includes a first pad and a second pad, the first pad is electrically connected with the electrode ring, and the second pad is electrically connected with the silicon-based substrate. | 2022-05-05 |
20220140052 | DISPLAY AND DISPLAY DEVICE - A display includes a display substrate and a flexible circuit board. The display substrate includes a silicon substrate, a driving circuit of which at least part is embedded in the silicon substrate, and a first pad electrically connected with the driving circuit. The driving circuit includes a transistor with a semiconductor layer; the flexible circuit board includes a flexible substrate, a first wiring layer, and a first reinforcement plate. The first wiring layer includes a main wiring portion and a second pad electrically connected with the main wiring portion, and the second pad is electrically connected with the first pad by a conductive adhesive layer. The first reinforcement plate covers the main wiring portion and does not cover the second pad. The first reinforcement plate is located outside the display substrate and there is a non-zero distance between the first reinforcement plate and the display substrate. | 2022-05-05 |
20220140053 | DISPLAY PANEL AND DISPLAY DEVICE - The present disclosure relates to the field of display technologies and, in particular to a display panel and a display device. The display panel includes a circuit board assembly, a plurality of sub-pixels, a base substrate, and a plurality of connecting wires. The circuit board assembly includes a plurality of first bonding pads; a plurality of second bonding pads are disposed in the non-display area of the base substrate; the plurality of connecting wires connect the plurality of first bonding pads and the plurality of second bonding pads. Adjacent connecting wires have different maximum stretchable heights in a direction perpendicular to the base substrate. | 2022-05-05 |
20220140054 | DISPLAY DEVICE - A display device according to an embodiment includes a substrate including a display area, a first peripheral area disposed outside the display area, and a second peripheral area disposed between the display area and the first peripheral area; a common voltage supply line disposed on the first peripheral area and the second peripheral area of the substrate; and a common electrode electrically connected to the common voltage supply line, wherein the common voltage supply line includes a first opening disposed in the first peripheral area; and a second opening disposed in the second peripheral area, and the first opening and the second opening are different in size or arrangement. | 2022-05-05 |
20220140055 | DISPLAY DEVICE - A display device includes a substrate including a display area and a non-display area, a plurality of pixels disposed in the display area, a common voltage supply wiring overlapping the non-display area and disposed on the substrate, a driving voltage supply wiring overlapping the non-display area and disposed on the substrate, and a data voltage supply wiring overlapping the non-display area and electrically connected to the plurality of pixels, where at least one of the common voltage supply wiring and the driving voltage supply wiring includes a chamfered area, the data voltage supply wiring includes a first data voltage supply wiring, a second data voltage supply wiring, and a third data voltage supply wiring, and the first to third data voltage supply wirings are disposed in different layers. | 2022-05-05 |
20220140056 | DISPLAY DEVICE - A display device includes first power supply terminal electrodes and second power supply terminal electrodes. The first power supply terminal electrodes in a first terminal portion of a frame area at least partially overlap, in a plan view, at least a part of the second power supply terminal electrodes in a second terminal portion of a flexible printed board. The second power supply terminal electrodes are electrically connected to the first power supply terminal electrodes. Either the first power supply terminal electrodes or the second power supply terminal electrodes are inclined from the others. | 2022-05-05 |
20220140057 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - A display device includes a display region and a frame region surrounding the display region. The display device includes a TFT layer, a light-emitting element layer formed with a plurality of light-emitting elements each including a first electrode, a light-emitting layer, and a second electrode, and having a luminescent color different from each other, and a sealing layer including an organic film and configured to seal the light-emitting element layer. The second electrode is an electrode common to the plurality of light-emitting elements, and includes metal nanowires which are mesh-shaped. | 2022-05-05 |
20220140058 | DISPLAY APPARATUS - A display apparatus includes a substrate, a thin-film transistor, a display element, a pad, a contact layer, and a pad-protecting layer. The substrate includes a display area and a peripheral area outside the display area. Each of the thin-film transistor and the display element is arranged in the display area. The pad is arranged in the peripheral area. The contact layer is electrically connected to the pad. The pad-protecting layer is on the contact layer and exposes a portion of the contact layer to the outside. The pad includes a first pad layer and a second pad layer. The first pad layer is connected to a connection wiring through a first contact hole. The second pad layer is spaced apart from the first pad layer and is connected to the first pad layer through a second contact hole. | 2022-05-05 |
20220140059 | DISPLAY DEVICE - A display device includes a pixel electrode disposed on a first surface of a substrate, a light emitting layer disposed on the pixel electrode, a common electrode disposed on the light emitting layer, a supply voltage line disposed on the first surface of the substrate and applying a voltage to the common electrode, a first auxiliary conductive layer disposed on a second surface of the substrate, and a first connection conductive layer at least partially disposed on a side surface of the substrate and electrically connecting the first auxiliary conductive layer to the supply voltage line. | 2022-05-05 |
20220140060 | ELECTROLUMINESCENCE DISPLAY DEVICE - An electroluminescence display device comprises a substrate including a pixel area having a light emitting portion and a non-light emitting portion adjacent to the light emitting portion; a first electrode in the light emitting portion of the pixel area; an auxiliary electrode in the non-light emitting portion of the pixel area and spaced apart from the first electrode; a light emitting layer on the first electrode; a second electrode on the light emitting layer in the pixel area and connected to the light emitting layer; and an auxiliary power electrode below the first electrode and electrically connected with the auxiliary electrode. | 2022-05-05 |
20220140061 | DISPLAY DEVICE - According to one embodiment, a display device includes a bank covering an edge and a side surface of a pixel electrode and having an opening exposing a part of an upper surface of the pixel electrode, a hole transport layer arranged in the opening and disposed over the pixels, a metal line disposed with the hole transport layer sandwiched on a top area of the bank, a light emitting layer disposed between a plurality of the banks adjacent to each other and disposed in the opening in each of the pixels, wherein the light emitting layer comprises a first light emitting layer in the first pixel, a second light emitting layer in the second pixel, and a third light emitting layer in the third pixel, and the metal line is in contact with the third light emitting layer. | 2022-05-05 |
20220140062 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a display device includes forming a sacrificial layer on a carrier substrate, forming a first base layer on the carrier substrate that surrounds the sacrificial layer and includes a different material from the sacrificial layer, forming pad electrodes on the first base layer that contact the sacrificial layer, forming a pixel structure on the first base layer that is electrically connected to the pad electrodes, separating the carrier substrate from the first base layer and the sacrificial layer, removing the sacrificial layer to expose the pad electrodes, and attaching a conductive film under the pad electrodes that contacts the pad electrodes. | 2022-05-05 |
20220140063 | DISPLAY APPARATUS - A display apparatus includes a substrate; a plurality of display units on the substrate, each including a thin film transistor including at least one inorganic layer, a passivation layer on the thin film transistor, and a display device electrically connected to the thin film transistor; and a plurality of encapsulation layers respectively encapsulating the plurality of display units. The substrate includes a plurality of islands spaced apart, a plurality of connection units connecting the plurality of islands, and a plurality of through holes penetrating through the substrate between the plurality of connection units. The plurality of display units are on the plurality of islands, respectively. The at least one inorganic layer and the passivation layer extend on the plurality of connection units. The passivation layer includes a trench exposing the at least one inorganic layer. The encapsulation layer contacts the at least one inorganic layer exposed via the trench. | 2022-05-05 |
20220140064 | DISPLAY DEVICE, TILING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a display device, a tiling display device, and a method of manufacturing a tiling display device and the display device according to an aspect of the present disclosure includes: a display panel; a metal plate disposed on a rear side of the display panel; a plurality of magnets disposed on a rear side of the metal plate; and a plurality of ferromagnetic materials disposed on both side of the plurality of magnets. Therefore, the plurality of magnets and the plurality of ferromagnetic materials are used to easily attach and detach the display device and install, maintain, and repair the display device. | 2022-05-05 |
20220140065 | SEMICONDUCTOR DEVICE STRUCTURE WITH MAGNETIC ELEMENT - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an adhesive element between the magnetic element and the substrate. The adhesive element extends exceeding opposite edges of the magnetic element. The semiconductor device structure further includes an isolation element extending exceeding the opposite edges of the magnetic element. The isolation element partially covers a top surface of the magnetic element. In addition, the semiconductor device structure includes a conductive line over the isolation element. | 2022-05-05 |
20220140066 | CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Provided are a capacitor and a semiconductor device including the capacitor. The capacitor includes a first electrode; a plurality of dielectric films on the first electrode in a sequential series, the plurality of dielectric layers having different conductances from each other; and a second electrode on the plurality of dielectric films, wherein the capacitor has a capacitance which converges to a capacitance of one of the plurality of dielectric films. | 2022-05-05 |
20220140067 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A semiconductor device includes a lower electrode; an upper electrode disposed to be spaced apart from the lower electrode; and a dielectric layer disposed between the lower electrode and the upper electrode, and including a first metal oxide region, a second metal oxide region, and a third metal oxide region. | 2022-05-05 |
20220140068 | CAPACITOR ARCHITECTURES IN SEMICONDUCTOR DEVICES - Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed. | 2022-05-05 |
20220140069 | CAPACITOR ARCHITECTURES IN SEMICONDUCTOR DEVICES - Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed. | 2022-05-05 |
20220140070 | CAPACITOR STRUCTURE - A capacitor structure implemented as a layered structure including a plurality of alternating dielectric and metallization layers, and a method of manufacturing such capacitor structure. The capacitor structure including at least one lateral parallel plate capacitor part (LPP part) including two first electrodes on two different layers separated by dielectric material of a plurality of the alternating layers, and at least one vertical parallel plate capacitor part (VPP part) including two second electrodes each including a plurality of superimposed slabs or bars arranged on a plurality of the metallization layers. The at least one LPP part is electrically coupled with the at least one VPP part to form the capacitor structure. A variation in capacitance value of the at least one LPP part due to a variation of thickness of dielectric material is at least partially compensated by an opposite variation in capacitance value of the at least one VPP part. | 2022-05-05 |
20220140071 | SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF - A semiconductor structure and a formation method thereof are provided. The formation method includes: forming a plurality of lower electrodes on a base, the lower electrode including a ring-like wall and a petal-like wall extending along a direction perpendicular to a surface of the base, and the petal-like wall dividing the ring-like wall internally into a plurality of discrete first openings; forming a dielectric layer on a bottom and a sidewall of the first opening; and forming an upper electrode in the first opening, the dielectric layer being located between the lower electrode and the upper electrode. The lower electrode according to the present application includes the ring-like wall and the petal-like wall, so that a surface area of the lower electrode is increased. | 2022-05-05 |
20220140072 | SEMICONDUCTOR DEVICE WITH VOLTAGE RESISTANT STRUCTURE - A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion. | 2022-05-05 |
20220140073 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A power semiconductor device includes an epitaxial layer of a first conductivity type, a first doped region of a second conductivity type, a second doped region of the first conductivity type, a contact metal layer, a device electrode, a first termination electrode, and a second termination electrode. The epitaxial layer includes an active region and a termination region. | 2022-05-05 |
20220140074 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure. | 2022-05-05 |
20220140075 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first region and a second region, first and second nanowires disposed sequentially on the substrate in the first region, and extending respectively in a first direction, third and fourth nanowires disposed sequentially on the substrate in the second region, and extending respectively in the first direction, a first inner spacer between the first nanowire and the second nanowire, and including hydrogen of a first hydrogen mole fraction, and a second inner spacer between the third nanowire and the fourth nanowire, and including hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction. | 2022-05-05 |
20220140076 | SOURCE-CHANNEL JUNCTION FOR III-V METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS) - Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed. | 2022-05-05 |
20220140077 | SEMICONDUCTOR DEVICE - The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion. | 2022-05-05 |
20220140078 | Nano-Sheet-Based Devices with Asymmetric Source and Drain Configurations - A device includes a semiconductor substrate, a source feature and a drain feature over the semiconductor substrate, a stack of semiconductor layers interposed between the source feature and the drain feature, a gate portion, and an inner spacer of a dielectric material. The gate portion is between two vertically adjacent layers of the stack of semiconductor layers and between the source feature and the drain feature. Moreover, the gate portion has a first sidewall surface and a second sidewall surface opposing the first sidewall surface. The inner spacer is on the first sidewall surface and between the gate portion and the drain feature. The second sidewall surface is in direct contact with the source feature. | 2022-05-05 |
20220140079 | Melt Anneal Source and Drain Regions - A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal. | 2022-05-05 |
20220140080 | P-TYPE FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure. | 2022-05-05 |
20220140081 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device including an active pattern on a substrate and extending lengthwise in a first direction parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure along the first direction; a source/drain layer on a portion of the active pattern adjacent to the gate structure in the first direction, the source/drain layer contacting the channels; inner spacers between the gate structure and the source/drain layer, the inner spacers contacting the source/drain layer; and channel connection portions between each of the inner spacers and the gate structure, the channel connection portions connecting the channels with each other. | 2022-05-05 |
20220140082 | SEMICONDUCTOR APPARATUS - Provided is a semiconductor apparatus comprising: a semiconductor substrate; an element electrode provided above the semiconductor substrate; an element electrode pad electrically connected to the element electrode; and a wire configured to connect to the element electrode pad at a plurality of connection points, wherein the semiconductor substrate includes an emitter region of a first conductivity type arrayed in an array direction, the emitter region facing the element electrode on an upper surface of the semiconductor substrate, wherein a density of the emitter region below a connection point of any of the wires is different from a density of the emitter region below a connection point of any other of the wires. | 2022-05-05 |
20220140083 | OXIDE SEMICONDUCTOR FILM AND SEMICONDUCTOR DEVICE - A first raw material solution containing at least aluminum is atomized to generate first atomized droplets and a second raw material solution containing at least gallium and a dopant is atomized to generate second atomized droplets, and subsequently, the first atomized droplets are carried into a film forming chamber using a first carrier gas and the second atomized droplets are carried into the film forming chamber using a second carrier gas, and then the first atomized droplets and the second atomized droplets are mixed in the film forming chamber, and the mixed atomized droplets are thermally reacted in the vicinity of a surface of the base to form an oxide semiconductor film on the base, the oxide semiconductor film including, as a major component, a metal oxide containing at least aluminum and gallium, wherein the oxide semiconductor film has a mobility of no less than 5 cm | 2022-05-05 |
20220140084 | OXIDE FILM AND SEMICONDUCTOR DEVICE - A first raw material solution containing at least aluminum is atomized to generate first atomized droplets and a second raw material solution containing at least gallium and a dopant is atomized to generate second atomized droplets, and subsequently, the first atomized droplets are carried into a film forming chamber using a first carrier gas and the second atomized droplets are carried into the film forming chamber using a second carrier gas, and then the first atomized droplets and the second atomized droplets are mixed in the film forming chamber, and the mixed atomized droplets are thermally reacted in the vicinity of a surface of the base to form an oxide film on the base, the oxide film including, as a major component, a metal oxide containing at least aluminum and gallium, the oxide film having a corundum structure, wherein a principal surface of the oxide film is an m-plane. | 2022-05-05 |
20220140085 | QUANTUM COMPUTING ASSEMBLIES - Disclosed herein are quantum computing assemblies, as well as related computing devices and methods. For example, in some embodiments, a quantum computing assembly may include: a quantum device die to generate a plurality of qubits; a control circuitry die to control operation of the quantum device die; and a substrate; wherein the quantum device die and the control circuitry die are disposed on the substrate. | 2022-05-05 |
20220140086 | QUANTUM DOT DEVICES WITH SINGLE ELECTRON TRANSISTOR DETECTORS - Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates. | 2022-05-05 |
20220140087 | ELECTRONIC DEVICE WITH GALLIUM NITRIDE TRANSISTORS AND METHOD OF MAKING SAME - Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure. | 2022-05-05 |
20220140088 | STACKED, HIGH-BLOCKING INGAAS SEMICONDUCTOR POWER DIODE - A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs. | 2022-05-05 |
20220140089 | PARASITIC CHANNEL MITIGATION USING SILICON CARBIDE DIFFUSION BARRIER REGIONS - Semiconductor structures and methods of forming semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a semiconductor substrate and a III-nitride material region over a top surface of the semiconductor substrate. The semiconductor substrate includes a bulk region below the top surface and a parasitic channel that extends to a depth from the top surface toward the bulk region of the semiconductor substrate. The parasitic channel comprises a first region and a second region. The first region of the parasitic channel comprises an implanted species having a relative atomic mass of less than 5, and the second region of the parasitic channel is free from the implanted species or the implanted species is present in the second region at a concentration that is less than in the first region. | 2022-05-05 |
20220140090 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a memory transistor. The memory transistor includes a conductor including an opening, a first insulator provided in contact with an inner side of the opening, a second insulator provided in contact with an inner side of the first insulator, a third insulator provided in contact with an inner side of the second insulator, a first oxide provided in contact with an inner side of the third insulator, and a second oxide provided in contact with an inner side of the first oxide. An energy gap of the second oxide is narrower than an energy gap of the first oxide. | 2022-05-05 |
20220140091 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Provided is a semiconductor device including a semiconductor substrate; a hydrogen donor that is provide inside the semiconductor substrate in a depth direction, has a doping concentration that is higher than a doping concentration of a dopant of the semiconductor substrate, has a doping concentration distribution peak at a first position that is a predetermined distance in the depth direction of the semiconductor substrate away from one main surface of the semiconductor substrate, and has a tail of the doping concentration distribution where the doping concentration is lower than at the peak, farther on the one main surface side than where the first position is located; and a crystalline defect region having a crystalline defect density center peak at a position shallower than the first position, in the depth direction of the semiconductor substrate. | 2022-05-05 |
20220140092 | FIELD-PLATE TRENCH FET AND ASSOCIATED METHOD FOR MANUFACTURING - A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode. | 2022-05-05 |
20220140093 | FIELD-PLATE TRENCH FET AND ASSOCIATED METHOD FOR MANUFACTURING - A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode. | 2022-05-05 |
20220140094 | SEMICONDUCTOR DEVICE WITH MULTICHANNEL HETEROSTRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor heterostructure layer and a conductive structure. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. 2DHGs may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. The conductive structure includes a plurality of conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction, so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHG. | 2022-05-05 |
20220140095 | SEMICONDUCTOR DEVICE AND METHOD FOR MANURACTURING THE SAME - A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region. | 2022-05-05 |
20220140096 | TRANSISTOR DEVICES AND METHODS OF FORMING TRANSISTOR DEVICES - A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer. | 2022-05-05 |
20220140097 | Semiconductor Structures and Methods Thereof - A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material. | 2022-05-05 |
20220140098 | Nano Transistors with Source/Drain Having Side Contacts to 2-D Material - A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces. | 2022-05-05 |
20220140099 | INTEGRATED CIRCUIT INCLUDING GATE-ALL-AROUND TRANSISTOR - An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number. | 2022-05-05 |
20220140100 | SEMICONDUCTOR DEVICE INCLUDING SURFACE-TREATED SEMICONDUCTOR LAYER - Disclosed is a semiconductor device including a surface-treated semiconductor layer. The semiconductor device includes a metal layer, a semiconductor layer electrically contacting the metal layer and having a surface treated with an element having an electron affinity of about 4 eV or greater, and a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure. | 2022-05-05 |
20220140101 | Nanosheet Field-Effect Transistor Device and Method of Forming - A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material. | 2022-05-05 |
20220140102 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor structure is provided. The method comprises the following steps. A first silicon-containing gate electrode is formed on a semiconductor substrate in a first region. A second silicon-containing gate electrode is formed on the semiconductor substrate in a second region. A gate silicide element is formed on an upper surface of the first silicon-containing gate electrode. A source silicide element and a drain silicide element are formed on the semiconductor substrate on opposing sides of the second silicon-containing gate electrode respectively. The gate silicide element, the source silicide element and the drain silicide element are formed simultaneously. | 2022-05-05 |
20220140103 | METHOD FOR FORMING FINFET DEVICES WITH A FIN TOP HARDMASK - Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET. | 2022-05-05 |
20220140104 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - Provided is a ferroelectric semiconductor device including a ferroelectric layer and two or more electrode layers. The semiconductor device may include a first electrode layer and a second electrode layer which have thermal expansion coefficients less than the thermal expansion coefficient of the ferroelectric layer. The difference between the thermal expansion coefficients of the second electrode layer and the ferroelectric layer may be greater than the difference between the thermal expansion coefficients of the first electrode layer and the ferroelectric. The second electrode layer may have a thickness greater than the thickness of the first electrode layer. | 2022-05-05 |
20220140105 | FET USING TRENCH ISOLATION AS THE GATE DIELECTRIC - A semiconductor device includes a Silicon-on-Insulator (SOI) substrate including a top device layer, a buried oxide (BOX) layer, and a bottom handle portion. A filled trench is lined with a trench dielectric layer that extends to at least the BOX layer, defining an inner and an outer portion of the device layer. A field effect transistor (FET) includes an inner portion, a source region having a source contact thereto and a drain region having a drain contact thereto, each doped a first doping type. A gate region has a gate contact that is separated from the inner portion by the trench dielectric. The source and drain region are separated by a body region doped a second doping type having a body contact. | 2022-05-05 |
20220140106 | METHOD FOR MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DIODE DEVICE - A method for manufacturing a three-dimensional semiconductor diode device comprises providing a substrate comprising a silicon substrate and a first oxide layer formed on the silicon substrate; depositing a plurality of stacked structures on the substrate, each of the stacked structures comprising a dielectric layer and a conductive layer; etching the stacked structures through a photoresist layer which is patterned to form at least one trench in the stacked structures, a bottom of the trench exposing the first oxide layer; depositing a second oxide layer on the stacked structures and the trench; depositing a high-resistance layer on the second oxide layer, the high-resistance layer comprising a first polycrystalline silicon layer and a first conductive compound layer; and depositing a low-resistance layer on the high-resistance layer, the low-resistance layer comprising a second polycrystalline silicon layer and a second conductive compound layer. | 2022-05-05 |
20220140107 | FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers. | 2022-05-05 |
20220140108 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; an intermediate layer disposed on the second nitride semiconductor layer; and a conductive structure disposed on the intermediate layer, wherein a first even interface is formed between the intermediate layer and the second nitride semiconductor layer. | 2022-05-05 |
20220140109 | GATE STRUCTURE AND METHODS THEREOF - A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided. | 2022-05-05 |
20220140110 | THRESHOLD ADJUSTMENT FOR QUANTUM DOT ARRAY DEVICES WITH METAL SOURCE AND DRAIN - Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase V | 2022-05-05 |
20220140111 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method includes: forming a dummy gate dielectric layer over a channel region of a fin structure; forming a dummy gate over the dummy gate dielectric layer; removing the dummy gate and a first portion of the dummy gate dielectric layer to expose the channel region of the fin structure; removing a first nanowire of the fin structure above a second nanowire of the fin structure to remain the second nanowire of the fin structure; forming an interfacial layer surrounding the second nanowire; forming a material layer comprising dopants over the interfacial layer; and performing an annealing process to drive the dopants of the material layer into the interfacial layer, thereby forming a doped interfacial layer surrounding the second nanowire. | 2022-05-05 |
20220140112 | HIGH DENSITY 3D LAYOUT ENHANCEMENT OF MULTIPLE CMOS DEVICES - Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include forming a multilayer stack on a substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming at least one opening through the multilayer stack to uncover the substrate and forming at least two vertical channel structures within the opening that are stacked on each other. The vertical channel structures can have source, gate and drain regions being in contact with the metal layers of the multilayer stack, respectively. The method can also include removing a central portion of the vertical channel structures and filling the central portion of the vertical channel structures with a dielectric core. The dielectric core can isolate the vertical channel structures from each other and from the substrate. | 2022-05-05 |
20220140113 | METHOD FOR ADJUSTING GROOVE DEPTH AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The method for adjusting a groove depth includes: preparing masks having different thicknesses on respective top surfaces of a plurality of substrates made of silicon carbide; forming a first opening having a predetermined width and a second opening having a width wider than the first opening in each of the masks; simultaneously forming a first groove and a second groove in each of the substrates by selectively etching via the first opening and the second opening; measuring a depth ratio of the first groove to the second groove in each of the substrates; and acquiring a thickness of a mask such that the depth ratio is an intended value, from a relationship between each thickness of the masks and each depth ratio in the substrate. | 2022-05-05 |
20220140114 | METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR - Disclosed is a method of fabricating an oxide semiconductor thin-film transistor, the method including a step of forming an oxide semiconductor layer including a channel region, a source region, and a drain region on a substrate; a step of forming a gate insulating layer on the channel region; a step of forming a gate electrode on the gate insulating layer; and a step of forming a source electrode and a drain electrode on the source and drain regions, respectively, wherein the step of forming an oxide semiconductor layer includes a step of selectively plasma-treating the source and drain regions of the oxide semiconductor layer with a fluorine (F)-based gas, and the source and drain regions contain fluorine (F) at a concentration of 2×10 | 2022-05-05 |
20220140115 | Metal Gate Patterning Process and Devices Thereof - A method of fabricating a device includes providing a fin extending from a substrate, the fin having a plurality of semiconductor layers and a first distance between each adjacent semiconductor layers. The method further includes providing a dielectric fin extending from the substrate where the dielectric fin is adjacent to the plurality of semiconductor layers and there is a second distance between an end of each of the semiconductor layers and a first sidewall of the dielectric fin. The second distance is greater than the first distance. Depositing a dielectric layer over the semiconductor layers and over the first sidewall of the dielectric fin. Forming a first metal layer over the dielectric layer on the semiconductor layers and on the first sidewall of the dielectric fin, wherein portions of the first metal layer disposed on and interposing adjacent semiconductor layers are merged together. Finally removing the first metal layer. | 2022-05-05 |
20220140116 | JUNCTION FIELD EFFECT TRANSISTOR ON SILICON-ON-INSULATOR SUBSTRATE - A semiconductor device includes a junction field effect transistor (JFET) on a silicon-on-insulator (SOI) substrate. The JFET includes a gate with a first gate segment contacting the channel on a first lateral side of the channel, and a second gate segment contacting the channel on a second, opposite, lateral side of the channel. The first gate segment and the second gate segment extend deeper in the semiconductor layer than the channel. The JFET further includes a drift region contacting the channel, and may include a buried layer having the same conductivity type as the channel, extending at least partway under the drift region. | 2022-05-05 |
20220140117 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a method for manufacturing a semiconductor device, includes forming a first insulating film which covers a gate electrode, forming an island-shaped oxide semiconductor in contact with the first insulating film, forming a second insulating film which covers the oxide semiconductor, forming a source electrode in contact with the oxide semiconductor, forming a drain electrode in contact with the oxide semiconductor, forming a third insulating film which covers the source electrode and the drain electrode and forming a channel region between the source electrode and the drain electrode by supplying oxygen from the third insulating film to the oxide semiconductor via the second insulating film. | 2022-05-05 |
20220140118 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: an N | 2022-05-05 |
20220140119 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a carrier stored layer; an upper-stage active portion disposed on a first insulating film along an inner wall of an upper portion of a trench penetrating the carrier stored layer, the upper-stage active portion being upper-stage polysilicon connected to a gate electrode; and lower-stage polysilicon disposed on a second insulating film along an inner wall of a lower portion of the trench, the lower-stage polysilicon provided with a third insulating film disposed between the upper-stage active portion and the lower-stage polysilicon. The lower end of the upper-stage active portion is positioned below the lower end of the carrier stored layer. | 2022-05-05 |
20220140120 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - According to one embodiment, a semiconductor device includes first to fourth electrodes, a semiconductor member, and first and second insulating members. The semiconductor member is located between the second and first electrodes, and includes a first semiconductor region a second semiconductor region between the first semiconductor region and the first electrode, a third semiconductor region between the second semiconductor region and the first electrode, a fourth semiconductor region between the second semiconductor region and the first electrode, a fifth semiconductor region between the first semiconductor region and the second electrode, a sixth semiconductor region between the fifth semiconductor region and the second electrode, and a seventh semiconductor region between the fifth semiconductor region and the second electrode. A portion of the first insulating member is between the third electrode and the semiconductor member. A portion of the second insulating member is between the fourth electrode and the semiconductor member. | 2022-05-05 |
20220140121 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed. | 2022-05-05 |
20220140122 | GROUP III NITRIDE SEMICONDUCTOR DEVICE WITH FIRST AND SECOND CONDUCTIVE LAYERS - A semiconductor device is provided with, a group-III nitride semiconductor layered structure that includes a heterojunction, an insulating layer which has a gate opening that reaches the group-III nitride semiconductor layered structure and which is disposed on the group-III nitride semiconductor layered structure, a gate insulating film that covers the bottom and the side of the gate opening, a gate electrode defined on the gate insulating film inside the gate opening, a source electrode and a drain electrode which are disposed to be spaced apart from the gate electrode so as to sandwich the gate electrode, a first conductive layer embedded in the insulating layer between the gate electrode and the drain electrode, and a second conductive layer that is embedded in the insulating layer above the first conductive layer in a region closer to the drain electrode side than the first conductive layer. | 2022-05-05 |
20220140123 | HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH A BACK BARRIER LAYER - Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN). | 2022-05-05 |
20220140124 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. | 2022-05-05 |
20220140125 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first member, and a first insulating member. The first semiconductor layer includes Al | 2022-05-05 |
20220140126 | GROUP III-V SEMICONDUCTOR STRUCTURES HAVING CRYSTALLINE REGROWTH LAYERS AND METHODS FOR FORMING SUCH STRUCTURES - A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer. | 2022-05-05 |
20220140127 | WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS - An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact. | 2022-05-05 |
20220140128 | WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS - An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact. | 2022-05-05 |
20220140129 | INTEGRATED SCHOTTKY DIODE WITH GUARD RING - Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact. | 2022-05-05 |
20220140130 | VERTICAL FIELD EFFECT TRANSISTOR DEVICE AND METHOD OF FABRICATION - A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p− type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n− type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region. | 2022-05-05 |
20220140131 | TRANSISTOR WITH PHASE TRANSITION MATERIAL REGION BETWEEN CHANNEL REGION AND EACH SOURCE/DRAIN REGION - A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (I | 2022-05-05 |
20220140132 | PASSIVATION STRUCTURES FOR SEMICONDUCTOR DEVICES - Semiconductor devices, and more particularly passivation structures for semiconductor devices are disclosed. A semiconductor device may include an active region, an edge termination region that is arranged along a perimeter of the active region, and a passivation structure that may form a die seal along the edge termination region. The passivation structure may include a number of passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. A patterned layer may be at least partially embedded in the passivation structure in an arrangement that forms the corresponding pattern in overlying portions of the passivation structure. | 2022-05-05 |
20220140133 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a conductive member, and an insulating member. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first and second partial regions. The second semiconductor region is between the first partial region and the third semiconductor region. The conductive member is located between the second partial region and the third electrode. The conductive member includes a first end portion and a first other-end portion. The first end portion is between the first other-end portion and the third electrode. The conductive member includes first to third portions. The second portion is between the third portion and the third electrode. The first portion is between the second portion and the third electrode. The first portion includes the first end portion. The second portion contacts the first and third portions. | 2022-05-05 |