| 18th week of 2022 patent applcation highlights part 72 |
| Patent application number | Title | Published |
|---|
| 20220139834 | INTERCONNECT STRUCTURE - An interconnect structure is provided. The interconnect structure includes a first via in a first dielectric layer, a first metal line on and electrically connected to the first via, a first etching stop layer over the first dielectric layer, a second metal line over the first etching stop layer, and an encapsulating layer. The encapsulating layer includes a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line. The interconnect structure also includes a second dielectric layer nested within the encapsulating layer. | 2022-05-05 |
| 20220139835 | INTEGRATED CIRCUIT WITH BURIED POWER RAIL AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices. | 2022-05-05 |
| 20220139836 | SEMICONDUCTOR MEMORY DEVICE INCLUDING WIRING CONTACT PLUGS - A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material. | 2022-05-05 |
| 20220139837 | CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY - Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers. | 2022-05-05 |
| 20220139838 | PAD STRUCTURE FOR ENHANCED BONDABILITY - Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress. | 2022-05-05 |
| 20220139839 | Integrated Circuit Package and Method - In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias. | 2022-05-05 |
| 20220139840 | THROUGH-SILICON VIA (TSV) KEY FOR OVERLAY MEASUREMENT, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING TSV KEY - A through-silicon via (TSV) key for overlay measurement includes: a first TSV extending through at least a portion of a substrate in a first direction that is perpendicular to a top surface of the substrate; and at least one ring pattern, which is apart from and surrounds the first TSV in a second direction that is parallel to the top surface of the substrate, the at least one ring pattern being arranged in a layer that is lower than a top surface of the first TSV in the first direction, wherein an inner measurement point corresponds to the first TSV, an outer measurement point corresponds to the at least one ring pattern, and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV. | 2022-05-05 |
| 20220139841 | SEMICONDUCTOR WAFER AND METHOD FOR FABRICATING THE SAME - A semiconductor wafer includes a wafer body including an active layer having a first crystal orientation and having first and second surfaces opposing each other, and a support layer having a second crystal orientation different from the first crystal orientation and having third and fourth surfaces opposing each other, a bevel portion that extends along an outer periphery of the wafer body to connect the first surface to the fourth surface, and a notch portion formed at a predetermined depth in a direction from the outer periphery of the wafer body toward a center portion of the wafer body. The bevel portion includes a first beveled surface connected to the first surface and a second beveled surface connected to the fourth surface. The first beveled surface has a width in a radial direction of the wafer body that is 300 μm or less. | 2022-05-05 |
| 20220139842 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided, including several first patterns located in a photoresist layer with a thickness greater than 1.2 μm and arranged in a first direction, and several second patterns arranged in a second direction. The first direction and the second direction have an included angle. The first patterns have a first arrangement length in the first direction. The second patterns have a second arrangement length in the second direction. An area sum of the first patterns and the second patterns is less than ½ of a product of the first arrangement length and the second arrangement length. | 2022-05-05 |
| 20220139843 | RESILIENT ELECTRICAL CONNECTORS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING STRUCTURES IN INTEGRATED CIRCUIT ASSEMBLIES - An integrated circuit assembly may be formed having at least one integrated circuit device electrically attached to an electronic substrate. The integrated circuit assembly may further include at least one electromagnetic interference structure attached to the electronic substrate adjacent to the at least one integrated circuit device. The at least one electromagnetic interference structure may be electrically attached to the electronic substrate with at least one resilient connector extending therebetween. In one embodiment, the at least one electromagnetic interference structure may be grounded to the electronic substrate. | 2022-05-05 |
| 20220139844 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first molded resin containing first insulating fillers having particle sizes smaller than the opening size of a wire mesh is formed inside the wire mesh to seal a semiconductor chip, bonding wires, and bond pads, and a second molded resin containing second insulating fillers having particle sizes larger than the opening size of the wire mesh is formed outside the wire mesh to seal the semiconductor ship, the bonding wires, and the bond pads via the first molded resin and the wire mesh. This allows for reducing warpage during solder mounting and for improving productivity. | 2022-05-05 |
| 20220139845 | SEMICONDUCTOR PACKAGE WITH ELECTROMAGNETIC SHIELD - The present disclosure is directed to a semiconductor package that include a non-conductive encapsulation layer encapsulation an integrated circuit chip, and a conductive encapsulation layer over the non-conductive encapsulation layer. A lead is exposed from the non-conductive encapsulation layer and contacts the conductive encapsulation layer. The conductive encapsulation layer and the lead provide EMI shielding for the integrated circuit chip. | 2022-05-05 |
| 20220139846 | REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE - A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein. | 2022-05-05 |
| 20220139847 | LEADLESS LEADFRAME AND SEMICONDUCTOR DEVICE PACKAGE THEREFROM - A semiconductor device package includes a leadless leadframe, and a plurality of terminal pads extending to a periphery of the leadframe. At least two of the plurality of terminal pads are interior extending terminal pads that include an interior portion having a shape including at least one curved portion and an exterior portion that extends to the periphery of the leadframe. An integrated circuit (IC) die having at least a semiconductor surface includes circuitry configured for at least one function having nodes connected to bond pads on the leadframe. There is a bonding arrangement between the plurality of terminal pads and the bond pads. A mold compound is for encapsulation of the semiconductor device package. | 2022-05-05 |
| 20220139848 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die disposed over the substrate, and a frame disposed over the substrate. The frame is adjacent to the semiconductor die, and an upper surface of the frame is lower than the upper surface of the semiconductor die. IN addition, a passive component is disposed on the substrate and located between the frame and the semiconductor die. | 2022-05-05 |
| 20220139849 | WAFER-LEVEL BONDING OF OBSTRUCTIVE ELEMENTS - A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation. | 2022-05-05 |
| 20220139850 | Embedded Resistor-Capacitor Film for Fan Out Wafer Level Packaging - A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected. | 2022-05-05 |
| 20220139851 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure and method of manufacturing a package structure are provided. The package structure comprises two semiconductor structures and two bonding layers sandwiched between both semiconductor structures. Each bonding layer has a plurality of bonding pads separated by an isolation layer. Each bonding pad has a bonding surface including a bonding region and at least one buffer region. The bonding regions in both bonding layers bond to each other. The buffer region of one semiconductor structure bonds to the isolation layer of the other semiconductor structure. A ratio of a surface area of the buffer region to that of the bonding region in each metal pad is from about | 2022-05-05 |
| 20220139852 | TRANSISTOR PACKAGES WITH IMPROVED DIE ATTACH - A transistor device structure may include a submount, a transistor device on the carrier submount, and a metal bonding layer between the submount and the transistor die, the metal bonding stack providing mechanical attachment of the transistor die to the submount. The metal bonding stack may include gold, tin and nickel. A weight percentage of a combination of nickel and tin in the metal bonding layer is greater than 50 percent and a weight percentage of gold in the metal bonding layer is less than 25 percent. | 2022-05-05 |
| 20220139853 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Even in a case where a pad becomes smaller, solder connection strength is improved. A semiconductor device includes a pad, a diffusion layer, and a melting layer. The pad included by the semiconductor device includes a concave portion on a surface at which solder connection is to be performed. The diffusion layer included by the semiconductor device is disposed at the concave portion and constituted with a metal which remains on the surface of the pad while diffusing into solder upon the solder connection. The melting layer included by the semiconductor device is disposed adjacent to the diffusion layer and constituted with a metal which diffuses and melts into the solder upon the solder connection. | 2022-05-05 |
| 20220139854 | BONDING STRUCTURE, PACKAGE STRUCTURE, AND METHOD FOR MANUFACTURING PACKAGE STRUCTURE - A bonding structure, a package structure, and a method for manufacturing a package structure are provided. The package structure includes a first substrate, a first passivation layer, a first conductive layer, and a first conductive bonding structure. The first passivation layer is disposed on the first substrate and has an upper surface. The first passivation layer and the first substrate define a first cavity. The first conductive layer is disposed in the first cavity and has an upper surface. A portion of the upper surface of the first conductive layer is below the upper surface of the first passivation layer. The first conductive bonding structure is disposed on the first conductive layer. | 2022-05-05 |
| 20220139855 | SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME - A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad. | 2022-05-05 |
| 20220139856 | SELECTIVE MICRO DEVICE TRANSFER TO RECEIVER SUBSTRATE - A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques. | 2022-05-05 |
| 20220139857 | SELECTIVE MICRO DEVICE TRANSFER TO RECEIVER SUBSTRATE - A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques. | 2022-05-05 |
| 20220139858 | PILLAR BUMP WITH NOBLE METAL SEED LAYER FOR ADVANCED HETEROGENEOUS INTEGRATION - A pillar bump structure, and a method for forming the same includes forming, on a semiconductor substrate, a blanket liner followed by a seed layer including a noble metal. A first photoresist layer is formed directly above the seed layer followed by the formation of a first plurality of openings within the photoresist layer. A first conductive material is deposited within each of the first plurality of openings to form first pillar bumps. The first photoresist layer is removed from the semiconductor structure followed by removal of portions of the seed layer extending outward from the first pillar bumps, a portion of the seed layer remains underneath the first pillar bumps. | 2022-05-05 |
| 20220139859 | CHIP STRUCTURE, PACKAGING STRUCTURE AND MANUFACTURING METHOD FOR CHIP STRUCTURE - The present disclosure provides a chip structure, a packaging structure and a manufacturing method for the chip structure. The chip structure includes at least one chip body, each of which includes at least one radio frequency front-end device; the chip structure further includes a redistribution layer stacked on the chip body and at least one pin on the redistribution layer; each radio frequency front-end device corresponds to one pin, which is electrically connected to the radio frequency front-end device through an electrical connector extending through the redistribution layer; an extending direction of the radio frequency front-end device is consistent with an extending direction of the pin corresponding to the radio frequency front-end device; a surface of the pin distal to the redistribution layer is a first plane. In the present disclosure, with the first plane, the chip may be directly and electrically connected to a flexible circuit board. | 2022-05-05 |
| 20220139860 | Multi-Bump Connection to Interconnect Structure and Manufacturing Method Thereof - A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad. | 2022-05-05 |
| 20220139861 | SEMICONDUCTOR DEVICE - A semiconductor device includes an electric conductor, a semiconductor element, and a bonding layer. The electric conductor has a main surface and a rear surface opposite to the main surface in a thickness direction. The semiconductor element includes a main body and electrodes. The main body has a side facing the main surface of the conductor, and the electrodes each protrude toward the main surface from the side of the main body to be electrically connected to the main surface. The bonding layer is held in contact with the main surface and the electrodes. Each electrode includes a base portion in contact with the main body, and a columnar portion protruding toward the main surface from the base portion to be held in contact with the bonding layer, which is a sintered body of a metal powder. | 2022-05-05 |
| 20220139862 | RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME - The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die. | 2022-05-05 |
| 20220139863 | INTEGRATED CIRCUIT CHIP HAVING BS-PDN STRUCTURE - An integrated circuit chip includes a substrate having an active surface and a back surface opposite to the active surface; a front-end-of-line (FEOL) structure disposed on the active surface of the substrate; a first back-end-of-line (BEOL) structure disposed on the FEOL structure; an intermediate connection layer disposed under the back surface of the substrate, the intermediate connection layer including a charge storage, and metal posts disposed around the charge storage; and a re-distribution structure layer disposed under the intermediate connection layer. | 2022-05-05 |
| 20220139864 | BONDING FILM, TAPE FOR WAFER PROCESSING, METHOD FOR PRODUCING BONDED BODY, AND BONDED BODY AND PASTED BODY - A bonding film for bonding a semiconductor element and a substrate. The bonding film has an electroconductive bonding layer formed by molding an electroconductive paste including metal fine particles (P) into a film form, and a tack layer having tackiness and laminated on the electroconductive bonding layer. The tack layer includes 0.1% to 1.0% by mass of metal fine particles (M) with respect to the metal fine particles (P) in the electroconductive bonding layer, and the metal fine particles (M) have a melting point of 250° C. or lower. | 2022-05-05 |
| 20220139865 | BONDED BODY AND METHOD FOR MANUFACTURING SAME - A bonded body is provided including: a bonding layer containing Cu; and a semiconductor element bonded to the bonding layer. The bonding layer includes an extending portion laterally extending from a peripheral edge of the semiconductor element. In a cross-sectional view in a thickness direction, the extending portion rises from a peripheral edge of a bottom of the semiconductor element or from the vicinity of the peripheral edge of the bottom of the semiconductor element, and includes a side wall substantially spaced apart from a side of the semiconductor element. Preferably, the extending portion does not include any portion where the side wall and the side of the semiconductor element are in contact with each other. A method for manufacturing a bonded body is also provided. | 2022-05-05 |
| 20220139866 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR MANUFACTURING APPARATUS - A method for manufacturing a semiconductor package structure and a semiconductor manufacturing apparatus are provided. The method includes: (a) providing a package body disposed on a chuck, wherein the package body includes at least one semiconductor element encapsulated in an encapsulant; and (b) sucking the package body through the chuck to create a plurality of negative pressures on a bottom surface of the package body sequentially from an inner portion to an outer portion of the package body. | 2022-05-05 |
| 20220139867 | DIRECT BONDING METHODS AND STRUCTURES - A bonding method can include polishing a first bonding layer of a first element for direct bonding, the first bonding layer comprises a first conductive pad and a first non-conductive bonding region. After the polishing, a last chemical treatment can be performed on the polished first bonding layer. After performing the last chemical treatment, the first bonding layer of the first element can be directly bonded to a second bonding layer of a second element without an intervening adhesive, including directly bonding the first conductive pad to a second conductive pad of the second bonding layer and directly bonding the first non-conductive bonding region to a second nonconductive bonding region of the second bonding layer. No treatment or rinse is performed on the first bonding layer between performing the last chemical treatment and directly bonding. | 2022-05-05 |
| 20220139868 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Electrical connection between electrodes provided respectively at facing positions in joint surfaces of substrates to be joined by chip lamination technology is conducted more securely. A method of manufacturing a semiconductor device includes: a first step of embedding electrodes in insulating layers exposed to the joint surfaces of a first substrate and a second substrate; a second step of subjecting the joint surfaces of the first substrate and the second substrate to chemical mechanical polishing, to form the electrodes into recesses recessed as compared to the insulating layers; a third step of laminating insulating films of a uniform thickness over the entire joint surfaces; a fourth step of forming an opening by etching in at least part of the insulating films covering the electrodes of the first substrate and the second substrate; a fifth step of causing the corresponding electrodes to face each other and joining the joint surfaces of the first substrate and the second substrate to each other; and a sixth step of heating the first substrate and the second substrate joined to each other, causing the electrode material to expand and project through the openings, and joining the corresponding electrodes to each other. | 2022-05-05 |
| 20220139869 | DIRECT BONDING METHODS AND STRUCTURES - A bonding method can include activating a first bonding layer of a first element for direct bonding to a second bonding layer of a second element. The bonding method can include, after the activating, providing a protective layer over the activated first bonding layer of the first element. | 2022-05-05 |
| 20220139870 | METHOD OF MANUFACTURING A BONDED SUBSTRATE STACK - A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; and providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal. The hybrid interface layers are surface-activated by particle bombardment which is configured to remove atoms of the first hybrid interface layer and atoms of the second hybrid interface layer to generate dangling bonds on the hybrid interface layers. The surface-activated hybrid interface layers are brought into contact, such that the dangling bonds of the first hybrid interface layer and the dangling bonds of the second hybrid interface layer bond together to form first insulator to second insulator bonds and first metal to second metal bonds. | 2022-05-05 |
| 20220139871 | LIGHT-EMITTING ELEMENT INK AND METHOD OF MANUFACTURING DISPLAY DEVICE USING THE LIGHT-EMITTING ELEMENT INK - A light-emitting element ink and a method of manufacturing a display device using the light-emitting element ink are provided. The light-emitting element ink comprises a solvent, a dispersant mixed with the solvent, and a plurality of light-emitting elements dispersed in the solvent, each of the light-emitting elements including a plurality of semiconductor layers and an insulating film surrounding parts of outer surfaces of the semiconductor layers, wherein the dispersant includes an aqueous dispersant or an organic dispersant, if the dispersant is the aqueous dispersant, the solvent has a hydrogen bonding parameter, of Hansen's solubility parameters, of less than 7, and if the dispersant is the organic dispersant, the solvent has a hydrogen bonding parameter, of Hansen's solubility parameters, of 7 or greater. | 2022-05-05 |
| 20220139872 | METHOD AND SYSTEM FOR MANUFACTURING A SEMICONDUCTOR PACKAGE STRUCTURE - A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d). | 2022-05-05 |
| 20220139873 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a lower semiconductor chip having a lower semiconductor substrate and upper pads on a top surface of the lower semiconductor substrate, an upper semiconductor chip stacked on the lower semiconductor chip, the upper semiconductor chip including an upper semiconductor substrate and solder bumps on a bottom surface of the upper semiconductor substrate, and a curing layer between the lower semiconductor chip and the upper semiconductor chip, the curing layer including a first curing layer adjacent to the upper semiconductor chip, the first curing layer including a first photo-curing agent, and a second curing layer between the first curing layer and the top surface of the lower semiconductor substrate, the second curing layer including a first thermo-curing agent. | 2022-05-05 |
| 20220139874 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first semiconductor chip including a first semiconductor layer having a first forward surface having a first integrated circuit thereon and a first rear surface and a plurality of first through vias electrically connected to the first integrated circuit and including at least first and second groups of first through vias, a second semiconductor chip including a second integrated circuit electrically connected to the first group of first through vias, and a third semiconductor chip including third through vias electrically connected to the second group of first through vias, wherein the first group of first through vias transfer input/output signals of the first integrated circuit, and the second group of first through vias transfer power to the first integrated circuit, may be provided. | 2022-05-05 |
| 20220139875 | SEMICONDUCTOR PACKAGE - Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface. | 2022-05-05 |
| 20220139876 | Asic Package With Photonics And Vertical Power Delivery - The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets. | 2022-05-05 |
| 20220139877 | ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE - The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction. | 2022-05-05 |
| 20220139878 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A SHARED WORD LINE DRIVER ACROSS DIFFERENT TIERS AND METHODS FOR MAKING THE SAME - A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line. | 2022-05-05 |
| 20220139879 | SEMICONDUCTOR PACKAGE - Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack. | 2022-05-05 |
| 20220139880 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power. | 2022-05-05 |
| 20220139881 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package may include a package substrate, semiconductor chips, signal bumps, and first and second heat dissipation bumps. The semiconductor chips may be stacked on an upper surface of the package substrate, have first and second regions having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bumps may be arranged between the semiconductor chips. The first heat dissipation bumps may be arranged between the semiconductor chips in the first region by a first pitch. The second heat dissipation bumps may be arranged between the semiconductor chips in the second region by a second pitch narrower than the first pitch. Heat generated from the second region of the semiconductor chips may be dissipated through the second heat dissipation bumps, which may be relatively closely arranged with each other. | 2022-05-05 |
| 20220139882 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure. | 2022-05-05 |
| 20220139883 | Network On Layer Enabled Architectures - The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer. | 2022-05-05 |
| 20220139884 | HIGH CONNECTIVITY DEVICE STACKING - The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like. | 2022-05-05 |
| 20220139885 | Integrating Passive Devices in Package Structures - A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device. | 2022-05-05 |
| 20220139886 | LIGHT-EMITTING PACKAGE AND METHOD OF MANUFACTURING THE SAME - A light-emitting package includes an encapsulating member, a plurality of light-emitting components disposed in the encapsulating member, a plurality of first electrode pads, a plurality of second electrode pads, and a plurality of conductive connection structures. The encapsulating member has a first surface and a second surface opposite to each other. Each light-emitting component has a light-emitting surface exposed on the first surface. Both the first electrode pads and the second electrode pads are exposed on the second surface. A first bonding surface of each first electrode pad and a second bonding surface of each second electrode pad are both flush with the second surface. The light-emitting components disposed on the first electrode pads are electrically connected to the first electrode pads. The conductive connection structures passing through the encapsulating member are electrically connected to the light-emitting components and the second electrode pads. | 2022-05-05 |
| 20220139887 | MICRO-LIGHT-EMITTING-DIODE ARRAY AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a micro-light-emitting diode (LED) array includes: providing a first substrate including a plurality of circular grooves formed on a first surface thereof; supplying a plurality of micro-LEDs onto the first surface of the first substrate; and aligning the plurality of micro-LEDs with the plurality of circular grooves, wherein at least two electrodes are formed on a second surface of each of the plurality of micro-LEDs to be apart from each other, and the at least two electrodes include a first electrode formed to be relatively close to a center of the second surface and at least one second electrode formed at an edge of the second surface. | 2022-05-05 |
| 20220139888 | DISPLAY DEVICE - According to an aspect of the present disclosure, the display device includes a stretchable lower substrate and a plurality of first substrates disposed on the lower substrate and including a first pixel and a second pixel. The display device also includes a plurality of second substrates configured to couple first substrates adjacent to each other among the plurality of first substrates. The display device further includes a plurality of connection lines disposed on the plurality of second substrates and configured to couple the first pixel and the second pixel. The plurality of connection lines includes a plurality of first connection lines extended in a first direction, a plurality of second connection lines extended in a second direction and a plurality of third connection lines extended in a third direction. Thus, the display device may be improved in resolution and may be uniformly stretched in all directions. | 2022-05-05 |
| 20220139889 | DISPLAY APPARATUS - A display apparatus includes a substrate in which a plurality of pads are disposed, a plurality of micro LEDs, wherein each micro LED from among the plurality of micro LEDs is electrically connected to a respective group of pads from among the plurality of pads and mounted on the substrate, and a plurality of protrusion members, wherein each protrusion member from among the plurality of protrusion members protrudes from the substrate and is formed adjacent to a respective pad from among the plurality of pads. | 2022-05-05 |
| 20220139890 | LIGHT-EMITTING DIODE PACKAGING MODULE - A light-emitting diode (LED) packaging module includes LED chips, a wiring layer, and an encapsulant component. Each of the LED chips includes a chip first surface, a chip second surface, a chip side surface, and an electrode unit. The wiring layer is disposed on the chip second surfaces of the LED chips, and contacts and is electrically connected to the electrode units. The encapsulant component includes a first encapsulating layer that covers the chip side surface, and a second encapsulating layer that covers the wiring layer. The LED chip has a thickness TA, the first encapsulating layer has a thickness T | 2022-05-05 |
| 20220139891 | LIGHT EMITTING DEVICE WITH LED STACK FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME - A light emitting device including a first LED sub-unit, a second LED sub-unit disposed under the first LED sub-unit, a third LED sub-unit disposed under the second LED sub-unit, a first ohmic electrode interposed between the first LED sub-unit and the second LED sub-unit, and in ohmic contact with the first LED sub-unit, a second ohmic electrode interposed between the second LED sub-unit and the third LED sub-unit, and in ohmic contact with the second LED sub-unit, a third ohmic electrode interposed between the second ohmic electrode and the third LED sub-unit, and in ohmic contact the third LED sub-unit, a plurality of electrode pads disposed on the first LED sub-unit, in which at least one of the first ohmic electrode, the second ohmic electrode, and the third ohmic electrode has a patterned structure. | 2022-05-05 |
| 20220139892 | TILED DISPLAY DEVICE - A tiled display device including a first display device; a second display device located at one side of the first display device in a first direction; a first chassis disposed under the first display device to support the first display device; and a second chassis disposed under the second display device to support the second display device. An end portion of the first chassis and an end portion of the second chassis are directly connected to each other, and an end portion of the first display device and an end portion of the second display device come into direct contact with each other. | 2022-05-05 |
| 20220139893 | LIGHT EMITTING DEVICE AND LIGHT EMITTING MODULE - A light emitting device including a plurality of element structures each including a submount, a light emitting element, and a light transmissive member, in this order. The light emitting device further includes a first cover member holding the element structures by covering lateral faces of each of the element structures. | 2022-05-05 |
| 20220139894 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a waveguide. The photonic integrated circuit includes an optical coupler. The electronic integrated circuit is disposed aside the photonic integrated circuit. The waveguide is optically coupled to the optical coupler, wherein the waveguide is disposed at an edge of the photonic integrated circuit and protrudes from the edge of the photonic integrated circuit. | 2022-05-05 |
| 20220139895 | MEMORY DEVICE HAVING WAFER-TO-WAFER BONDING STRUCTURE - A memory device includes a cell wafer having a first pad on one surface thereof; and a peripheral wafer bonded to the one surface of the cell wafer, and having a second pad coupled to the first pad. The cell wafer includes a memory cell array; first and second bit lines coupled to the memory cell array; and a bit line selection circuit configured to couple one of the first and second bit lines to the first pad. The peripheral wafer includes a page buffer low-voltage circuit including a first page buffer low-voltage unit corresponding to the first bit line and a second page buffer low-voltage unit corresponding to the second bit line; and a page buffer high-voltage circuit configured to couple one of the first and second page buffer low-voltage units to the second pad. | 2022-05-05 |
| 20220139896 | DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE - The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network. | 2022-05-05 |
| 20220139897 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner. | 2022-05-05 |
| 20220139898 | METHODS OF MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES - A method of manufacturing a three-dimensional integrated circuit structure includes the following steps. A first die is provided. A plurality of second dies are bonded onto the first die, wherein a gap is formed between the plurality of second dies. A dielectric material is filled in the gap by performing at least one cycle of: by a first deposition process, forming a first dielectric layer having a smaller thickness at a top portion of a sidewall of the gap than a bottom portion of the sidewall of the gap; and by a second deposition process, forming a second dielectric layer on the first dielectric layer over the gap. A portion of the dielectric material is removed to form a dielectric structure between the plurality of second dies, wherein a top surface of the dielectric structure is substantially coplanar with tops surfaces of the plurality of second dies. | 2022-05-05 |
| 20220139899 | INTEGRATED CIRCUIT INCLUDING A CAPACITIVE STRUCTURE OF THE METAL-INSULATOR-METAL TYPE AND CORRESPONDING MANUFACTURING METHOD - An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer. | 2022-05-05 |
| 20220139900 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device comprising a substrate that includes a cell region and a dummy region, a first metal layer on the substrate and including a dummy line on the dummy region, a power delivery network on a bottom surface of the substrate, and a first through via that penetrates the substrate and extends from the power delivery network toward the dummy line. The first through via is electrically connected to the dummy line. The power delivery network includes a plurality of lower lines and a pad line below the lower lines. The pad line is electrically connected through the lower lines to the first through via. | 2022-05-05 |
| 20220139901 | SEMICONDUCTOR DEVICES - A semiconductor device includes standard cells in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, and filler cells between ones of the standard cells. Each of the standard cells includes an active region, a gate structure that intersects the active region, source/drain regions on the active region on both sides of the gate structure, and interconnection lines. Each of the filler cells includes a filler active region and a filler gate structure that intersects the filler active region. The standard cells include first to third standard cells in first to third rows sequentially in the second direction, respectively. First interconnection lines are arranged with a first pitch, second interconnection lines are arranged with a second pitch, and third interconnection lines are arranged with a third pitch different from the first and second pitches. | 2022-05-05 |
| 20220139902 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a gate dielectric layer and a conductive layer that are stacked, and the gate dielectric layer is located between the substrate and the conductive layer. The substrate includes a semiconductor substrate and an insulating substrate which are arranged on the same layer. The conductive layer includes: a gate conductor layer, a projection of which on the substrate covers the semiconductor substrate, and an external connecting layer, a projection of which on the substrate covers the insulating substrate. A groove is formed on a bottom surface, towards the substrate, of the external connecting layer and the groove is filled with an insulator. | 2022-05-05 |
| 20220139903 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature. | 2022-05-05 |
| 20220139904 | INTEGRATED CIRCUIT DEVICE WITH PROTECTIVE ANTENNA DIODES INTEGRATED THEREIN - An integrated circuit device includes a semiconductor substrate having components of a peripheral circuit structure formed in and on a surface of the semiconductor substrate. The peripheral circuit structure comprising a plurality of protective antenna diodes therein. A memory cell array structure is provided on at least a portion of the peripheral circuit structure. A charge accumulating conductive plate is provided, which extends between the peripheral circuit structure and the memory cell array structure. The conductive plate is electrically connected to current carrying terminals of the antenna diodes within the peripheral circuit structure. The conductive plate may have a generally rectangular planar shape with four corners, and the antenna diodes may be arranged into four groups, which extend between respective corners of the conductive plate and the semiconductor substrate. | 2022-05-05 |
| 20220139905 | Semiconductor Device - A semiconductor device has an N-type substrate, a through conductor penetrating the N-type substrate, a protection target circuit provided on the N-type substrate, and an ESD protection circuit provided on the N-type substrate. The protection target circuit and the ESD protection circuit are connected together to the through conductor. | 2022-05-05 |
| 20220139906 | CONCEPT FOR SILICON FOR CARBIDE POWER DEVICES - A modular concept for Silicon Carbide power devices is disclosed where a low voltage module (LVM) is designed separately from a high voltage module (HVM). The LVM having a repeating structure in at least a first direction, the repeating structure repeats with a regular distance in at least the first direction, the HVM comprising a buried grid ( | 2022-05-05 |
| 20220139907 | SEMICONDUCTOR DEVICE WITH LOW NOISE TRANSISTOR AND LOW TEMPERATURE COEFFICIENT RESISTOR - A semiconductor device includes a resistor having a resistor body including polysilicon, with fluorine in the polysilicon. The resistor body has a laterally alternating distribution of silicon grain sizes. The semiconductor device further includes an MOS transistor having a gate including polysilicon with fluorine. The fluorine in the gate has a higher average concentration than the fluorine in the resistor body. The semiconductor device may be formed by forming a gate/resistor layer including polysilicon. A fluorine implant mask is formed over the gate/resistor layer, exposing the gate/resistor layer in an area for the gate and over implant segments in an area for the resistor body. The implant segments do not cover the entire area for the resistor body. Fluorine is implanted into the gate/resistor layer where exposed by the fluorine implant mask. The gate/resistor layer is patterned to form the gate and the resistor body. | 2022-05-05 |
| 20220139908 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region. | 2022-05-05 |
| 20220139909 | LONG CHANNEL AND SHORT CHANNEL VERTICAL FET CO-INTEGRATION FOR VERTICAL FET VTFET - A semiconductor including a short channel device including a vertical FET (Field-Effect Transistor), and a long channel device comprising a second vertical FET integrated with the short channel device. The long channel device including a plurality of short channel devices. | 2022-05-05 |
| 20220139910 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact. | 2022-05-05 |
| 20220139911 | USE OF A PLACEHOLDER FOR BACKSIDE CONTACT FORMATION FOR TRANSISTOR ARRANGEMENTS - Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement. | 2022-05-05 |
| 20220139912 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin. | 2022-05-05 |
| 20220139913 | ISOLATION IN INTEGRATED CIRCUIT DEVICES - Disclosed herein are techniques for providing isolation in integrated circuit (IC) devices, as well as IC devices and computing systems that utilize such techniques. In some embodiments, a protective layer may be disposed on a structure in an IC device, prior to deposition of additional dielectric material, and the resulting assembly may be treated to form a dielectric layer around the structure. | 2022-05-05 |
| 20220139914 | Semiconductor Device with Gate Isolation Structure and Method for Forming the Same - Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece including a substrate, an isolation feature over the substrate, a first fin-shaped structure protruding through the isolation feature, and a second fin-shaped structure protruding through the isolation feature, forming a dielectric fin between the first and second fin-shaped structures, and forming first and second gate structures over the first and second fin-shaped structures, respectively. The exemplary manufacturing method also includes etching the isolation feature from the backside of the workpiece to from a trench exposing the dielectric fin, etching the dielectric fin from the backside of the workpiece to form an extended trench, and depositing a seal layer over the extended trench. The seal layer caps an air gap between the first and second gate structures. | 2022-05-05 |
| 20220139915 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - The method includes: providing a substrate, the substrate including a first region and a second region; forming an insulating layer on the substrate; etching a portion of the insulating layer in the second region, the insulating layer in the first region being configured as a first insulating layer, a remaining portion of the insulating layer in the second region being configured as a second insulating layer; forming a first barrier layer covering the first insulating layer and a second barrier layer covering the second insulating layer; etching the first barrier layer, a portion of the second barrier layer and the first insulating layer to form a through hole in the first insulating layer, and to form a hole segment in the second barrier layer; and removing the first barrier layer and the second barrier layer. | 2022-05-05 |
| 20220139916 | SEMICONDUCTOR DEVICE - The present disclosure technology provides memory cells and a semiconductor device including the same. According to the present technology, a semiconductor device comprises a plurality of active layers vertically stacked along a first direction over a substrate and horizontally extending along a second direction crossing the first direction; a plurality of bit lines coupled to respective first sides of the active layers and horizontally extending in a third direction crossing the first direction and the second direction; a plurality of capacitors coupled to respective second sides of the active layers; a word line vertically extending through the active layers along the first direction; an upper-level interconnection coupled to an upper end of the word line; and a lower-level interconnection coupled to a lower end of the word line. | 2022-05-05 |
| 20220139917 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE MEMORY DEVICE - A novel memory device is provided. The memory device includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor; a first conductor and a second conductor provided over a top surface of the first oxide semiconductor; a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor; a first insulator provided in contact with the second oxide semiconductor; and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor; a second insulator over the second conductor; and a fourth conductor over the second insulator. The first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor. | 2022-05-05 |
| 20220139918 | Novel Three-Dimensional DRAM Structures - Novel three-dimensional DRAM structures are disclosed, together with methods of making the same. Each DRAM cell comprises a vertical transistor and a storage capacitor stacked vertically. Storage capacitors are arranged in a rectangular pattern in the array of DRAM cells. This arrangement improves the area efficiency of storage capacitors over honeycomb type. A first embodiment of the present disclosure uses cup-shaped storage capacitors. The exterior of the cup as well as the interior may contribute to the capacitance. In a second embodiment, a single capacitor pillar forms the internal electrode of each storage capacitor. A third embodiment employs double-pillar storage capacitors. Common to all embodiments are options to dispose contact plugs between vertical transistors and storage capacitors, dispose an etch-stop layer over the gate of vertical transistors, dispose one or more mesh layers for storage capacitors, and widen semiconductor pillars within available space in bit-line direction. | 2022-05-05 |
| 20220139919 | ARRAY STRUCTURE OF CAPACITORS, METHOD FOR MANUFACTURING ARRAY STRUCTURE OF CAPACITORS, AND DYNAMIC RANDOM ACCESS MEMORY - An array structure of capacitors are provided. The array structure of capacitors includes a substrate and a first connection pad, a second connection pad, a first capacitive structure and a second capacitive structure that are disposed on the substrate. The first capacitive structure is disposed outside the second capacitive structure and adjacent to an edge of the substrate. The bottom surface of the first capacitive structure towards the substrate and the top surface of the first connection pad are disposed at intervals. | 2022-05-05 |
| 20220139920 | Methods of Making Novel Three-Dimensional DRAM - Novel three-dimensional DRAM structures are disclosed, together with methods of making the same. Each DRAM cell comprises a vertical transistor and a storage capacitor stacked vertically. Storage capacitors are arranged in a rectangular pattern in the array of DRAM cells. This arrangement improves the area efficiency of storage capacitors over honeycomb type. A first embodiment of the present disclosure uses cup-shaped storage capacitors. The exterior of the cup as well as the interior may contribute to the capacitance. In a second embodiment, a single capacitor pillar forms the internal electrode of each storage capacitor. A third embodiment employs double-pillar storage capacitors. Common to all embodiments are options to dispose contact plugs between vertical transistors and storage capacitors, dispose an etch-stop layer over the gate of vertical transistors, dispose one or more mesh layers for storage capacitors, and widen semiconductor pillars within available space in bit-line direction. | 2022-05-05 |
| 20220139921 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate. | 2022-05-05 |
| 20220139922 | MEMORY DEVICE AND FABRICATION METHOD THEREOF - A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided. | 2022-05-05 |
| 20220139923 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - The present application relates to the technical field of manufacturing semiconductor, and in particular to a method of manufacturing semiconductor structure and a semiconductor structure. The method of manufacturing semiconductor structure includes: forming a conductive layer on a substrate, and removing part of the conductive layer to form a contact structure composed of a plurality of contact pads; where each of the contact pads is electrically connected to a transistor structure on the substrate; and, after the contact pads are formed, removing residual core on top ends of the contact pads away from the substrate by dry etching. | 2022-05-05 |
| 20220139924 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure and the semiconductor structure are provided. The method for forming the semiconductor structure includes: providing a substrate, wherein a separate bit line structure is formed on the substrate; forming a first sacrificial layer on the side wall of the bit line structure; forming a first dielectric layer filling gap between the bit line structures; patterning the first dielectric layer and the first sacrificial layer to form a through hole, wherein the through hole and the remaining first dielectric layer and first sacrificial layer are alternately arranged; forming a second sacrificial layer on the side wall of the through hole, and filling the through hole to form a contact plug; forming a contact structure on the contact plug; and removing the first sacrificial layer to form a first air gap, and removing the second sacrificial layer to form a second air gap. | 2022-05-05 |
| 20220139925 | Semiconductor Memory Device And Method Making The Same - This application relates to a semiconductor memory device and a method of forming the same. The method includes the following steps: providing a substrate with a bit line contact area in the substrate, wherein the surface of the substrate is disposed with a dielectric layer; forming a through trench penetrating the dielectric layer and exposing the bit line contact area; filling a first conductive material in the trench to forum a bit line, wherein the top surface of the bit line is configured to be lower than the top surface of the dielectric layer; filling an insulating material in the trench to form a bit line cap layer on the top surface of the bit line. This application does not cause misalignment problem due to the small line width of the bit line and in addition, reduces the internal resistance inside the memory device. | 2022-05-05 |
| 20220139926 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF - A forming method of a semiconductor structure includes: providing a substrate including an array area and a peripheral area; forming a first insulating dielectric layer in the array area and the peripheral area at the same time, and etching the first insulating dielectric layer and the component dielectric layer in the array area; filling the plurality of trenches; performing back etching on the reference isolation structure and the first insulating dielectric layer; forming a second insulating dielectric layer in the array area and the peripheral area; patterning the second insulating dielectric layer; removing the first insulating dielectric layer in the array area; and removing the second insulating dielectric layer to form a contact material in the contact window. | 2022-05-05 |
| 20220139927 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film. | 2022-05-05 |
| 20220139928 | PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME | 2022-05-05 |
| 20220139929 | MEMORY STRUCTURES AND METHODS OF FORMING MEMORY STRUCTURES - A memory structure may be provided, including a substrate, and a first well region, a second well region, and a third well region arranged within the substrate, where the first well region and the third well region may have a first conductivity type, and the second well region may have a second conductivity type different from the first conductivity type, and where the second well region may be arranged laterally between the first well region and the third well region. The memory structure may further include a first gate structure and a second gate structure arranged over the second well region. The first gate structure may extend over the third well region and the second gate structure may extend over the first well region. | 2022-05-05 |
| 20220139930 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern. | 2022-05-05 |
| 20220139931 | MEMORY CELL ARRANGEMENTS AND METHODS THEREOF - A memory cell arrangement may include: a first memory cell including a first field-effect transistor structure, a first capacitive memory structure coupled to a gate of the first field-effect transistor structure, and a first capacitive lever structure coupled to the gate of the first field-effect transistor structure, and wherein a second memory cell of the plurality of memory cells includes a second field-effect transistor structure, a second capacitive memory structure coupled to a gate of the second field-effect transistor structure, and a second capacitive lever structure coupled to the gate of the second field-effect transistor structure; wherein at least one of the first capacitive memory structure and/or the second capacitive memory structure is disposed in a memory structure region between the first capacitive lever structure and the second capacitive lever structure. | 2022-05-05 |
| 20220139932 | MEMORY CELL, CAPACITIVE MEMORY STRUCTURE, AND METHODS THEREOF - According to various aspects, a memory cell is provided, the memory cell including: a capacitive memory structure, the capacitive memory structure including a first electrode, a second electrode, and a memory structure disposed between the first electrode and the second electrode; and a field effect transistor structure, the field effect transistor structure including a gate structure coupled to the capacitive memory structure, wherein the first electrode of the capacitive memory structure includes a first electrode material having a first work-function and the second electrode of the capacitive memory structure includes a second electrode material having a second work-function, wherein the first work-function is different from the second work-function. | 2022-05-05 |
| 20220139933 | MEMORY CELL AND METHODS THEREOF - According to various aspects, a memory cell comprise: a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal to control the memory cell; a first memory element (FeFET | 2022-05-05 |
