| 18th week of 2016 patent applcation highlights part 69 |
| Patent application number | Title | Published |
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| 20160126903 | WEIGHTED MEMORY POLYNOMIAL METHOD AND SYSTEM FOR POWER AMPLIFIERS PREDISTORTION - A system and method for linearizing a power amplifier using digital predistortion technique is provided including processing circuitry, the processing circuitry configured to apply a digital predistortion function based on a weighted static polynomial function, a weighted dynamic polynomial function and a threshold parameter which splits the nonlinear transfer characteristics of the device under test into a region where the static nonlinearity predominates and a region where the dynamic distortions predominate. | 2016-05-05 |
| 20160126904 | APPARATUS AND METHOD FOR CONTROLLING IMPEDANCE TUNING BY USING HYBRID CONTROL ALGORITHM - An impedance tuning control apparatus has a processing circuit and an output circuit. The processing circuit determines a first control setting according to a first performance metric, and performs a search operation with a search start point set by the first control setting to find a second control setting according to a second performance metric. The second performance metric is different from the first performance metric. The output circuit outputs a final control setting to a tuner, wherein the final control setting is derived from the second control setting. | 2016-05-05 |
| 20160126905 | BROADBAND RADIO FREQUENCY POWER AMPLIFIERS, AND METHODS OF MANUFACTURE THEREOF - An embodiment of an amplifier has a bandwidth defined by low and upper cutoff frequencies. The amplifier includes an input impedance matching circuit and a transistor. The transistor has a gate, a first current conducting terminal coupled to an output of the amplifier, and a second current conducting terminal coupled to a reference node. The input impedance matching circuit has a filter input coupled to an input of the amplifier, a filter output coupled to the gate of the transistor, and a multiple pole filter coupled between the filter input and the filter output. A first pole of the filter is positioned at a first frequency within the bandwidth, and a second pole of the filter is positioned at a second frequency outside the bandwidth. The input impedance matching circuit is configured to filter the input RF signal to produce a filtered RF signal at the filter output. | 2016-05-05 |
| 20160126906 | LOW NOISE AMPLIFIER - Circuitry includes a floating-body main field-effect transistor (FET) device, a body-contacted cascode FET device, and biasing circuitry coupled to the floating-body main FET device and the body-contacted cascode FET device. The floating-body main FET device includes a gate contact, a drain contact, and a source contact. The body-contacted cascode FET device includes a gate contact, a drain contact coupled to a supply voltage, and a source contact coupled to the drain contact of the floating-body main FET device and to a body region of the body-contacted cascode FET device. The biasing circuitry is coupled to the gate contact of the floating-body main FET device and the gate contact of the body-contacted cascode FET device and configured to provide biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a majority of the supply voltage is provided across the body-contacted cascode FET device. | 2016-05-05 |
| 20160126907 | AMPLIFIER CONTROL APPARATUS - An apparatus for controlling a pulse width modulation (PWM) amplifier is disclosed. In one aspect, the apparatus includes a delay circuit configured to delay an input signal and provide the delayed input signal to the PWM amplifier. The apparatus also includes a controller configured to generate and provide a supply voltage to the PWM amplifier based at least in part on the input signal such that the PWM amplifier generates an output signal based at least partially on the delayed input signal and the supply voltage. | 2016-05-05 |
| 20160126908 | POWER STAGE WITH SWITCHED MODE AMPLIFIER AND LINEAR AMPLIFIER - A method for producing an output voltage to a load may include, in a power stage comprising power converter having a power inductor, a plurality of switches arranged to sequentially operate in a plurality of switch configurations, and an output for producing the output voltage comprising a first output terminal and a second output terminal, controlling the linear amplifier to transfer electrical energy from the input source of the power stage to the load in accordance with one or more least significant bits of a digital input signal, and controlling the power converter in accordance with bits of the digital input signal other than the one or more least significant bits to sequentially apply switch configurations from the plurality of switch configurations to selectively activate or deactivate each of the plurality of switches in order to transfer electrical energy from the input source of the power stage to the load. | 2016-05-05 |
| 20160126909 | Programmable Hysteresis Comparator - In one embodiment, a circuit includes a differential amplifier having a differential pair with a first transistor and second transistor. Each of the first and the second transistors include a front gate contact and a back gate contact. A first digital feedback loop is coupled between an output of the differential amplifier to the back gate contact of the first transistor. A second digital feedback loop is coupled to the back gate contact of the second transistor. The first digital feedback loop is configured to be opposite in phase to the second digital feedback loop. | 2016-05-05 |
| 20160126910 | Power Increase Based on Packet Type - Techniques for controlling one or more audio amplifiers in or associated with a device coupled on a local area network are disclosed. The device receives at least one selected source from other devices also coupled on the network According to one aspect of the techniques, an automatic shutdown control module is provided in the device to power down the audio amplifiers when there is no audio data flow coming to the device or power up the audio amplifiers when there is audio data flow coming to the device. In one embodiment, the procedure to power down or power up the amplifiers is in accordance with a hysteresis, wherein the hysteresis, being lagging of an effect behind its cause, protects the amplifiers and makes the powering-down or powering-up procedure unnoticeable to a user. | 2016-05-05 |
| 20160126911 | SIGNAL AMPLIFYING SYSTEM, AC SIGNAL GENERATING CIRCUIT, AMPLIFYING GAIN ACQUIRING METHOD, AND AC SIGNAL GENERATING METHOD - A signal amplifying system comprising: an amplifying module with a plurality of PGAs coupled in series; a test signal generating circuit, for generating a test signal fed to one test input PGA; and a control circuit. If the test input PGA is not a final PGA, the final PGA outputs an output test signal amplified by the test input PGA and the PGA following the test input PGA, wherein each the PGA following the test input PGA has a known amplifying gain. The control circuit acquires an accumulated gain for the test input PGA and the PGA following the test input PGA based on the output test signal, and acquires a amplifying gain of the test input PGA based on the accumulated gain. | 2016-05-05 |
| 20160126912 | Attenuator Control for a Signal Processing Chain - An attenuator control method of a signal processing chain comprising two or more signal processing units is disclosed. One of the two or more signal processing units is a signal attenuator adapted to apply adaptive signal attenuation of an attenuator input signal based on one or more attenuation parameters to provide an attenuator output signal. At least one of the two or more signal processing units has an associated wearout process and a corresponding wearout budget, wherein a wearout event of the wearout process occurs when a level of a wearout indication signal of the signal processing chain is in a wearout region, and wherein the wearout process is modeled by a wearout event cost associated with a corresponding wearout event. The method comprises obtaining an indication of whether a wearout event of the wearout process has occurred. If the obtained indication shows that a wearout event of the wearout process has occurred, the method comprises updating a wearout accumulation metric of the wearout process by the associated wearout event cost, comparing the wearout accumulation metric of the wearout process with one or more wearout thresholds of the wearout process, and adapting the attenuation parameters of the signal attenuator based on the comparison. The method also comprises controlling the signal attenuator based on the attenuation parameters. Corresponding attenuator control arrangement is also disclosed. | 2016-05-05 |
| 20160126913 | NOISE-BASED GAIN ADJUSTMENT AND AMPLITUDE ESTIMATION SYSTEM - Methods and systems for amplitude estimation and gain adjustment using noise as a reference are described. An example receiver can include an antenna and a front raid amplifier coupled to the antenna. The receiver can also include a detector circuit coupled to the front end amplifier. The receiver can be configured to determine a power of a received signal at the antenna based on a gain of the receiver. The gain of the receiver can be determined based on a noise figure of the front end amplifier and a noise amplitude. | 2016-05-05 |
| 20160126914 | ADVANCED COMMUNICATION EARPIECE DEVICE AND METHOD - An earpiece device ( | 2016-05-05 |
| 20160126915 | FILTER COEFFICIENT GROUP COMPUTATION DEVICE AND FILTER COEFFICIENT GROUP COMPUTATION METHOD - A filter coefficient group computation device is configured from a means for performing inverse Fourier transform on a frequency characteristic inputted through an input means; a means for performing short-term Fourier transform on a numerical string obtained by the inverse Fourier transform; a means for performing windowing on a frequency domain signal, obtained by the short-term Fourier transform, using a function of which a window length shortens as frequency increases; a means for performing short-term inverse Fourier transform on the frequency domain signal after the windowing; a means for performing overlap addition on a numerical string obtained by the short-term inverse Fourier transform; and a means for determining a numerical string after the overlap addition as a filter coefficient group which forms a filter having the frequency characteristic inputted through the input means. | 2016-05-05 |
| 20160126916 | ADAPTIVE EQUALIZATION FOR AN ULTRASONIC AUDIO SYSTEM - An ultrasonic audio system includes adaptive equalization techniques configured to adjust the overall output of the ultrasonic audio system. This can be done by adjusting the equalization of the electronic audio signal representing the audio content being reproduced by the ultrasonic audio system. For example, in various embodiments, systems and methods can be implemented to increase the gain of higher frequency portions of the electronic audio signal while making a corresponding decrease in the amount of gain at the lower frequency portions of the same signal. | 2016-05-05 |
| 20160126917 | MULTILAYER ELECTRONIC COMPONENT - A multilayer electronic component includes: a body including one or more ceramic layers or magnetic layers; an inductor part including coil portions disposed in the body to be perpendicular to a lower surface of the body; a plurality of internal electrodes disposed in the body to be perpendicular to the lower surface of the body; and an input terminal, an output terminal, and a ground terminal disposed on the lower surface of the body, wherein the body includes a capacitor part comprising at least one among the plurality of internal electrodes and at least one among the coil portions with at least one of the ceramic layers or magnetic layers interposed therebetween. | 2016-05-05 |
| 20160126918 | MULTILAYER ELECTRONIC COMPONENT - A multilayer electronic component includes a body including a dielectric layer and/or a magnetic layer, a terminal part including an input terminal, an output terminal, and a ground terminal connected to the body, and a filter part including a coil part disposed in the body and a capacitor part connected to the coil part and filtering a high frequency component of an input signal input to the input terminal. The capacitor part includes a plurality of first internal electrodes connected to the coil part and a plurality of second internal electrodes exposed to an exterior of the body. | 2016-05-05 |
| 20160126919 | NOISE FILTER - A noise filter is provided with a filter circuit including a first condenser and a second condenser; the first condenser and the second condenser are connected in parallel with each other by a first wiring lead for connecting one terminal of the first condenser with one terminal of the second condenser and a second wiring lead for connecting the other terminal of the first condenser with the other terminal of the second condenser; the first wiring lead and the second wiring lead are arranged in such a way as to intersect each other odd-number times. | 2016-05-05 |
| 20160126920 | OUTPUT MATCHING NETWORK HAVING A SINGLE COMBINED SERIES AND SHUNT CAPACITOR COMPONENT - A matching network requiring a predetermined shunt capacitance in a transformation of the impedance at the output to a transistor to a load. The matching network includes a vertically stacked shunt capacitor, for providing the entire predetermined capacitance, and a series DC blocking capacitor. | 2016-05-05 |
| 20160126921 | DYNAMIC POWER DIVIDER CIRCUITS AND METHODS - The present disclosure includes dynamic power divider circuits and methods. In one embodiment, a dynamic power divider includes first and second quarter wave lines that receive an input signal and produce first and second signal on second terminals of the lines. Dynamic power division of the input signal uses a variable impedance circuit between the second terminal of the first quarter wave line and the second terminal of the second quarter wave line. The variable impedance may reduce impedance between two output paths as the input signal power increases or increase impedance between the output paths as the input signal power decreases. | 2016-05-05 |
| 20160126922 | MULTIPLEXERS USING WEAKLY-COUPLED NETWORKS IN RF FRONT END CIRCUITRY - Multiplexing circuitry is disclosed that includes filtering circuitry, which provides a first transfer function between a common port and a first port and a second transfer function between the common port and a second port. The first transfer function and second transfer function provide a first passband and a second passband, respectively. The first transfer function also has a stopband provided within the second passband of the second transfer function due to the filtering circuitry including a first parallel resonant circuit provided in series in a first filter path being weakly coupled to a second parallel resonant provided in shunt with respect to a second filter path. The weak coupling between the first parallel resonant circuit and the second parallel resonant circuit thus naturally provides a stopband in the first transfer function within the second passband of the second transfer function. | 2016-05-05 |
| 20160126923 | VIBRATOR ELEMENT, ELECTRONIC DEVICE, ELECTRONIC APPARATUS, MOVING OBJECT, AND METHOD OF MANUFACTURING VIBRATOR ELEMENT - A vibrator element includes drive vibrating arms extending from an end of a base section, the drive vibrating arms are each provided with an obverse surface, a reverse surface disposed on an opposite side to the obverse surface, and a side surface connecting the obverse surface and the reverse surface to each other, a tilted section facing toward the obverse surface is disposed at least a part of the side surface, and there are disposed a first drive electrode and a second drive electrode obtained by bisection with an electrode separation section disposed in the tilted section. | 2016-05-05 |
| 20160126924 | VIBRATING ELEMENT, ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOVING OBJECT - A tuning fork-type vibrator element as a vibrating element includes a drive vibrating arm that performs a flexural vibration, and a drive electrode (a first drive electrode and a second drive electrode) provided on the drive vibrating arm. When a direction in which the drive vibrating arm extends is a Y-axis, a direction in which the drive vibrating arm performs a primary vibration is an X-axis, and a direction orthogonal to the Y-axis and the X-axis is a Z-axis, the drive vibrating arm performs the flexural vibration with a displacement ratio of greater than 0% and 20% or less where the displacement ratio is obtained by dividing a displacement amount in the Z-axis direction by a displacement amount in the X-axis direction. | 2016-05-05 |
| 20160126925 | SEMICONDUCTOR RESONATORS WITH REDUCED SUBSTRATE LOSSES - A resonator includes a laminate, an inductive element on the laminate, and a semiconductor die attached to the inductive element and the laminate. The semiconductor die includes a substrate and a device layout area. The device layout area is separated into a number of device layout sub-areas, each of which has an area between about 1.0 μm | 2016-05-05 |
| 20160126926 | MICROELECTROMECHANICAL RESONATORS - Embodiments relate to MEMS resonator structures and methods that enable application of a maximum available on-chip voltage. In an embodiment, a MEMS resonator comprises a connection between a ground potential and the gap electrode of the resonator. Embodiments also relate to manufacturing systems and methods that are less complex and enable production of MEMS resonators of reduced dimensions. | 2016-05-05 |
| 20160126927 | SURFACE ACOUSTIC WAVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a surface acoustic wave element and a method of manufacturing the same, and more specifically, to a surface acoustic wave element and a method of manufacturing the same, the element including a piezoelectric substrate; a plurality of IDT electrodes formed on the piezoelectric substrate; a plurality of resonator electrodes formed on the piezoelectric substrate; a wiring metal layer formed as a wiring area to electrically connect the plurality of IDT electrodes and the plurality of resonator electrodes; and an insulation layer formed on the piezoelectric substrate, the plurality of IDT electrodes, the plurality of resonator electrodes and the wiring metal layer. | 2016-05-05 |
| 20160126928 | Electroacoustic Transducer having Reduced Losses due to Transverse Emission and Improved Performance due to Suppression of Transverse Modes - An electroacoustic transducer has reduced loss due to acoustic waves emitted in the transverse direction. For this purpose, a transducer comprises a central excitation area, inner edge areas flanking the central excitation area, outer edge areas flanking the inner edge areas, and areas of the busbar flanking the outer edge areas. The longitudinal speed of the areas can be set so that the excitation profile of a piston mode is obtained. | 2016-05-05 |
| 20160126929 | RADIO FREQUENCY FILTERING CIRCUITRY WITH RESONATORS - RF multiplexer circuitry includes a first signal path coupled between a first intermediate node and a common node, a second signal path coupled between a second intermediate node and the common node, first resonator circuitry coupled between the first signal path and ground, and second resonator circuitry coupled between the second signal path and ground. The first resonator circuitry is configured to allow signals within a first frequency pass band to pass between the first intermediate node and the common node, while attenuating signals outside of the first frequency pass band. The first resonator circuitry includes a first LC resonator. The second resonator circuitry is configured to allow signals within a second frequency pass band to pass between the second intermediate node and the common node, while attenuating signals outside of the second frequency pass band. | 2016-05-05 |
| 20160126930 | BULK ACOUSTIC WAVE RESONATOR COMPRISING A RING - An acoustic resonator includes a first electrode disposed over a substrate; a piezoelectric layer disposed over the first electrode; and a second electrode disposed over the piezoelectric layer; a passivation layer disposed over the second electrode and a ring disposed between the substrate and the passivation layer | 2016-05-05 |
| 20160126931 | ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREFOR - In an electronic component, a functional circuit, signal wiring electrically connected to the functional circuit, and ground wiring electrically connected to the functional circuit and electrically connected to a ground potential are located on one surface of a circuit substrate, a frame member is provided to secure a region between itself and an outer peripheral edge of a first main surface of the circuit substrate and so as to surround the functional circuit, the ground wiring extends from inside to outside the frame member, and a shield member extends from a second main surface of the circuit substrate to a region on the first main surface via the side surfaces, the shield member being electrically connected to the ground wiring in the region outside the frame member. | 2016-05-05 |
| 20160126932 | DUPLEXER AND COMMUNICATION MODULE - A branching | 2016-05-05 |
| 20160126933 | FINITE IMPULSE RESPONSE FILTER AND FILTERING METHOD - A finite impulse response (FIR) filter and a corresponding filtering method are provided. The FIR filter receives an input sequence. The input sequence includes a plurality of input values. The FIR filter includes at least one first adder, at least one multiplier, and a second adder. Each first adder performs multiple addition operations simultaneously in parallel. Each addition operation outputs a sum of two of the input values. Each multiplier performs multiple multiplication operations simultaneously in parallel. Each multiplication operation outputs a product of one of the sums and one of a plurality of coefficients of the FIR filter. The second adder outputs a total sum of the products. | 2016-05-05 |
| 20160126934 | SWITCHABLE CAPACITOR ARRAY AND METHOD FOR DRIVING A SWITCHABLE CAPACITOR ARRAY - An improved switchable capacitor array comprises a plurality of n≧2 capacitor units, each comprising a capacitor with a capacitance and a switch unit. The capacitor units are electrically connected in series. Equidistantly spaced impedance values can be obtained if the values of the capacitances are chosen properly. | 2016-05-05 |
| 20160126935 | CIRCUIT AND METHOD FOR COMPENSATING FOR EARLY EFFECTS - Early effects are intrinsically present in bipolar junction transistors (BJTs). Described are examples of complimentary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) cells that reduce errors associated with the Early effects that would otherwise be present. | 2016-05-05 |
| 20160126936 | Data Storage Element and Signal Processing Method - A data storage element comprises a master stage (MS) with a first and a second latch (LI, L | 2016-05-05 |
| 20160126937 | LATCH AND FREQUENCY DIVIDER - A latch and a frequency divider are provided. The latch includes: a first logic cell coupled between a power supply and a ground wire, wherein the first logic cell has a first control terminal, a first input terminal and a first output terminal; a second logic cell having a structure symmetrical to that of the first logic cell; wherein the second logic cell has a second control terminal, a second input terminal and a second output terminal; and a feedforward control unit adapted to control the first logic cell or the second logic cell based on signals inputted into the first input terminal and the second input terminal. Accordingly, current loss under static working conditions of a latch can be eliminated, and current loss under dynamic working conditions of the latch can be reduced. | 2016-05-05 |
| 20160126938 | LATCH AND FREQUENCY DIVIDER - A latch and a frequency divider are provided. The latch includes: a first logic unit coupled between a power supply and a ground wire, wherein the first logic unit comprises a first control terminal, a first input terminal and a first output terminal; a second logic unit having a structure symmetrical to that of the first logic unit, wherein the second logic unit comprises a second control terminal, a second input terminal and a second output terminal; and a feedforward control unit adapted for cutting off a current path in the first logic unit or the second logic unit based on signals inputted into the first input terminal and the second input terminal. Power consumption of the latch can be reduced in both static working condition and dynamic working condition. | 2016-05-05 |
| 20160126939 | SYNCHRONISER FLIP-FLOP - A synchroniser flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node. | 2016-05-05 |
| 20160126940 | SPEED BOOSTER FOR COMPARATOR - Representative implementations of devices and techniques provide a speed increase to a comparator circuit. An active clamp device may be positioned between an input stage and an output stage of the comparator, limiting the voltage range of the output of the first stage. | 2016-05-05 |
| 20160126941 | SWITCHING CIRCUIT - A circuit has an operational voltage supply node that carries an operational voltage having an operational voltage value, a reference voltage supply node that carries a reference voltage having a reference voltage value, and a sub-circuit and switching circuit between the operational voltage supply node and the reference voltage supply node. The switching circuit is in series with the sub-circuit and controls a current through the sub-circuit based on a difference between the operational voltage value and a nominal operational voltage value. | 2016-05-05 |
| 20160126942 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device is provided with first and second regions that are operated by mutually different voltages, and a signal wiring that supplies a signal from the first region to the second region. The second region includes a circuit that is connected to between a first wiring to which a voltage is selectively supplied and a third terminal to which a voltage is supplied, and is operated by a differential voltage between the voltage in the first wiring and the voltage supplied to the third terminal, and a discharge circuit for discharging a charge in the first wiring. By using the discharge circuit, the potential difference between the signal wiring and the first wiring is prevented from becoming larger, and thus makes it possible to reduce damages of the circuit included in the second region. | 2016-05-05 |
| 20160126943 | High Frequency Absorptive Switch Architecture - An absorptive switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common terminal and one or more ports, any of which may be selectively coupled to the common terminal by closing an associated path switch; non-selected, unused ports are isolated from the common terminal by opening an associated path switch. Between each path switch and a port are associated shunt switches for selectively coupling an associated signal path to circuit ground. Between each path switch and a port is an associated absorptive switch module. Each absorptive switch module includes a resistor coupled in parallel with a switch. The combination of the resistor and the switch of the absorptive switch module is placed in series with a corresponding signal path from each port to the common terminal, rather than in a shunt configuration. | 2016-05-05 |
| 20160126944 | P-CHANNEL MOSFET HIGH VOLTAGE DRIVER - In accordance with one or more aspects of the disclosed embodiments, a drive circuit having a source of modulation for producing a modulated signal, a level shifter configured to receive the modulated signal and produce a level-shifted driver signal, an inverter circuit configured to receive the level-shifted driver signal and produce a MOSFET control signal, and at least one p-channel metal oxide semiconductor field effect transistor (MOSFET) configured to receive the MOSFET control signal and modulate an application of high current to a load, where the MOSFET control signal is supplied directly to the p-channel MOSFET through the inverter circuit. | 2016-05-05 |
| 20160126945 | SWITCHING CIRCUIT - According to embodiments of the present invention, a switching circuit is provided. The switching circuit includes a transmission line arrangement including a plurality of transmission lines coupled to each other, and at least one switching element arrangement coupled to at least one transmission line of the plurality of transmission lines, wherein, in a first mode of operation, the at least one switching element arrangement is configured in a first state, wherein, in a second mode of operation, the at least one switching element arrangement is configured in a second state, and wherein the transmission line arrangement is configured to, depending on whether the at least one switching element arrangement is configured in the first state or the second state, generate a standing wave from an input signal received by the transmission line arrangement for coupling into an output signal, wherein the output signal is transmitted from the transmission line arrangement. | 2016-05-05 |
| 20160126946 | CONTROL OF A HALF-BRIDGE - A control for an electrical consumer includes a first switching device for connecting an output for the consumer to a first potential, a second switching device for connecting the output to a second potential, a control device for activating the switching devices, a first scanning device for providing a first signal as a function of a switching state of the first switching device, a second scanning device for providing a second signal as a function of a switching state of the second switching device, and a comparator device for determining a difference in the switch-on times of the switching devices on the basis of the determined signals. | 2016-05-05 |
| 20160126947 | GOA CIRCUIT BASED ON LTPS SEMICONDUCTOR TFT - The present invention provides a GOA circuit based on LTPS semiconductor TFT, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part ( | 2016-05-05 |
| 20160126948 | GOA CIRCUIT BASED ON LTPS SEMICONDUCTOR TFT - The present invention provides a GOA circuit based on LTPS semiconductor TFT, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part ( | 2016-05-05 |
| 20160126949 | ADJUSTABLE INTERNAL GATE RESISTOR - The disclosure describes a method for controlling a voltage that is applied to a voltage controlled circuit element. In one example, the method includes controlling, by a semiconductor light source, a resistance value of a photoresistor coupled to a voltage controlled circuit element. The method includes applying, by a gate driver and via the photoresistor, a voltage to the voltage controlled circuit element. The method further includes controlling the voltage applied to the voltage controlled circuit element in order to control a current through the voltage controlled circuit element. In some examples, controlling the voltage applied to the voltage controlled circuit element may be accomplished by controlling the resistance value of the photoresistor in order to control a voltage drop across the photoresistor. Circuits that implement the method are also described. | 2016-05-05 |
| 20160126950 | POWER OUTLET SOCKET SENSOR SWITCH - A mains electrical power outlet assembly; said power outlet assembly including at least one power outlet socket; said power outlet assembly including at least one sensing module, operating a power switching module and a microprocessor; said sensing module including a sensor responsive to proximity to said sensor of selected objects; proximity of a said selected object switching status of a said power outlet socket from a current state to another state. | 2016-05-05 |
| 20160126951 | INTEGRATED MAGNETIC FIELD SENSOR-CONTROLLED SWITCH DEVICES - Embodiments relate to integrated magnetic field sensor-controlled switch devices, such as transistors, current sources, and power switches, among others. In an embodiment, a magnetic switch and a load switch are integrated in a single integrated circuit device. In embodiments, the magnetic switch is configured to sense a dynamic change in magnetic field caused by movement of a magnet in at least one of a linear, three-dimensional, and rotational direction. | 2016-05-05 |
| 20160126952 | CONTROL UNIT FOR CONTROLLING ELECTRICAL APPARATUS - A control unit for controlling electrical apparatus. The control unit has (i) a control device which may be wall-mounted; (ii) an actuation plate which may be secured to the control device and comprises a cover surface which is at least partially transparent; (iii) a sensor member for detecting when a user's finger or another body comes into contact with a touch zone; and (iv) a control designed to control the electrical apparatus according to a specific function following detection of the contact action. The control device comprises a switching device associated with the touch zone through the control in such a way that the actuation of the switching device controls the electrical apparatus according to the same function associated with the touch zone. | 2016-05-05 |
| 20160126953 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor. | 2016-05-05 |
| 20160126954 | METHODS AND APPARATUSES FOR SUB-THREHOLD CLOCK TREE DESIGN FOR OPTIMAL POWER - A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage. | 2016-05-05 |
| 20160126955 | Apparatus for Mixed Signal Interface Circuitry and Associated Methods - An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks. | 2016-05-05 |
| 20160126956 | NEGATIVE-LEVEL SHIFTING CIRCUIT AND A SOURCE DRIVER AND A DISPLAY DEVICE USING THE CIRCUIT - A negative-level shifting circuit includes a first level shifter including an input circuit configured to receive a logic signal having a first voltage level and a load circuit configured to generate a first output signal having a second voltage level based on a voltage generated by the input circuit, and a second level shifter configured to receive the first output signal from the first level shifter and generate a second output signal having a third voltage level. The first level shifter further includes a shielding circuit connected between the input circuit and the load circuit and configured to separate an operating voltage region of the input circuit from an operating voltage region of the load circuit such that the input circuit operates in a positive voltage region and the load circuit operates in a negative voltage region. | 2016-05-05 |
| 20160126957 | HAND-ACTIVATED COUNTING DEVICE - A hand-activated counting device includes a pressing module having an elastic assembly and a counting module coupled to the pressing module. The elastic assembly includes a first deformable elastic membrane with a first connecting portion, a second deformable elastic membrane with a second connecting portion, and an insulating element. The counting module includes a housing, a circuit board supported by the housing, a counter, a power supply, and a display. The first deformable elastic membrane is positioned opposite the second deformable elastic membrane with the insulating element separating the first deformable elastic membrane from the second deformable elastic membrane. The power supply is electronically connected to the display and electronically connected to the counter by the elastic assembly. The first connecting portion is coupled to a first contact of the counter and the second connecting portion is coupled to a second contact of the counter. | 2016-05-05 |
| 20160126958 | PLC HIGH SPEED COUNTER AND OPERATING METHOD THEREOF - Disclosed herein are a PLC high speed counter and an operating method thereof. The PLC high speed counter includes: an input circuit configured to convert and output a high-speed pulse train input from an encoder into a CMOS level; a micro processor unit configured to receive the pulse train from the input circuit, generate a count value by counting the pulse train in a linear count manner and calculate a current ring count value based on the count value; and a buffer configured to receive the count value from the micro processor unit and store the same as a current linear count value, wherein, when a current value request is received from an external device, the micro processor unit determines an operation mode and transmits, if the operation mode is a ring counter mode, the current ring count value. | 2016-05-05 |
| 20160126959 | OSCILLATOR, A CLOCK GENERATOR AND A METHOD FOR GENERATING A CLOCK SIGNAL - An oscillator configured to generate an oscillation signal is provided. The oscillator includes a transistor pair and a cross-coupled transistor pair. The transistor pair is coupled to a first current source and has a first transconductance. The first transconductance is changed in response to a current value of the first current source. The cross-coupled transistor pair is coupled to a second current source and has a second transconductance. The second transconductance is changed in response to a current value of second current source. The transistor pair and the cross-coupled transistor pair are mutually coupled by a plurality of inductors. A frequency of the oscillation signal is determined according to the first transconductance and the second transconductance. Furthermore, a clock generator and a method for generating a clock signal thereof are also provided. | 2016-05-05 |
| 20160126960 | OPERATING PARAMETER CIRCUITRY AND METHOD - An operating parameter method and circuitry are provided that generate operating parameter signals that are compensated for noise. Such operating parameter circuitry includes control loop circuitry that operates from a first power supply to provide an operating parameter signal to functional circuitry operating from a second power supply separate from the first power supply. The control loop circuitry comprises generator circuitry to generate the operating parameter signal based on an input signal. Replica generator circuitry operates from the second power supply to generate a further operating parameter signal based on the input signal. Adjustment circuitry performs a comparison on the operating parameter signal and the further operating parameter signal and causes an adjusted input signal to be produced in dependence on a result of the comparison. The adjusted input signal is received by the generator circuitry. Consequently, the generator circuitry is able to produce an operating parameter signal that has been compensated for noise in the circuit. | 2016-05-05 |
| 20160126961 | PHASE DETECTOR - A phase detector including a first latch and a control logic is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal. | 2016-05-05 |
| 20160126962 | CLOCK GENERATION CIRCUIT, SUCCESSIVE COMPARISON A/D CONVERTER, AND INTEGRATED CIRCUIT DEVICE - A clock generation circuit includes a first loop circuit configured to generate a first clock, and a second loop circuit configured to generate a second clock including a period different from a period of the first clock. A fluctuation in an amount of delay of the first clock is adjusted based on the second clock and the first clock including the period adjusted is output. | 2016-05-05 |
| 20160126963 | PHASE DETECTOR AND PHASE-LOCKED LOOP - A phase detector for generating a phase difference signal indicative of a phase difference between a first bi-level signal of frequency F1 and a second bi-level signal of frequency F2 is proposed. The phase detector may include first and second detector inputs first and second flip-flops, a NAND gate, and a first and second overphase detection units. An output of the first overphase detection unit may be connected to a direct input of the second flip-flop and may be arranged to output the level “1” in response to F1≦F2 and the level “0” in response to F1>F2. An output of the second overphase detection unit may be connected to a direct input of the first flip-flop and may be arranged to output the level “1” in response to F2≦F1 and the level “0” in response to F2>F1. | 2016-05-05 |
| 20160126964 | REFERENCE FREQUENCY CALIBRATION MODULE AND APPARATUS USING THE SAME - A reference frequency calibration module is provided. The reference frequency calibration module includes an oscillator, a frequency divider, a phase-locked loop (PLL) and a frequency-offset calibration unit. The frequency divider couples to the oscillator. The phase-locked loop couples to the frequency divider. The frequency-offset calibration unit couples to the frequency divider and the phase-locked loop. The oscillator is configured for operatively generating an oscillating signal having an oscillating frequency. The frequency divider divides the oscillating signal having the oscillating frequency by a first division parameter to generate a first clock signal having a first reference frequency. The phase-locked loop generates a second clock signal having a second reference frequency according to the first clock signal. The frequency-offset calibration unit is configured for operatively generating the first division parameter according to the second clock signal. | 2016-05-05 |
| 20160126965 | ATOMIC CELL MANUFACTURING METHOD, ATOMIC CELL, QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, ELECTRONIC DEVICE, AND MOVING OBJECT - An atomic cell manufacturing method includes a preparing process of preparing a structure that includes a wall portion which forms an inner space and a portion thereof is a light transmission portion, and in which liquid or solid alkaline metals are disposed in the light transmission portion, and an adjusting process of adjusting distribution such that alkaline metals are distributed so as to be intensively disposed on an outer circumferential portion side of the light transmission portion compared to a center portion of the light transmission portion, by heating the light transmission portion. | 2016-05-05 |
| 20160126966 | Successive approximation analog-to-digital converter and conversion method - The present invention discloses a successive approximation analog-to-digital converter capable of improving the accuracy of analog-to-digital conversion. An embodiment of this converter comprises: a successive approximation analog-to-digital converting circuit operable to generate M bits according to an analog input signal in which the M bits include a most significant bit (MSB) and successive M−1 bit(s) in succession to the MSB while the number M is an integer greater than one; and a multi-bit generating circuit operable to receive a capacitor array output signal and a comparison signal outputted from the successive approximation analog-to-digital converting circuit for a predetermined time after the generation of the M bits, and then generate N bits at a time accordingly in which the N bits include a least significant bit (LSB) and successive N−1 bit(s) ahead of the LSB while the number N is an integer greater than one. | 2016-05-05 |
| 20160126967 | APPARATUS AND METHOD FOR ANALOG-DIGITAL CONVERTING - Provided is an apparatus for analog-digital converting that includes a Most Significant Bit (MSB)-Digital Analog Converter (DAC) for converting a digital signal into an analog signal, a trim capacitor, a Least Significant Bit (LSB)-DAC, coupled to the trim capacitor, for converting a digital signal into an analog signal, a bridge capacitor connecting the MSB-DAC and the LSB-DAC, a comparator for measuring a voltage value at the MSB-DAC and LSB-DAC and outputting a result of comparing with a sampled voltage value, and a controller for generating first measurement data by digital converting a first measurement value output from the comparator by applying a reference voltage to a unit capacitor of the MSB-DAC, for generating second measurement data by digital converting a second measurement value output from the comparator by applying the reference voltage to the LSB-DAC, and controlling the trim capacitor by comparing the first and second measurement data. | 2016-05-05 |
| 20160126968 | ANALOGUE-TO-DIGITAL CONVERTER - This application relates to analogue-to-digital converters (ADCs). An ADC | 2016-05-05 |
| 20160126969 | IMPROVED METHOD OF SIGNAL PROCESSING AND SYSTEM INCLUDING THE SAME - A method of measuring signal change including performing at least one calculation or iteration step based on one or more chaos non-linear dynamical functions on first and second input signals, or sample of signals, to produce iteration values. Performing at least a second iteration step by repeating the at least one calculation or iteration step based on one or more non-linear dynamical functions on the first iteration values to produce a second iteration values and subtracting one set of iteration values generated from either the first or second input signal from the corresponding iteration values generated from the other input signal. | 2016-05-05 |
| 20160126970 | Receiver with Adjustable Reference Voltages - A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators. | 2016-05-05 |
| 20160126971 | Monotonic Segmented Digital to Analog Converter - In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word. | 2016-05-05 |
| 20160126972 | TOUCH CONTROL DETECTION SYSTEM, DELTA-SIGMA MODULATOR AND MODULATING METHOD THEREOF - A touch control detection system, a delta-sigma modulator and a modulating method thereof are provided. The delta-sigma modulator includes a quantizer and N integrating units. The quantizer generates a modulating result signal. The integrating units are coupled in series. Each of the integrating receives an input signal, and each of the integrating units receives a plurality of gain parameters, N is a positive integer. The quantizer quantizes a signal on an output end of the N | 2016-05-05 |
| 20160126973 | CURRENT TYPE D/A CONVERTER, DELTA SIGMA MODULATOR, AND COMMUNICATIONS DEVICE - This D/A converter includes a plurality of D/A converter elements, each comprising current sources configured to supply output currents to output nodes, and first switches configured to control the output currents. The output nodes are connected to a capacitor section having second switches and a capacitive load. The D/A converter further includes a switch control circuit configured to control the first switches responsive to digital signals, and also control the second switches in accordance with the control of the ON/OFF state of the first switches. | 2016-05-05 |
| 20160126974 | APPARATUS AND METHOD FOR PERFORMING CONVERSION OPERATION - An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value. | 2016-05-05 |
| 20160126975 | APPARATUS AND METHOD FOR PERFORMING CONVERSION OPERATION - An apparatus comprises processing circuitry to perform a conversion operation to convert a floating-point value to a vector comprising a plurality of data elements representing respective bit significance portions of a binary value corresponding to the floating-point value. | 2016-05-05 |
| 20160126976 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR OPTIMIZED MESSAGE DECODING - Methods, systems, and computer readable media for optimized message decoding are disclosed. According to one exemplary method, the method includes receiving a message containing one or more information elements (IEs). The method also includes determining a length associated with the message. The method further includes determining, using the length associated with message, whether the message can be accurately decoded using a mask stored in a memory. The method also includes in response to determining that the message can be accurately decoded using the mask, decoding the message using the mask. | 2016-05-05 |
| 20160126977 | COMMUNICATION APPARATUS, IMAGE FORMING APPARATUS, COMMUNICATION METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - A communication apparatus includes a serializer configured to convert parallel data into serial data and output the serial data; and a deserializer configured to convert the serial data output from the serializer into parallel data and output the parallel data. The serializer is configured to add first data used for detecting unique data in the parallel data before the unique data, add second data used for detecting the unique data after the unique data, and add third data whose length is variable to each of the first data and the second data. | 2016-05-05 |
| 20160126978 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technology relates to a data processing device and a data processing method so that an LDPC code with a good bit error rate is provided. | 2016-05-05 |
| 20160126979 | ENCODING METHOD, AND DECODING METHOD - An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula. | 2016-05-05 |
| 20160126980 | REMOVING ERROR PATTERNS IN BINARY DATA - A method and a device for removing pathologic error patterns in binary data are proposed. The method comprises the operations of identifying a pathologic error pattern in the binary data, and inverting all bits of the identified pathologic error pattern. | 2016-05-05 |
| 20160126981 | METHOD AND SYSTEM FOR FLEXIBLE RADIO COMMUNICATIONS USING A WIDEBAND RADIO - A method and system for flexible radio communications using a wideband radio includes a wideband radio and multiple separable radio definition modules, wherein the wideband radio is configured to operate over a large portion of the radio-frequency (RF) spectrum and each of the radio definition modules are configured to operate in a specific frequency band. The separability of the radio definition modules maintains the capability of the wideband radio to operate over the large portion of the RF spectrum, as well as enabling its robust and reliable operation in a specific frequency band associated with the attached radio definition module. | 2016-05-05 |
| 20160126982 | FRONT-END CIRCUIT - A front-end circuit includes a multiplexer, a circulator, reception ports, and variable filters. A port in the multiplexer is connected to an antenna. A port in the circulator is connected to a port in the multiplexer. The reception ports are connected to a port in the circulator with the variable filters interposed therebetween. The multiplexer outputs a communication signal having a frequency in a low band to the port and outputs a communication signal having a frequency in a middle band to a port. Each of the low band and the middle band includes a plurality of frequency bands. The middle band is a range of frequencies higher than those in the low band and does not overlap the low band. | 2016-05-05 |
| 20160126983 | MULTI-BAND AMPLIFIER - A multi-band amplifier may operate in a first frequency band and a second frequency band. The multi-band amplifier may include a first amplifier, a second amplifier, and a coupler. The coupler may couple a signal, such as a communication signal, to a selected amplifier. In some embodiments, the coupler may include one or more inductive elements to couple the signal to the first or the second amplifier. In some embodiments, the inductive elements may include a balun. | 2016-05-05 |
| 20160126984 | MULTI-MODE AND MULTI-BAND FRONT-END DEVICE - A multi-mode and multi-band front-end device comprises at least one amplifier unit, at least one switching unit, at least one control unit, a plurality of transmission paths, and a plurality of frequency matching networks. The switching unit comprises at least input end and a plurality of connecting ends. Wherein the input end is electrically connected to the amplifier unit, and each of connecting ends is connected to each of transmission paths, respectively. Each of frequency matching networks is configured on each of transmission paths, and achieves impedance matching at different frequency bands, respectively. The multi-mode and multi-band front-end device is able to select one of transmission paths to transmit RF signal according to the frequency band of RF signal to be transmitted so as to improve the output power of the multi-mode and multi-band front-end device. | 2016-05-05 |
| 20160126985 | Signal cancellation method and device for wireless communication system - Provided is a signal cancellation method for a wireless communication system, including: splitting a transmitted signal to obtain a main channel signal transmitted on a main channel and an auxiliary channel signal transmitted on an auxiliary channel; performing digital domain channel characteristic matching processing on the main channel signal and the auxiliary channel signal respectively to obtain a main channel characteristic matched signal and an auxiliary channel characteristic matched signal; and combining the main channel characteristic matched signal and the auxiliary channel characteristic matched signal which are coupled to a receiving channel in order for signal cancellation. A signal cancellation device for a wireless communication system is also provided. Through the technical solution of the disclosure, the signal cancellation problem of a bandwidth can be solved better. | 2016-05-05 |
| 20160126986 | COMMUNICATION DEVICES AND METHODS - Devices and methods are provided where a first signal is provided via an interface, and a second signal is provided related to the suitability of the first signal for transmission via the interface. | 2016-05-05 |
| 20160126987 | DIVERSITY RECEIVER FRONT END SYSTEM WITH IMPEDANCE MATCHING COMPONENTS - A receiving system can include a controller configured to selectively activate one or more of a plurality of paths between an input of the receiving system and an output of the receiving system. The receiving system can further include a plurality of amplifiers. Each one of the plurality of amplifiers can be disposed along a corresponding one of the plurality of paths and can be configured to amplify a signal received at the amplifier. The receiving system can further include a plurality of impedance matching components. Each one of the plurality of impedance matching components can be disposed along a corresponding one of the plurality of paths and can be configured to reduce at least one of an out-of-band noise figure or an out-of-band gain of the one of the plurality of paths. | 2016-05-05 |
| 20160126988 | BROADBAND SUPERHETRODYNE RECEIVER WITH AGILE INTERMEDIATE FREQUENCY FOR INTERFERENCE MITIGATION - A broadband superheterodyne receiver. Embodiments include an input for receiving an RF signal including an RF data signal at a carrier frequency. An RF mixer coupled to the input shifts the RF data signal from the carrier frequency to an IF frequency. An IF band pass filter coupled to the mixer has a pass band, and band pass filters the signal near the IF frequency. A spectrum analyzer provides information representative of the spectral characteristics of the received RF signal around the RF data signal at the carrier frequency. An IF controller is coupled to the RF mixer and to the spectrum analyzer. The IF controller: (1) determines an interference-mitigating IF frequency within the pass band of the band pass filter that will result in attenuation of undesired portions of the RF signal, and (2) controls the RF mixer to shift the RF data signal to the interference-mitigating IF frequency. | 2016-05-05 |
| 20160126989 | MULTIPLE ANTENNA INTERFERENCE REJECTION IN ULTRA-WIDEBAND REAL TIME LOCATING SYSTEMS - Systems, methods, apparatuses, and computer readable media are disclosed for providing interference rejection in ultra-wideband real time locating systems. In one embodiment, an ultra-wideband (UWB) receiver is configured to: receive an interference signal from a source positioned outside a monitored region; receive a composite signal transmitted from a tagged object moving about a playing field within the monitored region, wherein the composite signal comprises a location signal and a component of the interference signal; detect whether the component of the interference signal exceeds a threshold value; and adjust, via a processor, filtering of the composite signal to attenuate the component of the interference signal based on whether the component of the interference signal exceeds the threshold value. Some embodiments provide for filtering of the composite signal using a combiner while others employ a tunable notch filter. Corresponding systems, methods, and computer-readable storage medium are also provided. | 2016-05-05 |
| 20160126990 | DIVERSITY RECEIVE MODULES USING ONE OR MORE SHARED TUNABLE NOTCH FILTERS FOR TRANSMIT BLOCKER REJECTION - A carrier aggregation front-end module with a receive sub-module for receiving signals from a plurality of transmit modules. The module comprises a first receive path configured to receive a first set of signals from one or more of a plurality of antennas, wherein the first set of signals comprises at least one desired receive signal and at least one undesired transmit blocker signal from the plurality of transmit modules. The second receive path is configured to receive a second set of signals from one or more of a plurality of antennas comprising at least one desired receive signal and at least one undesired transmit blocker signal from the plurality of transmit modules. The module also comprises at least one shared tunable notch filter configured to reject at least one of the undesired transmit blocker signals for each of the first receive path and the second receive path. | 2016-05-05 |
| 20160126991 | DIGITAL FILTER FOR NARROWBAND INTERFERENCE REJECTION - A digital filter for narrowband interference rejection, including modules of narrowband interference rejection connected in series, each of which includes the following elements connected in series: a block of successive vector rotation based on the CORDIC vector rotation algorithm for integers, a block of reduction of the length of the rotated vector to maintain the same number of bits for digital signal representation, a block of high-pass filters for orthogonal components of the reduced vector in order to remove the interference from zero frequency region. The filter can be implemented without multiplication. | 2016-05-05 |
| 20160126992 | Inter-Radio Access Technology Spur Mitigation - Various embodiments provide methods, devices, and non-transitory processor-readable storage media for mitigating local oscillator (LO) spur interference between radio access technologies (RATs) operating on a multi-active communication device. The various embodiments provide methods, devices, and non-transitory processor-readable storage media to determine residual frequency error for a multi-active communication device and generate LO spur handling tables that may enable the multi-active communication device to compensate for the residual frequency error. A multi-active communication device may mitigate LO spurs by applying mitigation techniques to one or more RATs according to the LO spur handling tables. A multi-active communication device may mitigate LO spurs by turning off a LOs for one or more RATs according to the LO spur handling tables. | 2016-05-05 |
| 20160126993 | DIVERSITY RECEIVER FRONT END SYSTEM WITH IMPEDANCE MATCHING COMPONENTS - Diversity receiver front end system with tunable input and output matching circuits. A receiving system can include a controller configured to selectively activate one or more of a plurality of paths between an input of the receiving system and an output of the receiving system. The receiving system can include a plurality of amplifiers. Each one of the plurality of amplifiers can be disposed along a corresponding one of the plurality of paths and can be configured to amplify a signal received at the amplifier. The receiving system can include one or more tunable matching circuits. Each one of the one or more tunable matching circuits can disposed at the input or the output and configured to present an impedance based on a tuning signal received from the controller. | 2016-05-05 |
| 20160126994 | DIVERSITY RECEIVER FRONT END SYSTEM WITH VARIABLE-GAIN AMPLIFIERS - Diversity receiver front end system with variable-gain amplifiers. A receiving system can include a controller configured to selectively activate one or more of a plurality of paths between an input of a first multiplexer and an output of a second multiplexer. The receiving system can further include a plurality of bandpass filters, each one of the plurality of bandpass filters disposed along a corresponding one of the plurality of paths and configured to filter a signal received at the bandpass filter to a respective frequency band. The receiving system can further include a plurality of variable-gain amplifiers (VGAs), each one of the plurality of VGAs disposed along a corresponding one of the plurality of paths and configured to amplify a signal received at the VGA with a gain controlled by an amplifier control signal received from the controller. | 2016-05-05 |
| 20160126995 | SYSTEM AND METHOD FOR PORTABLE INFOTAINMENT VIA DYNAMIC SIM TWINNING WITH TEMPORARY SERVICE PLAN TRANSFERRING IN CONNECTED CAR - An apparatus comprises processing circuitry configured to determine that a primary user equipment (UE) entered a vehicle. The processing circuitry is configured to initiates transmission of an entrance notification to a carrier network server notifying that the primary UE entered the vehicle. The processing circuitry is configured to receive an assignment message from the carrier network server. The assignment message indicates that twinning has been configured between the primary UE and the apparatus. The twinning configuration includes a transfer of assignment of a service plan corresponding to the primary UE from the primary UE to the apparatus. | 2016-05-05 |
| 20160126996 | Mobile Communication Using a Plurality of Subscriber Identity Modules - An electronic device is provided. The electronic device may include a first subscriber identity module, a second subscriber identity module, and a communication module to communicate data via a first network using the first subscriber identity module, wherein the communication module may activate the second subscriber identity module during a tune-away period for a second network to communicate the data. | 2016-05-05 |
| 20160126997 | DEVICE FOR AFFIXING SIM CARD AND MOBILE TERMINAL - A device for affixing SIM card and a mobile terminal are provided. The device is arranged in the mobile terminal, which includes: a card tray, a card holder, and a locking mechanism for fitting the card tray. The card holder includes a first elastic component. The locking mechanism includes: a press component, a lock rod and a second elastic component. The lock rod includes a lock catch, while the card tray includes a lock piece. The press component includes a first driving surface in contact with the lock rod. The second elastic component is connected to the lock rod and configured to reset the lock rod after the card tray is removed. | 2016-05-05 |
| 20160126998 | METHOD, APPARATUS AND TERMINAL FOR ELECTROMAGNETIC RADIATION CONVERSION - A method, an apparatus and a terminal for electromagnetic radiation conversion relates to the field of electromagnetic radiation protection technique, the method includes the steps of receiving a high frequency electromagnetic radiation by a high frequency receiving module, converting the high frequency electromagnetic radiation into a low frequency electromagnetic radiation by a frequency conversion module, and emitting, by a low frequency emission module, the low frequency electromagnetic radiation converted by the frequency conversion module. The method, apparatus and terminal for electromagnetic radiation conversion can be used to convert the harmful electromagnetic radiation emitted by the terminal into the electromagnetic radiation which benefits the human health and can also have a cosmetic effect. | 2016-05-05 |
| 20160126999 | COMMUNICATION ANTENNA UNIT AND MOBILE TERMINAL APPARATUS - A mobile terminal apparatus includes a casing in which a circuit board, a battery pack, and a power receptor are provided. A power feeder is provided in the battery pack and is connected to the power receptor. Terminal plates, with each having one end held on one surface which is included in the power receptor, and having two widest surfaces which are parallel to each other, one of which faces and is parallel to one of two widest surfaces of an adjacent terminal plate. The terminal plates are aligned along a direction orthogonal to the two widest surfaces. A flexible circuit board includes a flexible bendable portion provided along the direction in which the terminal plates are aligned and connects the circuit board to the power receptor. | 2016-05-05 |
| 20160127000 | PICTURE CHANGING ASSEMBLY FOR MOBILE PHONE CASES - An apparatus is provided in one example embodiment and includes a motor, a first endless belt encircling a first pair of spaced apart shafts, a second endless belt encircling a second pair of spaced apart shafts, a drive element connecting the motor to one shaft each of the first pair of shafts and the second pair of shafts, and a continuous strip of film having a first end and a second end attached to the first endless belt and the second endless belt respectively. The motor activates the drive element to rotate one shaft each of the first pair of shafts and the second pair of shafts causing the belts to rotate, unwinding the film from the first endless belt and winding it on the second endless belt. | 2016-05-05 |
| 20160127001 | COVER WITH SHAPE MEMORY MATERIAL - A cover includes a cover body, and an arm coupled to the cover body. A shape memory material in the arm may be able to place the arm into a first shape and a second shape. In the first shape, the arm may be adjacent to a display device when the arm is attached to the display device. In the second shape, the arm may form a stand for the display device. | 2016-05-05 |
| 20160127002 | Cover Glass for Mobile Terminals, Manufacturing Method of the Same and Mobile Terminal Device - To provide cover glass for mobile terminals exhibiting high strength in a thin plate thickness state to enable reductions in thickness of apparatuses when inserted in the apparatuses, cover glass ( | 2016-05-05 |
