| 18th week of 2016 patent applcation highlights part 63 |
| Patent application number | Title | Published |
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| 20160126303 | DISPLAY DEVICE - A display device is disclosed. In one aspect, the device includes a substrate including a display area displaying an image via a plurality of pixels and a non-display area adjacent to the display area. The device also includes a first line and a second line in the display area. The display device also includes a first connection line and a second connection line in the non-display area, wherein the first and second connection lines are respectively connected to the first and second lines and extend in different directions to cross each other. The display device also includes an insulating layer formed over the substrate and including a first portion and a second portion, the first portion corresponding to the display area and the second portion corresponds to a crossing area where the first and second connection lines cross each other, the thickness of the first and second portions are different. | 2016-05-05 |
| 20160126304 | ORGANIC LIGHT-EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light-emitting diode (OLED) display includes pixel electrodes, each pixel electrode corresponding to a pixel region disposed in a display region of a substrate, a first pixel region disposed at a center portion of the display region, a second pixel region disposed at an edge portion of the display region, auxiliary lines, each auxiliary line disposed adjacent to at least one pixel electrode, emission layers disposed on the pixel electrodes, and an opposite electrode disposed on the emission layers, the opposite electrode contacting each of the auxiliary lines through contact holes, wherein a total contact area between the opposite electrode and an auxiliary line in the first pixel region is greater than a total contact area between the opposite electrode and the auxiliary line in the second pixel region. | 2016-05-05 |
| 20160126305 | MULTILAYER MIM CAPACITOR - A semiconductor capacitor and method of fabrication is disclosed. A MIM stack, having alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers. | 2016-05-05 |
| 20160126306 | SIC TRANSIENT VOLTAGE SUPPRESSOR - A high power, high current Unidirectional Transient Voltage Suppressor, formed on SiC starting material is disclosed. The device is structured to avalanche uniformly across the entire central part (active area) such that very high currents can flow while the device is reversely biased. Forcing the device to avalanche uniformly across designated areas is achieved in different ways but consistently in concept, by creating high electric fields where the device is supposed to avalanche (namely the to active area) and by relaxing the electric field across the edge of the structure (namely in the termination), which in all embodiments meets the conditions for an increased reliability under harsh environments. | 2016-05-05 |
| 20160126307 | SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR MANUFACTURING SUPER JUNCTION STRUCTURE - A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a plurality of pillars of a second conductivity type, a plurality of gate trenches, an insulating layer and a plurality of doped wells of the second conductivity type. The epitaxial layer of the first conductivity type is on the substrate. The pillars of the second conductivity type are in the epitaxial layer, in which the second conductivity type is opposite to the first conductivity type. The gate trenches are individually corresponding to and over the pillars. The insulating layer is in the gate trenches. The doped wells of the second conductivity type are in the epitaxial layer, in which each of the doped wells is between two adjacent gate trenches. A method for manufacturing the semiconductor device and a method for manufacturing a super junction structure are also provided. | 2016-05-05 |
| 20160126308 | SUPER-JUNCTION EDGE TERMINATION FOR POWER DEVICES - A semiconductor power device includes a junction termination extension (JTE) region that is defined by a gradually reducing width extending towards a periphery of the semiconductor device. In one advantageous aspect, the JTE design achieves a flat electric field profile across the JTE region. In another advantageous aspect, area efficiency of implementations can be increased, thereby reducing cost and complexity of fabrication. | 2016-05-05 |
| 20160126309 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack positioned over the semiconductor substrate. The semiconductor device structure includes a first doped structure and a second doped structure positioned at two opposite sides of the first gate stack and embedded in the semiconductor substrate. The semiconductor device structure includes a second gate stack positioned over the semiconductor substrate and adjacent to the second doped structure. The semiconductor device structure includes a third gate stack positioned over the semiconductor substrate. The semiconductor device structure includes an isolation structure embedded in the semiconductor substrate and between the second gate stack and the third gate stack. The isolation structure is wider and thinner than the second doped structure, and the isolation structure is made of an epitaxial material. | 2016-05-05 |
| 20160126310 | S/D CONNECTION TO INDIVIDUAL CHANNEL LAYERS IN A NANOSHEET FET - A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer. | 2016-05-05 |
| 20160126311 | STACKED THIN CHANNELS FOR BOOST AND LEAKAGE IMPROVEMENT - A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same. | 2016-05-05 |
| 20160126312 | SEMICONDUCTOR STRUCTURE INCLUDING A DOPED BUFFER LAYER AND A CHANNEL LAYER AND A PROCESS OF FORMING THE SAME - A semiconductor structure can include a substrate, a high-voltage blocking layer overlying the substrate, a doped buffer layer overlying the high-voltage layer, and a channel layer overlying the doped buffer layer, wherein the doped buffer layer and the channel layer include a same compound semiconductor material, and the doped buffer layer has a carrier impurity type at a first carrier impurity concentration, the channel buffer layer has the carrier impurity type at a second carrier impurity concentration that is less than the first carrier impurity concentration. In an embodiment, the channel layer has a thickness of at least 650 nm. In another embodiment, the high-voltage blocking includes a proximal region that is 1000 nm thick and adjacent to the doped buffer layer, and each of the proximal region, the doped buffer layer, and the channel layer has an Fe impurity concentration less than 5×10 | 2016-05-05 |
| 20160126313 | SEMICONDUCTOR DEVICE - Provided is an integrated circuit having a LOCOS-drain type MOS transistor mounted thereon in which, even in the case of poor pattern formation, a withstand voltage is not lowered and a poor withstand voltage does not result. A drain oxide film thicker than a gate oxide film is formed on an active region on a drain side of the LOCOS-drain type MOS transistor, to thereby prevent the withstand voltage of the MOS transistor from being lowered even if the gate electrode reaches the active region on the drain side. | 2016-05-05 |
| 20160126314 | SEMICONDUCTOR DEVICE - A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. A MOS gate structure formed of n source regions, p channel regions, p contact regions, a gate oxide film, and polysilicon gate electrodes is formed immediately below the source electrode. The p well regions are formed immediately below the gate pad electrode. The p channel regions are linked to the p well regions via extension portions. By making the width of the p well regions wider than the width of the p channel regions, it is possible to reduce a voltage drop caused by a reverse recovery current generated in a reverse recovery process of a body diode. Breakdown of a portion of a gate insulating film immediately below the center of the gate pad electrode and breakdown of the semiconductor device are thus prevented | 2016-05-05 |
| 20160126315 | III-Nitride Semiconductor Structure with Intermediate and Transition Layers - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 2016-05-05 |
| 20160126316 | TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF - Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure. | 2016-05-05 |
| 20160126317 | GRAPHENE LAYER, METHOD OF FORMING THE SAME, DEVICE INCLUDING GRAPHENE LAYER AND METHOD OF MANUFACTURING THE DEVICE - A graphene layer, a method of forming the graphene layer, a device including the graphene layer, and a method of manufacturing the device are provided. The method of forming the graphene layer may include forming a first graphene at a first temperature using a first source gas and forming a second graphene at a second temperature using a second source gas. One of the first and second graphenes may be a P-type graphene, and the other one of the first and second graphenes may be an N-type graphene. The first graphene and the second graphene together form a P—N junction. | 2016-05-05 |
| 20160126318 | SILICON EPITAXIAL WAFER AND METHOD OF PRODUCING SILICON EPITAXIAL WAFER - A silicon epitaxial wafer including: a second intermediate epitaxial layer on a silicon substrate produced by being cut from a silicon single crystal ingot grown by the CZ method so as to have a carbon concentration ranging from 3×10 | 2016-05-05 |
| 20160126319 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a MOS gate structure includes forming a device structure on a semiconductor substrate; forming an interlayer dielectric to cover the device structure; forming a contact hole through the interlayer dielectric; forming a transition metal film (e.g., Ni) on a portion of the semiconductor substrate exposed by the contact hole; (e) forming a metal film (e.g., Ti) on the entire surface of the semiconductor substrate; forming an oxide film in the surface of the metal film; selectively removing the metal film in which the oxide film has been formed, to thereby expose the transition metal film; and (h) exposing, to a hydrogen plasma atmosphere, the semiconductor substrate in which the transition metal film and the oxide film have been exposed, to thereby cause the transition metal film to generate heat and react with the semiconductor substrate and form an ohmic contact there between. | 2016-05-05 |
| 20160126320 | SUBSTRATE WITH SILICON CARBIDE FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SUBSTRATE WITH SILICON CARBIDE FILM - A substrate with a silicon carbide film includes a silicon substrate, a SiC film, and a mask | 2016-05-05 |
| 20160126321 | SUBSTRATE WITH SILICON CARBIDE FILM, METHOD FOR PRODUCING SUBSTRATE WITH SILICON CARBIDE FILM, AND SEMICONDUCTOR DEVICE - A substrate with a silicon carbide film includes a Si substrate, and a SiC film and a mask stacked on the Si substrate. The SiC film has a first SiC film provided on the upper side of the Si substrate and a second SiC film provided on the upper side of the first SiC film. The mask has a first mask provided on the Si substrate and including an opening (first opening) and a second mask provided on the first SiC film and including an opening (second opening). The width W | 2016-05-05 |
| 20160126322 | METHOD AND STRUCTURE TO IMPROVE FILM STACK WITH SENSITIVE AND REACTIVE LAYERS - Embodiments of the present disclosure generally relate to a film stack including layers of group III-V semiconductor materials. The film stack includes a phosphorous containing layer deposited over a silicon substrate, a GaAs containing layer deposited on the phosphorous containing layer, and an aluminum containing layer deposited on the GaAs containing layer. The GaAs containing layer between the phosphorous containing layer and the aluminum containing layer improves the surface smoothness of the aluminum containing layer. | 2016-05-05 |
| 20160126323 | METHOD OF PREPARING MONOATOMIC LAYER BLACK PHOSPHOROUS BY IRRADIATING ULTRASOUND - A method of preparing monoatomic layer black phosphorous by irradiating an ultrasound includes: putting black phosphorus into a solvent and irradiating the ultrasound; recovering a solution from a solution to which the ultrasound is irradiated; and collecting black phosphorus remaining after the solution has been recovered, putting the black phosphorus into a solvent, irradiating the ultrasound, and recovering a solution. | 2016-05-05 |
| 20160126324 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region. | 2016-05-05 |
| 20160126325 | Semiconductor device and manufacturing method therefor - A semiconductor device comprises: a semiconductor device active region; an electrode shape controlling layer disposed on the semiconductor device active region, the electrode shape controlling layer containing aluminum, the content of aluminum being changed in a direction from bottom to up from the semiconductor device active region, an electrode region being disposed on the electrode shape controlling layer, a groove extended toward the semiconductor device active region and penetrating through the electrode shape controlling layer longitudinally being disposed in the electrode region, all or part of a side surface of the groove having a shape corresponding to the content of aluminum in the electrode shape controlling layer; and an electrode disposed in the groove in the electrode region entirely or partially, the electrode having a shape matching with the shape of the groove, a bottom portion of the electrode being contacted with the semiconductor device active region. | 2016-05-05 |
| 20160126326 | Semiconductor Devices Including Contact Patterns Having a Rising Portion and a Recessed Portion - Semiconductor devices may include a gate pattern and a contact pattern disposed on an active region. The contact pattern may include a recessed portion near the gate pattern, and a rising portion away from the gate pattern. The gate pattern may include a gate insulating layer and a gate electrode disposed on the gate insulating layer. An upper surface of the recessed portion may be lower than an upper surface of the rising portion. | 2016-05-05 |
| 20160126327 | METHOD OF MAKING A SPLIT GATE MEMORY CELL - A method includes forming a first dielectric layer over a memory region and a second dielectric layer over a logic region. A first polysilicon layer is formed over the first and second dielectric layers. An opening is formed in the first polysilicon layer in the memory region. A charge storage layer is formed over the first polysilicon layer and in the opening. A second polysilicon layer is formed over the charge storage layer including in the opening. The second polysilicon layer is etched to remove the second polysilicon layer from over the first polysilicon layer and to leave a portion of the second polysilicon layer in the opening. The first polysilicon layer is etched to form a first gate in the logic region and the second polysilicon layer is etched in the opening to define a control gate of a first NVM cell and a control gate of a second NVM cell. | 2016-05-05 |
| 20160126328 | MEMORY DEVICES CAPABLE OF REDUCING LATERAL MOVEMENT OF CHARGES - Memory devices are provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell. | 2016-05-05 |
| 20160126329 | ELECTRONIC DEVICE FOR DATA STORAGE AND A METHOD OF PRODUCING AN ELECTRONIC DEVICE FOR DATA STORAGE - An electronic device for data storage and a method of producing an electronic device for data storage includes a memory storage element arranged to represent two or more memory states of the electronic device; wherein the memory storage element includes a plurality of metal nanoparticles. | 2016-05-05 |
| 20160126330 | THERMAL TREATED SEMICONDUCTOR/GATE DIELECTRIC INTERFACE FOR GROUP IIIA-N DEVICES - A method of fabricating a gate stack for a power transistor device includes thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is >5 A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited on the first dielectric layer. A metal gate electrode is formed on the second dielectric layer. | 2016-05-05 |
| 20160126331 | METAL GATE STRUCTURE AND METHOD OF FORMING THE SAME - The present invention provides a metal gate structure which is formed in a trench of a dielectric layer. The metal gate structure includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench and comprises a bottom portion and a side portion, wherein a ratio between a thickness of the bottom portion and a thickness of the side portion is between 2 and 5. The trench is filled with the metal layer. The present invention further provides a method of forming the metal gate structure. | 2016-05-05 |
| 20160126332 | SEMICONDUCTOR DEVICE - A semiconductor device includes a pillar-shaped silicon layer on a fin-shaped silicon layer. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A contact resides on the metal gate line and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of the contact. A vertical thickness of the nitride film relative to the substrate is greater than a horizontal thickness of the nitride film on the sidewall of the metal gate electrode and gate line relative to the substrate. | 2016-05-05 |
| 20160126333 | SEMICONDUCTOR DEVICE WITH IMPROVED INSULATED GATE - A semiconductor device includes a semiconductor body and an insulated gate contact on a surface of the semiconductor body over an active channel in the semiconductor device. The insulated gate contact includes a channel mobility enhancement layer on the surface of the semiconductor body, a diffusion barrier layer over the channel mobility enhancement layer, and a dielectric layer over the diffusion barrier layer. By using the channel mobility enhancement layer in the insulated gate contact, the mobility of the semiconductor device is improved. Further, by using the diffusion barrier layer, the integrity of the gate oxide is retained, resulting in a robust semiconductor device with a low on-state resistance. | 2016-05-05 |
| 20160126334 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor structure, including a substrate, having a fin structure disposed thereon, a gate structure, crossing over parts of the fin structure. The top surface of the fin structure which is covered by the gate structure is defined as a first top surface, and the top surface of the fin structure which is not covered by the gate structure is defined as a second top surface. The first top surface is higher than the second top surface, and a spacer covers the sidewalls of the gate structure. The spacer includes an inner spacer and an outer spacer, and the outer pacer further contacts the second top surface of the fin structure directly. | 2016-05-05 |
| 20160126335 | LATTICE MATCHED ASPECT RATIO TRAPPING TO REDUCE DEFECTS IN III-V LAYER DIRECTLY GROWN ON SILICON - A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions. | 2016-05-05 |
| 20160126336 | METHOD OF IMPROVED CA/CB CONTACT AND DEVICE THEREOF - Processes for forming merged CA/CB constructs and the resulting devices are disclosed. Embodiments include providing a replacement metal gate (RMG) between first and second sidewall spacers surrounded by an insulator on a substrate, the RMG having a dielectric layer directly on the first and second sidewall spacers and having metal on the dielectric layer; providing an oxide layer over the insulator, the first and second sidewall spacers, and the RMG; forming a source/drain contact hole through the oxide layer and the insulator, adjacent to the first sidewall spacer; forming a gate contact hole through the oxide layer over the source/drain contact hole and extending to the metal of the RMG; enlarging the source/drain contact hole to the metal of the RMG; and filling the enlarged source/drain contact hole and gate contact hole with metal. | 2016-05-05 |
| 20160126337 | SUBSTRATE PROCESSING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a substrate having an SiGe film or Ge film exposed on at least a portion of a surface thereof, a process chamber configured to process the substrate, an etching gas supply part configured to supply an etching gas into the process chamber, a deposition gas supply part configured to supply gas containing at least an Si-containing gas as a deposition gas into the process chamber, and a control part configured to control the deposition gas supply part and the etching gas supply part so as to remove a Ge oxide film formed on a surface of the SiGe film or the Ge film by supplying the etching gas and to epitaxially grow an Si-containing film on at least the SiGe film or the Ge film by supplying the Si-containing gas after removing the Ge oxide film by the supply of the etching gas. | 2016-05-05 |
| 20160126338 | TRANSISTOR AND FABRICATION METHOD THEREOF - A method for forming transistors is provided. The method includes providing a substrate having a base and at least a fin on the base; and forming a gate layer on the fin, the gate layer has first side surfaces parallel to a longitudinal direction of the fin and second side surfaces perpendicular to the fin. The method also includes forming a protective layer on the first side surfaces of the gate layer to protect a vertex of the top of the gate layer from having EPI particles; and forming sidewall spacers on side surfaces of the protective layer and the second side surfaces of the gate layer. Further, the method includes forming a stress layer in the fin at both sides of the sidewall spacers and the gate layer. | 2016-05-05 |
| 20160126339 | HIGH-ELECTRON-MOBILITY TRANSISTOR - A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern. | 2016-05-05 |
| 20160126340 | MULTICHANNEL DEVICES WITH IMPROVED PERFORMANCE AND METHODS OF MAKING THE SAME - A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. | 2016-05-05 |
| 20160126341 | Field Effect Transistor with Conduction Band Electron Channel and Uni-Terminal Response - A uni-terminal transistor device is described. In one embodiment, an n-channel transistor having p-terminal characteristics comprises a first semiconductor layer having a discrete hole level; a second semiconductor layer having a conduction band whose minimum level is lower than that of the first semiconductor layer; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level below the minimum level of the conduction band of the second semiconductor layer for zero bias applied to the gate metal layer and to obtain p-terminal characteristics. | 2016-05-05 |
| 20160126342 | CARBON DOPING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×10 | 2016-05-05 |
| 20160126343 | FinFETs with Source/Drain Cladding - A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors. | 2016-05-05 |
| 20160126344 | TFT SUBSTRATE WITH VARIABLE DIELECTRIC THICKNESS - A transistor includes a substrate and an electrically conductive gate over the substrate. The gate has a gate length. A source electrode and a drain electrode are over the substrate, and are separated by a gap defining a channel region. The channel region has a channel length that is less than the gate length. A semiconductor layer is in contact with the source electrode and drain electrode. A dielectric stack is in contact with the gate, and has first, second, and third regions. The first region is in contact with the semiconductor layer in the channel region, and has a first thickness. The second region is adjacent to the first region that has the first thickness. The third region is adjacent to the second region, and has a thickness that is greater than the first thickness. | 2016-05-05 |
| 20160126345 | Semiconductor device and method for manufacturing the same - A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region. | 2016-05-05 |
| 20160126346 | SILICON CARBIDE FIELD EFFECT TRANSISTOR - A silicon carbide field effect transistor includes a silicon carbide substrate, an n-type drift layer, a p-type epitaxy layer, a source region, a trench gate, at least one p-type doped region, a source, a dielectric layer and a drain. The p-type doped region is disposed at the n-type drift layer to be adjacent to one lateral side of the trench gate, and includes a first doped block and a plurality of second doped blocks arranged at an interval from the first doped block towards the silicon carbide substrate. Further, a thickness of the second doped blocks does not exceed 2 um. Accordingly, not only the issue of limitations posed by the energy of ion implantation is solved, but also an electric field at a bottom and a corner of the trench gate is effectively reduced, thereby enhancing the reliability of the silicon carbide field effect transistor. | 2016-05-05 |
| 20160126347 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A trench reaches a first layer of a first conductivity type from a second main surface through a third layer of the first conductivity type and a second layer of a second conductivity type. A contact region extends from the second main surface through the third layer and the second layer to a position deeper than an interface between the first layer and the second layer, and comes in contact with an embedded region. The contact region is higher in impurity concentration than the second layer. The embedded region has a first portion lying between the contact region and a first main surface in a direction of thickness and a second portion extending from the first portion toward the trench. | 2016-05-05 |
| 20160126348 | INSULATED GATE SEMICONDUCTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE AND METHOD - A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, which has a lower doping concentration. A trench structure having an insulated shield electrode and an insulated gate electrode is provided in the semiconductor region. The semiconductor device further includes one or more features configured to improve operating performance. The features include terminating the trench structure in the junction blocking region, providing a localized doped region adjoining a lower surface of a body region and spaced apart from the trench structure, disposing a notch proximate to the lower surface of the body region, and/or configuring the insulated shield electrode to have a wide portion adjoining a narrow portion. | 2016-05-05 |
| 20160126349 | SEGMENTED POWER TRANSISTOR - A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe. | 2016-05-05 |
| 20160126350 | LDMOS TRANSISTORS FOR CMOS TECHNOLOGIES AND AN ASSOCIATED PRODUCTION METHOD - In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region ( | 2016-05-05 |
| 20160126351 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region. | 2016-05-05 |
| 20160126352 | HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR - A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed. | 2016-05-05 |
| 20160126353 | FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN - A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure. | 2016-05-05 |
| 20160126354 | Methods of Forming Transistors - Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate. | 2016-05-05 |
| 20160126355 | Thin film transistors with metal oxynitride active channels for electronic displays - In one embodiment of the invention, a high electron mobility thin film transistor with a plurality of gate insulating layers and a metal oxynitride active channel layer is provided for forming a backplane circuit for pixel switching in an electronic display, to reduce unwanted ON state series resistance in the metal oxynitride active channel layer and minimize unwanted power dissipation in the backplane circuit. | 2016-05-05 |
| 20160126356 | ACTIVE DEVICE CIRCUIT SUBSTRATE - An active device circuit substrate includes a substrate, a plurality of active devices, and a first planarization layer. Each active device includes a gate electrode, a channel layer stacked with the gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode are disposed on the channel layer and located on opposite sides of the channel layer to define a channel area of the channel layer. The active devices include a first active device and a second active device. The first active device is disposed between the first planarization layer and the substrate, and the first planarization layer is disposed between the first active device and the second active device. A minimum linear distance between the channel area of the first active device and the channel area of the second active device along a direction parallel to the substrate is not smaller than 5 μm. | 2016-05-05 |
| 20160126357 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating layer having a first side wall, an oxide semiconductor layer located on the first side wall, a gate insulating layer located on the oxide semiconductor layer, the oxide semiconductor layer being located between the first side wall and the gate insulating layer, a gate electrode facing the oxide semiconductor layer located on the first side wall, the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a first electrode located below the oxide semiconductor layer and connected with one portion of the oxide semiconductor layer, and a second electrode located above the oxide semiconductor layer and connected with the other portion of the oxide semiconductor layer. | 2016-05-05 |
| 20160126358 | THIN-FILM TRANSISTOR - A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided. | 2016-05-05 |
| 20160126359 | SPLIT GATE FLASH CELL SEMICONDUCTOR DEVICE - A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors. | 2016-05-05 |
| 20160126360 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film. | 2016-05-05 |
| 20160126361 | SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - A solar cell module comprises an upper cover plate, a front adhesive layer, a cell array, a back adhesive layer and a back plate superposed in sequence, the cell array comprising multiple cells, adjacent cells connected by a plurality of conductive wires, at least two conductive wires comprising the metal wire which extends reciprocally between surfaces of adjacent cells, the conductive wires being in contact with the cells, the front adhesive layer in direct contact with the conductive wires and filling between adjacent conductive wires. | 2016-05-05 |
| 20160126362 | SOLAR CELL ARRAY, SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - A solar cell array comprises a plurality of cells, adjacent cells connected by a metal wire. At least one metal wire extends reciprocally between a surface of a first cell and a surface of a second cell adjacent to the first cell to form a plurality of conductive wires. The number of the conductive wires is n, y−y×20%≦n≦y+y×20%, in which n is an integer and y=4.0533X | 2016-05-05 |
| 20160126363 | SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - A solar cell module comprises an upper glass plate, a front adhesive layer, a solar cell array, a back adhesive layer and a back plate superposed in sequence. The solar cell array comprises a plurality of cells, adjacent cells connected by a metal wire. At least one metal wire extends reciprocally between a surface of a first cell and a surface of a second cell adjacent to the first cell to form at least two conductive wires. The cells comprise secondary grid lines disposed on front surfaces thereof. The conductive wires are being welded with the secondary grid lines. At least one of the front adhesive layer and the back adhesive layer has a thickness of larger than or equal to the metal wire in a direction perpendicular to the cell, and smaller than 400 μm. | 2016-05-05 |
| 20160126364 | SOLAR CELL UNIT, SOLAR CELL ARRAY, SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - A solar cell unit comprises a cell. The cell includes a cell substrate and a secondary grid line disposed on a front surface of the cell substrate. The solar cell unit also comprises a conductive wire intersecting and welded with the secondary grid line. The secondary grid line has a width in a welding position with the conductive wire greater than a width thereof in a non-welding position. | 2016-05-05 |
| 20160126365 | SOLAR CELL UNIT, SOLAR CELL ARRAY, SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - A solar cell unit comprises a cell. The cell includes a cell substrate and a plurality of secondary grid lines disposed on a front surface of the cell substrate. The secondary grid lines comprises an edge secondary grid line adjacent to an edge of the cell substrate and a middle secondary grid line disposed inside of the edge secondary grid line. The at least one edge secondary grid line has a width greater than the middle secondary grid line. The solar cell unit also comprises a plurality of conductive wires spaced apart from each other. The plurality of conductive wires intersects and is connected with the secondary grid lines. | 2016-05-05 |
| 20160126366 | SOLAR CELL UNIT, SOLAR CELL ARRAY, SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - A solar cell unit comprises a cell. The cell includes a cell substrate and a plurality of secondary grid lines disposed on a front surface of the cell substrate. The secondary grid lines comprises an edge secondary grid line adjacent to an edge of the cell substrate and a middle secondary grid line disposed inside of the edge secondary grid line. The secondary grid line comprises a welding portion. At least one welding portion of the edge secondary grid line has a projection area in the cell substrate larger than a welding portion of the middle secondary grid line. The solar cell unit also comprises a plurality of conductive wires spaced apart from each other and welded with the secondary grid lines in the welding portion. | 2016-05-05 |
| 20160126367 | Solar Photovaltaic Module Rapid Shutdown and Safety System - A photovoltaic (PV) module safety shutdown system includes a module-on switch coupled with a PV module coupled with an alternating current (AC) mains panel through an inverter. A system monitor couples with the module-on switch and with the AC mains panel and generates a system-on signal. A module discharge switch couples with an inherent capacitance of the inverter and with the system monitor. The module discharge switch discharges the inherent capacitance, by coupling the inherent capacitance with a discharge element, in response to the system monitor not generating the system-on signal. In implementations a module short switch shorts the PV module in response to a passage of a predetermined amount of time after the module discharge switch is switched on. The module-on switch, module discharge switch, and module short switch may be included in a junction box of the PV module and coupled with the system monitor through multiple opto-isolators. | 2016-05-05 |
| 20160126368 | SOLAR CELL - A solar cell is discussed. The solar cell according to an embodiment includes a semiconductor substrate containing impurities of a first conductive type, a metal oxide layer positioned on the semiconductor substrate, an emitter region positioned on the metal oxide layer and having a second conductive type opposite the first conductive type, a first electrode connected to the emitter region, and a second electrode connected to the semiconductor substrate. | 2016-05-05 |
| 20160126369 | SEMICONDUCTOR DEVICE AND PATTERNING METHOD FOR PLATED ELECTRODE THEREOF - The present invention discloses in detail a semiconductor device and a patterning method for the plated electrode thereof. By using the laser ablation method according to the prior art, the semiconductor substrate below the ARC is damaged by direct destructive burning. According to the present invention, an additional protection layer is inserted between the ARC and the semiconductor substrate. Then a laser is used for heating and liquefying the protection layer below the ARC, and thus separating the ARC from the liquefied protection layer underneath and forming pattered openings. Afterwards, by a plating process, nickel and copper can plated. | 2016-05-05 |
| 20160126370 | Solar Cell, Manufacturing Method Therefor, Solar Cell Module, and Manufacturing Method Therefor - A solar cell of the present invention includes a collecting electrode extending in one direction on a first principal surface of a photoelectric conversion section. The collecting electrode includes first and second electroconductive layers in this order from the photoelectric conversion section side, and further includes an insulating layer provided with openings between the electroconductive layers. The first electroconductive layer is covered with the insulating layer, and the second electroconductive layer is partially in conduction with the first electroconductive layer through the openings of the insulating layer. The first electroconductive layer has non-central portions within a range from both ends of the first electroconductive layer, and a central portion between the two non-central portions, in a direction orthogonal to an extending direction of the first electroconductive layer. A density of openings at the central portion is higher than a density of openings at the non-central portion. | 2016-05-05 |
| 20160126371 | SEMICONDUCTOR OPTICAL SENSOR - A semiconductor optical sensor includes a plurality of sensing units and to senses an incident optical signal to generate an electrical signal. One of the sensing units includes a substrate, an optical sensing element, a lens and an optical shielding element. The optical sensing element, whose material is different from that of the substrate, converts the incident optical signal into the electrical signal. The lens, whose material includes the same as that of the substrate, guides the incident optical signal to the optical sensing element by changing the propagation path of the incident optical signal. The optical shielding element, which surrounds the optical sensing element, alters the propagation path or propagation distance of the incident optical signal after the incident optical signal passes through the lens such that the incident optical signal will not reach an optical sensing element of an adjacent sensing unit. | 2016-05-05 |
| 20160126372 | SOLAR CELL ARRAY, SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - A solar cell array comprises a plurality of cells. Each cell has a front surface on which light is incident when the cell is in operation and a back surface opposite to the front surface. The solar cell array also comprises a plurality of conductive wires. Adjacent cells are connected by the plurality of conductive wires. The solar cell array further comprises secondary grid lines disposed on the front surface of the respective cell. The secondary grid lines comprise middle secondary grid lines disposed in the middle of the respective cell and intersecting with the conductive wires, and edge secondary grid lines disposed on the edges of the respective cell and non-intersecting with the conductive wires. The solar cell array also comprises short grid lines disposed on the front surface of the cell. The short grid lines connect the edge secondary grid lines with the conductive wires or with at least one middle secondary grid line. | 2016-05-05 |
| 20160126373 | METHOD FOR MANUFACTURING SOLAR CELL MODULE - A solar cell module, comprising an upper cover plate, a front adhesive layer, a cell, a back adhesive layer and a back plate superposed in sequence, a secondary grid line being disposed on the cell, a conductive wire comprising a metal wire being disposed between the front adhesive layer and a front surface of the cell, a welding layer disposed on a welding position where the conductive wire and the secondary grid line are welded, the welding layer being an alloy containing Sn, Bi and at least one of Cu, In, Ag, Sb, Pb and Zn, in which an amount of Bi is 15 to 60 weight percent. | 2016-05-05 |
| 20160126374 | METHOD FOR MANUFACTURING SOLAR CELL HAVING SELECTIVE EMITTER AND SOLAR CELL MANUFACTURED THEREBY - The present invention relates to a method for manufacturing a solar cell comprising a selective emitter, the method comprising the steps of: forming an electrode pattern and an alignment mark by performing a first impurity doping locally on one surface of a substrate; and performing a second impurity doping on the entire surface of the first doped substrate, wherein, as a result of the first and second doping, the alignment mark is formed on a first emitter or a second emitter, and the electrode pattern is formed on the second emitter. When manufacturing the selective emitter, the alignment mark is formed by doping processes. The use of the alignment mark may increase the matching of the electrode pattern formed in the selective emitter and the resulting electrode line. Further, a solar cell having the selective emitter has excellent conversion efficiency and a high fill factor value. | 2016-05-05 |
| 20160126375 | SOLAR CELL, METHOD FOR MANUFACTURING THE SAME, AND SOLAR CELL MODULE - A solar cell includes: a first-conductivity-type semiconductor substrate including an impurity diffusion layer, in which a second-conductivity-type impurity element is diffused, on one surface side; a light-receiving surface-side electrode including a grid electrode and a bus electrode having a wider width than the grid electrode and in electrical communication with the grid electrode, and formed on the one surface side and electrically connected to the impurity diffusion layer; and a rear surface side electrode formed on a rear surface and electrically connected to the impurity diffusion layer, wherein the light-receiving surface-side electrode includes a first metal electrode layer directly bonded to the one surface side, and a second metal electrode layer that is formed of a metal material different from the first metal electrode layer and having electrical resistivity substantially equivalent to the first metal electrode layer and is formed to cover the first metal electrode layer. | 2016-05-05 |
| 20160126376 | METHOD FOR MANUFACTURING THIN FILM SOLAR CELL AND MODULE STRUCTURE OF THIN FILM SOLAR CELL - A method for manufacturing a thin film solar cell includes: depositing a transparent first rear electrode on a first surface of a transparent substrate; depositing a second rear electrode having a high-conductive metal on the first rear electrode; performing a first laser scribing process to separate a double layer of the first and second rear electrodes; depositing a light absorption layer having selenium (Se) or sulfur (S) on the second rear electrode; performing a second laser scribing process by inputting a laser to a second surface of the transparent substrate to separate the light absorption layer; depositing a transparent electrode on the light absorption layer; and performing a third laser scribing process by inputting a laser to the second surface to separate the transparent electrode. Accordingly, patterning may be performed in a substrate-incident laser manner to improve price, productivity and precision of the patterning process. | 2016-05-05 |
| 20160126377 | Flexible Kesterite Photovoltaic Device on Ceramic Substrate - Kesterite-based photovoltaic devices formed on flexible ceramic substrates are provided. In one aspect, a method of forming a photovoltaic device includes the steps of: forming a back contact on a flexible ceramic substrate; forming a kesterite absorber layer on a side of the back contact opposite the flexible ceramic substrate; annealing the kesterite absorber layer; forming a buffer layer on a side of the kesterite absorber layer opposite the back contact; and forming a transparent front contact on a side of the buffer layer opposite the kesterite absorber layer. A roll-to-roll-based method of forming a photovoltaic device and a photovoltaic device are also provided. | 2016-05-05 |
| 20160126378 | Photovoltaic Devices and Methods for Making the Same - A photovoltaic device includes a support layer; a first layer comprising cadmium, tellurium and copper and being of n-type; a second layer comprising cadmium, tellurium and copper and being of p-type; and a transparent conductive oxide layer. A method for making a photovoltaic device includes providing a stack comprising a cadmium and tellurium comprising layer and a copper comprising layer on the cadmium and tellurium comprising layer; and thermally annealing the stack to form a first layer and a second layer each comprising cadmium, tellurium and copper, the first layer being of n-type, the second layer being of p-type. | 2016-05-05 |
| 20160126379 | SOLAR CELL AND METHOD FOR MANUFACTURING SAME - Disclosed is a solar cell including a substrate, a back electrode, a light-absorbing layer, a buffer layer, and a front transparent electrode. The buffer layer includes a titanium (Ti) compound. The light-absorbing layer includes a compound composed of M | 2016-05-05 |
| 20160126380 | FLEXIBLE SOLAR PANEL AND METHOD OF FABRICATING THE SAME - Flexible solar panel, flexible solar panel module, and method of fabricating the same. The method includes cutting solar cell into unit cells and processing the unit cells, forming unit electric lines matched up with lower electrodes of each cut and processed unit cell on flexible substrate so that the unit electric lines are arranged at an interval and forming serial lines connecting the positive electrode terminal path and negative electrode terminal path of adjacent unit electric lines so that the unit electric lines are serially connected, coating solder alloy on the unit electric lines, and arranging the lower electrodes of the unit cells and the unit electric lines of the flexible substrate so that the lower electrodes are matched up with the unit electric lines, attaching the lower electrodes and the unit electric lines, and performing soldering processing on the lower electrodes and the unit electric lines by applying heat higher than melting point of the solder alloy. | 2016-05-05 |
| 20160126381 | MICROSTRUCTURE ENHANCED ABSORPTION PHOTOSENSITIVE DEVICES - Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures arc described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more. | 2016-05-05 |
| 20160126382 | ENERGY CONVERSION DEVICE WITH MULTIPLE VOLTAGE OUTPUTS AND POWER TRANSISTOR MODULE USING THE SAME - An energy conversion device in electrical communication with at least one fin is provided to output multiple voltages. The at least one fin which is originating from inside the energy conversion device, which is formed from a metal contact disposed between energy conversion device components, and which is spaced with a first end contact and a second end contact. A power transistor module includes at least one transistor, a gate driver and the energy conversion device. The gate driver is configured to drive the at least one transistor. The energy conversion device is configured to supply isolated voltages to the gate driver. | 2016-05-05 |
| 20160126383 | PHOTOVOLTAIC MODULE WITH IMPROVED BONDING - A solar module can include a laminate having an edge and a receptacle of a frame portion connected to the edge of the laminate. In an embodiment, an adhesive can be formed in the receptacle of the frame portion. In one embodiment, the adhesive can bond the laminate to the frame portion. In an embodiment, the adhesive can be a partially cured adhesive, where the partially cured adhesive can be heated to form a cured adhesive and to bond the laminate to a frame. In an embodiment, the adhesive can be an epoxy, B-stage epoxy or a silicone sealant. | 2016-05-05 |
| 20160126384 | A BACKSHEET FOR PHOTOVOLTAIC MODULES - A backsheet for a photovoltaic module includes a support and a primer provided on a side of the support facing a sealing layer, the primer including an acrylic resin and a crosslinking agent, characterized in that the acrylic resin is a copolymer including at least 5 wt % of an acrylate monomer unit containing a UV absorbing group and at least 2 wt % of an acrylate monomer unit containing a crosslinkable group both relative to the total weight of monomer units. | 2016-05-05 |
| 20160126385 | ROOF PANEL HAVING SOLAR CELL OF VEHICLE - A roof panel of a vehicle is equipped with a solar cell module that is capable of satisfying an opening sense of the roof panel and preventing a voltage drop due to contact between heterogeneous solar cells. The solar cell module has the heterogeneous solar cell modules simultaneously mounted, and maintains output voltages of the heterogeneous solar cells to be the same by providing a plurality of cells in at least one of the solar cell modules, or individually controlling power output from the same kinds of solar cells by electric wire parts individually connected to the heterogeneous solar cells to maximize performance of the solar cell. | 2016-05-05 |
| 20160126386 | SOLAR CELL MODULE - A solar cell module having an improved wiring structure is disclosed. The solar cell module includes a plurality of solar cells each including first electrodes and second electrodes which are alternately arranged in parallel with each other, a plurality of wiring members configured to electrically connect the plurality of solar cells, and which are positioned adjacent to each other among the plurality of solar cells, in a direction crossing the first electrodes and the second electrodes, and a plurality of bonding layers configured to fix the plurality of wiring members to the plurality of solar cells. | 2016-05-05 |
| 20160126387 | SOLAR CELL MODULE - A solar cell module includes solar cells, each including a first bus bar electrode provided on a first principal surface and a second bus bar electrode provided on a second principal surface; a wiring member connecting the first bus bar electrode of one of adjacent two solar cells and the second bus bar electrode of the other solar cell; and a resin adhesive layer connecting the wiring member and any one of the first bus bar electrode and the second bus bar electrode. A distance between an end portion of the resin adhesive layer on the adjacent side and an end portion, on the adjacent side, of the solar cell provided with the resin adhesive layer is longer than a distance between the end portion of the solar cell and an end portion of the adjacent solar cell. | 2016-05-05 |
| 20160126388 | SOLAR CELL ARRAY, SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - A solar cell array comprises a plurality of solar cells and a metal wire disposed on adjacent solar cells. The metal wire extends between a surface of a first cell and a surface of a second cell adjacent to the first cell in a serpentine pattern of at least two passes on each cell. The solar cell array also comprises a plurality of secondary grid lines disposed on front surfaces of each cell and welded with the at least two passes. | 2016-05-05 |
| 20160126389 | SOLAR CELL UNIT, SOLAR CELL ARRAY, SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - In one aspect, a solar cell unit comprises a cell. The cell includes a cell substrate and a plurality of secondary grid lines disposed on a front surface of the cell substrate. The solar cell unit also comprises a plurality of conductive wires spaced apart from each other. The plurality of conductive wires intersects and is connected with the secondary grid lines. At least one secondary grid line has at least one gap located between adjacent conductive wires. | 2016-05-05 |
| 20160126390 | SOLAR CELL UNIT, SOLAR CELL ARRAY, SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - A solar cell unit comprises a cell. The cell includes a cell substrate and a secondary grid line disposed on a front surface of the cell substrate. The solar cell unit also comprises a conductive wire intersecting and welded with the secondary grid line. The solar cell unit further comprises a welding portion disposed in a welding position of the secondary grid line with the conductive wire. The welding portion has a projection area larger than that of the secondary grid line with an equal length to the welding portion in a non-welding position. | 2016-05-05 |
| 20160126391 | SOLAR CELL MODULE AND MANUFACTURING METHOD THEREOF - The present disclosure discloses a solar cell module and a manufacturing method thereof. The solar cell module includes an upper glass plate, a front adhesive layer, a solar cell array, a back adhesive layer and a back plate superposed in sequence. The back plate is a water vapor insulation back plate having a transmission rate less than or equal to 0.1 mg/m | 2016-05-05 |
| 20160126392 | SOLAR-CELL MODULE - This solar-cell module is provided with a plurality of solar cells and a connecting member that connects the light-receiving-surface side of one solar cell to the back-surface side of an adjacent solar cell. Said connecting member comprises a conductor that includes the following: a flat section laid out on the light-receiving-surface side of the aforementioned one solar cell, a flat section laid out on the back-surface side of the other solar cell, and a middle section that joins said flat sections to each other. The hardness of a boundary region between one of the flat sections and the middle section is no more than 1.25 times the hardness of that flat section. | 2016-05-05 |
| 20160126393 | AERODYNAMIC SOLAR PODS - A solar pod system, comprising of an oval transparent enclosure. The oval transparent enclosure encapsulates a circular paraboloidal reflector mounted on solar cell. The solar cell extends over the circular parabolic reflector to place the focus of the paraboloidal reflector on the solar cell, whereby the solar cell receives light reflected by the circular parabolic reflector. | 2016-05-05 |
| 20160126394 | PHOTOVOLTAIC CELL AND METHOD FOR MANUFACTURING SUCH A PHOTOVOLTAIC CELL - A photovoltaic cell includes a semiconductor substrate of a first conductivity type, with a first surface arranged with a highly doped surface field layer of the first conductivity type. The substrate has on the highly doped surface field layer at least one contacting area for contacting the surface field layer with a respective contact. In the first surface at the location of the at least one contacting area a doping concentration in the highly doped surface field layer is increased relative to the doping concentration in the surface area outside the first contacting area, and in the first surface at the location of each contacting area the highly doped surface field layer has a profile depth that is larger than a profile depth of the doped surface field layer outside the contacting area. | 2016-05-05 |
| 20160126395 | PHOTOVOLTAIC DEVICES AND METHOD OF MANUFACTURING - A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer. | 2016-05-05 |
| 20160126396 | PHOTOVOLTAIC DEVICES AND METHOD OF MANUFACTURING - A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer. | 2016-05-05 |
| 20160126397 | Photovoltaic Device Including a Back Contact and Method of Manufacturing - A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer. | 2016-05-05 |
| 20160126398 | PHOTOVOLTAIC DEVICES INCLUDING DOPED SEMICONDUCTOR FILMS - A photovoltaic cell can include a dopant in contact with a semiconductor layer. | 2016-05-05 |
| 20160126399 | Solar Cell, Production Method Therefor, and Solar Cell Module - A solar cell of the invention includes a collecting electrode on a first principal surface of a photoelectric conversion section. The collecting electrode includes a first electroconductive layer and a second electroconductive layer in this order from the photoelectric conversion section. On the first principal surface of the photoelectric conversion section, an insulating layer is provided in a first electroconductive layer-non-formed region where the first electroconductive layer is not formed. The insulating layer includes a first insulating layer is in contact with the first electroconductive layer on the first principal surface of the photoelectric conversion section, and a second insulating layer that is formed so as to cover at least a part of the first insulating layer. | 2016-05-05 |
| 20160126400 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell and a method for manufacturing the same are disclosed. The solar cell includes a semiconductor substrate containing impurities of a first conductive type, a tunnel layer positioned on the semiconductor substrate, an emitter region positioned on the tunnel layer and containing impurities of a second conductive type opposite the first conductive type, a dopant layer positioned on the emitter region and formed of a dielectric material containing impurities of the second conductive type, a first electrode connected to the semiconductor substrate, and a second electrode configured to pass through the dopant layer and connected to the emitter region. | 2016-05-05 |
| 20160126401 | TANDEM PHOTOVOLTAIC DEVICE - A tandem solar cell. The tandem solar cell includes a bottom cell, a joining layer directly on the bottom cell, and a top cell directly on the joining layer. The bottom cell is a silicon solar cell and the joining layer includes a transparent conductive oxide layer. The transparent conductive layer facilitates the flow of current through the device, and passivates the silicon bottom cell. | 2016-05-05 |
| 20160126402 | SYSTEMS AND METHODS FOR DETECTORS HAVING IMPROVED INTERNAL ELECTRICAL FIELDS - A radiation detector is provided including a cathode, an anode, and a semiconductor wafer. The semiconductor wafer has opposed first and second surfaces. The cathode is mounted to the first surface, and the anode is mounted to the second surface. The semiconductor wafer is configured to be biased by a voltage between the cathode and the anode to generate an electrical field in the semiconductor wafer and to generate electrical signals responsive to absorbed radiation. The electrical field has an intensity having at least one local maximum disposed proximate to a corresponding at least one of the first surface or second surface. | 2016-05-05 |
