| 18th week of 2016 patent applcation highlights part 62 |
| Patent application number | Title | Published |
|---|
| 20160126203 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. | 2016-05-05 |
| 20160126204 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: arranging a solder material containing at least tin, between a semiconductor element and a joined member provided with a nickel layer and a copper layer, such that the solder material is in contact with the copper layer, the nickel layer being provided on a surface of the joined member, and the copper layer being provided on at least a portion of a surface of the nickel layer; and melting and solidifying the solder material to form Cu | 2016-05-05 |
| 20160126205 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICE - A semiconductor device includes first and second semiconductor elements and first and second conductive members. A first electrode on the first semiconductor element is bonded to a first stack part of the first conductive member by a first bonding layer. A second electrode on the second semiconductor element is bonded to a second stack part of the second conductive member by a second bonding layer. A first joint part of the first conductive member is bonded to a second joint part of the second conductive member by an intermediate bonding layer. A first surface of the first joint part facing the second joint part, a side surface of the first joint part continuous from the first surface, a second surface of the second joint part facing the first joint part, and a side surface of the second joint part continuous from the second surface are covered by nickel layers. | 2016-05-05 |
| 20160126206 | THICK-SILVER LAYER INTERFACE - A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer. | 2016-05-05 |
| 20160126207 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a joined member that is joined to the semiconductor element and includes a nickel film; and a joining layer that is joined to the joined member and contains 2.0 wt % or higher of copper, in which the joining layer includes a solder portion and a Cu | 2016-05-05 |
| 20160126208 | COATED BONDING WIRE AND METHODS FOR BONDING USING SAME - A semiconductor device includes a bond formed on a bond pad. The bond is formed of a wire that includes a central core of conductive metal, a first coating over the central core of conductive metal that is more chemically active than the conductive metal, and a second coating over the central core of conductive metal that is less chemically active than the central core of conductive metal. | 2016-05-05 |
| 20160126209 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an insulating substrate including an insulating plate and a circuit board on the insulating plate; a semiconductor chip having an electrode on a front surface thereof, a back of the semiconductor chip being fixed to the circuit board; a printed circuit board that faces the circuit board and the front surface of the semiconductor chip; and one or more conductive posts each having one end connected via solder to the circuit board or to the electrode on the semiconductor chip, another end connected to the printed circuit board, and one or more grooves that extend from said one end of the conductive post that contacts the solder to said another end of the conductive post connected to the printed circuit board. | 2016-05-05 |
| 20160126210 | Electronic Component, System and Method - In an embodiment, an electronic component includes a power semiconductor device embedded in a dielectric core layer and at least one contact layer protruding from a first side face of the dielectric core layer. The contact layer includes an electrically insulating layer and at least one contact pad arranged on the electrically insulating layer. The at least one contact pad is electrically coupled with the power semiconductor device. | 2016-05-05 |
| 20160126211 | SEMICONDUCTOR ARRANGEMENT, METHOD FOR PRODUCING A SEMICONDUCTOR CHIP - A semiconductor assembly is described. In accordance with one example of the invention, the semiconductor assembly comprises a semiconductor body, a top main electrode arranged on a top side, a bottom main electrode arranged on an underside, and a control electrode arranged on the top side. The semiconductor assembly further includes a spring element for the pressure contacting of the control electrode with a pressure force generated by the spring element. | 2016-05-05 |
| 20160126212 | CHIP ASSEMBLAGE, PRESS PACK CELL AND METHOD FOR OPERATING A PRESS PACK CELL - One aspect of the invention relates to a chip assemblage. The latter comprises a number of semiconductor chips, each of which has a semiconductor body having an underside, and also a top side, which is spaced apart from the underside in a vertical direction. A top main electrode is arranged on the top side and a bottom main electrode is arranged on the underside. Moreover, each of the semiconductor chips has a control electrode, by means of which an electric current between the top main electrode and the bottom main electrode can be controlled. The semiconductor chips are connected to one another by a dielectric embedding compound to form a solid assemblage. The chip assemblage additionally comprises a common control terminal, and a common reference potential terminal. The common control terminal is electrically conductively connected to each of the control electrodes via a control electrode interconnection structure, and the common reference potential terminal is electrically conductively connected to each of the first main electrodes via a main electrode interconnection structure. Moreover, a dedicated, electrically conductive top compensation lamina is present for each of the semiconductor chips, said top compensation lamina being arranged on that side of the top main electrode which faces away from the semiconductor body and being cohesively and electrically conductively connected to the top main electrode. | 2016-05-05 |
| 20160126213 | THERMO-COMPRESSION BONDING SYSTEM, SUBSYSTEMS, AND METHODS OF USE - Co-planarity adjustment systems and methods, gantries capable of applying high force without imposing moment loads to their bearings, systems and methods for achieving rapid heating and cooling and efficient slidable seal systems capable of sealing a chamber and injecting one or more fluids into the chamber as well as actively recovering portions of such fluid which have migrated into the seal itself are disclosed in the context of thermo-compression bonding systems, apparatuses and methods, although many alternative uses will be apparent to those of skill in the art. | 2016-05-05 |
| 20160126214 | SEMICONDUCTOR PACKAGE WITH ADHESIVE MATERIAL PRE-PRINTED ON THE LEAD FRAME AND CHIP, AND ITS MANUFACTURING METHOD - This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity. | 2016-05-05 |
| 20160126215 | METHOD FOR ASSEMBLING TWO SUBSTRATES OF DIFFERENT NATURES VIA A DUCTILE INTERMEDIATE LAYER - A method for manufacturing a heterostructure, including: contacting a first substrate having a first coefficient of thermal expansion and a second substrate having a different second coefficient of thermal expansion; annealing an assembly formed by contacting the first substrate and the second substrate; after annealing, returning the assembly to room temperature; providing, before the contacting, at least one intermediate layer at a surface of at least one of the first and second substrates, the at least one intermediate layer being made of a material which is ductile during the annealing and returning to room temperature; performing the contacting with the at least one intermediate layer sandwiched between the first and the second substrates; upon returning to room temperature, applying an outer pressure to the assembly to maintain it compressed. | 2016-05-05 |
| 20160126216 | Method of forming an interconnection and arrangement for a direct interconnect chip assembly - Various embodiments provide a method of forming an interconnection between an electric component and an electronic component, wherein the method comprises forming a first interconnection sublayer on an electric component, wherein the first interconnection sublayer comprises a metal and has a main surface opposite to the electric component, wherein the main surface has a first surface roughness; forming a second interconnection sublayer on an electronic component, wherein the second interconnection sublayer comprises the metal and has a surface opposite to the electronic component, wherein the surface has a second surface roughness, wherein the first surface roughness and the second surface roughness are in the same order of magnitude; and interconnecting the first interconnection sublayer and the second interconnection sublayer by contacting the same and applying pressure and heat to the contacted first and second interconnection sublayers. | 2016-05-05 |
| 20160126217 | SYSTEMS, METHODS AND DEVICES FOR INTER-SUBSTRATE COUPLING - Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets. | 2016-05-05 |
| 20160126218 | BONDING METHOD OF SEMICONDUCTOR CHIP AND BONDING APPARATUS OF SEMICONDUCTOR CHIP - According to one embodiment, there is provided a bonding method of a semiconductor chip. The bonding method includes arranging an activated front surface of a semiconductor chip and an activated front surface of a substrate so as to face each other with a back surface of the semiconductor chip attached to a sheet. The bonding method includes pushing the back surface of the semiconductor chip through the sheet to closely attach the activated front surface of the semiconductor chip and the activated front surface of the substrate. The bonding method includes stripping the sheet from the back surface of the semiconductor chip while maintaining a state in which the activated front surface of the semiconductor chip is closely attached to the activated front surface of the substrate. | 2016-05-05 |
| 20160126219 | PACKAGE INCLUDING A SEMICONDUCTOR DIE AND A CAPACITIVE COMPONENT - In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar. | 2016-05-05 |
| 20160126220 | Electrostatic Discharge Protection Structure and Method - A semiconductor package comprises a top package and a bottom package with a plurality of fan-out interconnect structures. A plurality of inter-package connectors are formed inside a gap between the top package and the bottom package. A conductive protection layer is formed over the semiconductor package, wherein the conductive protection layer seals the gap around its perimeter, wherein the conductive protection layer covers an upper surface and a side wall of the top package, and wherein the conductive protection layer covers portions of an upper surface of the bottom package that extend beyond a boundary of the top package and a top portion of a side wall of the bottom package. | 2016-05-05 |
| 20160126221 | LIGHT-EMITTING DIODE MODULE - A light-emitting diode module for emitting white light includes a first light emitting diode chip for generating radiation in the blue spectral range having a first peak wavelength, a second light emitting diode chip for generating radiation in the blue spectral range having a second peak wavelength, a third light emitting diode chip for generating radiation in the red spectral range having a third peak wavelength, a first and a second phosphors disposed downstream of the first and the second light emitting diode chips, respectively. The first light emitting diode chip with the first phosphor generates a first mixed radiation and the second light emitting diode chip with the second phosphor generates a second mixed radiation. The first phosphor exhibits a first absorption maximum at a wavelength greater than the first peak wavelength. The second phosphor exhibits a second absorption maximum at a wavelength less than the second peak wavelength. | 2016-05-05 |
| 20160126222 | LIGHT-EMITTING DIODE LIGHTING DEVICE - A light-emitting diode (LED) lighting device includes a substrate, a first bottom electrode, a bottom transparent isolation layer, a first vertical LED, a second vertical LED, a first top transparent electrode, and a second top transparent electrode. The first bottom electrode is disposed on the substrate and is reflective. The first vertical LED and the second vertical LED are disposed on the first bottom electrode. The bottom transparent isolation layer covers the substrate and the first bottom electrode and exposes the first vertical LED and the second vertical LED. The first top transparent electrode is electrically connected to the first vertical LED. The second top transparent electrode is electrically connected to the second vertical LED. The first top transparent electrode, the second top transparent electrode, and the first bottom electrode cooperate to electrically connect the first vertical LED and the second vertical LED in series. | 2016-05-05 |
| 20160126223 | LIGHT-EMITTING DIODE LIGHTING DEVICE - A light-emitting diode (LED) lighting device includes a substrate, a first bottom electrode, a bottom transparent isolation layer, a first vertical LED, a second vertical LED, a first top transparent electrode, and a second top transparent electrode. The substrate has a first recess therein. The first bottom electrode is disposed in the first recess and is reflective. The first vertical LED and the second vertical LED are disposed in the first recess and on the first bottom electrode. The first bottom transparent isolation layer is disposed in the first recess. The first top transparent electrode is electrically connected to the first vertical LED. The second top transparent electrode is electrically connected to the second vertical LED. The first top transparent electrode, the second top transparent electrode, and the first bottom electrode cooperate to electrically connect the first vertical LED and the second vertical LED in series. | 2016-05-05 |
| 20160126224 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a first electrode; a second electrode; and a plurality of semiconductor light emitting devices coupled to a conductive adhesive layer, and electrically connected to the first electrode and the second electrode, wherein at least one of the plurality of semiconductor light emitting devices includes: a first conductive electrode and a second conductive electrode spaced from each other; a protruding unit extending from the second conductive electrode, and protruding from a side surface of at least one of the plurality of semiconductor light emitting devices; and a protection unit configured to cover at least part of the protruding unit for protection of the protruding unit. | 2016-05-05 |
| 20160126225 | LIGHT-EMITTING DEVICE - A light-emitting device includes light-emitting units and an electrical connection layer. Each light-emitting unit includes a light-emitting stacking layer, a first electrode layer, an insulation layer, and a second electrode layer. The light-emitting stacking layer includes first and second-type doped semiconductor layers, an active layer, and a first inner opening passing through the second-type doped semiconductor layer and the active layer. The second electrode layer is close to and is electrically connected to the second-type doped semiconductor layer. The insulation layer is disposed on a sidewall of the first inner opening and forms a second inner opening. The first electrode layer is disposed in the second inner opening and electrically connected to the first-type doped semiconductor layer. The electrical connection layer is electrically connected to the first electrode layer of one of two adjacent light-emitting units and the second electrode layer of the other adjacent light-emitting unit. | 2016-05-05 |
| 20160126226 | Integrated Fan-Out Structure and Method - A semiconductor package comprises a top package and a bottom package with fan-out interconnect structures. A plurality of inter-package connectors electrically connect the top package and the bottom package, and are located near a perimeter of the semiconductor package. A first material is located in a space delimited by a lower surface of the top package, an upper surface of the bottom package, and the inner-most inter-package connectors of the semiconductor package, wherein the first material partially fills the space. A second material different from the first material encapsulates the inter-package connectors. | 2016-05-05 |
| 20160126227 | Method for Attaching a Semiconductor Die to a Carrier - A method for fabricating an electronic device includes providing a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first semiconductor die and a first solder interconnect layer applied to a main face of the first semiconductor die. The second semiconductor chip has a second semiconductor die, an insulating layer applied to a main face of the second semiconductor die, and a second solder interconnect layer applied to the insulating layer. The method further includes attaching the first semiconductor chip with the first solder interconnect layer to a first carrier and attaching the second semiconductor chip with the second solder interconnect layer to a second carrier. | 2016-05-05 |
| 20160126228 | FAN-OUT WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures. | 2016-05-05 |
| 20160126229 | SEMICONDUCTOR CHIP AND A SEMICONDUCTOR PACKAGE HAVING A PACKAGE ON PACKAGE (POP) STRUCTURE INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate. | 2016-05-05 |
| 20160126230 | TRIPLE STACK SEMICONDUCTOR PACKAGE - A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals. | 2016-05-05 |
| 20160126231 | LEDGE-FREE DISPLAY - This disclosure provides systems, methods and apparatus for a ledge-free display. In one aspect, row driver circuits and column driver circuits may be provided from the backside of the display to reduce the size of the bezel around the display and eliminate the need for a bonding ledge for a ledge-free display. | 2016-05-05 |
| 20160126232 | CIRCUIT LAYOUT, LAYOUT METHOD AND SYSTEM FOR IMPLEMENTING THE METHOD - A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second finger group, the first finger group comprising a first number of fingers, and the second finger group comprising a second number of fingers. The circuit layout further includes a second device having a second set of fingers, wherein the second set of fingers includes a third finger group having a third number of fingers. The first finger group, the second finger group and the third finger group extend across a first doped region, and the third finger group is between the first finger group and the second finger group. | 2016-05-05 |
| 20160126233 | METHOD AND CIRCUITRY FOR ON-CHIP ELECTRO-STATIC DISCHARGE PROTECTION SCHEME FOR LOW COST GATE DRIVER INTEGRATED CIRCUIT - An apparatus includes an integrated circuit, a plurality of bi-directional pins, and an electro-static discharge (ESD) clamp. The integrated circuit is configured to provide a ground potential. The plurality of bi-directional pins are configured to provide a differential input signal for the integrated circuit. The electro-static discharge (ESD) clamp is coupled between the ground potential and the plurality of bi-directional pins. | 2016-05-05 |
| 20160126234 | BIPOLAR TRANSISTOR INCLUDING LATERAL SUPPRESSION DIODE - A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a lateral suppression diode. The emitter is disposed at a top surface of the transistor and configured to receive electrical current from an external source. The base is configured to conduct the electrical current from the collector to the emitter. The base is disposed at the top surface of the transistor and laterally between the emitter and the collector. The collector is configured to attract and collect minority carriers from the base. The cathode of the first conductivity type is surrounded by the base and disposed between the emitter and the collector, and the cathode is configured to suppress a lateral flow of the minority carriers from the base to the collector. | 2016-05-05 |
| 20160126235 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode. | 2016-05-05 |
| 20160126236 | METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a semiconductor device may include a first transistor having a first current carrying electrode, a second current carrying electrode, and a control electrode; a first bipolar transistor having a collector coupled to the first current carrying electrode of the first transistor, a base coupled to the second current carrying electrode of the first transistor, and an emitter of the first bipolar transistor coupled to a first node of the semiconductor device. In an embodiment, the first node is connected to a terminal of a semiconductor package. An embodiment may include a semiconductor component coupled between the base of the first bipolar transistor and the emitter of the second bipolar transistor. | 2016-05-05 |
| 20160126237 | SEMICONDUCTOR DEVICE - A semiconductor device including metal-on-semiconductor (MOS) and bipolar junction (BJ) structures formed in a substrate. The MOS structure includes a first region, a second region formed over the first region, a third region, and a fourth region formed over the third region. The first, second, and fourth regions have a first-type conductivity, being drain region, drain electrode, and source region of the MOS structure. Doping level of the second region is higher than that of the first region. The third region has a second-type conductivity, including channel and body regions of the MOS structure. The channel region is formed between the first and fourth regions. The BJ structure includes a fifth region formed over the first region, contacting the second region, having the second-type conductivity, and being an emitter region of the BJ structure. The second and third regions are base and collector regions of the BJ structure. | 2016-05-05 |
| 20160126238 | POWER SOURCE CIRCUIT, ELECTRONIC CIRCUIT, AND INTEGRATED CIRCUIT - A power source circuit includes: a P-type transistor one of a source and a drain of which is connected to a first power source line and the other of the source and the drain of which is connected to an output node; a resistor connected between a back gate of the P-type transistor and the first power source line; and a capacitance element connected to the back gate of the P-type transistor and to a second power source line having a potential lower than a potential of the first power source line. | 2016-05-05 |
| 20160126239 | INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM MIM CAPACITOR MATERIAL AND METHODS FOR FABRICATING SAME - Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area. | 2016-05-05 |
| 20160126240 | METHODS AND APPARATUSES FOR FORMING MULTIPLE RADIO FREQUENCY (RF) COMPONENTS ASSOCIATED WITH DIFFERENT RF BANDS ON A CHIP - A device includes a first radio frequency (RF) component on a die. The first RF component includes a first lightly doped region having a first value of a characteristic, and the first RF component is configured to operate in a first RF band associated with a first frequency. The device further includes a second RF component on the die. The second RF component includes a second lightly doped region having a second value of the characteristic that is different from the first value. The second RF component is configured to operate in a second RF band associated with a second frequency that is different from the first frequency. | 2016-05-05 |
| 20160126241 | ENHANCEMENT-DEPLETION MODE INVERTER WITH TWO TRANSISTOR ARCHITECTURES - An enhancement-depletion-mode inverter includes a load transistor and a drive transistor. The load transistor has a top gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The load transistor is configured to operate in a depletion mode. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness that is different from the load dielectric thickness. The drive transistor is configured to operate in a normal mode or an enhancement mode. The first source is electrically connected to the second drain and the first gate. | 2016-05-05 |
| 20160126242 | ENHANCEMENT MODE INVERTER WITH VARIABLE THICKNESS DIELECTRIC STACK - An enhancement-mode inverter includes a load transistor and a drive transistor. The load transistor has a bottom gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness less than the load dielectric thickness. The first source is electrically connected to the second drain and the first gate is electrically connected to the first drain. The load gate dielectric and the drive gate dielectric are part of a common shared dielectric stack. | 2016-05-05 |
| 20160126243 | Semiconductor Device with Enhancement and Depletion FinFET Cells - A semiconductor device includes enhancement FinFET cells and depletion FinFET cells. The enhancement FinFET cells include first gate structures separating first semiconductor fins. The depletion FinFET cells include second gate structures separating second semiconductor fins. Between the first and second gate structures a connection structure separates the first semiconductor fins from the second semiconductor fins. The connection structure has a specific conductance which is higher than a specific conductance in the second semiconductor fins. | 2016-05-05 |
| 20160126244 | FORMING IV FINS AND III-V FINS ON INSULATOR - A semiconductor structure including: a set of first fins in a pFET region and a set of second fins in an nFET region, the first fins and the second fins are on a buried insulator layer, the first fins have a bottom surface coplanar with a bottom surface of the second fins, the first fins have a first pitch between adjacent first fins that is equal to a second pitch between adjacent second fins, the first fins include a group IV semiconductor material, the second fins include a group III-V semiconductor material. | 2016-05-05 |
| 20160126245 | EMBEDDED DRAM IN REPLACEMENT METAL GATE TECHNOLOGY - Methods for forming an eDRAM with replacement metal gate technology and the resulting device are disclosed. Embodiments include forming first and second dummy electrodes on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an ILD; removing the first and second dummy electrodes, forming first and second cavities, respectively; forming a hardmask over the substrate, exposing the first cavity; forming a deep trench in the substrate through the first cavity; removing the hardmask; and forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity. | 2016-05-05 |
| 20160126246 | INTEGRATED CIRCUIT DEVICES HAVING METAL-INSULATOR-SILICON CONTACT AND METHODS OF FABRICATING THE SAME - Integrated circuit devices and methods of forming the devices are provided. The devices may include an active area, a gate electrode in the active area and a source/drain area adjacent a side of the gate electrode in the active area. The source/drain area may include a doped semiconductor material. The devices may also include an interlayer insulating layer on the active area, and the interlayer insulating layer may include a recess exposing an upper surface of the source/drain area. The devices may further include a conductive plug that is in the recess and includes a first metal and an insulating layer that is in the recess and includes a second metal. The insulating layer may be between the upper surface of the source/drain area and a lower surface of the conductive plug and may contact the doped semiconductor material. | 2016-05-05 |
| 20160126247 | NONVOLATILE MEMORY DEVICES HAVING SINGLE-LAYERED GATES - A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates. | 2016-05-05 |
| 20160126248 | BAND GAP TAILORING FOR A TUNNELING DIELECTRIC FOR A THREE-DIMENSIONAL MEMORY STRUCTURE - The band gap structure of a tunneling dielectric can be tailored to facilitate programming and erasing of stored information, while enhancing charge storage during states without electrical bias between a semiconductor channel and charge storage elements. The tunneling dielectric includes a layered stack including at least, from outside to inside, a dielectric metal oxide layer and a silicon oxide layer. Upon application of electrical bias for programming or erasing, the band gap structure of the tunneling dielectric provides a lower tunneling barrier than an ONO stack of a comparable effective oxide thickness. Additionally, due to higher capacitive coupling to the channel with high-k metal oxide layer(s) in the tunneling dielectric, the efficiency of program, erase and read operations can be improved. During a zero-bias state, the tunneling dielectric can provide a higher energy barrier than the ONO stack, thereby providing enhanced data retention than the ONO stack. | 2016-05-05 |
| 20160126249 | FINFET VERTICAL FLASH MEMORY - A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions. | 2016-05-05 |
| 20160126250 | CHARGE-TRAPPING MEMORY DEVICE - A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region. | 2016-05-05 |
| 20160126251 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate that includes a first region and a second region; a stacked body that is disposed on the first region of the substrate and includes a plurality of first metal layers and a plurality of voids each of which is disposed between the plurality of first metal layers; a columnar portion that penetrates the stacked body, extends in a direction of stacking in the stacking body; a transistor that is disposed on the second region; and the interconnect portion that is disposed on the transistor and includes the plurality of first metal layers and a plurality of second metal layers each of which is disposed between the plurality of first metal layers. The transistor is electrically connected to the channel body or the first metal layer of the stacked body through a interconnect portion. | 2016-05-05 |
| 20160126252 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film. | 2016-05-05 |
| 20160126253 | Semiconductor Memory Devices Having Increased Distance Between Gate Electrodes and Epitaxial Patterns and Methods of Fabricating the Same - A semiconductor memory device is provided including a substrate, a plurality of interlayer insulating layers and gate electrodes alternately stacked on the substrate. The plurality of interlayer insulating layers and the gate electrodes define a channel hole that vertically penetrates the plurality of interlayer insulating layers and the gate electrodes to expose at least a portion of the substrate. A channel recess is provided in the substrate exposed by the channel hole. An epitaxial pattern fills the channel recess. The epitaxial pattern has an upper surface that is concave and curves inward in a middle portion thereof | 2016-05-05 |
| 20160126254 | DISPLAY DEVICE - A display device includes a first substrate and an insulating layer over the first substrate. The display device further includes a semiconductor layer over the insulating layer and a dielectric layer over the semiconductor layer, having an opening partially exposing the semiconductor layer and the insulating layer, wherein the opening has a first width along a first direction. In addition, the display device further includes a conductive line extending over the dielectric layer along a second direction that is different from the first direction and filling the opening to electrically connect to the semiconductor layer exposed by the opening. The conductive line includes a first portion over a top surface of the dielectric layer and a second portion in the opening. The first portion of the conductive line has a second width along the first direction. The first width is greater than the second width. | 2016-05-05 |
| 20160126255 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a gate metal pattern including a gate line on a base substrate and extending in a first direction, and a gate electrode electrically connected with the gate line, a data metal pattern on the gate metal pattern and including a data line extending in a second direction crossing the first direction, a source electrode electrically connected with the gate line and a drain electrode spaced apart from the source electrode, a first electrode pattern on the data metal pattern, a low-resistance electrode pattern on the first electrode pattern and entirely overlapping with the gate metal pattern and the data metal pattern and a second electrode pattern overlapping with the first electrode pattern. | 2016-05-05 |
| 20160126256 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A TFT substrate including a base substrate that includes a plurality of pixel areas; a gate line on the base substrate and extending in a first direction; a data line on the gate line and extending in a second direction; a TFT connected to the gate line and the data line, the TFT including a gate electrode, a semiconductor pattern, and source and drain electrodes, the semiconductor pattern overlapping the gate electrode, the source electrode and the drain electrode overlapping the semiconductor pattern, and the drain electrode being spaced apart from the source electrode; an inorganic insulating pattern covering the data line, the inorganic insulating pattern including an opening aligned with the pixel areas; a shielding electrode overlapping the data line, the shielding electrode on the inorganic insulating pattern; and a pixel electrode on the pixel areas, the pixel electrode being electrically connected to the drain electrode through a first contact hole. | 2016-05-05 |
| 20160126257 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - An array substrate includes a substrate, a plurality of gate lines and a plurality of data lines intersecting each other and being insulating from each other, and a plurality of pixel units arranged in an array and surrounded by the intersecting gate lines and data lines. The array substrate also includes at least one temperature measuring unit and at least one gate signal start control line. The temperature measuring unit includes at least one thin film transistor. The array substrate further includes a signal input line, a signal output line, and resistor is arranged on the signal input line. The temperature measuring unit includes a first terminal electrically connected with the signal input line and a second terminal electrically connected with the signal output line. | 2016-05-05 |
| 20160126258 | LOW TEMPERATURE POLY-SILICON ARRAY SUBSTRATE AND FORMING METHOD THEREOF - A low temperature poly-silicon (LTPS) array substrate is disclosed. The array substrate includes a first substrate and a stack structure on the first substrate, where the stack structure includes a first conductive layer, and a second conductive layer. The first and second conductive layers are insulated from each other. The array substrate also includes a polysilicon layer above the first and second conductive layers, an interlayer insulating layer above the polysilicon layer, and a source-drain metal layer on the interlayer insulating layer. The source-drain metal layer includes a source and a drain, the source and the drain are electrically connected with the polysilicon layer through a first via, and one of the source and the drain is electrically connected with the first conductive layer through a second via. | 2016-05-05 |
| 20160126259 | ARRAY SUBSTRATE AND METHOD OF PRODUCING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE - Embodiments of the present invention provide an array substrate and a method of producing the same, a display panel and a display device, solving problems of detaching of film formed by CVD in the array substrate in prior art. The array substrate includes a plurality of data lines and a plurality of gate lines that are disposed in cross orientation. The array substrate further includes: a conductive repairing structure located at a damaged region of the data line and/or a damaged region of the gate line; and an insulating protective film configured to cover a region where at least one conductive repairing structure is located. As the region where the at least one conductive repairing structure is located is covered by the insulating protective film, the conductive repairing structure covered by the insulating protective film is not prone to be detached off. | 2016-05-05 |
| 20160126260 | LIQUID CRYSTAL DISPLAY - A liquid crystal display including a plurality of pixels that display an image, each pixel includes a thin film transistor that includes a gate electrode, a source electrode having a bar-shape and partially overlapping the gate electrode, and a drain electrode facing the source electrode at a location corresponding to the gate electrode, the drain electrode includes a first end portion having a C-shape that surrounds a distal end of the bar-shaped source electrode. This design eliminates an overlap between a data line and the gate electrode, which eliminates an overlap between the data line and the channel area of a semiconductor layer, which reduces a parasitic capacitor of the data line, resulting in less current to drive the data line, resulting in reduced power consumption of the display. | 2016-05-05 |
| 20160126261 | ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, AND DISPLAY DEVICE - The present invention provides an array substrate, a method of fabricating the array substrate, and a display device. The method of fabricating the array substrate of the present invention comprises steps of: sequentially forming a first transparent conductive film and a source-drain metal film on a substrate; forming a source-drain metal pattern by performing a patterning process on the source-drain metal film; forming a pattern comprising a pixel electrode and a compensation structure that is provided below the source-drain metal pattern by performing a patterning process on the first transparent conductive film. | 2016-05-05 |
| 20160126262 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device is disclosed. In one aspect, the device includes a plurality of pixels. Each of the pixels includes a first thin-film transistor (TFT) formed over a substrate and comprising gate electrode, a source electrode, and a drain electrode. Each pixel also includes a storage capacitor formed over the substrate, wherein the storage capacitor includes first and second electrodes, and a dielectric layer interposed between the first and second electrodes. The first electrode, the dielectric layer, and the second electrode have substantially the same pattern. | 2016-05-05 |
| 20160126263 | Manufacturing method of a thin film transistor and pixel unit thereof - The present invention provides a method of manufacturing a thin film transistor pixel unit, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate, wherein the metal oxide layer is in a thin film transistor region; through a same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate for forming a gate region, source and drain regions for forming contact vias, a gate interface region, and a storage capacitor region, respectively. Through additional steps including etching, metallizing, and filling, a source contact via is formed in the source region, a drain contact via is formed in the drain region, and a connecting contact via is formed in the gate interface region, respectively. | 2016-05-05 |
| 20160126264 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. | 2016-05-05 |
| 20160126265 | IMAGE SENSOR HAVING IMPROVED QUANTUM EFFICIENCY AT LARGE WAVELENGTHS - The invention relates to an image sensor specially adapted to vision in low-light conditions (notably night vision).The sensor is formed on an integrated circuit chip starting from a silicon substrate. It comprises: a matrix of rows and columns of active pixels each comprising at least one photodiode and transistors, control circuits for the matrix, external to the matrix, and signal read circuits, external to the matrix. The photodiodes of the sensor are formed within an active layer of single-crystal silicon whose resistivity is at least 500 ohms·cm if this active layer is an epitaxial layer grown on the silicon substrate and at least 2000 ohms·cm if this active layer consists of the upper part of the silicon substrate. The control circuits and the read circuits of the sensor are formed in at least one doped global well, of the same type as the active layer of single-crystal silicon and having a resistivity lower than or equal to 30 ohms·cm, this well being formed within the active layer and not including the matrix. | 2016-05-05 |
| 20160126266 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode. | 2016-05-05 |
| 20160126267 | IMAGING SYSTEMS WITH BACKSIDE ISOLATION TRENCHES - An image sensor such as a backside illumination image sensor may be provided with analog circuitry, digital circuitry, and an image pixel array on a semiconductor substrate. Trench isolation structures may separate the analog circuitry from the digital circuitry on the substrate. The trench isolation structures may be formed from dielectric-filled trenches in the substrate that isolate the portion of the substrate having the analog circuitry from the portion of the substrate having the digital circuitry. The trench isolation structures may prevent digital circuit operations such as switching operations from negatively affecting the performance of the analog circuitry. Additional trench isolation structures may be interposed between portions of the substrate on which bond pads are formed and other portions of the substrate to prevent capacitive coupling between the bond pad structures and the substrate, thereby enhancing the high frequency operations of the image sensor. | 2016-05-05 |
| 20160126268 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND CAMERA MODULE - Certain embodiments provide a solid-state imaging device including: a semiconductor substrate having a top surface on which a light receiving section that receives light is provided, the semiconductor substrate having a through hole which is provided in a part of the semiconductor substrate; an electrode pad provided on the top surface side of the semiconductor substrate including an area right above the through hole to be in contact with the first wiring, the electrode pad having a slit between the area right above the through hole and the first wiring; an insulating film provided on a side surface of the through hole; and a second wiring provided on the insulating film to be in contact with the electrode pad. | 2016-05-05 |
| 20160126269 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device comprises a photodetecting section, an unnecessary carrier capture section, and a vertical shift register. The unnecessary carrier capture section has carrier capture regions arranged in a region between the photodetecting section and the vertical shift register for respective rows. Each of the carrier capture regions includes a transistor and a photodiode. The transistor has one terminal connected to the photodiode and the other terminal connected to a charge elimination line. The charge elimination line is short-circuited to a reference potential line. | 2016-05-05 |
| 20160126270 | ELECTRONIC DEVICE - An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire. | 2016-05-05 |
| 20160126271 | SOLID-STATE IMAGE SENSING DEVICE - A solid-state image sensing device is provided including a first semi-conducting layer of first conductivity, a second semi-conducting layer of first conductivity disposed on the first semi-conducting layer, a semiconductor region of second conductivity different from the first conductivity disposed in the second semi-conducting layer, a deep trench configured to isolate a plurality of neighboring pixels from each other, and an electrode implanted into the deep trench, where the semiconductor region of second conductivity, the second semi-conducting layer, and the first semi-conducting layer are disposed in that order from a proximal side to a distal side, the second semi-conducting layer is split by the deep trench into sections that correspond to the pixels, an impurity concentration of first conductivity of the first semi-conducting layer is higher than an impurity concentration of first conductivity of the second semi-conducting layer, and the deep trench contacts the first semi-conducting layer. | 2016-05-05 |
| 20160126272 | CURVED IMAGE SENSOR, METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME - The curved image sensor may include: a first substrate including a plurality of photoelectric conversion elements and having a curved first surface; a bonding pattern formed over a second surface opposite to the first surface of the first substrate, formed along an edge of the first substrate, and having an opening; a second substrate bonded to the second surface of the first substrate by the bonding pattern; and a sealing material filling the opening so that a cavity defined by the first substrate, the second substrate, and the bonding pattern is sealed by the sealing material. | 2016-05-05 |
| 20160126273 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern. Each of the pixels has a photoelectric conversion portion configured to photoelectrically convert light incident from a rear surface side of a semiconductor substrate. The plurality of on-chip lenses are arranged for every other pixel. The on-chip lenses are larger in size than the pixels. Each of color filters at the pixels where the on-chip lenses are present has a cross-sectional shape whose upper side close to the on-chip lens is the same in width as the on-chip lens and whose lower side close to the photoelectric conversion portion is shorter than the upper side. | 2016-05-05 |
| 20160126274 | IMAGE PICKUP APPARATUS - To provide an image pickup apparatus that can increase capacitance value of an input node in a connection state without decreasing amplification transistor gain when capacitance is in a non-connection state. In an image pickup apparatus according to an aspect of the present disclosure, a gate electrode of an amplification transistor is arranged on a main surface of the semiconductor substrate, a third semiconductor region having a second conductivity type is arranged in a lower part of the gate electrode, and an added impurity concentration of impurity having the second conductivity type on a PN junction surface of a capacitance is higher than a highest value of an added impurity concentration having the second conductivity type in a region from the main surface up to a depth at which a source and a drain of the amplification transistor are arranged in the third semiconductor region. | 2016-05-05 |
| 20160126275 | Imaging Device and Electronic Device - An imaging device that does not need a lens is provided. The imaging device includes a first layer, a second layer, and a third layer. The second layer is positioned between the first layer and the third layer. The first layer includes a diffraction grating. The second layer includes a photoelectric conversion element. The third layer includes a transistor including an oxide semiconductor in an active layer. | 2016-05-05 |
| 20160126276 | SOLID-STATE IMAGING ELEMENT, METHOD OF MANUFACTURING THE SAME, AND IMAGING DEVICE - In pixels that are two-dimensionally arranged in a matrix fashion in the pixel array unit of a solid-state imaging element, a photoelectric conversion film having a light shielding film buried therein is formed and stacked on the light incident side of the photodiode. The present technique can be applied to a CMOS image sensor compatible with the global shutter system, for example. | 2016-05-05 |
| 20160126277 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes a substrate including two or more photoelectric conversion regions corresponding to two or more pixels, respectively, two or more color filters formed on the substrate corresponding to the photoelectric conversion regions, an interlayer insulation layer including an interconnection line and formed on the substrate, two or more condensing patterns each having a plurality of high refractive index regions and a plurality of low refractive index regions, which are alternately disposed, wherein line widths of the high and low refractive index regions are different in the respective condensing patterns depending on the pixels. | 2016-05-05 |
| 20160126278 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD OF THE PHOTOELECTRIC CONVERSION DEVICE - A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member. | 2016-05-05 |
| 20160126279 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto. | 2016-05-05 |
| 20160126280 | SOLID-STATE IMAGE SENSOR AND IMAGING SYSTEM - At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise. | 2016-05-05 |
| 20160126281 | Grounding System for Integrated Circuits of Particular Usefulness for Circuits Incorporating Backside-Illuminated Photosensor Arrays - A backside-illuminated photosensor array IC is formed in a thinned circuit wafer. Silicon is removed in at least one substrate-stripped zone where a doped edge-contact ring surrounds the substrate-stripped zone, the edge-contact ring formed in a same first side of the wafer as a plurality of transistors, and opposite to a backside of the wafer. Backside metal is disposed on the backside of the wafer, the backside metal having window openings over the photosensors, and having sidewalls contacting the edge-contact ring around the substrate-stripped zone. The edge contact region is formed in the first side of the device wafer before providing structural support and thinning the device wafer. Substrate-stripped zones, such as bondpad openings and guardring openings, are formed by removing silicon to expose the edge-contact region, and backside metal is deposited with sidewall metal at edges of the substrate-stripped zones and thereby contacting the edge-contact region. | 2016-05-05 |
| 20160126282 | CMOS IMAGE SENSOR WITH ENHANCED DYNAMIC RANGE - An image sensor includes a semiconductor substrate having a main surface, a transfer transistor having a transfer gate disposed on the main surface, a light-sensing structure on one side of the transfer gate, a floating diffusion node on the other side of the transfer gate, a reset transistor serially connected to the transfer transistor via the floating diffusion node, a source-follower transistor having a source-follower gate, and a vertical capacitor having a first vertical electrode plate and a second vertical electrode plate. The first vertical electrode plate is electrically connected to the source-follower gate and the floating diffusion node. | 2016-05-05 |
| 20160126283 | SEMICONDUCTOR DEVICE, IMAGING DEVICE, AND ELECTRONIC DEVICE - Provided is a novel semiconductor device, a semiconductor device with reduced area, or a versatile semiconductor device. The semiconductor device includes a pixel portion including a first pixel, a second pixel, a third pixel, and a fourth pixel; a first switch and a second switch located outside the first to fourth pixels; a first wiring located outside the first to fourth pixels; a second wiring electrically connected to the first and second pixels; and a third wiring electrically connected to the third and fourth pixels. A first terminal of the first switch is electrically connected to the first wiring. A second terminal of the first switch is electrically connected to the second wiring. A first terminal of the second switch is electrically connected to the first wiring. A second terminal of the second switch is electrically connected to the third wiring. | 2016-05-05 |
| 20160126284 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE - According to an embodiment, provided is a solid-state imaging device. The solid-state imaging device is provided with a semiconductor layer, a gate of a pixel transistor, a gate of a peripheral circuit transistor, a silicon nitride film and a sidewall. A photo diode and a floating diffusion are provided in the semiconductor layer. The gate of the pixel transistor is provided on a surface of the semiconductor layer with the gate oxide film interposed therebetween. The gate of the peripheral circuit transistor is provided on the surface of the semiconductor layer with the gate oxide film interposed therebetween. The silicon nitride film is provided on an upper surface of the photo diode in the semiconductor layer with the gate oxide film interposed therebetween. The sidewall is provided on at least one side surface of the gate of the pixel transistor except for a side surface on the photo diode. | 2016-05-05 |
| 20160126285 | SOLID-STATE IMAGING DEVICE AND IMAGING SYSTEM - A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate. | 2016-05-05 |
| 20160126286 | METHOD FOR PRODUCING IMAGE PICKUP APPARATUS AND METHOD FOR PRODUCING SEMICONDUCTOR APPARATUS - A method for producing an image pickup apparatus includes: a process of cutting an image pickup chip substrate where electrode pads are formed around each of the light receiving sections to fabricate image pickup chips; a process of bonding image pickup chips determined as non-defective products to a glass wafer to fabricate a joined wafer; a process of filling a sealing member among the image pickup chips on the joined wafer; a machining process including a thinning a thickness of the joined wafer to flatten a machining surface and a forming through-hole interconnections, each of which is connected to each of the electrode pads; a process of forming a plurality of external connection electrodes, each of which is connected to each of the electrode pads via each of the through-hole interconnections; and a process of cutting the joined wafer. | 2016-05-05 |
| 20160126287 | DISPLAY PANEL FOR COMPENSATING NEGATIVE POWER SUPPLY VOLTAGE, DISPLAY MODULE AND MOBILE DEVICE INCLUDING THE SAME - A display panel including: a cathode electrode formed in a cathode region of the display panel, the cathode electrode entirely covering an active region of the display panel a plurality of pixel units in columns and rows in the active region of the display panel; a ring-shaped edge negative voltage line formed in a ring-shaped edge portion of the cathode electrode configured to supply a negative power supply voltage to the cathode electrode; and a plurality of compensation negative voltage lines connected to the ring-shaped edge negative voltage line, the compensation negative voltage lines extending along a column direction of the display panel and arranged along a row direction of the display panel. | 2016-05-05 |
| 20160126288 | Magnetic Memory Devices - A STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the MTJ element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical distance away from the location of the MTJ stack. In a laser thermal annealing, a short wavelength of a laser has a shallow thermal penetration depth and a high thermal resistance from the bit line to the MTJ stack only causes a temperature rise of the MTJ stack being much smaller than that of the bit line. As the temperature of the MTJ element during the laser thermal annealing of bit line copper layer is controlled under 300-degree C., possible damages on MTJ and magnetic property can be avoided. | 2016-05-05 |
| 20160126289 | SEMICONDUCTOR DEVICE INCLUDING MAGNETO-RESISTIVE DEVICE - A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution. | 2016-05-05 |
| 20160126290 | Memory Arrays And Methods Of Forming An Array Of Memory Cell - A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed. | 2016-05-05 |
| 20160126291 | ELECTRICALLY RECONFIGURABLE INTERPOSER WITH BUILT-IN RESISTIVE MEMORY - An integrated interposer may include a substrate and a resistive-type non-volatile memory (NVM) array(s). The integrated interposer may also include a contact layer on a first surface of the substrate. The contact layer may include interconnections configured to couple the resistive-type NVM array(s) to a die(s). The resistive-type NVM array(s) may be partially embedded within the contact layer of the integrated interposer. | 2016-05-05 |
| 20160126292 | CONCAVE WORD LINE AND CONVEX INTERLAYER DIELECTRIC FOR PROTECTING A READ/WRITE LAYER - An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device. | 2016-05-05 |
| 20160126293 | ACTIVE MATRIX LIGHT EMITTING DIODES DISPLAY MODULE WITH CARBON NANOTUBES CONTROL CIRCUITS AND METHODS OF FABRICATION - An active matrix light emitting diodes display module integrated with single-walled carbon nanotubes control circuits includes a light emitting diode pixel having a crystalline semiconductor light emitting diode, single-walled carbon nanotubes switching transistors and a charge storage capacitor | 2016-05-05 |
| 20160126294 | ELECTRO-OPTICAL APPARATUS, MANUFACTURING METHOD FOR ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC DEVICE - An electro-optical apparatus includes a first pixel and a second pixel. The first pixel and the second pixel include a reflective layer, an insulating layer, a functional layer, and an opposing electrode. The insulating layer includes a first insulating layer, a second insulating layer having a first opening, and a third insulating layer having a second opening. A first pixel electrode is provided on the first insulating layer in the first opening. A second pixel electrode is provided on the second insulating layer. | 2016-05-05 |
| 20160126295 | DISPLAY DEVICE - A display device includes plural unit areas each of which includes low definition pixels as sub-pixels larger than a specified standard and high definition pixels as sub-pixels smaller than the specified standard and which are regularly arranged. The low definition pixels include a blue pixel and a red pixel, and the high definition pixels include a white pixel and a green pixel. | 2016-05-05 |
| 20160126296 | Pixel Arrangement Structure for Organic Light-Emitting Diode - A pixel arrangement structure for an organic light-emitting diode includes a plurality of red subpixel groups, a plurality of green subpixel groups, and a plurality of blue subpixel groups. Each red subpixel group is comprised of a plurality of red subpixels. Each green subpixel group is comprised of a plurality of green subpixels. Each blue subpixel group is comprised of a plurality of blue subpixels. The red subpixel groups, the green subpixel groups, and the blue subpixel groups are spaced from each other. One of the red subpixels of the red subpixel groups, one of the green subpixels of the green subpixel groups, and one of the blue subpixels of the blue subpixel groups, which are adjacent to each other, together form a pixel. The subpixels of the same color are gathered to form a subpixel group to increase the aperture ratio of metal masks. | 2016-05-05 |
| 20160126297 | ORGANIC LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting device can include a first electrode and a second electrode, and a red emission layer, a green emission layer and a blue emission layer which are positioned between the first electrode and the second electrode. Each of the red emission layer, the green emission layer and the blue emission layer can be disposed in an entirety of a red sub-pixel area, a green sub-pixel area and a blue sub-pixel area. A distance between the first electrode and the second electrode in at least one of the red sub-pixel area, the green sub-pixel area and the blue sub-pixel area can be a first-order optical distance equal to λ/2n, where λ is a wavelength of light emitted from each of the sub-pixel areas, and n is an average refractive index of a plurality of organic material layers disposed between the first electrode and the second electrode. | 2016-05-05 |
| 20160126298 | Pixel Arrangement Structure for Organic Light-Emitting Diode Display - A pixel arrangement structure for an organic light-emitting diode display includes at least one first sub-pixel line having alternately disposed first and second sub-pixel units in a first direction. Each first sub-pixel unit includes four diagonally disposed red sub-pixels. Each second sub-pixel unit includes four diagonally disposed green sub-pixels. At least two second sub-pixel lines are respectively located on two sides of the first sub-pixel line. Each second sub-pixel line includes third sub-pixel units arranged in the first direction. Each third sub-pixel unit is located between one of the first sub-pixel units and one of the second sub-pixel units in a second direction perpendicular to the first direction and includes two blue sub-pixels arranged in the second direction. A red sub-pixel, a green sub-pixel, and a blue sub-pixel, which are adjacent to each other and which are respectively of the first sub-pixel line and the second sub-pixel line, form a pixel. | 2016-05-05 |
| 20160126299 | Semiconductor device and manufacturing method thereof - As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film. | 2016-05-05 |
| 20160126300 | DISPLAY PANEL AND SYSTEM FOR DISPLAYING IMAGES UTILIZING THE SAME - A display panel is provided. The display panel includes a substrate having a pixel region and a peripheral region, a control element overlying the pixel region of the substrate, a first metal layer overlying the substrate in the peripheral region and in the pixel region, a first insulating layer formed on the first metal layer in the peripheral region, wherein the first insulating layer includes at least an opening, and the opening is disposed on the first metal layer, a second metal layer overlying the first insulating layer and electrically connected to the first metal layer, wherein a portion of the second metal layer is disposed in the opening, a second insulating layer overlying the second metal layer, and an electrode layer disposed on the second insulating layer. | 2016-05-05 |
| 20160126301 | Organic Light Emitting Device - Disclosed is an organic light emitting device, (OLED) comprising a substrate on which a driving transistor is formed, a bank formed on the substrate providing a boundary for a pixel region, a first electrode formed on the substrate and electrically connected with the driving transistor, the first electrode comprising a first and second cross sectional area both oriented in a direction perpendicular to a vertical direction of the substrate, the first area adjacent to the bank, the second area surrounded by the first area, an organic layer formed on the first electrode within the boundary provided by the bank, and a second electrode formed on the organic layer, wherein during operation of the OLED a first electric field between the first area of the first electrode and the second electrode is greater than a second electric field between the second area of the first electrode and the second electrode. | 2016-05-05 |
| 20160126302 | ORGANIC LIGHT-EMITTING DIODE (OLED) DEVICE AND DISPLAY DEVICE - The present disclosure relates to an organic light-emitting diode (OLED) device and a display device. The OLED device may include a substrate, thin film transistors (TFTs), an anode, a cathode, and an organic light-emitting layer between the anode and the cathode and configured to emit light. The organic light-emitting layer may be provided with a light-blocking layer which is configured to block ultraviolet (UV) light and arranged at a light-exiting side of the organic light-emitting layer. The display device may include the OLED device. | 2016-05-05 |
