18th week of 2016 patent applcation highlights part 61 |
Patent application number | Title | Published |
20160126103 | RECESS FILLING METHOD AND PROCESSING APPARATUS - There is provided a method of filling a recess of a workpiece, which includes: forming a first thin film made of a semiconductor material along a wall surface defining a recess in a semiconductor substrate; annealing the workpiece within a vessel whose internal process is set to a first pressure, and forming an epitaxial region which is generated by crystallizing the semiconductor material of the first thin film, along a surface defining the recess, without moving the first thin film; forming a second thin film made of the semiconductor material along the wall surface defining the recess; and annealing the workpiece within the vessel whose internal pressure is set to a second pressure lower than the first pressure, and forming a further epitaxial region which is generated by crystallizing the semiconductor material of the second thin film which is moved toward a bottom of the recess. | 2016-05-05 |
20160126104 | SYSTEMS AND METHODS FOR ELECTROCHEMICAL DEPOSITION ON A WORKPIECE INCLUDING REMOVING CONTAMINATION FROM SEED LAYER SURFACE PRIOR TO ECD - In one embodiment of the present disclosure, a method for electrochemical deposition on a workpiece includes (a) obtaining a workpiece including a feature; (b) depositing a first conductive layer in the feature; (c) moving the workpiece to an integrated electrochemical deposition plating tool configured for hydrogen radical H* surface treatment and electrochemical deposition; (d) treating the first conductive layer using a hydrogen radical H* surface treatment in a treatment chamber of the plating tool to produce a treated first conductive layer; and (e) maintaining the workpiece in the same plating tool and depositing a second conductive layer in the feature on the treated first conductive layer in an electrochemical deposition chamber of the plating tool. | 2016-05-05 |
20160126105 | System and Method for Damage Reduction in Light-Assisted Processes - A method embodiment for forming a semiconductor device includes providing a dielectric layer having a damaged surface and repairing the damaged surface of the dielectric layer. Repairing the damaged surface includes exposing the damaged surface of the dielectric layer to a precursor chemical, activating the precursor chemical using light energy, and filtering out a spectrum of the light energy while activating the precursor chemical. | 2016-05-05 |
20160126106 | SELECTIVE GROWTH METHOD AND SUBSTRATE PROCESSING APPARATUS - There is provided a selective growth method of selectively growing a thin film on exposed surfaces of an underlying insulation film and an underlying metal film, which includes: selectively growing a film whose thickness is decreased by combustion on the underlying metal film using metal of the underlying metal film as a catalyst; and selectively growing a silicon oxide film on the underlying insulation film while combusting the film whose thickness is decreased by combustion. | 2016-05-05 |
20160126107 | ETCHANT COMPOSITIONS FOR NITRIDE LAYERS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - An etchant composition for nitride layers includes phosphoric acid in an amount ranging from about 80 weight percent to about 90 weight percent, a silicon-fluorine compound in an amount ranging from about 0.02 weight percent to about 0.1 weight percent, and a remainder of water, based on a total weight of the etchant composition. The silicon-fluorine compound includes a bond between a silicon atom and a fluorine atom (Si—F bonding). | 2016-05-05 |
20160126108 | METHOD OF REDUCING GATE LEAKAGE IN A MOS DEVICE BY IMPLANTING GATE LEAKAGE REDUCING SPECIES INTO THE EDGE OF THE GATE - In a MOS device, gate leakage is reduced by implanting gate oxide leakage reduction species such as nitrogen into the gate oxide along the edges of the gate to reduce gate leakage and hence reduce data retention fails in SRAM devices and allow low Vdd SRAM operation without increasing gate oxide thickness. By implanting nitrogen along the edges of the gate it simultaneously replaces lost gate oxide nitrogen to further reduce gate leakage. | 2016-05-05 |
20160126109 | Method for Manufacturing a Transistor Device Comprising a Germanium Channel Material on a Silicon Based Substrate, and Associated Transistor Device - Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si | 2016-05-05 |
20160126110 | METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT - A method for manufacturing a three-dimensional integrated circuit is disclosed. The method includes: providing a substrate; forming at least one metal layer and at least one dielectric layer on the substrate; forming a plurality of electrical connection points on the metal layer; dicing to generate a plurality package units, each of the package units adhered to a diced substrate; reversing each of the package units and connecting each of the reversed package units to a surface of a wiring substrate to form an integrated substrate; and removing the diced substrate of each of the reversed package units. The present disclosure can improve an assembling process. | 2016-05-05 |
20160126111 | METHODS OF MANUFACTURING A PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN PLACE OF A LOW-RESISTIVITY HANDLE LAYER - A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 10 | 2016-05-05 |
20160126112 | SUBSTRATE LIQUID PROCESSING APPARATUS - Gas-liquid separation of an exhaust gas from a liquid processing unit can be improved. A substrate liquid processing apparatus includes a liquid processing unit, a first exhaust pipe and a second exhaust pipe. The liquid processing unit is configured to process a substrate with a processing liquid. At least a part of the first exhaust pipe at is located above the liquid processing unit. One end of the second exhaust pipe is connected to the liquid processing unit, and the second exhaust pipe is configured to evacuate the liquid processing unit through the first exhaust pipe by an exhaust device. Further, the other end of the second exhaust pipe is connected to a portion of the first exhaust pipe which is located above the liquid processing unit. | 2016-05-05 |
20160126113 | ROLL-TYPE PROCESSING MEMBER, PENCIL-TYPE PROCESSING MEMBER, AND SUBSTRATE PROCESSING APPARATUS INCLUDING ANY ONE OF THESE - A roll-type cleaning member for scrubbing and cleaning a target cleaning surface of a substrate includes a plurality of nodules formed on a surface thereof. Each nodule includes a slit which extends so as not to be parallel to the rotation direction of the roll-type cleaning member, upstream edges are formed by the slit so as to serve as edges first contacting the target cleaning surface when a cleaning surface of the nodule contacts the target cleaning surface of the substrate by the rotation of the roll-type cleaning member, and the upstream edges are provided at a plurality of positions of the cleaning surface of the nodule in the circumferential direction. | 2016-05-05 |
20160126114 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a processing chamber, a table disposed in the processing chamber, a dielectric window provided at the processing chamber, and a surrounding body made of a dielectric material surrounding a processing space between the table and the dielectric window. The dielectric window and the surrounding body are separated from each other in a vertical direction with a predetermined gap therebetween. | 2016-05-05 |
20160126115 | Methods for Controlling Plasma Constituent Flux and Deposition During Semiconductor Fabrication and Apparatus for Implementing the Same - A time-dependent substrate temperature to be applied during a plasma process is determined. The time-dependent substrate temperature at any given time is determined based on control of a sticking coefficient of a plasma constituent at the given time. A time-dependent temperature differential between an upper plasma boundary and a substrate to be applied during the plasma process is also determined. The time-dependent temperature differential at any given time is determined based on control of a flux of the plasma constituent directed toward the substrate at the given time. The time-dependent substrate temperature and time-dependent temperature differential are stored in a digital format suitable for use by a temperature control device defined and connected to direct temperature control of the upper plasma boundary and the substrate. A system is also provided for implementing upper plasma boundary and substrate temperature control during the plasma process. | 2016-05-05 |
20160126116 | SINGULATION APPARATUS AND METHOD - A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process. | 2016-05-05 |
20160126117 | SAMPLE HOLDER - A sample holder of the present invention includes a base body formed of ceramic substrates laminated to each other and having an upper surface functioning as a sample holding surface. In this sample holder, the base body includes a first ceramic substrate including a flow path for a heating medium and a second ceramic substrate which is laminated at an upper side than the first ceramic substrate, which has an upper surface functioning as the sample holding surface, and which is formed of the same material as that of the first ceramic substrate, and the average grain diameter of ceramic grains forming the second ceramic substrate is smaller than that of ceramic grains forming the first ceramic substrate. | 2016-05-05 |
20160126118 | PEDESTAL WITH MULTI-ZONE TEMPERATURE CONTROL AND MULTIPLE PURGE CAPABILITIES - Substrate support assemblies for a semiconductor processing apparatus are described. The assemblies may include a pedestal and a stem coupled with the pedestal. The pedestal may be configured to provide multiple regions having independently controlled temperatures. Each region may include a fluid channel to provide a substantially uniform temperature control within the region, by circulating a temperature controlled fluid that is received from and delivered to internal channels in the stem. The fluid channels may include multiple portions configured in a parallel-reverse flow arrangement. The pedestal may also include fluid purge channels that may be configured to provide thermal isolation between the regions of the pedestal. | 2016-05-05 |
20160126119 | LASER ANNEALING APPARATUS - A laser annealing apparatus includes a process chamber with a chamber window to transmit a laser beam, and a chuck in the process chamber, a top surface of the chuck supporting a loaded substrate, and a width of the chuck being smaller than a width of the loaded substrate. | 2016-05-05 |
20160126120 | WORK-IN-PROGRESS SUBSTRATE PROCESSING METHODS AND SYSTEMS FOR USE IN THE FABRICATION OF INTEGRATED CIRCUITS - Disclosed herein are methods and systems for semiconductor fabrication. In one embodiment, a method for fabricating semiconductors utilizing a semiconductor fabrication system includes performing a semiconductor fabrication process on a first lot of unprocessed semiconductor substrates with a semiconductor fabrication equipment unit to form a first lot of processed substrates and communicating processing data regarding the first lot of processed substrates from the semiconductor fabrication equipment unit to a just-in-time (JIT) module of the semiconductor fabrication system. The method further includes determining a processing priority of the first lot of processed substrates and a processing priority of a second lot of unprocessed substrates at the JIT module and scheduling removal of the first lot of processed substrates from the semiconductor fabrication equipment unit and delivery of the second lot of unprocessed substrates to the semiconductor fabrication equipment unit by the JIT module based on the processing data and the priority of one or both of the first lot of processed substrates and the second lot of unprocessed substrates. | 2016-05-05 |
20160126121 | SENSOR SYSTEM FOR SEMICONDUCTOR MANUFACTURING APPARATUS - A chamber monitoring system may include a parallel architecture in which a single sensor control system is coupled to a number of different processing chamber control board sensor lines. In an illustrative embodiment, a single rotation sensor such as a tachometer may reside in a central control unit remote from the processing chambers such that rotation data may be processed by a single system and thereafter routed according to a variety of different network communication protocols to the main system controller, a factory interface, or both. In this and other embodiments, pull-up networks in the central control unit and the chamber control boards are matched so as to reduce electrical signal anomalies such as crowbar effects. The central control unit may be programmed via a main system controller to operate according to user defined parameters, which in turn may enable the system to differentiate between certain operating states. | 2016-05-05 |
20160126122 | SUBSTRATE STORING CONTAINER - The bottom plate has a plate-like shape, is arranged to face an outer face of a lower wall, and has a locking portion. The groove member has: a groove-forming portion having a groove opening downward formed therein, a surrounding wall portion, which is connected to the groove-forming portion, and is arranged around the groove-forming portion; and a locked portion, which is connected to the surrounding wall portion, is elastically deformable, and is locked by way of the locking portion of the bottom plate by being elastically deformed. The groove member is supported and fixed by way of the lower wall and the bottom plate. | 2016-05-05 |
20160126123 | Method For Improving Performance Of A Substrate Carrier - A method of modifying a substrate carrier to improve process performance includes depositing material or fabricating devices on a substrate supported by a substrate carrier. A parameter of layers deposited on the substrate is then measured as a function of their corresponding positions on the substrate carrier. The measured parameter of at least some devices fabricated on the substrate or a property of the deposited layers is related to a physical characteristic of substrate carrier to obtain a plurality of physical characteristics of the substrate carrier corresponding to a plurality of positions on the substrate carrier. The physical characteristic of the substrate carrier is then modified at one or more of the plurality of corresponding positions on the substrate carrier to obtain desired parameters of the deposited layers or fabricated devices as a function of position on the substrate carrier. | 2016-05-05 |
20160126124 | ELECTROSTATIC CHUCK - An electrostatic chuck is disclosed. In one aspect, the electrostatic chuck includes a top plate, wherein first and second regions adjacent to each other are formed at a surface of the top plate. The electrostatic chuck also includes a first absorption plate positioned at the first region and a second absorption plate positioned at the second region to be separated from the first absorption plate. The first and second absorption plates are configured to support the absorption target. | 2016-05-05 |
20160126125 | ELECTROSTATIC CHUCK - An electrostatic chuck includes: a body substrate having a substrate front surface and a substrate rear surface and made of ceramic; an attraction electrode provided in the body substrate; a metal base having a base front surface and a base rear surface, and placed such that the base front surface faces the substrate rear surface of the body substrate; and an internal through hole formed so as to penetrate the base front surface and the base rear surface of the metal base. The body substrate has a plurality of heating regions in each of which a heater electrode is provided. In the internal through hole, a plurality of heater electrode terminals are provided which are electrically connected to the heater electrode in each heating region. The plurality of heater electrode terminals provided in the internal through hole are electrically connected to a connection member provided in the internal through hole. | 2016-05-05 |
20160126126 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles. | 2016-05-05 |
20160126127 | Adhesive Sheet, Method for Manufacturing Semiconductor Device Using Same, Method for Manufacturing Thermal Airflow Sensor Using Same, and Thermal Airflow Sensor - Provided is a thermal type airflow volume meter improving measurement accuracy, a method for manufacturing the same, and an adhesive sheet for use therein, the adhesive sheet divided into at least two or more per adherend and having a thickness of approximately 0.1 mm or less is divided to correspond to a shape of the adherend and generates or increases adhesion or stickiness by external energy. | 2016-05-05 |
20160126128 | WAFER ALIGNER - A semiconductor wafer transport apparatus includes a frame, a transport arm movably mounted to the frame and having at least one end effector movably mounted to the arm so the at least one end effector traverses, with the arm as a unit, in a first direction relative to the frame, and traverses linearly, relative to the transport arm, in a second direction, and an edge detection sensor mounted to the transport arm so the edge detection sensor moves with the transport arm as a unit relative to the frame, the edge detection sensor being a common sensor effecting edge detection of each wafer simultaneously supported by the end effector, wherein the edge detection sensor is configured so the edge detection of each wafer is effected by and coincident with the traverse in the second direction of each end effector on the transport arm. | 2016-05-05 |
20160126129 | CLAMP ASSEMBLY - A clamp assembly is for clamping an outer peripheral portion of a substrate to a support in a plasma processing chamber. An RF bias power is applied to the support during the plasma processing of the substrate. The clamp assembly includes an outer clamp member, and an inner clamp member which is received by the outer clamp member, the inner clamp member defining an aperture which exposes the substrate to the plasma processing. The outer clamp member has an inner portion terminating in an inner edge, wherein the inner portion is spaced apart from the inner clamp member. | 2016-05-05 |
20160126130 | Air Gaps Structures for Damascene Metal Patterning - A pattern of parallel lines defines first regions where no conductive material is to be located, a distance between adjacent lines in the first regions being smaller than a predetermined distance, and defines second regions where conductive material is to be located, a distance between adjacent lines in the second regions being larger than the predetermined distance. A subsequent layer caps air gaps between lines in the first regions. Conductive material is then deposited and planarized to form lines of conductive material in the second regions. | 2016-05-05 |
20160126131 | Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure - An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other. | 2016-05-05 |
20160126132 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ISOLATION REGIONS HAVING UNIFORM STEP HEIGHTS - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height. | 2016-05-05 |
20160126133 | METAL-ASSISTED CHEMICAL ETCHING OF A SEMICONDUCTIVE SUBSTRATE WITH HIGH ASPECT RATIO, HIGH GEOMETIC UNIFORMITY, AND CONTROLLED 3D PROFILES - An embodiment of a method for metal-assisted chemical etching of a semiconductive substrate comprises forming a patterned coating on a top surface of a substrate layer of a silicon wafer; applying a noble metal layer over the patterned coating such that a portion of the noble metal layer is in contact with the top surface of the substrate layer; and immersing the silicon wafer in a wet etching solution to form a trench under the portion of the noble metal layer that is contact with the top surface of the substrate layer. Further, the trench may be filled with copper material to form a through silicon via structure. Such embodiments provide etching techniques that enable etched formations that are deep (e.g., high-aspect-ratio) and uniform as opposed to shallow etchings (i.e., low-aspect-ratio) or non-uniform deep etchings. | 2016-05-05 |
20160126134 | SYSTEMS AND METHODS FOR REMOVING CONTAMINATION FROM SEED LAYER SURFACE - An electrochemical deposition plating tool in accordance with one embodiment of the present disclosure includes one or more electrochemical deposition chambers and a hydrogen radical H* generation chamber. | 2016-05-05 |
20160126135 | METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A METAL SILICIDE CAPPING LAYER - One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact. | 2016-05-05 |
20160126136 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a low-adhesion film, a pair of substrates, and a metal electrode. The low-adhesion film has lower adhesion to metal than a semiconductor oxide film. The pair of substrates is provided with the low-adhesion film interposed therebetween. The metal electrode passes through the low-adhesion film and connects the pair of substrates, and includes, between the pair of substrates, a part thinner than parts embedded in the pair of substrates. A portion of the metal electrode embedded in one substrate is provided with a gap interposed between the portion and the low-adhesion film on the other substrate. | 2016-05-05 |
20160126137 | COMBINING CUT MASK LITHOGRAPHY AND CONVENTIONAL LITHOGRAPHY TO ACHIEVE SUB-THRESHOLD PATTERN FEATURES - Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion. | 2016-05-05 |
20160126138 | WAFER PROCESSING METHOD - A wafer is formed with a plurality of division lines on a front surface of a single crystal substrate having an off angle and formed with devices in a plurality of regions partitioned by the division lines. The wafer is processed by setting a numerical aperture (NA) of a focusing lens for focusing a pulsed laser beam so that a value obtained by dividing the numerical aperture (NA) by a refractive index (N) of the single crystal substrate falls within the range from 0.05 to 0.2. The pulsed laser beam is applied along the division lines, with a focal point of the pulsed laser beam positioned at a desired position from a back surface of the single crystal substrate, so as to form shield tunnels each composed of a pore and a pore-shielding amorphous portion along the division lines from the focal point positioned inside the single crystal substrate. | 2016-05-05 |
20160126139 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a high-k dielectric layer thereon; forming a first work function layer on the high-k dielectric layer; and forming a first oxygen-containing layer on the first work function layer. | 2016-05-05 |
20160126140 | INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - A method of manufacturing an integrated circuit structure includes forming a plurality of gate stacks on a first area and a second area of a substrate. A photo-resist layer is formed over the gate stacks on the first area. An ion-doped layer is formed in the second area. The photo-resist layer is removed. A first etching recess is formed in the first area and between two gate stacks. A second etching recess is formed in the second area and between two gate stacks. An epitaxial material is filled into the first etching recess and the second etching recess to form a first epitaxial structure and a second epitaxial structure. | 2016-05-05 |
20160126141 | METHODS FOR FORMING FINFETS HAVING A CAPPING LAYER FOR REDUCING PUNCH THROUGH LEAKAGE - A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer. | 2016-05-05 |
20160126142 | Equal Gate Height Control Method for Semiconductor Device with Different Pattern Densites - A method of forming a semiconductor integrated circuit (IC) includes forming a first semiconductor layer over a substrate, the first semiconductor layer having an uneven upper surface, forming a stop layer over the first semiconductor layer, the first semiconductor layer disposed between the substrate and the stop layer, and treating the stop layer to change its etch selectivity relative to the first semiconductor layer. | 2016-05-05 |
20160126143 | METHOD OF FORMING HORIZONTAL GATE ALL AROUND STRUCTURE - This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. Accordingly, compared to conventional methods limited by fin height from the STI, the double STI recess method provides greater fin height, which is a larger process window for HGAA nanowire formation, to easily produce multi-stack HGAA nanowires with high current density. The number of layers used in the multi-stack HGAA nanowires is not limited and may vary based on different designs. | 2016-05-05 |
20160126144 | METHODS OF FORMING A METAL-INSULATOR-SEMICONDUCTOR (MIS) STRUCTURE AND A DUAL CONTACT DEVICE - A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer. | 2016-05-05 |
20160126145 | LOW THRESHOLD VOLTAGE CMOS DEVICE - A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings. | 2016-05-05 |
20160126146 | EFFICIENT MAIN SPACER PULL BACK PROCESS FOR ADVANCED VLSI CMOS TECHNOLOGIES - Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si gate stacks on an upper surface of a substrate; forming a hardmask over the second poly-Si gate stack; forming eSiGe with a silicon cap at opposite sides of the first poly-Si gate stack; removing the hardmask; forming nitride spacers at opposite sides of each of the poly-Si gate stacks; forming deep source/drain regions at opposite sides of the second poly-Si gate stack; forming a wet gap fill layer around each of the poly-Si gate stacks to a thickness less than the poly-Si gate stack height from the substrate's upper surface; removing an upper portion of the nitride spacers down to the height of the wet gap fill layer followed by removing the wet gap fill layer; and performing silicidation of the deep source/drain regions and the silicon cap. | 2016-05-05 |
20160126147 | STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY - A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material. | 2016-05-05 |
20160126148 | SYSTEM AND METHOD FOR PERFORMING A WET ETCHING PROCESS - A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a wafer before and after each etching steps in the process. The system also includes a controller to analyze the thickness measurements in view of a target wafer profile and generate an etch recipe, dynamically and in real time, for each etching step. In addition, the process controller can cause a single wafer wet etching station to etch the wafer according to the generated etching recipes. In addition, the system can, based on the pre and post-etch thickness measurements and target etch profile, generate and/or refine the etch recipes. | 2016-05-05 |
20160126149 | METHOD FOR PROCESSING A SUBSTRATE AND A METHOD OF PROCESS SCREENING FOR INTEGRATED CIRCUITS - According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may include a plurality of test regions; forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions; simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions from each other. | 2016-05-05 |
20160126150 | SYSTEM AND METHOD FOR GENERATING AN ARM SCAN PROFILE - A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a wafer before and after each etching steps in the process. The system also includes a controller to analyze the thickness measurements in view of a target wafer profile and generate an etch recipe, dynamically and in real time, for each etching step. In addition, the process controller can cause a single wafer wet etching station to etch the wafer according to the generated etching recipes. In addition, the system can, based on the pre and post-etch thickness measurements and target etch profile, generate and/or refine the etch recipes. | 2016-05-05 |
20160126151 | METHOD FOR PRODUCING A PLURALITY OF MEASUREMENT REGIONS ON A CHIP, AND CHIP WITH MEASUREMENT REGIONS - A a chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in which, in order to reliably separate the individual measurement regions from one another, a monolayer of a fluorosilane is formed on the chip surface which has strongly hydrophobic properties. Therefore, during spotting with a liquid, the drops of liquid applied by spotting can be reliably prevented from coalescing, and thus, causing mixing of the substances in the drops of liquid which are supposed to be immobilized in the measurement regions. | 2016-05-05 |
20160126152 | TEST STRUCTURE FOR DETERMINING OVERLAY ACCURACY IN SEMICONDUCTOR DEVICES USING RESISTANCE MEASUREMENT - Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns. | 2016-05-05 |
20160126153 | PRINTED CIRCUIT BOARD AND ELECTRONIC EQUIPMENT - A plurality of lands is formed apart from each other on a surface of a package substrate. Another plurality of lands is formed apart from each other on a surface of a printed wiring board. The surface of the package substrate and the surface of the printed wiring board face each other. The plurality of lands and another plurality of lands are bonded to each other with solder having a height of 30% or less of a diameter of a solder bonding portion at the corresponding land. A ratio of a solder bonded area of at least each of lands, among another plurality of the lands, of which distance value to a corresponding one of the lands is larger than an average distance value between the lands and another lands, to a solder bonded area of the corresponding one of the lands is 56% or more and 81% or less. | 2016-05-05 |
20160126154 | Power Semiconductor Module and Method for Producing a Power Semiconductor Module - A power semiconductor module includes a module housing and a circuit carrier having a dielectric insulation carrier and an upper metallization layer applied onto an upper side of the dielectric insulation carrier. A semiconductor component is arranged on the circuit carrier. The power semiconductor module also has an electrically conductive terminal block connected firmly and electrically conductively to the circuit carrier and/or to the semiconductor component. The terminal block has a screw thread that is accessible from an outer side of the module housing. A method for producing such a power semiconductor module is also provided. | 2016-05-05 |
20160126155 | SEMICONDUCTOR DEVICE - Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip. | 2016-05-05 |
20160126156 | SEMICONDUCTOR DEVICE - A ground working tool comprising a tubular base body with an inner receiving space for receiving a cylindrical core of solid ground material, connector mechanism for connecting the tubular base body with a rotary drive and locking mechanism for locking the core in the receiving space of the tubular base body. The locking mechanism involves at least one locking unit having a guide rail being disposed at an inner side of the tubular base body and arranged with a deviation angle relative to a tangential direction of the tubular base body and the locking unit further comprises at least one locking element, which is moveably mounted on the guide rail between a radially outer releasing position and a radially inner locking position, in which the core is clamped within the receiving space by means of the at least one locking element. | 2016-05-05 |
20160126157 | DOUBLE-SIDED COOLING POWER MODULE AND METHOD FOR MANUFACTURING THE SAME - A double-sided cooling power module may include a lower-end terminal, at least one pair of power semiconductor chips mounted on the lower-end terminal, at least one pair of horizontal spacers mounted on the at least one pair of power semiconductor chips, an upper-end terminal mounted on the at least one pair of horizontal spacers, and at least one pair of vertical spacers disposed between the upper-end terminal and the lower-end terminal | 2016-05-05 |
20160126158 | INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES - An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer | 2016-05-05 |
20160126159 | INTERPOSER FOR MULTI-CHIP ELECTRONICS PACKAGING - An interposer for vertically separating device die is disclosed. The interposer includes a compliant layer comprising a plurality of thermally conductive plugs that are physically disconnected within the plane of the compliant layer, where the space between the plugs is filled with a compliant medium. In some embodiments, at least one of the top and bottom surfaces of the compliant layer is coated with a thin layer of electrically insulating material. | 2016-05-05 |
20160126160 | SYSTEM FOR COOLING DUAL SIDES OF POWER SEMICONDUCTOR DEVICE - A system for cooling dual sides of power semiconductor devices includes two (2) cooling water flow passages, each of which being bent in the “ | 2016-05-05 |
20160126161 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a packaging substrate having a first surface and a second surface opposite to the first surface; and a semiconductor die assembled on the first surface of the packaging substrate. The semiconductor die includes a plurality of first bump pads and second bump pads on an active surface of the semiconductor die, a plurality of first copper pillars on the first bump pads, and a plurality of second copper pillars on the second bump pads. The first copper pillars have a diameter that is smaller than that of the second copper pillars. | 2016-05-05 |
20160126162 | PACKAGE WITH MULTIPLE I/O SIDE-SOLDERABLE TERMINALS - Consistent with an example embodiment, there is leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. There are at least five I/O terminals wherein each of said terminals comprise a respective metal side pad wherein the respective metal side pad is disposed in a recess. A feature of this embodiment is that the each of the side pads is electroplated. The electroplated side pads accept solder and the solder menisci are contained by the recesses. | 2016-05-05 |
20160126163 | LEAD FRAME STRIP WITH MOLDING COMPOUND CHANNELS - A lead frame strip has a plurality of unit lead frames. Each of the unit lead frames has a periphery structure connecting adjacent ones of the unit lead frames, a die paddle inside of the periphery structure, a plurality of leads connected to the periphery structure and extending towards the die paddle, and a molding compound channel in the periphery structure configured to guide liquefied molding material. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles, electrically connecting each of the semiconductor dies to the leads, and forming a liquefied molding compound on each of the unit lead frames. The liquefied molding compound is formed such that the liquefied molding compound encapsulates the semiconductor dies and flows into the molding compound channels thereby forming molding extensions that extend onto the periphery structures. | 2016-05-05 |
20160126164 | CAVITY PACKAGE WITH PRE-MOLDED CAVITY LEADFRAME - A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow. | 2016-05-05 |
20160126165 | METHOD OF CONNECTING A SUBSTRATE AND CHIP ASSEMBLY - A method of connecting a substrate is provided, wherein the substrate may include a first main surface and a second main surface opposite the first main surface. The method may include forming at least one protrusion on the first main surface of the substrate, forming a fixing agent over the first main surface of the substrate and over the at least one protrusion; and arranging the substrate on a carrier. The at least one protrusion may contact a surface of the carrier and may be configured to keep the first main surface of the substrate at a distance to the contacted surface of the carrier corresponding to a height of the protrusion, thereby forming a space between the first main surface of the substrate and the carrier. During the arranging the substrate on the carrier, at least a part of the fixing agent formed over the at least one protrusion may be displaced into the space between the first main surface of the substrate and the carrier. | 2016-05-05 |
20160126166 | FLIP-CHIP ON LEADFRAME SEMICONDUCTOR PACKAGING STRUCTURE AND FABRICATION METHOD THEREOF - Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed there-over is provided. A barrier layer is formed on the copper pillars. A solder material is coated on the barrier layer. A layer of soldering flux is coated on the solder material. A leadframe with electric leads formed thereon is provided. An insulating layer is formed an the leadframe and having a plurality of openings to expose portion of the electric leads. The semiconductor chip is placed upside down onto the leadframe to have the soldering flux in contact with the portion of the electric leads exposed in the openings. The solder material flows back to form conductive interconnections between the copper pillars and the portion of the electric leads exposed in the openings. The semiconductor chip is packaged with the leadframe using a mold compound. | 2016-05-05 |
20160126167 | SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MODULE, AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE - A semiconductor module is configured such that heat radiation substrates are connected to lead frames and semiconductor chips are directly connected to the lead frames, so that the semiconductor chips are not connected to the lead frames through conductive portions of the heat radiation substrates. Therefore, the conductive portions can have a solid shape without being divided. As such, an occurrence of curving of the heat radiation substrates is suppressed when a temperature is reduced from a high temperature to a room temperature after resin-sealing at the high temperature or the like. Therefore, connection between the semiconductor chip and the lead frames and connection between the lead frames and the heat radiation substrates enhance. | 2016-05-05 |
20160126168 | SEMICONDUCTOR DEVICE - A first switching element and a second switching element are thermally connected to each other since the first switching element and the second switching element are fixed on a second substrate. An upper arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element. The lower arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element. | 2016-05-05 |
20160126169 | LEADLESS SEMICONDUCTOR DEVICE AND METHOD OF MAKING THEREOF - Consistent with an example embodiment, there is a leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. At least five I/O terminals each of said terminals comprise a respective metal side pad; and the respective metal side pad has a step profile. A feature of this embodiment is that these metal side pads, having a step profile, are electroplated to enhance their solderability. | 2016-05-05 |
20160126170 | SOLID STATE CONTACTOR WITH IMPROVED INTERCONNECT STRUCTURE - A printed circuit board for selectively communicating power from a power source to a use has an input bus for receiving a power supply. A transistor is connected to the input bus and is positioned on one side of the input bus in a first direction. An output bus is connected to the transistor on an opposed side of the transistor relative to the input bus. The transistor is intermediate at the first input and output buses in the first dimension. A power supply system is also disclosed. | 2016-05-05 |
20160126171 | CIRCUIT BOARD WITH CONSTRAINED SOLDER INTERCONNECT PADS - Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a solder mask on a circuit board with a first opening that has a sidewall. A solder interconnect pad is formed in the first opening. The sidewall sets the lateral extent of the solder interconnect pad. | 2016-05-05 |
20160126172 | SEMICONDUCTOR DEVICE PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device package includes a substrate having a first surface and a second surface that is opposite to the first surface, a plurality of solder joints disposed on the first surface of the substrate, a semiconductor chip disposed above the second surface of the substrate, and a support member disposed between the second surface of the substrate and the semiconductor chip. At least one of the solder joints is in contact with the first surface of the substrate opposite to a region on the second surface in which the support member is not disposed. | 2016-05-05 |
20160126173 | HIGH DENSITY FAN OUT PACKAGE STRUCTURE - A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die. | 2016-05-05 |
20160126174 | SUBSTRATES AND METHODS OF MANUFACTURE - An interposer ( | 2016-05-05 |
20160126175 | CIRCUIT SUBSTRATE AND SEMICONDUCTOR PACKAGE STRUCTURE - The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface. A first through via plug passes through the core substrate. A first conductive line pattern and a second conductive line pattern adjacent to the first conductive line are disposed on the chip-side surface. A pad is disposed on the bump-side surface. The first through via plug is in direct contact with and partially overlapping the first conductive line pattern and the pad. The first conductive line pattern, the second conductive line pattern and the first through via plug are configured to transmit voltage supplies of the same type. | 2016-05-05 |
20160126176 | PACKAGE SUBSTRATE, PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package substrate is provided, which includes: a body having opposite first and second surfaces, each having adjacent first and second regions defined thereon; first and second circuit layers formed on the first and second surfaces of the body, respectively; a first insulating layer formed on the first surface of the body and having a plurality of first openings formed in the first insulating layer and positioned in the first and second regions; and a second insulating layer formed on the second surface of the body and having a plurality of second openings formed in the second insulating layer and positioned in the second region. Further, at least a third opening is formed in the second insulating layer and positioned in the first region to reduce the volume of the second insulating layer, thereby facilitating even distribution of thermal stresses through the first and second insulating layers during thermal cycling and hence preventing warpage of the package substrate. | 2016-05-05 |
20160126177 | Packaged Assembly for High Density Power Applications - A packaged assembly for high density power applications includes a case having shelves on opposing walls, and a double-sided substrate disposed on the shelves of the case, the double-sided substrate having a semiconductor die on a first side of the double-sided substrate and circuit elements on a second side of the double-sided substrate. The case includes aluminum silicon (AlSi). The double-sided substrate is secured to the case by an epoxy. The double-sided substrate a thick film substrate and includes beryllium oxide (BeO) or aluminum oxide (Al | 2016-05-05 |
20160126178 | MEMORY CELL HAVING MULTI-LEVEL WORD LINE - A memory cell comprises a first word line in a first layer on a first level. The memory cell also comprises a second word line having a first portion in the first layer and a second portion in a second layer. The second layer is on a second level different from the first level. The memory cell further comprises a first via layer coupling the first portion of the second word line with the second portion of the second word line. | 2016-05-05 |
20160126179 | Buried Etch Stop Layer for Damascene Bit Line Formation - A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs. | 2016-05-05 |
20160126180 | VIA STRUCTURE FOR OPTIMIZING SIGNAL POROSITY - An apparatus including a conductive stack structure includes an M | 2016-05-05 |
20160126181 | Methods of Fabricating Integrated Circuitry - A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via. | 2016-05-05 |
20160126182 | DUMMY PATTERNS - A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having second sizes, and a plurality of bar-like third dummy patterns having varied third sizes. The pattern densities are smartly equalized by positioning the second dummy patterns. | 2016-05-05 |
20160126183 | ELECTRICALLY CONDUCTIVE INTERCONNECT INCLUDING VIA HAVING INCREASED CONTACT SURFACE AREA - An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature. | 2016-05-05 |
20160126184 | DIAGONAL HARDMASKS FOR IMPROVED OVERLAY IN FABRICATING BACK END OF LINE (BEOL) INTERCONNECTS - Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials. | 2016-05-05 |
20160126185 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1. | 2016-05-05 |
20160126186 | BOND PAD STRUCTURE WITH DUAL PASSIVATION LAYERS - A bond pad structure with dual passivation layers is disclosed. The bond pad structure includes: a pad material layer on a first passivation layer; a protection layer on the top surface of the pad material layer; a second passivation layer covering on the first passivation layer and the protection layer; and an opening formed through the second passivation layer and the protection layer to expose the pad material layer. | 2016-05-05 |
20160126187 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element having a gate and source electrodes; an insulating substrate which is provided with an insulating plate, a first circuit plate and a second circuit plate, the first circuit plate provided in a main surface of the insulating plate to be electrically connected to the gate electrode, the second circuit plate provided in the main surface to surround the first circuit plate and to be electrically connected to the source electrode; a first terminal, being column-shaped and electrically and mechanically connected to the first circuit plate; and a second terminal which is provided with a cylindrical body portion and support portions, the body portion has a through hole into which the first terminal is inserted with a gap, the support portions disposed in end portions of the body portion and electrically and mechanically connected to the second circuit plate. | 2016-05-05 |
20160126188 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output. | 2016-05-05 |
20160126189 | Programmable Devices and Methods of Manufacture Thereof - Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link. | 2016-05-05 |
20160126190 | METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A CONDUCTIVE CAPPING LAYER - One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact. | 2016-05-05 |
20160126191 | METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate. | 2016-05-05 |
20160126192 | Power Semiconductor Module Having a Direct Copper Bonded Substrate and an Integrated Passive Component, and an Integrated Power Module - A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided. | 2016-05-05 |
20160126193 | METHOD OF FABRICATING A TUNGSTEN PLUG IN A SEMICONDUCTOR DEVICE - In an semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug. | 2016-05-05 |
20160126194 | MEASUREMENT MARK STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a measurement mark structure, including a plurality of inner patterns, the inner patterns being arranged along a first direction, and an outer pattern, positioned surrounding the inner patterns, and the outer pattern is rectangular frame shaped. | 2016-05-05 |
20160126195 | NON-MAGNETIC PACKAGE AND METHOD OF MANUFACTURE - A non-magnetic hermetic package includes walls that surround an open cavity, with a generally planar non-magnetic and metallic seal ring disposed in a continuous loop around upper edges of the walls; a sensitive component that is bonded within the cavity; and a non-magnetic lid that is sealed to the seal ring to close the cavity by a metallic seal. | 2016-05-05 |
20160126196 | PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN PLACE OF A LOW-RESISTIVITY HANDLE LAYER - A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 10 | 2016-05-05 |
20160126197 | SEMICONDUCTOR DEVICE HAVING A STRESS-COMPENSATED CHIP ELECTRODE - A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main surface. The chip electrode includes a first metal layer and wherein the first metal layer is arranged between the semiconductor chip and the second metal layer. | 2016-05-05 |
20160126198 | Arrangement for Energy Conditioning - Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences. | 2016-05-05 |
20160126199 | SIGNAL PATHS FOR RADIO-FREQUENCY MODULES - Signal paths for radio-frequency (RF) modules. In some embodiments, an RF module can include a plurality of components configured to facilitate processing of an RF signal, and a packaging substrate on which the plurality of components are mounted. The packaging substrate can have multiple layers and include an RF signal path implemented on a selected layer. Each of at least one neighboring layer above the selected layer and at least one neighboring layer below the selected layer can be configured to be sufficiently free of a ground feature relative to the RF signal path to yield a reduced parasitic capacitance while substantially maintaining a desired impedance for the RF signal path. | 2016-05-05 |
20160126200 | SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRATED ANTENNA FOR WIRELESS APPLICATIONS - A semiconductor device package is provided with integrated antenna for wireless applications. The semiconductor device package comprises a substrate including a semiconductor chip mounted thereon: a protective layer covering the semiconductor chip; a metal pattern mounted on the protective layer; and a first connective member connecting the semiconductor chip and the metal pattern. According to this configuration, the semiconductor device package is capable of being easily manufactured while minimizing the electrical distance between the metal pattern for use as an antenna and the semiconductor chip. | 2016-05-05 |
20160126201 | DUAL LAYER STACK FOR CONTACT FORMATION - A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer. | 2016-05-05 |
20160126202 | BRIDGING ARRANGEMENT, MICROELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING A BRIDGING ARRANGEMENT - A bridging arrangement includes a first and a second surface defining a gap therebetween. At least one surface of the first and second surface has an anisotropic energy landscape. A plurality of particles defines a path between the first and second surface bridging the gap. | 2016-05-05 |