18th week of 2016 patent applcation highlights part 59 |
Patent application number | Title | Published |
20160125903 | PERPENDICULAR MAGNETIC RECORDING MEDIUM HAVING AN OXIDE SEED LAYER AND RU ALLOY INTERMEDIATE LAYER - In one embodiment, a perpendicular magnetic recording medium includes a substrate; a soft magnetic underlayer positioned above the substrate; a seed layer structure positioned above the soft magnetic underlayer, the seed layer structure including a first seed layer and a second seed layer positioned above the first seed layer; an interlayer structure positioned above the seed layer structure, the interlayer structure including a first interlayer, a second interlayer positioned above the first interlayer, and a third interlayer positioned above the second interlayer; and a magnetic recording layer positioned above the interlayer structure, where the second seed layer includes a Ni alloy including at least one oxide, and where the first interlayer includes a Ru alloy. | 2016-05-05 |
20160125904 | PERPENDICULAR MAGNETIC RECORDING DISK WITH PATTERNED TEMPLATE LAYER - A perpendicular magnetic recording (PMR) disk has a patterned template layer for the growth of the magnetic grains and the nonmagnetic material surrounding the grains. The template layer is a substantially planar platinum (Pt) or palladium (Pd) layer that is patterned to have Pt or Pd regions arranged in a hexagonal-close-packed (hcp) pattern with the Pt or Pd regions surrounded by Pt-oxide or Pd-oxide regions. The two separate regions of the template layer have different surface chemistries and energies, which provide a “chemical contrast” to impinging atoms during deposition of the metallic magnetic material and nonmagnetic (typically oxide) material, effectively guiding the deposition. The metallic magnetic material is preferentially deposited on the pristine, epitaxial Pt or Pd regions to form the magnetic grains, while the oxide migrates to the oxidized Pt or Pd regions due to the matching of lower surface energy. | 2016-05-05 |
20160125905 | APPARATUS AND METHOD FOR DETECTING A SYMBOL ON A TWO-DIMENSIONAL STORAGE MEDIUM - The invention relates to an apparatus and method for detecting a symbol from a set of readout values from a local neighborhood of a two-dimensional storage medium, comprising: evaluating a joint probability distribution for a given observation and a complete set of data patterns in the local neighborhood; and choosing as detection output a weighted average of the center values of the data patterns, using the values of the associated joint probability distribution as weights; wherein the joint probability distribution is a multi variant Gaussian probability distribution which employs vectorial observations, vectorial averages, and covariance matrixes. | 2016-05-05 |
20160125906 | HOLOGRAM REPRODUCING DEVICE AND HOLOGRAM REPRODUCING METHOD - A hologram reproducing device which reproduces information from a recording medium having information recorded by interfering a signal beam and a reference beam, provided with a first light-angle change unit which changes an irradiation angle of the reference beam; a second light-angle change unit which changes the irradiation angle of the reference beam; a photodetector which detects a reproduction beam; a first light-angle drive-signal output unit which outputs a drive signal of the first light-angle change unit; a first light-angle control unit which controls the first light-angle change unit on the basis of the output of the photodetector; a second light-angle drive-signal output unit which outputs a drive signal of the second light-angle change unit; a second light-angle control unit which controls the second light-angle change unit; and a light-angle interpolation processing unit which controls a control target value of the second light-angle control unit. | 2016-05-05 |
20160125907 | INFORMATION RECORDING MEDIUM AND METHOD FOR REPRODUCING THE SAME - An information recording medium ( | 2016-05-05 |
20160125908 | OPTICAL INFORMATION RECORDING MEDIUM, REPRODUCTION METHOD, AND REPRODUCTION DEVICE - In a case where (i) a reflectance calculated from a reflected light amount obtained from a longest pit (P | 2016-05-05 |
20160125909 | TENSION FEEDBACK FOR TAPE TENSION - A tension feedback signal is generated to reduce tension variation on a tape occurring at a reel frequency. Tension variation information may be obtained and used to generate the tension feedback signal. The tension feedback signal may be combined with a constant tension preset signal. The combined signal may be used to drive a tape reel at a tape reel speed adjusted according to the combined signal. | 2016-05-05 |
20160125910 | Networked Divided Electronic Video Messaging System and Method - A video received over a network is provided to a computing device with machine executable display instructions for allowing a display of each frame of a plurality of frames of a video in a separate successive screen display. The video may be divided at one or more computers prior to display. Each portion can be displayed in a subregion of a video display region corresponding to a subregion of the portion in the frame. One or more interfaces may also be provided to a user for dividing frames of a video, modifying an image parameter of one or more portions of one or more frames, designating a recipient for a transmitted video, providing additional visual information to a video, and/or for providing other functions. Systems, methods, and machine readable hardware storage media are provided for transmitting a video. | 2016-05-05 |
20160125911 | SYSTEMS AND METHODS FOR REDUCING AUDIO DISTORTION DURING PLAYBACK OF PHONOGRAPH RECORDS USING MULTIPLE TONEARM GEOMETRIES - Systems and methods are disclosed relating to electro-mechanical devices and related computer control and audio processing systems intended to optimize playback fidelity of phonograph records. Said recordings are manufactured by a process that employs a cutting head assembly driven in a straight path from the outer to the inner-most radius of the recordable surface. However, most record turntables device that are used to play back phonograph records rely on a stylus transducer attached to the end of a pivoting arm. Instead of the linear path followed by the original cutting head, said tonearm traces an arc across the surface of the recorded disk resulting in playback distortion proportional to error in alignment of said stylus relative to the tangent of the groove. This invention addresses this deficiency and produces an optimal audio quality of playback of phonograph records. | 2016-05-05 |
20160125912 | ADJUSTABLE DUAL TENSIONING TONE ARM DEVICE AND ASSEMBLY - A record player capable of playing phonographic records that may be played in a scratch style by a user. The record player includes a tonearm that is rotatably supported at or near an end of the tonearm by a structure having both horizontally and vertically fastening points to the tonearm. The fastening points are configured to receive a user activated tension adjustment element. A user may advance or retreat the tension adjustment element to selectably control the positioning, or relative tension in the tonearm such that any record skipping due to undesirable tonearm pressure is controlled, or to achieve a specific sound. | 2016-05-05 |
20160125913 | Playback Regulation Method and Apparatus - A play regulation method and apparatus is presented, which relates to the field of play control of multimedia files, so as to adjust play progress more precisely and reduce misoperations. A technical solution provided in the present disclosure includes: receiving a step and play hybrid regulation operation entered by a user, where the step and play hybrid regulation operation includes both an adjustment instruction for a step speed and a regulation instruction for play progress; and regulating the step speed and the play progress according to the step and play hybrid regulation operation. The present disclosure is applied to a terminal having a media player and a touchscreen. | 2016-05-05 |
20160125914 | Separated Viewing and Screen Capture Prevention System and Method for Electronic Video - Each frame of a plurality of frames of a video can be divided into a plurality of portions. The portions of the frames of a divided video can be displayed in separate successive screen displays. A divided video may be transmitted from one computer to another. One or more interfaces may be provided to a user for dividing frames of a video, modifying an image parameter of one or more portions of one or more frames, designating a recipient for a transmitted video, providing additional visual information to a video, and/or for providing other functions. Systems, methods, and machine readable hardware storage media are provided for displaying a video. | 2016-05-05 |
20160125915 | Electronic Video Division and Transmission System and Method - One or more frames of a video may be modified by having each of the one or more frames divided into a plurality of portions and in other ways. Dividing a frame may occur in a variety of ways including via the use of an interface and automatic dividing. An interface can be provided that allows a user to input instructions for dividing a frame into a plurality of portions such as by positioning one or more lines to divide the frame, defining a plurality of polygons, and other ways. A divided video may be displayed such that each of the plurality of portions of the one or more frames is displayed in a separate successive screen display. Systems, methods, and machine readable hardware storage media are provided for displaying an electronic image. | 2016-05-05 |
20160125916 | Collaborative Movie Creation - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described that enable crowd-sourced collaborative movie-making. An aggregate set of movies contributed by one or more users may be analyzed to determine statistical information regarding selection of different media clips by the crowd of contributors, as well as to determine metadata information of the media clips selected by the crowd of contributors. Based on the statistical usage information and the metadata information of the aggregate set of movies contributed by the crowd, different types of crowd-view movies may be generated that represent different views and themes of the collaborative movie-making effort of the crowd. Different crowd-view movies may therefore be generated from the same set of contributed movies based on the specific preferences of a viewer requesting to view a crowd-view movie. | 2016-05-05 |
20160125917 | SYSTEM, METHOD, AND APPARATUS FOR EMBEDDING PERSONAL VIDEO RECORDING FUNCTIONS AT PICTURE LEVEL - Described herein are system(s), method(s), and apparatus for embedding personal video recorder functions at the picture level. In one embodiment, there is presented a computer readable medium for storing a data structure. The data structure comprises a picture header and at least one command following the picture header. | 2016-05-05 |
20160125918 | WARP CORRECTION APPARATUS FOR PLATE-LIKE WORKPIECE AND WARP CORRECTION METHOD - A warp correction apparatus includes an elastic mat, a first sheet supply unit which supplies a first clean sheet on the elastic mat, a workpiece holding mechanism which supplies the plate-like workpiece (a frame unit) on the first clean sheet, a second sheet supply unit which supplies a second clean sheet above the first clean sheet, a pressure roller, a first elevator unit which moves the second clean sheet up and down, a second elevator unit which presses the pressure roller toward the elastic mat, and a roller moving mechanism. The pressure roller is moved along an upper surface of the elastic mat by the roller moving mechanism while the frame unit is sandwiched between the elastic mat and the pressure roller. | 2016-05-05 |
20160125919 | APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation. | 2016-05-05 |
20160125920 | MEMORY DEVICE WITH LOW POWER OPERATION MODE - A memory device that operates in a low-power operation mode includes a memory cell array, a page size changing circuit, and an encoding and decoding changing circuit. The page size changing circuit changes the number of data items prefetched in the memory cell array according to a power mode during a read operation. The encoding and decoding changing circuit changes a level of data written in the memory cell array according to the power mode during a read operation. | 2016-05-05 |
20160125921 | INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME, PROGRAM, AND STORAGE MEDIUM - An information processing apparatus, equipped with a WideIO memory device stacked on an SOC die including a CPU, and a method of controlling the same, are provide. The apparatus obtains temperature information of each of a plurality of memories of the WideIO memory device, and generates temperature distribution information of the WideIO memory device in accordance with respective execution of a plurality of function modules. Then, the apparatus determines a refresh rate of the WideIO memory device based on the maximum temperature of the WideIO memory device, decides a period, at which the refresh rate is determined, based on an operation mode of the information processing apparatus and a change rate of the maximum temperature for a predetermined time interval, and refreshes the WideIO memory device in accordance with the determined refresh rate. | 2016-05-05 |
20160125922 | THRESHOLD VOLTAGE GROUPING OF MEMORY CELLS IN SAME THRESHOLD VOLTAGE RANGE - A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell. | 2016-05-05 |
20160125923 | MULTI-CHANNEL MEMORY SYSTEM USING ASYMMETRIC CHANNEL FREQUENCY SCALING AND RELATED POWER MANAGEMENT METHOD - A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency. | 2016-05-05 |
20160125924 | MAGNETO-RESISTIVE DEVICES - Magneto-resistive devices with lower power consumption and higher stability are provided. The magneto-resistive devices may include a pinned layer, a free layer and an insulating layer between the pinned layer and the free layer. The pinned layer, the free layer and the insulating layer may constitute a magnetic tunnel junction. The free layer may include a first magnetic layer and a second magnetic layer that has a Curie temperature lower than a Curie temperature of the first magnetic layer. | 2016-05-05 |
20160125925 | ENERGY EFFICIENT THREE-TERMINAL VOLTAGE CONTROLLED MEMORY CELL - Memory cell, method for operating the memory cell and method for fabricating the memory cell are disclosed. The memory cell includes at least three terminals, a first magnetic tunnel junction (MTJ) structure and a second MTJ structure. The first MTJ is coupled between a first terminal (FT) and a third terminal. A portion of the first MTJ is configured to include a first barrier layer disposed between a first fixed layer and a free layer (FL). A magnetization direction of the FL is used to store data, the magnetization direction being controlled by an electric field. The second MTJ is coupled between the FT and a second terminal, where a portion of the second MTJ is configured to include a second barrier layer disposed between a second fixed layer and the FL, where a tunnel magnetoresistance of the second barrier layer is used to read the data. | 2016-05-05 |
20160125926 | SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY - A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance. | 2016-05-05 |
20160125927 | APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY - Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected. | 2016-05-05 |
20160125928 | BITCELL WTH MAGNETIC SWITCHING ELEMENTS - A method includes receiving a data bit value at a buffer in a bitcell based on a first state of a write bitline connected to the buffer, and transferring the data bit value from the buffer to a first magnetic switching cell in the bitcell for a later read operation at least by holding the write bitline to a reference value different from the first state, and asserting first and second predetermined voltage levels on respective first and second write wordlines connected to the buffer. | 2016-05-05 |
20160125929 | METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 2016-05-05 |
20160125930 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 2016-05-05 |
20160125931 | SEMICONDUCTOR MEMORY DEVICE THAT PERFORMS A REFRESH OPERATION - A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change. | 2016-05-05 |
20160125932 | SEMICONDUCTOR STORAGE DEVICE - There is provided a semiconductor storage device in which memory cells can easily be set at a proper potential in standby mode, along with a reduction in the area of circuitry for controlling the potential of source lines of memory cells. A semiconductor storage device includes static-type memory cells and a control circuit. The control circuit includes a first switching transistor provided between a source line being coupled to a source electrode of driving transistors and a first voltage, a second switching transistor provided in parallel with the first switching transistor, and a source line potential control circuit which makes the first and second switching transistors conductive to couple the source line to the first voltage, when the memory cells are operating, and sets the first switching transistor non-conductive and sets a gate electrode of the second switching transistor coupled to the source line in standby mode. | 2016-05-05 |
20160125933 | CIRCUIT-LEVEL ABSTRACTION OF MULTIGATE DEVICES USING TWO-DIMENSIONAL TECHNOLOGY COMPUTER AIDED DESIGN - A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the circuit, wherein the second static noise margin curve is complementary to the first static noise margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell. | 2016-05-05 |
20160125934 | METHOD OF CONTROLLING AUXILIARY BRANCHES FOR SRAM CELL - A method includes: during a read operation of a first storage node and a second storage node formed by cross-coupled inverters, based on data stored in the first storage node and the second storage node, causing a first auxiliary branch or a second auxiliary branch to assist a corresponding one of the cross-coupled inverters in holding data; and during a write operation of the first storage node and the second storage node, based on data to be written to the first storage node and the second storage node, causing the first auxiliary branch or the second auxiliary branch to assist a corresponding one of the cross-coupled inverters in flipping data. | 2016-05-05 |
20160125935 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device and a method of operating the same are provided. The method includes performing a program operation on a memory cell so that a threshold voltage of the memory cell is greater than a main verifying voltage, and while the program operation is performed, a bit line voltage applied to a bit line connected to the memory cell gradually increases based on the threshold voltage of the memory cell and the number of times a program voltage is applied to a word line connected to the memory cell. | 2016-05-05 |
20160125936 | PHASE CHANGE MEMORY WITH METASTABLE SET AND RESET STATES - A memory device that includes a phase change material. The phase change material is programmable to a metastable set state and metastable reset state. Furthermore, the phase change material includes an initial state with an initial electrical resistance between the set electrical resistance and the reset electrical resistance. The initial state is at a lower potential energy than the set state and the reset state. Thus, the electrical resistance of the phase change material programmed to the set state or the reset state drifts toward the initial electrical resistance over time. The memory device also includes a first electrode electrically coupled to a first area of the phase change material, and a second electrode electrically coupled to a second area of the phase change material. | 2016-05-05 |
20160125937 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A LEAKAGE CURRENT SENSING UNIT AND METHOD OF OPERATING THE SAME - A semiconductor integrated circuit device configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The semiconductor integrated circuit device may include a leakage current sensing unit configured for sensing a pure leakage current of a cell array, and a determination circuit unit configured for comparing a voltage level of the input node with a reference voltage and for determining a state of read data while in a read mode. Whereby an output current may be compared with a read current of the cell array at the input node, and the output current may include the summation of the pure leakage current and a reference current. | 2016-05-05 |
20160125938 | PHASE CHANGE MEMORY WITH METASTABLE SET AND RESET STATES - A memory device that includes a phase change material. The phase change material is programmable to a metastable set state and metastable reset state. Furthermore, the phase change material includes an initial state with an initial electrical resistance between the set electrical resistance and the reset electrical resistance. The initial state is at a lower potential energy than the set state and the reset state. Thus, the electrical resistance of the phase change material programmed to the set state or the reset state drifts toward the initial electrical resistance over time. The memory device also includes a first electrode electrically coupled to a first area of the phase change material, and a second electrode electrically coupled to a second area of the phase change material. | 2016-05-05 |
20160125939 | RESISTIVE MEMORY DEVICE AND OPERATING METHOD - Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current. | 2016-05-05 |
20160125940 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A LEAKAGE CURRENT SENSING UNIT AND METHOD OF OPERATING THE SAME - A semiconductor integrated circuit device and a system including the same, configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The system a controller and a memory configured to interface with the controller. The memory includes a semiconductor integrated circuit device includes a leakage current sensing unit configured to sense a pure leakage current of a cell array according to a command of the controller; and a determination circuit unit configured to compare a voltage level of an input node with a reference voltage and determine a state of read data while in a read mode. The voltage level of the input node is decided by comparing an output current and a read current and the output current is decided by summing the pure leakage current and a reference current. | 2016-05-05 |
20160125941 | RESISTIVE CHANGE ELEMENT ARRAYS USING RESISTIVE REFERENCE ELEMENTS - Methods for dynamically programming and dynamically reading one or more resistive change elements within a resistive change element array are disclosed. These methods include first pre-charging all of the array lines within a resistive change element array simultaneously and then grounding certain array lines while allowing other array lines to float in order to direct discharge currents through only selected cells. In this way, resistive change elements within resistive change element arrays made up of 1-R cells—that is, cells without in situ selection circuitry—can be reliably and rapidly accessed and programmed. | 2016-05-05 |
20160125942 | RESISTIVE MEMORY DEVICE AND OPERATING METHOD - A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval. | 2016-05-05 |
20160125943 | METHODS AND APPARATUS FOR PROGRAMING MEMORY OF A PRINTING CARTRIDGE - Methods to program a floating gate memory array include, in response to a request to program a second bit of the floating gate memory array, at a first time, outputting a programming voltage to cause a first node voltage at a first source of a first transistor corresponding to a first bit, wherein the first node voltage is greater than a second node voltage at a second source of a second transistor corresponding to the second bit. The method further includes at a second time, increasing the programming voltage of the floating gate memory array to program the second bit of the floating gate memory array. | 2016-05-05 |
20160125944 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment may include a memory string including a drain selection transistor, memory cells and a source selection transistor all coupled between a bit line and a common source line, and the drain selection transistor, the memory cells and the source selection transistor configured to operate, respectively, in response to voltages applied to a drain selection line, word lines and a source selection line. The semiconductor device may include an operation circuit configured for performing a program operation. The operation circuit may be configured for sequentially performing a first operation, a second operation, and a third operation. In the first operation memory cells adjacent to the drain selection transistor may be programmed. In the second operation memory cells adjacent to the source selection transistor may be programmed. In the third operation remaining memory cells may be programmed. | 2016-05-05 |
20160125945 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. | 2016-05-05 |
20160125946 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a memory array including memory blocks, and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the operation circuit performs the program loop on the selection transistors so that a difference occurs between threshold voltages of the selection transistors and a target threshold voltage based on a difference between a cell current value of the selected memory block and a reference cell current value. | 2016-05-05 |
20160125947 | PROGRAMMING METHOD FOR NAND-TYPE FLASH MEMORY - The invention provides a programming method for a NAND-type flash memory capable of reducing the drop in reliability due to data-rewriting. The programming method includes: when a block program mode is executed to perform programming for a plurality of pages in a block, while the data to be programmed is being loaded into a cache memory; and erasing the selected block; and programming the data to be programmed which is loaded into the cache memory to the erased block. | 2016-05-05 |
20160125948 | SENSE AMPLIFICATION CIRCUITS, OUTPUT CIRCUITS, NONVOLATILE MEMORY DEVICES, MEMORY SYSTEMS, MEMORY CARDS HAVING THE SAME, AND DATA OUTPUTTING METHODS THEREOF - An output circuit of a nonvolatile memory device includes a sense amplification circuit configured to, during a sensing operation, generate output data based on a comparison between a first voltage on a data line and a reference voltage on a reference data line during a sensing operation, the first voltage corresponding to data read from at least one memory cell, and the sense amplification circuit being further configured to connect the reference data line with a ground terminal during the sensing operation. | 2016-05-05 |
20160125949 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device includes applying a read voltage to a selected word line of a selected memory block, among a plurality of memory blocks including cell strings coupled between bit lines and a source line, detecting a voltage of the source line by forming a channel in cell strings of the selected memory block, comparing the voltage of the source line with a reference voltage corresponding to the selected memory block, and performing a least significant bit (LSB) read operation on memory cells coupled to the selected word line when the voltage of the source line is greater than the reference voltage, as a result of the comparing, and performing a most significant bit (MSB) read operation on the memory cells when the voltage of the source line is less than the reference voltage, as the result of the comparing. | 2016-05-05 |
20160125950 | DATA STORAGE DEVICE - According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode. | 2016-05-05 |
20160125951 | DETECTING VOLTAGE THRESHOLD DRIFT - Apparatuses, systems, methods, and computer program products are disclosed for detecting voltage threshold drift. A method includes programming a predetermined pattern to one page of at least three pages of a set of memory cells. A pattern may have a configuration to reduce a number of bit transitions between abodes of a set of memory cells based on a coding scheme for the set of memory cells. A method includes reading data from a different page of at least three pages. A method includes determining a direction for adjusting a read voltage threshold for a set of memory cells based on read data. | 2016-05-05 |
20160125952 | NONVOLATILE MEMORY ERASURE METHOD AND DEVICE - Disclosed are non-volatile memory erasure method and device for solving the problem of unnecessary time expenditure and complex process of the current erasure operation. The method comprises: after receiving an erasure instruction, performing a pre-reading verification on the target erasure area corresponding to the erasure instruction; if the pre-reading verification passes, then performing an erasure operation on the target erasure area; if not, then performing pre-programming verification on the target erasure area, and after the pre-programming verification passes, performing the erasure operation on the target erasure area. The method of the present application can eliminate the unnecessary pre-programming verification process while ensuring the target erasure area is in a full-erasure state before the erasure operation, thus saving erasure time and simplifying the erasure process. | 2016-05-05 |
20160125953 | OTP CELL WITH REVERSED MTJ CONNECTION - A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current. | 2016-05-05 |
20160125954 | SHIFT REGISTER AND A GATE DRIVING DEVICE - The present invention discloses a shift registor and a gate driving device, the shift register comprising: an input module for providing an input signal to a pull-up node; an output module for storing the input signal and providing a first clock signal to an output terminal; a reset module for providing a level signal to the pull-up node; a pull-up module for providing a second clock signal to a pull-down node; a first pull-down module for providing the level signal to the pull-down node; and a second pull-down module for providing the level signal to the pull-up node and providing the level signal to the output terminal. | 2016-05-05 |
20160125955 | Shift Register, Driving Method Thereof and Gate Driving Circuit - A shift register, driving method thereof and a gate driving circuit are disclosed, wherein the shift register comprises an input module, a reset module, a first output module, a second output module and a control module. The shift register uses the first clock signal to control the second node, and then controls the signal output by the signal output terminal by alternate high/low levels of the second node and the second clock signal, such that the signal output terminal can always output signals to eliminate noises and stabilize row output signals. In addition, since the second node has alternate high/low levels, the life span of the shift register can be protected. | 2016-05-05 |
20160125956 | Erase Stress and Delta Erase Loop Count Methods for Various Fail Modes in Non-Volatile Memory - Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including erase disturb and shallow erase. For detection of shallow erase, cells are programmed and then erased, where the variation (delta) in the number of erase loop counts can be used to determine defective blocks. To determine blocks prone to erase disturb, an erase stress is applied to unselected blocks, after which they are programmed: after then erasing one block, the next block can then be read to determine whether it has suffered erase disturb. | 2016-05-05 |
20160125957 | SCAN CHAIN FOR MEMORY SEQUENTIAL TEST - A method for constructing a scan chain for a memory sequential test, including determining an input boundary register of the memory; determining a number N of test vectors required according to the type of the memory input pins to which the input boundary register is connected; arranging the scan chain based on the number N, such that in the scan chain, upstream of the input boundary register and immediately adjacent to the input boundary register, there are at least (N−1) continuous non-boundary registers; and setting control signals of the input boundary register and the (N−1) non-boundary registers to make them receive scan test input as test vectors under memory sequential test mode. | 2016-05-05 |
20160125958 | TESTING STORAGE DEVICE POWER CIRCUITRY - The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails. | 2016-05-05 |
20160125959 | HEALTH STATE OF NON-VOLATILE MEMORY - An embodiment relates to a method for determining a health state of a non-volatile memory comprising: determining the health state based on at least one indicator for determining a predictable failure of the non-volatile memory. | 2016-05-05 |
20160125960 | SYSTEM AND METHOD FOR WRITE ABORT DETECTION - Systems, apparatuses, and methods are provided for write abort detection. A memory system may write data to one or more cells in a memory. An abrupt shutdown may interrupt the write, resulting in an uncertainty as to the state of the memory cells. In order to determine the state of the memory cells, after power-up, a first section of memory that includes the memory cells is analyzed, such as counting values of logic “0”s stored in the memory cells of the first section of memory. However, the values in the first section of memory may be subject to error, hindering the accuracy of write abort detection. In order to reduce or cancel the effect of the errors, a second section of memory (which may suffer from similar errors as the first section) is analyzed, such as by counting values of logic “0”s stored in the memory cells of the second section of memory. The differential value of the counts from the two sections is determined, thereby reducing or eliminating the effect of the errors, and then analyzed to determine the state of the first section of memory for write abort detection. | 2016-05-05 |
20160125961 | Semiconductor Device Having Hierarchically Structured Bit Lines - Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell. | 2016-05-05 |
20160125962 | System for Regulating a Liquid in a Circuit - This invention relates to a system for regulating a liquid in a circuit, with the system comprising: a plug valve comprising at least one inlet and one outlet, the plug comprising an internal passage through which is intended to pass the liquid flowing from the inlet to the outlet of the valve when the valve is open at least partially, an expansion reservoir in communication with the liquid flowing in the circuit and intended to contain liquid and a compensating gas, characterised in that the plug comprises at least partially an expansion channel which has at least one lateral opening located on a lateral face of the plug and which is conformed to provide a permanent communication between said lateral opening and the expansion reservoir, the valve being conformed in such a way that: at least when the valve is closed: the lateral opening is in direct communication with the liquid coming from the inlet or from the outlet of the valve, when the valve is open at least partially, the lateral opening cooperates with an inner wall integral with a body of the valve in such a way as to form a conduit in communication on the one hand with the expansion reservoir and on the other hand with the internal passage. The invention also relates to a circuit integrating this system as well as a use of this system. | 2016-05-05 |
20160125963 | INTRINSICALLY SAFE NUCLEAR REACTOR - An improved nuclear fission reactor of the liquid metal cooled type including a core configuration allowing for only two operational states, “Power” or “Rest”. The flow of the primary cooling fluid suspends the core in the “Power” state, with sufficient flow to remove the heat to an intermediate heat exchanger during normal operation. This invention utilizes the force of gravity to shut down the reactor after any loss of coolant flow, either a controlled reactor shut down or a “LOCA” event, as the core is controlled via dispersion of fuel elements. Electromagnetic pumps incorporating automatic safety electrical cut-offs are employed to shutdown the primary cooling system to disassemble the core to the “Rest” configuration due to a loss of secondary coolant or loss of ultimate heat sink. This invention is a hybrid pool-loop pressurized high-temperature or unpressurized reactor unique in its use of a minimum number of components, utilizing no moving mechanical parts, no rotating seals, optimized piping, and no control rods. Thus defining an elegantly simple intrinsically safe nuclear reactor. | 2016-05-05 |
20160125964 | SEISMIC ATTENUATION SYSTEM FOR A NUCLEAR REACTOR - A system for attenuating seismic forces includes a reactor pressure vessel containing nuclear fuel and a containment vessel that houses the reactor pressure vessel. Both the reactor pressure vessel and the containment vessel may include a bottom head. Additionally, the system may include a base support that is configured to contact a support surface on which the containment vessel is positioned in a substantially vertical orientation. An attenuation device may be located between the bottom head of the reactor pressure vessel and the bottom head of the containment vessel. Seismic forces that travel from the base support to the reactor pressure vessel via the containment vessel may be attenuated by the attenuation device in a direction that is substantially lateral to the vertical orientation of the containment vessel. | 2016-05-05 |
20160125965 | Power Plant - A power plant includes a steam generator, a turbine driven by steam generated by the steam generator, a condenser which cools the steam discharged from the turbine to form condensate water by using seawater, a condensate water pipe which supplies the condensate water from the condenser to the steam generator, at least one seawater leak detection device which is included in the condensate water pipe and measures water quality of the condensate water to detect a leak of seawater in the condenser, an attemperator spray which connects to the condensate water pipe to be supplied with the condensate water from a connecting point where the attemperator spray connects to the condensate water pipe, and sprays the condensate water to the steam inside the condenser, and a pipe which diverges from the condensate water pipe and supplies the condensate water to the steam generator, wherein if the seawater leak detection device detects a leak of the seawater in the condenser, the power plant stops pouring the condensate water from the connecting point to the steam generator and stops pouring the condensate water to the pipe diverging from the condensate water pipe. | 2016-05-05 |
20160125966 | STORAGE CONTAINER FOR IRRADIATED FUEL COMPRISING SHOCK-ABSORBING CASE GUIDE RAILS - A package ( | 2016-05-05 |
20160125967 | COMPOSITION ENABLING CONTROL OVER NEUTRALIZING RADIOACTIVITY USING MUON SURROGATE CATALYZED TRANSMUTATIONS AND QUANTUM CONFINEMENT ENERGY CONVERSION - A binding reaction creates transient, elevated effective mass electron quasiparticles as surrogates for a heavier muon, to cause muon-catalyzed fusion transmutations with the surrogates and creates a composition of matter that enables neutralizing certain radioactive waste nuclei. Tailoring a junction of a device enhances the control of the surrogate's transient effective mass. | 2016-05-05 |
20160125968 | X-RAY INTENSIFYING SCREENS INCLUDING MICRO-PRISM REFLECTIVE LAYER FOR EXPOSING X-RAY FILM, X-RAY FILM CASSETTES, AND X-RAY FILM ASSEMBLIES - An intensifying screen for exposing X-ray film includes a screen support backing, a luminescent layer having a luminescent material that emits light in the presence of X-rays, and a reflective layer disposed between the luminescent layer and the screen support backing, the reflective layer including a plurality of micro-prisms that reflect light emitted by the luminescent material. An X-ray film cassette includes at least one intensifying screen and a housing surrounding the at least one intensifying screen. | 2016-05-05 |
20160125969 | LIGHT-TRANSMITTING CONDUCTIVE FILM, DISPLAY DEVICE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD OF LIGHT-TRANSMITTING CONDUCTIVE FILM - An object is to provide a transparent conductive film having favorable transparency and conductivity at low cost. Another object is to reduce the resistivity of a transparent conductive film formed using conductive oxynitride including zinc and aluminum. Another object is to provide a transparent conductive film that is formed using conductive oxynitride including zinc and aluminum. When aluminum and nitrogen are made to be included in a transparent conductive film formed using oxide including zinc to form a transparent conductive film that is formed using conductive oxynitride including zinc and aluminum, the transparent conductive film can have reduced resistivity. Heat treatment after the formation of the transparent conductive film that is formed using conductive oxynitride including zinc and aluminum enables reduction in resistivity of the transparent conductive film. | 2016-05-05 |
20160125970 | CORE-SHELL NANO PARTICLE FOR FORMATION OF TRANSPARENT CONDUCTIVE FILM, AND MANUFACTURING METHOD OF TRANSPARENT CONDUCTIVE FILM USING THE SAME - Disclosed herein are a core-shell nano particle for formation of a transparent conductive film, a manufacturing method of the core-shell nano particle, and a manufacturing method of a transparent conductive film using the core-shell nano particle and, more particularly, a core-shell structured nano particle consisting of a core including indium or indium oxide and a shell including tin, a manufacturing method of the core-shell structured nano particle, and a manufacturing method of a transparent conductive film including (i) dispersing a core-shell structured nano particle into a solvent to manufacture a coating liquid, (ii) applying the coating liquid onto a substrate to form a coating layer, (iii) drying the coating layer, and (iv) performing an annealing process on the coating layer. | 2016-05-05 |
20160125971 | RESIN COMPOSITION FOR PRINTED WIRING BOARD MATERIAL AND PREPREG, RESIN SHEET, METAL FOIL-CLAD LAMINATE, AND PRINTED WIRING BOARD USING THE SAME - A resin composition used as a material of an insulating layer of a printed wiring board including the insulating layer and a conductor layer formed on a surface of the insulating layer by plating, the resin composition including: an epoxy compound; a cyanate compound; a maleimide compound; an inorganic filler; and an imidazole silane, wherein the maleimide compound includes a predetermined maleimide compound, a content of the maleimide compound is 25% by mass or less based on 100% by mass of a total content of the epoxy compound, the cyanate compound, and the maleimide compound, and the imidazole silane includes a compound represented by the formula (3). | 2016-05-05 |
20160125972 | RESIN COMPOSITION, PREPREG, RESIN SHEET AND METAL FOIL-CLAD LAMINATE - The resin composition of the present invention comprises a cyanate ester compound (A) obtained by cyanating a modified naphthalene formaldehyde resin, and an epoxy resin (B). | 2016-05-05 |
20160125973 | CABLE - A cable includes a conductor, an insulation coating layer on the conductor, and an outer coating layer on the insulation coating layer. The insulation coating layer is made of a composition containing 100 parts by mass of a base polymer (A) and 100 to 250 parts by mass of a non-halogen flame retardant. The polymer (A) contains 70% to 99% by mass of an ethylene-vinyl acetate copolymer (a1) containing an ethylene-vinyl acetate copolymer having a melting point of 70° C. or higher, and 1% to 30% by mass of an acid-modified polyolefin resin (a2) having a glass transition point of −55° C. or lower. The polymer (A) contains 25% to 50% by mass of a vinyl acetate component derived from the copolymer (a1). The outer coating layer is made of a composition containing 100 parts by mass of a base polymer (B) and 150 to 220 parts by mass of a non-halogen flame retardant. The polymer (B) contains 60% to 70% by mass of a linear low-density polyethylene (b1), 10% by mass or more of an ethylene-vinyl acetate copolymer (b2) having a melt flow rate of 100 g/10 min or more, and 10% to 20% by mass of a maleic acid-modified polyolefin (b3). | 2016-05-05 |
20160125974 | MEDIUM- OR HIGH-VOLTAGE ELECTRIC DEVICE - The invention relates to an electric device ( | 2016-05-05 |
20160125975 | MEDIUM- OR HIGH-VOLTAGE ELECTRIC DEVICE - The invention relates to an electrical device ( | 2016-05-05 |
20160125976 | CONDUCTIVE WIRE WITH SEAL FUNCTION AND MANUFACTURING METHOD THEREOF - A conductive wire includes a core formed of a plurality of conductive metal strands, a coating portion formed of an insulating material and configured to cover the core and seal portions arranged at intermediate positions in a coating portion and configured to hold clearances between the strands and between the core and the coating portion in a water-tight state. A sealant is supplied before the respective strands are twisted. By doing so, the sealant can be spread to a central part of the core and the clearances between the strands can be filled with the sealant. | 2016-05-05 |
20160125977 | OXIDE SUPERCONDUCTOR AND METHOD FOR MANUFACTURING SAME - An oxide superconductor includes: a substrate made of a metal; an insulating intermediate layer provided on the substrate; an oxide superconducting layer provided on the intermediate layer; a metal stabilizing layer provided on the oxide superconducting layer; and a plurality of dividing grooves which divide the metal stabilizing layer and the oxide superconducting layer along a longitudinal direction of the substrate, reach the inside of the intermediate layer through the oxide superconducting layer from the metal stabilizing layer, and do not reach the substrate. The metal stabilizing layer and the oxide superconducting layer are divided to form a plurality of filament conductors by the plurality of dividing grooves, and in each dividing groove of the plurality of dividing grooves, a width of a groove opening portion of the dividing groove is equal to or greater than a width of a groove bottom portion of the dividing groove. | 2016-05-05 |
20160125978 | Wire Harness Assembly System - A wire harness assembly system is disclosed. The wire harness assembly system includes a locking mount for receiving a wire routing accessory. The locking mount includes a main body with an upper portion, a base flange, and a lower portion. The lower portion includes a locating shaft extending from the base flange. The locating shaft has keyed members positioned opposite each other. The locating shaft and the keyed members of the locking mount are positioned in keyed holes in a grid tile. The locking mount is rotated to a locked position in the grid tile to secure the locking mount and the wire routing accessory mounted thereto. | 2016-05-05 |
20160125979 | ELECTRICALLY CONDUCTIVE PATH CONNECTING MEMBER - An electrically conductive path connecting member is provided with a plurality of conductors and one pair of insulating holding members. The plurality of conductors respectively have bent parts in a longitudinal direction. The one pair of insulating holding members hold both end parts of the conductors. | 2016-05-05 |
20160125980 | PROCESSING APPARATUS AND PROCESSING METHOD - According to one embodiment, a processing apparatus includes a container, a processor, a supply unit, a recovery unit, a calculator, and a replenishing liquid supply unit. The container contains buffered hydrogen fluoride. The processor performs processing of a processing object using the buffered hydrogen fluoride. The supply unit supplies the buffered hydrogen fluoride to the processor. The buffered hydrogen fluoride is contained in the container. The recovery unit recovers the buffered hydrogen fluoride used in the processor and supplies the recovered buffered hydrogen fluoride to the container. The calculator calculates an evaporation amount of the buffered hydrogen fluoride. The replenishing liquid supply unit supplies the same amount of a replenishing liquid as the calculated evaporation amount of the buffered hydrogen fluoride to the buffered hydrogen fluoride. The replenishing liquid includes ammonia and water. | 2016-05-05 |
20160125981 | RESISTOR, METHOD OF MANUFACTURING THE SAME, AND BOARD HAVING THE SAME - A resistor includes: a base substrate; a resistance layer disposed on one surface of the base substrate; first and second electrode layers disposed to be spaced apart from each other and covering portions of the resistance layer; and a third electrode layer disposed between the first and second electrode layers to be spaced apart from the first and second electrode layers and covering a portion of the resistance layer. | 2016-05-05 |
20160125982 | METAL NITRIDE MATERIAL FOR THERMISTOR, METHOD FOR PRODUCING SAME, AND FILM TYPE THERMISTOR SENSOR - Provided are a metal nitride material for a thermistor, which has a high heat resistance and a high reliability and can be directly deposited on a film or the like without firing, a method for producing the same, and a film type thermistor sensor. The metal nitride material for a thermistor consists of a metal nitride represented by the general formula: (M | 2016-05-05 |
20160125983 | VARISTOR DEVICE - A varistor device includes a main body, a conductive area, a specific-melting-point metallic pin, and an elastic unit. The main body has a first surface, and the conductive area is located at the first surface. The specific-melting-point metallic pin has a first section and a second section. The first section and the second section are one-piece formed. The first section is fixedly disposed on the conductive area. The second section has a specific melting point such that the second section melts when a current flows between the first surface and the second section so as to expose the second section to a temperature greater than the specific melting point. The elastic unit has an end connected to the second section, and the elastic unit provides an elastic force to the second section to break the second section so as to cut off the current when the second section melts. | 2016-05-05 |
20160125984 | SLIDE-TYPE VARIABLE RESISTOR - A slide-type variable resistor comprises a shell, two side guiding tracks, two end locking parts, a variable resistor circuit base, and a manipulating device. The two side guiding tracks are symmetrically assembled in the allocation space. The two end locking parts are symmetrically pressing against the two side guiding tracks respectively to have the two side guiding tracks positioned in the allocation space. The variable resistor circuit base is assembled to the shell and utilized for pressing against the two end locking parts to have the two end locking parts and the two side guiding tracks fixed in the allocation space. The manipulating device comprises a brush base, at least a brush, and a bar. The brush base has two symmetrically positioned sliding tracks slidably positioned in the two side guiding tracks. The brush is connected to the brush base and has elastic recovery to press against the variable resistor circuit base. The bar is connected to the brush base and extended outward from the position restriction hole of the shell. | 2016-05-05 |
20160125985 | Method Of Preparing A Hard Aluminum Film On The Surface Of A ND-FE-B Magnet - The present invention provides a Nd—Fe—B magnet including a first film of aluminum having a first predetermined hardness and an anti-corrosive coating of oxidized aluminum having a second predetermined hardness on the first film. The second predetermined hardness is at least eight times the first predetermined hardness. The present invention also provides a method for preparing a hard aluminum film on the Nd—Fe—B magnet. The method includes depositing the first film on the Nd—Fe—B magnet under vacuum, disposing the Nd—Fe—B magnet having the first film on the anode, and subjecting the Nd—Fe—B magnet having the first film to the anodic oxidation process under a solution containing an electrolyte present between 15 wt. % to 20 wt. % to form the anti-corrosive coating on the first film to prevent the Nd—Fe—B magnet from corroding. The electrolyte is selected from at least one of sulfuric acid, chromic acid, boric acid, and oxalic acid. | 2016-05-05 |
20160125986 | MAGNETIC STEEL SHEET HAVING A LAYER IMPROVING THE ELECTRICAL INSULATION AND METHOD FOR THE PRODUCTION THEREOF - A magnetic steel sheet including a layer adjoining at least one of a top side and bottom side of the magnetic metal sheet. The layer includes a metal oxide containing titanium oxide or tantalum oxide and the layer adjoins the magnetic steel sheet along a diffusion zone into which the titanium or tantalum of the metal oxide has diffused into the magnetic steel sheet. The diffusion zone is produced on at least one of a top surface and a bottom surface of the magnetic steel sheet and the diffusion layer diffuses one of tantalum and titanium as metal into the at least one surface. The metal of the at the at least one surface is converted into an associated metal oxide to form the layer including the metal oxide, and a residual content of the metal of the metal oxide remains in the diffusion zone. | 2016-05-05 |
20160125987 | SOFT MAGNETIC METAL COMPLEX - A soft magnetic metal complex includes a soft magnetic metal powder, an insulating nanopowder, and a polymer resin. Particles of the soft magnetic metal powder are coated with an insulating layer. The soft magnetic metal powder and the insulating nanopowder are contained in the polymer resin. | 2016-05-05 |
20160125988 | MAGNETIC ATTRACTION-FIXING ASSEMBLY, TWO-PIECE APPARATUS, AND ROTATING SUPPORT STRUCTURE FOR A PORTABLE DEVICE HAVING THE MAGNETIC ATTRACTION-FIXING ASSEMBLY - A magnetic attraction-fixing assembly and a rotating support structure for a portable device are provided. The magnetic attraction-fixing assembly includes two magnetic units, the two magnetic units stacked with and attracting each other; wherein each of the magnetic units respectively comprises a circular magnetic component and at least one annular magnetic component around the circular magnetic component, a magnetic pole of the circular plane of the circular magnetic component is an unlike pole to a magnetic pole of an annular plane of the annular magnetic component that is adjacent to the circular magnetic component. The rotating support structure comprises two magnetic units and a body. Magnetic attractions in both radial and axial directions are enhanced. | 2016-05-05 |
20160125989 | PERMANENT MAGNETIC CHUCKING DEVICE WITH LARGE FORCE DIFFERENTIAL - An apparatus usable as a chucking device to temporarily couple two mechanical objects together. In one embodiment, the apparatus includes an arbor configured to receive an at least partially ferromagnetic object; and a magnet assembly. The magnet assembly includes multiple permanent magnets mounted in a soft ferromagnetic enclosure. The magnet assembly is rotatably coupled to the arbor such that the magnet assembly and the arbor are positionable relative to one another in locking and unlocking positions upon relative rotation therebetween. The magnet assembly is configured to exert a pulling force on the object in the locking position and a lesser force in the unlocking position. | 2016-05-05 |
20160125990 | ACTUATOR WITH TRANSMISSION ELEMENT - An actuator ( | 2016-05-05 |
20160125991 | Methods and Systems For Push Pin Actuator - A push pin actuator apparatus is provided. The push pin actuator apparatus includes a housing, a wire coil arranged within the housing and arranged around a first armature and a second armature. The first armature is coupled to a first push pin and the second armature is coupled to a second push pin. The push pin actuator apparatus further includes a first permanent magnet and a second permanent magnet arranged on opposing sides of the first armature, and a third permanent magnet and a fourth permanent magnet arranged on opposing sides of the second armature. The first push pin is actuated in response to a current being applied to the wire coil in a first direction, and the second push pin is actuated in response to a current being applied to the wire coil in a second direction opposite to the first direction. | 2016-05-05 |
20160125992 | LINEAR ACTUATOR - A linear actuator ( | 2016-05-05 |
20160125993 | DETECTION OF PLUNGER MOVEMENT IN DC SOLENOIDS THROUGH CURRENT SENSE TECHNIQUE - An apparatus and method of detecting movement of a plunger of the solenoid includes detecting a peak (I | 2016-05-05 |
20160125994 | METHOD AND APPARATUS FOR NON-CONTACT AXIAL PARTICLE ROTATION AND DECOUPLED PARTICLE PROPULSION - An apparatus and method for magnetic particle manipulation enables the particle to be rotated and translated independently using magnetic fields and field gradients, which produce the desired decoupled translational and rotational motion. The apparatus and the method for manipulation may be implemented in parallel, involving many particles. The rotational magnetic field used to induce rotational motion may be varied to induce particle motion, which is either in phase or out of phase with the rotational magnetic field. The magnetic fields and gradients described herein may be generated with permanent magnets, electromagnets, or some combination of permanent magnets and electromagnets. | 2016-05-05 |
20160125995 | ARRAY OF INTERLEAVED 8-SHAPED TRANSFORMERS WITH HIGH ISOLATION BETWEEN ADJACENT ELEMENTS - An apparatus configured to isolate a direct current component voltage of a first circuit from a direct current component voltage of a second circuit in which the apparatus includes a first conductor and a second conductor. The first conductor has a first portion disposed to substantially enclose a first area, a second portion disposed within the first area, a third portion disposed to substantially enclose a second area, and a fourth portion disposed within the second area, the second area lacking an intersection with the first area. The second conductor is configured to be magnetically coupled to the first conductor and has a fifth portion disposed between the first portion and the second portion and a sixth portion disposed between the third portion and the fourth portion. | 2016-05-05 |
20160125996 | INDUCTOR APPARATUS FOR VEHICLE - An inductor apparatus for a vehicle includes an inductor boosting member configured to boost an input voltage. An inductor case has an insertion groove configured to receive the inductor boosting member inserted thereinto. An inductor cover is configured to close the inductor case. A coolant case is provided on a bottom surface of the inductor case. The coolant case has a coolant passage formed therein. A coolant cover is configured to close the coolant case. | 2016-05-05 |
20160125997 | APPARATUS FOR DISSIPATING HEAT OF INDUCTOR - Provided is an apparatus for effectively dissipating heat generated by an inductor of a DC-DC converter, and allowing for reducing a size and a weight of the DC-DC converter to thereby reduce manufacturing cost. The apparatus for dissipating heat of an inductor includes an inductor configured to protrude to outside; and a heat sink configured to be installed outside of the inductor and to receive the inductor. | 2016-05-05 |
20160125998 | FILTER ASSEMBLY AND METHOD - An electronic filter assembly includes a magnetically conductive annular body extending around a center axis, a set of magnetically conductive prongs radially extending from the center axis toward the annular body, and conductive windings extending around the prongs. The conductive windings can be disposed around the prongs instead of the annular body to assist in conduction of common mode magnetic flux, to reduce impedance of the filter assembly, and/or to more evenly distribute temperature in the filter assembly. A method for forming an electronic filter assembly includes forming an electronic filter assembly having a magnetically conductive annular body extending around a center axis and a set of magnetically conductive prongs radially extending from the center axis toward the annular body. The annular body and the prongs can be formed by coupling plural layers of magnetically conductive bodies together. | 2016-05-05 |
20160125999 | Apparatus for Reducing a Magnetic Unidirectional Flux Component in the Core of a Transformer - An apparatus for reducing a magnetic unidirectional flux component in the core of a transformer, i.e., a three-phase transformer, includes a plurality of compensation windings that are magnetically coupled to the core of the transformer, wherein a controllable current source for feeding current into the compensation windings is arranged electrically in series with the compensation windings, specifically with the neutral point thereof, which is forming by the inputs of the compensation windings, and a neutral earthing transformer is electrically connected to the outputs of the compensation windings, where the current source electrically interconnects the neutral point of the compensation windings and the neutral point of the neutral earthing transformer. | 2016-05-05 |
20160126000 | INDUCTOR DEVICE - An inductor device is provided. The inductor device includes a coil unit that includes a pair of first and second coils disposed adjacent to each other and coupled to each other, a core unit that surrounds inner and outer spaces of the coil unit, and an induction unit that is disposed in the coil unit and is induced by a magnetic field generated between the first and second coils. | 2016-05-05 |
20160126001 | WIRELESS CHARGING COIL PCB STRUCTURE WITH SLIT - A wireless charging coil PCB structure with slit includes at least one coil is disposed on a printed circuit board (PCB), wherein a slit defined on a portion of the conductive wire of the coil. The slit is located at the center of the coil wires and extending parallel to the conductive wire of the coil to increase the distance between the coil turns of the wire winding, and to overcome the proximity effect between the coil wires, and to reduce the coil impedance as well as enhance the heat dissipation effect. | 2016-05-05 |
20160126002 | Wireless Charging and Near Field Communication Dual Coils PCB Structure - A wireless charging (WLC) (A4WP) and near field communication (NFC) dual coils PCB structure comprising at least one WLC (A4WP) coil wire having spiral shape and disposed on a printed circuit board (PCB), and a NFC coil wire having spiral shape and disposed on the PCB. At least a portion of the coil wire of the spiral WLC (A4WP) coil is located on a region between two adjacent coil wires of the spiral NFC coil. Therefore, the present invention makes use of spaces of WLC (A4WP) coil such as A4WP or other relevant standards combined with the NFC coil, so that the dual coil of the present invention can reduce the area of the PCB occupied by the electronic device. | 2016-05-05 |