18th week of 2011 patent applcation highlights part 35 |
Patent application number | Title | Published |
20110103077 | LIGHT EMITTING DIODE PACKAGING METHOD WITH HIGH LIGHT EXTRACTION AND HEAT DISSIPATION USING A TRANSPARENT VERTICAL STAND STRUCTURE - A packaging method for light emitting diodes provides both high light extraction and heat dissipation using a transparent vertical stand structure. A light emitting diode (LED) is attached to a vertical stand structure for supporting the LED, wherein the LED is bonded to the vertical stand structure, so that one of the LED's sides faces vertically upwards, another of the LED's sides faces vertically downwards, a top surface of the LED faces horizontally sideways in one direction, and a bottom surface of the LED faces horizontally sideways in another direction. The vertical stand structure comprises a connecting stem between the LED and a header, and is made of a material that provides for heat dissipation and may also be transparent to light generated in the LED, such as sapphire or zinc oxide. The LED and the vertical stand structure may be encapsulated within a mold. | 2011-05-05 |
20110103078 | LED LAMP - An LED lamp includes a planar base, an LED module mounted on the base, an envelope covering the LED module, and a lamp housing having a configuration like a lantern and defining a cavity. An annular receiving groove is recessed from a bottom face of the base. The LED module is attached on the bottom face of the base and surrounded by the receiving groove. The envelope includes a recessed body and an engaging flange extending outwardly from a periphery of the body. The engaging flange of the envelope is received in the receiving groove. The base, the LED module and the envelope are received in the cavity. | 2011-05-05 |
20110103079 | ILLUMINATION DEVICE WITH HEAT DISSIPATION STRUCTURE - A solid state lighting source illumination device comprising a bracket and at least one solid state lighting source module. The solid state lighting source module comprises a substrate and at least one solid state lighting source. The substrate is set up with circuit and the solid state lighting source is set up on the substrate, and the electrode of the solid state lighting source is electrically connecting with the circuit on the substrate. The substrate and the bracket further comprise a heat dissipation structure which is a space between the substrate and a base of the bracket and through holes in the substrate near the solid state lighting source. | 2011-05-05 |
20110103080 | ILLUMINATION ELEMENT HAVING A PLASTIC SUPPORT - A lighting element including at least one light source, at least two connections, to supply electric current to the light source and a fixture to receive the light source. The light source includes a heat-generating section and the fixture contacts this heat-generating section, wherein the fixture consists of a thermally conductive plastic and is configured such that it dissipates the heat generated by the light source at least in part. | 2011-05-05 |
20110103081 | LIGHT SOURCE SUPPORT OF LIGHTING MODULE - A light source support on a first printed circuit for a lighting and/or signalling module, comprising a first housing intended to accommodate the first printed circuit and presenting an opening for the light source; means of positioning and fixation of the support; and means of positioning of a flexible printed circuit, intended to position the flexible printed circuit in relation to the first printed circuit, so as to link them electrically. | 2011-05-05 |
20110103082 | BASE FOR MOUNTING AN ELECTRICAL DEVICE SUCH AS A LIGHT-EMITTING DIODE - A base for the mounting of an electrical device includes a body ( | 2011-05-05 |
20110103083 | LAMP WITH SNOW REMOVING STRUCTURE - A lamp includes a bracket, a cover and a lamp body pivotably engaged with the shaft. The bracket includes a shaft with a flat top surface. The lamp body includes a first lateral portion and a second lateral portion. The lamp body defines a channel with a flat top surface. The cover is mounted over the second lateral portion. When the lamp body is at a first position, the top surface of the channel engages the top surface of the shaft. When the first lateral portion of the lamp body is subjected to weight of snow/ice accumulated thereon which is beyond a set value, the lamp body rotates around the shaft from the first position to a second position to enable the snow/ice to fall from the first lateral portion. | 2011-05-05 |
20110103084 | ILLUMINATION DEVICE FOR A MOTOR VEHICLE - An illumination device ( | 2011-05-05 |
20110103085 | VEHICLE LAMP - A lamp for a vehicle has a light source ( | 2011-05-05 |
20110103086 | OPTICAL MODULE FOR MOTOR VEHICLE HEADLAMP EQUIPPED WITH A DEVICE FOR ELECTRICAL CONNECTION TO REMOTE DEVICES - An optical module equipping a motor vehicle lighting and/or indicating device, provided with a assembly structure movably assembled on a bracket and means of electrical connection to at least one remote device, wherein the optical module is equipped with an electrical connection device comprising a flexible element integrating electrical conductors, the flexible element is connected between the assembly structure and the bracket such that the points of mechanical connection together produce a freedom of movement limited in space. | 2011-05-05 |
20110103087 | Independent Lighting Energy Interruption System With Energy Subdivisioning and Method - An auxiliary lighting energy interruption system for use with snow plows and like front-mounted vehicle accessories is disclosed which facilitates the interconnection of such systems to the lighting system of a vehicle upon which the vehicle accessory is mounted to provide power to and to control the auxiliary lights with the lighting system of the vehicle. The system provides first and second harness portions for respective installation on the vehicle and the vehicle accessory, with the first harness portion having a first configuration when it is not connected to the second harness portion and a second configuration when it is connected to the second harness portion. The first configuration allow the headlights on the vehicle to operate, while the second configuration allows only the headlights on the vehicle accessory to operate, with changes between the first and second configurations being accomplished without the need for a switch or a relay. | 2011-05-05 |
20110103088 | MULTI-MODE LIGHTING APPARATUS - A multi-mode lighting system includes a collector unit having a base including a cavity and a transparent or translucent cover mounted on the base. The system further includes a lighting module having a base, a transparent or translucent cover and a photovoltaic element mounted therein. A plurality of fiber optic filaments extend from the collector to the lighting module to transmit radiation from first ends of the fiber optic filaments to second ends of the fiber optic elements. The first ends of the fiber optic filaments are disposed in an array in the collector unit to receive radiation and second ends are disposed in an array in the lighting module to emit radiation received by the first ends of the fiber optic filaments. Radiation transmitted by the fiber optic filaments illuminates an area external to the lighting module and impinges the photovoltaic element to generate electricity. | 2011-05-05 |
20110103089 | LIGHT EMITTING APPARATUS AND DISPLAY APPARATUS HAVING THE SAME - A light emitting apparatus includes an array module including a first light emitting device which emits a light of a second color tinged with a first color, and a second light emitting device which emits a light of a fourth color tinged with a third color complementary to the first color of lights emitted from the first light emitting device. | 2011-05-05 |
20110103090 | LIGHT EMITTING MODULE - A light emitting module comprising a light-guide plate, a light source, and a light modulating film is provided. The light-guide plate has a light emitting surface and a light receiving surface. The light source is located at a side corresponding to the light receiving surface. The light modulating film is disposed on the light emitting surface. The light modulating film has a plurality of protruding bars located at a side away from the light emitting surface wherein each protruding bar has a vertex angle from 120° to 178°. | 2011-05-05 |
20110103091 | SPREAD ILLUMINATING APPARATUS - There is provided a spread illuminating apparatus including an LED, a light guide plate and a flexible printed circuit board on which the LED is mounted, wherein the light guide plate includes: a light entrance end surface at which the light source is disposed; a light emitting portion from which light emitted from the light source and introduced into the light guide plate exits out in a spread manner; a slope portion which is disposed between the light entrance end surface and the light emitting portion and which has a thickness decreasing toward the light emitting portion; and a seat block disposed at the slope portion and configured to fixedly receive the flexible printed circuit board. In the spread illuminating apparatus, the length of the slope portion is substantially 1.78 times as large as the largest thickness of the slope portion. | 2011-05-05 |
20110103092 | LIGHT GUIDING PANEL ASSEMBLY FOR DISPLAY, SIGNBOARD, SURFACE ILLUMINATION OR THE LIKE - A light source receiver | 2011-05-05 |
20110103093 | LIGHT SOURCE MODULE - A light source module includes a light bar and a stiffened bar. The light bar includes a flexible circuit strip and a plurality of light sources. The light sources are disposed on the flexible circuit strip along an extension direction of the flexible circuit strip. The stiffened bar overlaps the flexible circuit strip and is disposed on a face of the flexible circuit strip having the light sources. The stiffened bar surrounds at least one side of each light source and exposes the light sources. The rigidity of the stiffened bar is larger than the flexible circuit strip. | 2011-05-05 |
20110103094 | LIGHT SOURCE DEVICE AND DISPLAY UNIT EQUIPPED WITH LIGHT SOURCE DEVICE - Disclosed is a light source device which is made compact while suppressing increase in non-uniformity of brightness caused by existence of a non-light emitting portion between a plurality of light sources. A light source device is characterized in that a plurality of light diffusers have a first light diffuser located in front of a first light source in the light exit direction closely thereto, and a second light diffuser located in front of a second light source in the light exit direction closely thereto. The first light diffuser includes a first light absorbing material which absorbs visible light emitted from the first light source more easily than visible light emitted from the second light source, and the second light diffuser includes a second light absorbing material which absorbs visible light emitted from the second light source more easily than visible light emitted from the first light source. | 2011-05-05 |
20110103095 | LIGHT GUIDE PLATE AND METHOD FOR MANUFACTURING LIGHT GUIDE PLATE - A light guide plate that uses a resin film as a material for the light guide plate, that has a reflecting or scattering pattern formed by printing, and that guides a light propagating in the film to exit and emerge from the front surface thereof. The light guide plate is thinner and highly flexible, and has high reliability and durability. A base material of the light guide plate is formed from a thermosetting polyurethane sheet with a thickness of 0.4 mm or less. When a dot pattern is formed by ink-jetting, a white UV curable ink, for which the thermosetting polyurethane exhibits a swellability such that the thermosetting polyurethane increases by 10% or more in weight as a result of being soaked in the ink for one hour at a room temperature, is used as the ink. | 2011-05-05 |
20110103096 | THIRTY-SIX PULSE POWER TRANSFORMER AND POWER CONVERTER INCORPORATING SAME - Embodiments of the present invention provide novel techniques for using multiple 18-pulse rectifier circuits in parallel. In particular, each rectifier circuit may include an autotransformer having 15 inductors coupled in series, joined by 15 nodes interposed between pairs of the inductors. The inductors may be represented as a hexagon in which alternating sides of the hexagon have two and three inductors, respectively. Each rectifier circuit may also include three inputs for three-phase AC power coupled to alternating vertices of the hexagonal representation and nine outputs for AC power coupled between each node that is not a vertex of the hexagonal representation and a respective diode bridge. Outputs of the diode bridges for the rectifier circuits may be coupled to a DC bus. In addition, a means for reducing circulating current between the parallel rectifier circuits and for promoting load sharing between the parallel rectifier circuits is also provided. | 2011-05-05 |
20110103097 | METHOD AND APPARATUS FOR REGULATING GAIN WITHIN A RESONANT CONVERTER - An approach is provided for controlling a direct current gain of a resonant converter to increase power efficiency within a circuit. A phase shift module is configured to the resonant converter for generating a first control signal to control a primary driver of the resonant converter and a secondary control signal to control a secondary driver of the resonant converter. The first control signal and the second control signal has a phase shift for controlling a DC gain of the resonant converter. | 2011-05-05 |
20110103098 | METHOD AND APPARATUS FOR RESETTING A RESONANT CONVERTER - An approach is provided for limiting or eliminating residual energy in a resonant network before restarting a resonant converter including the resonant network. An energy resetting module is configured to the resonant converter for limiting a peak current occurring in a switching circuit of the resonant converter by resetting energy remaining in a resonant circuit of the resonant converter after the resonant converter is turned off. | 2011-05-05 |
20110103099 | SWITCHING CONTROL METHOD OF TRANSFORMER COUPLED BOOSTER - Provided is a switching control method of a transformer coupled booster to suppress an increase in energizing current in a transformer of the transformer coupled booster and downsize the transformer coupled booster. A primary coil current that flows through a primary coil of the transformer, and a secondary coil current that flows through a secondary coil of the transformer are detected. The current difference between the detected primary coil current and the detected secondary coil current is calculated. Based on the calculated current difference, the cycle of ON/OFF periods of four arms provided on the transformer coupled booster is maintained at a constant level. Control is carried out so that the ratio of the first arm's ON period to the OFF period is always equal to the ratio of the third arm's ON period to the OFF period. | 2011-05-05 |
20110103100 | ISOLATED SWITCHING POWER SUPPLY APPARATUS - In an isolated switching power supply apparatus, by performing on/off control of a first switching device and a second switching device, energy is transmitted from the primary side to the secondary side using a second primary winding and a second secondary winding while the first switching device is on, and energy is transmitted by a first primary winding and a first secondary winding while the second switching device is on. The first secondary winding and the second secondary winding are connected in series with one another, and an inductor is inserted in series to the second secondary winding. An output current is made to flow through the inductor irrespective of whether the first switching device is on or the second switching device is on. | 2011-05-05 |
20110103101 | INTEGRATED CONTROL CIRCUIT FOR CONTROLLING A SWITCHING POWER SUPPLY, SWITCHING POWER SUPPLY INCORPORATING THE SAME, AND A METHOD OF CONTROLLING A SWITCHING POWER SUPPLY - An integrated control circuit for controlling a switching power supply, a switching power supply incorporating the same, and a method of controlling the switching power supply, where the control IC includes a current comparator that detects current flowing through a switching device, a flip-flop circuit that controls the ON-period of the switching device, an averaging circuit that converts the peak load current value to a time-average, a comparator that detects an overloaded state from the load current, a delay circuit that sets a time from detecting the overcurrent state to stopping the switching operation, a latch circuit that stops the switching operation for a period of time, a first reference voltage supply used in the current comparator, which has a higher voltage value than a second reference voltage supply used in the comparator. | 2011-05-05 |
20110103102 | VOLTAGE CONVERTER WITH HIGH EFFICIENCY - A voltage converter transmits energy in multiple stages using a charge pump so as to decrease the voltage rating of the secondary side of the transformer and reduce the size of the transformer. Meanwhile, the voltage converter stores and recycles the leakage inductance energy by using a snubber circuit so as to increase the efficiency. | 2011-05-05 |
20110103103 | POWER SUPPLY WITH LOW POWER CONSUMPTION HICCUP STANDBY OPERATION - A power supply including a converter, a capacitance, and a hiccup control module. The converter converts an input voltage to both an output voltage and a preliminary standby voltage when in its active state. The capacitance stores the preliminary standby voltage which is charged to an upper voltage level when the converter is in its active state and which is discharged to a lower voltage level when the converter is in its inactive state. During the standby mode, the hiccup control module operates the converter in hiccup mode by toggling between placing the converter into its inactive state when the preliminary standby voltage is charged to the upper voltage level and placing the converter into its active state when the preliminary standby voltage is discharged to the lower voltage level. The hiccup mode of the power supply eliminates a need for a separate standby converter. | 2011-05-05 |
20110103104 | BIAS AND DISCHARGE SYSTEM FOR LOW POWER LOSS START UP AND INPUT CAPACITANCE DISCHARGE - A power supply including an AC input, a filter, a full wave rectifier, a converter, a second rectifier, and a bias system. The filter includes at least one differential capacitor coupled to the AC input. The full wave rectifier develops a DC bus voltage on a DC bus node. The converter includes a controller and operates to convert the DC bus voltage to a regulated output voltage. The second rectifier is coupled to the AC input for developing a DC bias voltage on a DC bias node. The bias system is coupled between the DC bias node and a reference node and provides at least one start-up voltage to the controller, such as a supply voltage or a sense voltage or the like. The bias circuit includes at least one current discharge path for discharging each differential capacitor within a predetermined time period when AC line voltage is removed. | 2011-05-05 |
20110103105 | POWER TRANSFORMER AND POWER CONVERTER INCORPORATING SAME - Embodiments of the present invention provide novel techniques for using multiple 18-pulse rectifier circuits in parallel. In particular, each rectifier circuit may include an autotransformer having 15 inductors coupled in series, joined by 15 nodes interposed between pairs of the inductors. The inductors may be represented as a hexagon in which alternating sides of the hexagon have two and three inductors, respectively. Each rectifier circuit may also include three inputs for three-phase AC power coupled to alternating vertices of the hexagonal representation and nine outputs for AC power coupled between each node that is not a vertex of the hexagonal representation and a respective diode bridge. Outputs of the diode bridges for the rectifier circuits may be coupled to a DC bus. In addition, a means for reducing circulating current between the parallel rectifier circuits and for promoting load sharing between the parallel rectifier circuits is also provided. | 2011-05-05 |
20110103106 | POWER CONVERSION DEVICE - In a power conversion device, reactors in an AC input filter absorbing a voltage at a carrier frequency of a PWM converter and reactors in an AC output filter absorbing a voltage at a carrier frequency of a PWM inverter include one six-leg six-phase iron core reactor. Accordingly, the device can be reduced in size when compared with a case where the reactors are composed of two four-leg six-phase iron core reactors. | 2011-05-05 |
20110103107 | RESONANCE CIRCUIT FOR DC-LINK VOLTAGE CONTROL IN DC-TO-AC INVERTER - The present disclosure relates to a resonance circuit for DC-link voltage control in a DC-to-AC inverter. The resonance circuit comprises two active switches. Before the active switches of the DC-to-AC inverter are turned on, a DC-link voltage is isolated by the active switches and the active switches of the DC-to-AC inverter are discharged by the resonance circuit to zero voltage at both ends. Then, the active switches of the DC-to-AC inverter are turned on again after the DC-link voltage is charged by the resonance circuit until the DC-link voltage restores to a normal voltage value. Hence, the active switches of the DC-to-AC inverter achieve zero-voltage switching. Not only the switching loss can be reduced to enhance the conversion efficiency, but also the electro-magnetic interference as well as the RF interference due to dynamic transient changes of the voltage (dv/dt) and of the current (di/dt) can be lowered. | 2011-05-05 |
20110103108 | Converter Valve - A converter valve unit including a plurality of parallel connected semiconducting elements, a free-wheeling diode and a control unit. | 2011-05-05 |
20110103109 | AC POWER SOURCE APPARATUS - An AC power source apparatus includes a first AC voltage generator having a first switch set, to output a first AC voltage having a positive-negative asymmetrical waveform by turning on/off the first switch set to a first end of a load; a second AC voltage generator having a second switch set, to output a second AC voltage having a positive-negative asymmetrical waveform and a phase difference of 180 degrees with respect to the first AC voltage by turning on/off the second switch set to a second end of the load; and a control circuit to turn on/off the first switch set, and by setting a phase difference of 180 degrees with respect to the turning on/off of the first switch set, turn on/off the second switch set. A voltage across the load is an AC voltage having a positive-negative symmetrical waveform. | 2011-05-05 |
20110103110 | Method of operating an inverter and inverter control arrangement - A method of operating an inverter for converting a DC power into AC power by use of a pulse width modulation switching scheme is provided is disclosed. The inverter is controlled by use of the pulse width modulation switching scheme to provide an alternating current based on a current demand signal defining an alternating current provided by the inverter. An upper current threshold and a lower current threshold are provided. An instantaneous value of the alternating current is measured. When the instantaneous value of the alternating current overshoots the upper current threshold or undershoots the lower current threshold, the pulse width modulation switching scheme is replaced by an amended switching scheme which controls the instantaneous value of the alternating current to be between the upper current threshold and the lower current threshold. The upper current threshold and the lower current threshold oscillate with at least one alternating phase. | 2011-05-05 |
20110103111 | Switching Power Converter With Efficient Switching Control Signal Period Generation - A power control system includes a switching power converter and a controller, and the controller responds to a time-varying voltage source signal by generating a switch control signal having a period that varies in accordance with at least one of the following: (i) the period of the switch control signal trends inversely to estimated power delivered to a load coupled to the switching power converter, (ii) the period of the switch control signal trends inversely to instantaneous voltage levels of the voltage source signal, and (iii) the period of the switch control signal trends directly with a line voltage level of the time-varying voltage source signal. In at least one embodiment, the controller achieves an efficient correlation between the switching period with associated switching losses and the instantaneous power transferred to the switching power converter while providing power factor correction (PFC). | 2011-05-05 |
20110103112 | CURRENT SENSING SIGNAL COMPARING DEVICE, AND CURRENT SENSING SIGNAL COMPARING METHOD - Provided is a current sensing signal comparing device and current sensing signal comparing method. The invention includes a current sensing circuit for detecting a current signal of a switching circuit and thereby generating a current sensing signal, a control unit for outputting a control signal, and a compensating circuit for compensating the current sensing signal according to the control signal. The compensated current sensing signal is compared with a constant current reference signal in order to issue a constant current control signal. The other aspect of the invention is provided to configure the compensating circuit to compensate the constant current reference signal, such that the current sensing signal is compared with the compensated constant current reference signal in order to issue a constant current control signal. | 2011-05-05 |
20110103113 | COMPOSITE AC TO DC POWER CONVERTER - A 24-pulse composite AC-to-DC converter is a converter using two or more conversion methods in parallel. The converter may include a main rectifier receiving at least a portion of an input AC signal, an autotransformer having an output voltage with lower amplitude than the input AC signal, and a plurality of auxiliary bridge rectifiers, each receiving the output from each leg of the autotransformer. In one embodiment of the invention, the main rectifier may receive a substantial portion of the load current, allowing each of the auxiliary bridge rectifiers to be generally smaller than the main rectifier. | 2011-05-05 |
20110103114 | SOLAR POWER CONVERSION CIRCUIT AND POWER SUPPLY SYSTEM USING THE SAME - A solar power supply system includes at least one solar power conversion circuit and an inverter circuit. Each solar power conversion circuit comprises a solar module and a direct current (DC) module. The solar module converts the solar power into the DC signals. The DC module with two-stage conversion comprises a DC transformer circuit and a maximum power point tracking circuit, to boost the DC signals and adjust output power of the solar module to a maximum value. The inverter circuit converts the boosted DC signals output from the solar power conversion circuits into AC signals and combines the AC signals into the AC utility network. | 2011-05-05 |
20110103115 | VOLTAGE SOURCE CONVERTER - A Voltage Source Converter having at least one phase leg connected to opposite poles of a direct voltage side of the converter and comprising a series connection of switching cells has inductance means comprising a plurality of inductors ( | 2011-05-05 |
20110103116 | PLANT FOR TRANSMITTING ELECTRIC POWER - A plant for transmitting electric power comprising a direct voltage network ( | 2011-05-05 |
20110103117 | GRID INTERCONNECTION INVERTER AND GRID INTERCONNECTION DEVICE - A grid interconnection inverter includes: a voltage conversion circuit configured to output an intermediate voltage by raising or lowering an input voltage from a direct current power source; and a waveform conversion circuit configured to convert the intermediate voltage into a alternating current power in a sine waveform shape. The voltage conversion circuit includes: a positive-side circuit arranged on a positive-side line between a positive polarity of the direct current power source and the waveform conversion circuit; and a negative-side circuit arranged on a negative-side line between a negative polarity of the direct current power source and the waveform conversion circuit. The positive-side circuit and the negative-side circuit have circuit configurations symmetric to each other. | 2011-05-05 |
20110103118 | NON-ISOLATED DC-DC CONVERTER ASSEMBLY - A non-isolated DC-DC converter assembly includes a boost converter and a Ćuk converter connected together in a specific way. The non-isolated DC-DC converter assembly allows for grounding of a source and load at the same time, and provides a complete adjustability of the output voltage of the non-isolated DC-DC converter. Further, the DC-DC converter assembly of the disclosure has a current source input characteristic, whereby the current absorbed from the power supply is continuous | 2011-05-05 |
20110103119 | APPARATUS FOR AND METHOD OF COOLING ELECTRONIC CIRCUITS - An electronic device such as an AC/DC power adapter includes a conductive heat dissipation system. The device contains heat generating components and is powered via power supply leads by an external power supply circuit. The device further contains a thermally conductive mass that is thermally coupled to both the heat generating components and to the power supply leads. When the power supply leads are coupled to receive electricity from the external power supply circuit, heat generated by the device is thermally conducted into the external power supply circuit via the power supply leads. | 2011-05-05 |
20110103120 | BINRAY CONTENT ADDRESSABLE MEMORY - The present invention relates to a binary content addressable memory (CAM), and more particularly, to a binary content addressable memory (CAM) in which the number of transistors constituting the content addressable memory can be reduced to decrease the size of the content addressable memory, thereby increasing the degree of integration and improving power consumption. According to the present invention, since the binary content addressable memory according to the present invention has a smaller number of transistors than those of the conventional binary content addressable memory, a memory can be fabricated in a smaller size, thereby improving the degree of integration as one of most important factors in the memory design. In addition, improvement of the degree of integration contributes to miniaturization and lightweightness of the product in its design. Further, the inventive binary content addressable memory performs its own function using a smaller number of transistors, thereby reducing power consumption. | 2011-05-05 |
20110103121 | STACKED SEMICONDUCTOR DEVICE AND AUTOMATIC CHIP RECOGNITION SELECTION CIRCUIT - A semiconductor device includes a plurality of stacked chips which are allocated with different self-chip addresses. Each of the plurality of stacked chips includes a frequency change circuit, a self-address storing circuit and a determination circuit. The frequency change circuit changes a first frequency of a signal into a second frequency of the signal. The self-address storing circuit stores a chip select address that is supplied to other chips, in a period of time when the signal as input to the frequency change circuit is different in logic level from the signals as input to the frequency change circuits in the other chips. The determination circuit determines whether the chip select address is identical to the self-chip address. | 2011-05-05 |
20110103122 | SYSTEM AND METHOD FOR OPTIMIZING INTERCONNECTIONS OF COMPONENTS IN A MULTICHIP MEMORY MODULE - An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub. | 2011-05-05 |
20110103123 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including: a first switch controlling connection between a first data line pair a second data line pair; a first amplifier connected to the first data line pair; a second switch controlling the connection between the second data line pair and a third data line pair; a second amplifier amplifying data on the second data line pair and delivering the amplified data to the third data line pair; a third amplifier connected to the third data line pair; and a switch control circuit controlling the second switch. Based upon a first control signal that controls precharging and equalization of the first data line pair, the switch control circuit renders the second switch conductive when precharging and equalization of the first data line pair is not carried out, and renders the second switch non-conductive when precharging and equalization of the first data line pair is carried out. | 2011-05-05 |
20110103124 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has: memory blocks; and a local bus connected to the memory blocks. Each memory block has: switches respectively provided between bit line pairs and the local bus and each of which is turned ON in response to a selection signal; a dummy local bus; first and second control circuits. The local bus and the dummy local bus are precharged to a first potential before a read operation. In the read operation, the first control circuit outputs the selection signal to a selected switch to electrically connect a selected bit line pair and the local bus, while the second control circuit supplies a second potential lower than the first potential to the dummy local bus. The first control circuit stops outputting the selection signal when a potential of the dummy local bus is decreased to a predetermined set potential that is between the first and second potentials. | 2011-05-05 |
20110103125 | MEMORY CELLS HAVING A FOLDED DIGIT LINE ARCHITECTURE - Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row. | 2011-05-05 |
20110103126 | SEMICONDUCTOR MEMORY DEVICE - A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period. | 2011-05-05 |
20110103127 | AND-TYPE ONE TIME PROGRAMMABLE MEMORY CELL - An AND-type anti-fuse memory cell, and a memory array consisting of AND-type anti-fuse memory cells. Chains of AND type anti-fuse cells are connected in series with each other, and with a bitline contact, in order to minimize the area occupied by the memory array. Each AND type anti-fuse cell includes an access transistor serially connectable to the bitline or the access transistors of other AND type anti-fuse cells, and an anti-fuse device. The channel region of the access transistor is connected to the channel region of the anti-fuse device, and both channel regions are covered by the same wordline. The wordline is driven to a programming voltage level for programming the anti-fuse device, or to a read voltage level for reading the anti-fuse device. | 2011-05-05 |
20110103128 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated. | 2011-05-05 |
20110103129 | VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME - A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells can be arranged in parallel with a corresponding series of control gates. A select gate can also be disposed in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell can include turning off the corresponding control gate, while turning on all other control gates. Various devices can include such a variable-resistance material memory array. | 2011-05-05 |
20110103130 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state. | 2011-05-05 |
20110103131 | NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE - Provided is a nonvolatile memory element which has a small variation in operation and allow stable operation. The nonvolatile memory element includes: a first electrode ( | 2011-05-05 |
20110103132 | NONVOLATILE MEMORY ELEMENT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE MEMORY ELEMENT - Provided are a nonvolatile memory element which is capable of effectively preventing an event that when a failure occurs in a certain nonvolatile memory element, data cannot be written to and read from another nonvolatile memory element belonging to the same column or row as that to which the nonvolatile memory element in a failed state belongs, and a semiconductor memory device including the nonvolatile memory element. | 2011-05-05 |
20110103133 | MEMORY CELL ARRAY, NONVOLATILE STORAGE DEVICE, MEMORY CELL, AND METHOD OF MANUFACTURING MEMORY CELL ARRAY - A method of manufacturing a memory cell array in which first conductive layers ( | 2011-05-05 |
20110103134 | RESISTANCE RANDOM ACCESS MEMORY HAVING COMMON SOURCE LINE - A method writes data to a resistance random access memory (RRAM) memory cell through first and second write paths, and includes; applying a positive source voltage to a selected source line, applying a word line drive voltage to a selected word line, and applying a voltage at least twice the level of the positive source voltage to a selected bit line via the first write path when writing data having the first state in the memory cell, and applying a ground voltage to the selected bit line via the second write path when writing data having the second state in the memory cell. | 2011-05-05 |
20110103135 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged. | 2011-05-05 |
20110103136 | SEMICONDUCTOR MEMORY DEVICE - A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation. | 2011-05-05 |
20110103137 | SOURCE CONTROLLED SRAM - Disclosed is a cmos sram cell including two cross-coupled inverters, each having a pmos and an nmos transistor, a first signal line connected to the sources of each of the nmos transistors, a second signal line, parallel to the first signal line, and connected to the source of one of said pmos transistors, and a third signal line connected to the source of the other of said pmos transistors. The third signal line may be orthogonal to the first and second signal lines. Also disclosed is a cmos sram cell including two cross-coupled inverters, a pair of bitlines for writing data to the cell, and at least one further bitline for reading data from the cell. | 2011-05-05 |
20110103138 | SINGLE-CHARGE TUNNELING DEVICE - A single-electron transistor ( | 2011-05-05 |
20110103139 | Double-pulse write for phase change memory - The present invention discloses a method including: writing a phase change material from a high RESET state to a weakened RESET state with a first step; writing the phase change material from the weakened RESET state to a SET state with a second step, the second step having a lower current than the first step; verifying a parameter of the phase change material wherein if the parameter is higher than a target for a SET state, then repeating the writing with the first step, the writing with the second step, and the verifying until the parameter is lower than the target wherein a current for the first step is decreased by a decrement with each iteration without becoming lower than a current for the second step. | 2011-05-05 |
20110103140 | DATA READ CIRCUIT FOR PHASE CHANGE MEMORY DEVICE AND APPARATUSES INCLUDING THE SAME - The data read circuit includes a variable current generation circuit and a data sensing circuit. The variable current generation circuit is configured to generate a variable current that varies in response to an external temperature. The data sensing circuit is configured to sense and amplify data on a bit line connected to a non-volatile memory cell according to the variable current and to configured to output the sensed and amplified data. The data sensing circuit controls a margin for sensing the data according to the variable current. | 2011-05-05 |
20110103141 | Reading a Phase Change Memory - A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals. | 2011-05-05 |
20110103142 | SEMICONDUCTOR DEVICE - In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus. | 2011-05-05 |
20110103143 | LOW CURRENT SWITCHING MAGNETIC TUNNEL JUNCTION DESIGN FOR MAGNETIC MEMORY USING DOMAIN WALL MOTION - A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall. | 2011-05-05 |
20110103144 | STRUCTURES AND METHODS OF TRIMMING THRESHOLD VOLTAGE OF A FLASH EEPROM MEMORY - A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density. | 2011-05-05 |
20110103145 | M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory. | 2011-05-05 |
20110103146 | MEMORY DEVICE OF THE ELECTRICALLY ERASABLE AND PROGRAMMABLE TYPE, HAVING TWO CELLS PER BIT - The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line select transistors. The common terminal between the bit line select transistor and the floating-gate transistor of each memory cell of the memory cell unit is connected to the control gate of the floating-gate transistor of the other memory cell of the memory cell unit. | 2011-05-05 |
20110103147 | NAND FLASH MEMORY DEVICES HAVING WIRING WITH INTEGRALLY-FORMED CONTACT PADS AND DUMMY LINES AND METHODS OF MANUFACTURING THE SAME - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 2011-05-05 |
20110103148 | Normally off gallium nitride field effect transistors (FET) - A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device. | 2011-05-05 |
20110103149 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar. The control circuit writs a first value to at least some of the memory cells, performs an erasing operation of the first value from the memory cell written with the first value, reads data stored in the memory cell having undergone the erasing operation, and sets the memory cell to be unusable in a case that the first value is read from the memory cell. | 2011-05-05 |
20110103150 | NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING - A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells. | 2011-05-05 |
20110103151 | Methods of Programming Semiconductor Memory Devices - To program a semiconductor memory device, a plurality of target threshold voltage groups are set by dividing target threshold voltages representing states of memory cells. The target threshold voltage groups are substantially simultaneously programmed by applying a plurality of program voltages to a word line. Program end times for the target threshold voltage groups are adjusted. | 2011-05-05 |
20110103152 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes. | 2011-05-05 |
20110103153 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases. | 2011-05-05 |
20110103154 | LOCAL SELF-BOOSTING METHOD OF FLASH MEMORY DEVICE AND PROGRAM METHOD USING THE SAME - Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell. | 2011-05-05 |
20110103155 | OPERATION METHOD OF MEMORY DEVICE - One embodiment of the present invention provides an operation method of a memory device. The memory device includes a source, a drain, and a channel region between the source and the drain, a gate dielectric with a charge storage layer on the channel region, and a gate on the gate dielectric, wherein the source, the drain and the channel region are located in a substrate. The operation method includes the following steps: applying a reverse bias between the gate and the drain of the memory device to generate band-to-band hot holes in the substrate near the drain; injecting the band-to-band hot holes to a drain side of the charge storage layer; and performing a program/erase operation upon the memory device. The band-to-band hot holes in the drain side of the charge storage layer are not completely vanished by the program/erase operation. | 2011-05-05 |
20110103156 | DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A data input/output circuit includes a rank selecting section and a data input/output section. The rank selecting section is selectively connected to one of the first and second ranks in response to a chip selection signal, and outputs data to a connected rank or receives data from the connected rank. The data input/output section outputs the data transmitted from the rank selecting section through a data pad to an external device during a read operation, and outputs the data inputted to the data pad to the rank selecting section during a write operation. | 2011-05-05 |
20110103157 | TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY - In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals. | 2011-05-05 |
20110103158 | LOW VOLTAGE SENSING SCHEME HAVING REDUCED ACTIVE POWER DOWN STANDBY CURRENT - A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 2011-05-05 |
20110103159 | Degradation Equalization for a Memory - In an embodiment, an integrated circuit includes a memory and a control circuit configured to cause an inversion of at least a portion of the data stored in the memory to more evenly balance the amount of time that a given memory cell in the memory stores a binary one or a binary zero. In some implementations, the inversion may be controlled for the memory as a whole via a global indication. In other implementations, data may be inverted on a row-by-row or column-by-column basis. In other embodiments, the global indication may be changed at each boot of a device including the integrated circuit. | 2011-05-05 |
20110103160 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus comprises: first and second memory banks located a predetermined distance from each other in a first direction; a common column selection control unit located at an outside region in the first and second memory banks in the first direction, and configured to commonly control access to column areas in the first and second memory banks and generate a column selection signal that controls data access to the corresponding memory cells in the first and second memory banks; a first data read/write unit configured to sense and amplify read data transferred from the first memory bank and transfer write data to the first memory bank; and a second data read/write unit configured to sense and amplify read data transferred from the second memory bank and transfer write data to the second memory bank. The first data read/write unit and the second data read/write unit are located so as to be spaced from each other in the first direction with the memory bank interposed therebetween. | 2011-05-05 |
20110103161 | METHOD OF REDUCING THE OCCURRENCE OF BURN-IN DUE TO NEGATIVE BIAS TEMPERATURE INSTABILITY - A method for alleviating burn-in effect and enabling performing a start-up process in respect of a device comprising a plurality of challengeable memory elements, wherein the memory elements are able to, upon start-up, generate a response pattern of start-up values useful for identification as the response pattern depends on physical characteristics of the memory elements, the method comprising the step of, after start-up of the memory elements, writing a data pattern to the memory elements which is inverse to a response pattern that was previously read from the same memory elements. Thus, degradation of the PMOS transistors due to NBTI can be alleviated. | 2011-05-05 |
20110103162 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: a plurality of memory banks disposed at a predetermined distance from each other in a first direction; a common column selection control unit disposed at an outside region of the plurality of memory banks in the first direction, and configured to commonly control access to column areas of the plurality of memory banks; and a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to the corresponding memory cells of the plurality of memory banks. The common column selection control unit generates the column selection signal, and a delay length of the column selection signal is adjusted based on a length of a transmission path of the column selection signal. | 2011-05-05 |
20110103163 | MULTI-BIT TEST CONTROL CIRCUIT - A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test. | 2011-05-05 |
20110103164 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR PERFORMING DATA COMPRESSION TEST OF THE SAME - A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of at least two of the plurality of parallel-to-serial conversion sections, and a plurality of data output circuits configured to output respective compression results of the plurality of data compression circuits to an outside of a chip. | 2011-05-05 |
20110103165 | SELF-REFRESH TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A self-refresh test circuit includes a test clock generation unit, a pulse generation unit, a period signal selection unit, and a self-refresh pulse control unit. The test clock generation unit divides a clock signal to generate a plurality of divided clock signals having different periods when a test enable signal is enabled, and outputs one of the plurality of divided clock signals as a selected clock signal. The pulse generation unit generates a test period signal in response to the selected clock signal. The period signal selection unit outputs one of the test period signal and a self-refresh period signal as a selected period signal. The self-refresh pulse control unit generates a self-refresh pulse in response to a self-refresh exit signal and the selected period signal. | 2011-05-05 |
20110103166 | LAYOUT STRUCTURE OF BIT LINE SENSE AMPLIFIERS FOR A SEMICONDUCTOR MEMORY DEVICE - A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier. | 2011-05-05 |
20110103167 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A local sense amplifier of a semiconductor memory apparatus includes a read amplification unit configured to amplify data of first data lines and transfer the amplified data to second data lines during a read operation; and a write amplification unit configured to amplify data of the second data lines and transfer the amplified data to the first data lines during a write operation. | 2011-05-05 |
20110103168 | BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE HAVING OPEN BIT LINE STRUCTURE - In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized. | 2011-05-05 |
20110103169 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS - A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal. In response to the oscillation signal, a self-request controller provides a self-refresh request signal in the self-refresh mode. The self-refresh signal is asynchoronized with the self-fresh mode signal and is provided to an address circuit to select a wordline for refreshing the memory cells thereof. The self-refresh request controller includes logic circuitry for arbitrating timing between initial active edges of the oscillation signal and the self-refresh mode signal and providing the self-refresh request and ceasing it, regardless of conflict between the self-refresh mode signal and the oscillation signal upon self-refresh mode entry and exit. The DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time. | 2011-05-05 |
20110103170 | NOVEL FUSE PROGRAMMING SCHEMES FOR ROBUST YIELD - An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession. | 2011-05-05 |
20110103171 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: first and second memory banks located at a predetermined distance from each other; a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to corresponding memory cells in the first and second memory banks; and a column selection signal repeater inserted in the common column selection signal transmission line, and configured to transfer the column selection signal for controlling data access to the memory cell in the first memory bank. A transmission path of the column selection signal for controlling data access to the memory cell in the first memory bank is longer than that of the column selection signal for controlling data access to the memory cell in the second memory bank. | 2011-05-05 |
20110103172 | HIGH PERFORMANCE GREEN CONCRETE MIXER AND HIGH PERFORMANCE MIXING METHOD FOR GREEN CONCRETE - A high performance green concrete mixer and a high performance mixing method of green concrete are provided. The high performance green concrete mixer includes a pan mixer, plural drum mixers and a funnel. Each of the drum mixers is inclined relative to the pan mixer, while the funnel is connected between the pan mixer and the drum mixers. | 2011-05-05 |
20110103173 | Position sensor - A position sensor device determines a position of a reciprocating object and includes, (a) at least one magnetically encoded region fixed on a reciprocating object, (b) at least one magnetic field detector, and (c) a position determining unit. The magnetic field detector is adapted to detect a signal generated by the magnetically encoded region when the magnetically encoded region reciprocating with the reciprocating object passes a surrounding area of the magnetically encoded region. The position determining unit is adapted to determine a position of a reciprocating object based on the detected magnetic signal. | 2011-05-05 |
20110103174 | MICROFLUIDIC DEVICE COMPRISING GAS PROVIDING UNIT, AND METHODS OF MIXING LIQUIDS AND FORMING EMULSION USING THE SAME - A microfluidic device including a reaction chamber, a first gas providing unit and a liquid providing unit. The reaction chamber includes an inlet through which gas or liquid flows into the reaction chamber. The first gas providing unit and a liquid providing unit are connected to the inlet of the reaction chamber in a fluid communicable manner. | 2011-05-05 |
20110103175 | MAGNETIC STIRRER WITH MOUNTING FEET - A magnetic stirrer ( | 2011-05-05 |
20110103176 | ACCURATE AND RAPID MICROMIXER FOR INTEGRATED MICROFLUIDIC DEVICES - The invention may provide a microfluidic mixer having a droplet generator and a droplet mixer in selective fluid connection with the droplet generator. The droplet generator comprises first and second fluid chambers that are structured to be filled with respective first and second fluids that can each be held in isolation for a selectable period of time. The first and second fluid chambers are further structured to be reconfigured into a single combined chamber to allow the first and second fluids in the first and second fluid chambers to come into fluid contact with each other in the combined chamber for a selectable period of time prior to being brought into the droplet mixer. | 2011-05-05 |