| 18th week of 2011 patent applcation highlights part 18 |
| Patent application number | Title | Published |
|---|
| 20110101376 | Optically-Initiated Silicon Carbide High Voltage Switch - An improved photoconductive switch having a SIC or other wide band gap substrate material, such as GaAs and field-grading liners composed of preferably SiN formed on the substrate adjacent the electrode perimeters or adjacent the substrate perimeters for grading the electric fields. | 2011-05-05 |
| 20110101377 | HIGH TEMPERATURE ION IMPLANTATION OF NITRIDE BASED HEMTS - A method is disclosed for forming a high electron mobility transistor. The method includes the steps of implanting a Group III nitride layer at a defined position with ions that when implanted produce an improved ohmic contact between the layer and contact metals, with the implantation being carried out at a temperature higher than room temperature and hot enough to reduce the amount of damage done to the Group III nitride layer, but below a temperature at which surface problems causing leakage at the gate or epitaxial layer dissociation would occur. An ohmic contact selected from the group consisting of titanium, aluminum, nickel and alloys thereof is added to the implanted defined position on the Group III nitride layer. | 2011-05-05 |
| 20110101378 | SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE - A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET. | 2011-05-05 |
| 20110101379 | Method for Manufacturing Light-Emitting Element, Light-Emitting Element, Light-Emitting Device, Lighting Device, and Electronic Appliance - One object is to provide a light-emitting element which overcomes the problems of electrical characteristics and a light reflectivity have been solved. The light-emitting element is manufactured by forming a first electrode including aluminum and nickel over a substrate; by forming a layer including a composite material in which a metal oxide is contained in an organic compound so as to be in contact with the first electrode after heat treatment is performed with respect to the first electrode; by forming a light-emitting layer over the layer including a composite material; and by forming a second electrode which has a light-transmitting property over the light-emitting layer. Further, the first electrode is preferably formed to include the nickel equal to or greater than 0.1 atomic % and equal to or less than 4.0 atomic %. | 2011-05-05 |
| 20110101380 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE USING THE SAME - An object of the present invention is to provide a light emitting element having slight increase in driving voltage with accumulation of light emitting time. Another object of the invention is to provide a light emitting element having slight increase in resistance value with increase in film thickness. A light emitting element of the invention includes a first layer for generating holes, a second layer for generating electrons and a third layer comprising a light emitting substance between first and second electrodes. The first and third layers are in contact with the first and second electrodes, respectively. The second and third layers are connected to each other so as to inject electrons generated in the second layer into the third layer when applying the voltage to the light emitting element such that a potential of the second electrode is higher than that of the first electrode. | 2011-05-05 |
| 20110101381 | LED Module with Silicon Platform - An LED module having an LED semiconductor chip mounted directly or indirectly on a platform. The platform is made from silicon and extends laterally beyond the LED semiconductor chip having an active light emitting layer and a substrate. At least one electronic component that is part of the control circuitry for the LED semiconductor chip is integrated in the silicon platform. | 2011-05-05 |
| 20110101382 | LIGHT CONVERTING CONSTRUCTION - Light converting constructions are disclosed. The light converting construction includes a phosphor slab that has a first index of refraction for converting at least a portion of light at a first wavelength to light at a longer second wavelength; and a structured layer that is disposed on the phosphor slab and has a second index of refraction that is smaller than the first index of refraction. The structured layer includes a plurality of structures that are disposed directly on the phosphor slab and a plurality of openings that expose the phosphor slab. The light converting construction further includes a structured overcoat that is disposed directly on at least a portion of the structured layer and a portion of the phosphor slab in the plurality of openings. The structured overcoat has a third index of refraction that is greater than the second index of refraction. | 2011-05-05 |
| 20110101383 | Semiconductor Component and Method for Producing a Semiconductor Component - A semiconductor component comprising at least one optically active first region ( | 2011-05-05 |
| 20110101384 | LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE, AND ILLUMINATION DEVICE - According to one embodiment, a light-emitting device includes a substrate, a plurality of pads and a plurality of light-emitting elements. The pads has electric conductance, and are arranged on the substrate. A reflecting layer which is formed by electroplating is provided on a surface of each of the pads. The light-emitting elements are mounted on the pads. A depressed part is left on the substrate. The depressed part is formed on the substrate by removing a pattern on the substrate, by which the pads are electrically connected. | 2011-05-05 |
| 20110101385 | PACKAGED SEMICONDUCTOR LIGHT EMITTING DEVICES HAVING MULTIPLE OPTICAL ELEMENTS AND METHODS OF FORMING THE SAME - Methods of packaging a semiconductor light emitting device include providing a substrate having the semiconductor light emitting device on a front face thereof. A first optical element is formed from a first material on the front face proximate the semiconductor light emitting device but not covering the semiconductor light emitting device and a second optical element is formed from a second material, different from the first material, over the semiconductor light emitting device and the first optical element. Packaged semiconductor light emitting devices are also provided. | 2011-05-05 |
| 20110101386 | DISPLAY APPARATUS AND METHOD OF PRODUCING SAME - To further improve light extraction efficiency, a light-emitting apparatus includes a cavity for resonating light emitted from a emission layer between a first reflective surface and a second reflective surface. The first reflective surface is located on a first electrode side relative to the emission layer. The second reflective surface is located on a second electrode side relative to the emission layer. A periodic structure for extracting, to outside of a light-emitting device, light which is generated from the emission layer and wave-guided in an in-plane direction of the light-emitting device between the first reflective surface and the second reflective surface is formed in the first reflective surface, or in the second reflective surface, or between the first reflective surface and the second reflective surface. | 2011-05-05 |
| 20110101387 | LIGHT EMITTING DEVICE AND IMAGE DISPLAY DEVICE - By a light emitting device including a light emitting element, and a semiconductor phosphor microparticle having a core/shell structure having a shell part absorbing at least a part of the light emitted by the light emitting element, and an image display device including a light emitting element, and a semiconductor phosphor microparticle having a core/shell structure having a shell part that absorbs at least a part of the light emitted by the light emitting element, a light emitting device and an image display device having high luminous efficiency are provided. | 2011-05-05 |
| 20110101388 | LIGHT EMITTING DEVICE - It is an object of the present invention to provide a light emitting device which is less affected by a malfunction caused in a light emitting element. It is another object of the invention to provide a light emitting device in which light emitting elements are connected in series. As to a light emitting device of the invention, groups of circuits each having a light emitting element and a limiter are connected in parallel. Here, a light emitting element and a limiter are connected in series. The number of the circuits may be at least two or more. Further, each circuit group includes at least one light emitting element. | 2011-05-05 |
| 20110101389 | MULTICHIP TYPE LED PACKAGE STRUCTURE FOR GENERATING LIGHT-EMITTING EFFECT SIMILAR TO CIRCLE SHAPE BY SINGLE WIRE OR DUAL WIRE BONDING METHOD ALTERNATIVELY - A multichip type LED package structure for generating light-emitting effect similar to circle shape includes a substrate unit, a light-emitting unit and a package unit. The substrate unit has a substrate body and a plurality of conductive circuits separated from each other by a predetermined distance and disposed on the substrate body. Each conductive circuit has a plurality of extending portions, and the extending portions of every two conductive circuits are adjacent to each other and are alternated with each other. The light-emitting unit has a plurality of LED chips selectively electrically disposed on the substrate unit. The package unit has a light-transmitting package resin body formed on the substrate unit to cover the LED chips. | 2011-05-05 |
| 20110101390 | Monolithic, Optoelectronic Semiconductor Body and Method for the Production Thereof - An optoelectronic semiconductor body comprises a semiconductor layer sequence which is subdivided into at least two electrically isolated subsegments. The semiconductor layer sequence has an active layer in each subarea. Furthermore, at least three electrical contact pads are provided. A first line level makes contact with a first of the at least two subsegments and with the first contact pad. A second line level makes contact with the second of the at least two subsegments and with a second contact pad. A third line level connects the two subsegments to one another and makes contact with the third contact pad. Furthermore, the line levels are each arranged opposite a first main face, wherein the first main face is intended to emit electromagnetic radiation that is produced. | 2011-05-05 |
| 20110101391 | GROUP III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND LAMP - A Group III nitride semiconductor device of the present invention is obtained by laminating at least a buffer layer ( | 2011-05-05 |
| 20110101392 | PACKAGE SUBSTRATE FOR OPTICAL ELEMENT AND METHOD OF MANUFACTURING THE SAME - Disclosed is a package substrate for an optical element, which includes a metal core having a hole formed therein, an insulating layer formed on the surface of the metal core, a first metal layer formed to a predetermined thickness on the surface of the insulating layer so as to include therein the metal core insulated by the insulating layer, an optical element mounted on the first metal layer, and a fluorescent resin material applied on the optical element in order to protect the optical element, thereby simplifying a package substrate process and improving light uniformity, light reflectivity and heat dissipating properties compared to a conventional configuration. A method of manufacturing the package substrate is also provided. | 2011-05-05 |
| 20110101393 | LIGHT-EMITTING DIODE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) package structure includes a LED chip, an interconnecting substrate, a first conductive lead and a second conductive lead. The LED chip is provided with first and second electrical contacts formed on the same side thereof. The upper surface of the interconnecting substrate is provided with two conductive traces and first, second, third and fourth conductive pads. The first and second conductive pads are electrically connected to the third and fourth conductive pads by the two conductive traces, respectively. The first and second conductive leads are directly soldered to the third and fourth conductive pads, respectively. The LED chip is mounted onto the upper surface of the interconnecting substrate in a flip-chip configuration so that the first and second conductive pads thereof are mechanically and electrically connected to the first and second electrical contacts, respectively. | 2011-05-05 |
| 20110101394 | ULTRA HIGH THERMAL PERFORMANCE PACKAGING FOR OPTOELECTRONICS DEVICES - A light emitting module comprises a light emitting device (LED) mounted on a high thermal dissipation sub-mount, which performs the traditionally function of heat spread and the first part of the heat sinking. The sub-mount is a grown metal that is formed by an electroplating, electroforming, electrodeposition or electroless plating process, thereby minimising thermal resistance at this stage. An electrically insulating and thermally conducting layer is at least partially disposed across the interface between the grown semiconductor layers of the light emitting device and the formed metal layers of the sub-mount to further improve the electrical isolation of the light emitting device from the grown sub-mount. The top surface of the LED is protected from electroplating or electroforming by a wax or polymer or other removable material on a temporary substrate, mould or mandrel, which can be removed after plating, thereby releasing the LED module for subsequent processing. | 2011-05-05 |
| 20110101395 | LIGHT EMITTING DIODE WITH THIN MULTILAYER PHOSPHOR FILM - A multiple layer film and a method of manufacturing the same, the film having a phosphor bearing layer including phosphor and a carrier, and a rigid protective layer. In some embodiments a mixture including phosphor and an uncurable fluid are dispensed onto a surface, and the mixture is at least partially dried. A curable fluid is dispensed onto the at least partially dried mixture, and the curable fluid is cured. | 2011-05-05 |
| 20110101396 | ORGANIC LIGHT-EMITTING DIODE LIGHTING APPARATUS - Disclosed herein is an organic light-emitting diode lighting apparatus. The organic light-emitting diode lighting apparatus may include a transparent substrate main body with a plurality of groove lines formed therein, auxiliary electrodes formed in at least of the plurality of groove lines, a first electrode formed on the substrate main body, positive temperature coefficients configured to connect the auxiliary electrodes and the first electrode, an organic emission layer formed on the first electrode, and/or a second electrode formed on the organic emission layer. | 2011-05-05 |
| 20110101397 | LIGHT EMITTING DIODE PACKAGE HAVING LENS - Provided is a light emitting diode package. The light emitting diode package includes a package body, a light emitting diode chip, and a package lens. The light emitting diode chip is installed in the package body. The package lens is installed in the package body to cover the light emitting diode chip, and is formed to have a shape corresponding to a radiation angle pattern of the light emitting diode chip. | 2011-05-05 |
| 20110101398 | ORGANIC EL DEVICE MANUFACTURING METHOD, ORGANIC EL DEVICE, AND ELECTRONIC APPARATUS - In a method for manufacturing an organic EL device, a first luminescent layer emitting first color light is formed over a first anode disposed on a substrate by coating. A second luminescent layer emitting second color light is formed over a second anode disposed on the substrate. An intermediate layer having electron injection performance is formed on the first luminescent layer and the second luminescent layer. A third luminescent layer emitting third color light is formed over the intermediate layer and a third anode disposed on the substrate by vapor deposition. A cathode is formed on the third luminescent layer. | 2011-05-05 |
| 20110101399 | Solid element device and method for manufacturing the same - A solid element device includes a solid element, an electric power receiving and supplying part for receiving electric power from and supplying the electric power to the solid element, and an inorganic sealing material for sealing the solid element. The inorganic sealing material includes a low melting glass selected from SiO | 2011-05-05 |
| 20110101400 | LIGHT EMITTING DIODES (LEDS) WITH IMPROVED LIGHT EXTRACTION BY ROUGHENING - Systems and methods are disclosed for fabricating a semiconductor light-emitting diode (LED) device by forming an n-doped gallium nitride (n-GaN) layer on the LED device and roughening the surface of the n-GaN layer to extract light from an interior of the LED device. | 2011-05-05 |
| 20110101401 | ORGANIC LIGHT-EMITTING ELEMENT, METHOD FOR MANUFACTURING THE ORGANIC LIGHT-EMITTING ELEMENT, APPARATUS FOR MANUFACTURING THE ORGANIC LIGHT-EMITTING ELEMENT, AND ORGANIC LIGHT-EMITTING DEVICE USING THE ORGANIC LIGHT-EMITTING ELEMENT - Disclosed is an organic light-emitting display device that comprises a light-emitting layer formable simply by a wet process and has a prolonged service life. Also disclosed is an organic light-emitting device that comprises an upper transparent electrode having a lowered wiring resistance that can lower wiring resistance-derived power consumption. Further disclosed are a method and an apparatus for manufacturing an organic light-emitting element having a prolonged service life. In a first embodiment, an organic light-emitting display device is provided that comprises a moisture capturing layer provided between an upper electrode and a lower electrode. In a second embodiment, an organic light-emitting apparatus is provided that comprises a metal substrate, an organic light-emitting element provided on the metal substrate, and an upper transparent electrode connected electrically to the metal substrate through a contact hole. In a third embodiment, a method for manufacturing an organic light-emitting element comprising a first organic compound including a light-emitting layer and a second organic compound is provided that comprises the steps of forming the first organic compound, heating the first organic compound in vacuo, and forming the second organic compound. | 2011-05-05 |
| 20110101402 | SEMICONDUCTOR LIGHT CONVERTING CONSTRUCTION - Semiconductor light converting constructions are disclosed. The semiconductor light converting construction includes a semiconductor potential well for converting at least a portion of light at a first wavelength to light at a longer second wavelength; an outer layer that is disposed on the semiconductor potential well and has a first index of refraction; and a structured layer that is disposed on the outer layer and has a second index of refraction that is smaller than the first index of refraction. The structured layer includes a plurality of structures that are disposed directly on the outer layer and a plurality of openings that expose the outer layer. The semiconductor light converting construction further includes a structured overcoat that is disposed directly on at least a portion of the structured layer and a portion of the outer layer in the plurality of openings. The overcoat has a third index of refraction that is greater than the second index of refraction. | 2011-05-05 |
| 20110101403 | SEMICONDUCTOR LIGHT CONVERTING CONSTRUCTION - Semiconductor light converting constructions are disclosed. The semiconductor light converting construction includes a first semiconductor layer for absorbing at least a portion of light at a first wavelength; a semiconductor potential well for converting at least a portion of the light absorbed at the first wavelength to light at a longer second wavelength; and a second semiconductor layer that is capable of absorbing at least a portion of light at the first wavelength. The first semiconductor layer has a maximum first index of refraction at the second wavelength. The second semiconductor layer has a second index of refraction at the second wavelength that is greater than the maximum first index of refraction. | 2011-05-05 |
| 20110101404 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting device. The light-emitting device comprises: a substrate; and a first light-emitting unit comprising a plurality of light-emitting diodes electrically connected to each other on the substrate. A first light-emitting diode in the first light-emitting unit comprises a first semiconductor layer with a first conductivity-type, a second semiconductor layer with a second conductivity-type, and a light-emitting stack formed between the first and second semiconductor layers. The first light-emitting diode in the first light-emitting unit further comprises a first connecting layer on the first semiconductor layer for electrically connecting to a second light-emitting diode in the first light-emitting unit; a second connecting layer, separated from the first connecting layer, formed on the first semiconductor layer; and a third connecting layer on the second semiconductor layer for electrically connecting to a third light-emitting diode in the first light-emitting unit. | 2011-05-05 |
| 20110101405 | LIGHT-EMITTING DIODE PACKAGE - A light-emitting diode package is provided. The light-emitting diode package comprises a substrate and a first metal layer disposed over the substrate. A solder layer is disposed on the first metal layer and a light-emitting diode chip is disposed on the solder layer, wherein the light-emitting diode chip comprises a conductive substrate and a multilayered epitaxial structure formed on the conductive substrate, and wherein the conductive substrate is adjacent to the solder layer. | 2011-05-05 |
| 20110101406 | Light emitting device package and method for manufacturing the same - The present invention provides a light emitting device package including: a light emitting device structure having a light emitting device and a lead frame connected to the light emitting device; and a heat radiating structure bonded to the light emitting device structure and radiating heat generated from the light emitting device, wherein the heat radiating structure includes a conductive substrate, an insulating pattern covering a front surface of the conductive substrate opposite to the light emitting device structure, and a metal pattern bonded to the conductive substrate and the lead frame. | 2011-05-05 |
| 20110101407 | SEMICONDUCTOR LIGHT-EMITING DEVICE AND METHOD - A semiconductor light-emitting device can include a submount on which a semiconductor light-emitting element is mounted. The device can have a high light utilization efficiency with high reliability and can achieve a reduction in manufacturing cost as well as a decrease in size. The submount can have a reverse trapezoidal cross section having an upper surface that is larger than a bottom surface of the semiconductor light-emitting element. An adhesive can be used to fix the submount to the base board such that, when the submount is observed from above the semiconductor light-emitting element, the adhesive is not seen from above. In this state, the semiconductor light-emitting element can be connected to the base board via a bonding wire. | 2011-05-05 |
| 20110101408 | LED DIE HAVING HEAT DISSIPATION LAYERS - An LED die includes a multi-layer semiconductor with a first surface, a second surface opposite to the first surface, an inclined plane connecting to the first surface and the second surface, a first electrode and a second electrode respectively positioned on the first surface and the second surface, a first heat dissipation layer made of electrically-insulating and thermally conductive material being coated on the first surface and the inclined plane with a first opening exposing the first electrode, and a second heat dissipation layer made of electrically and thermally conductive material being coated on the first heat dissipation layer and contacting and electrically connecting with the first electrode. | 2011-05-05 |
| 20110101409 | LED Lamp Package with Integral Driver - A lamp package includes a leadframe. At least one light emitting diode is mechanically and electrically coupled to the leadframe. At least one electronic component is also mechanically and electrically coupled to the leadframe and electrically coupled to the light emitting diode, the electronic component controlling the supply of electrical power to the light emitting diode. At least one interconnect is electrically coupled to the leadframe. A formed structure is joined to the leadframe, the formed structure enclosing at least a portion of the leadframe. | 2011-05-05 |
| 20110101410 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE/POST HEAT SPREADER - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The heat spreader includes a first post, a second post and a base. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The first post extends from the base in a first vertical direction into a first opening in the first adhesive, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts. The conductive trace provides signal routing between the pad and the terminal. | 2011-05-05 |
| 20110101411 | SUPPORT MODULE FOR A SOLID STATE LIGHT SOURCE, A LIGHTING DEVICE COMPRISING SUCH A MODULE, AND A METHOD FOR MANUFACTURING SUCH A LIGHTING DEVICE - A support module ( | 2011-05-05 |
| 20110101412 | Light-emitting semiconductor device using group III nitrogen compound - A method of producing a light-emitting semiconductor device of a group III nitride compound includes forming an N-layer of an N-type conduction, the N-layer comprising gallium nitride, forming a high carrier concentration N | 2011-05-05 |
| 20110101413 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a semiconductor device. In the method, a growth substrate provided with a single crystal semiconductor thin layer, a support substrate, and a temporary substrate are prepared, the growth substrate, the support substrate, and the temporary substrate are bonded to one another with the support substrate therebetween through functional wafer coupling layers, the growth substrate is lifted off from the single crystal semiconductor thin layer, and the temporary substrate is lifted off from the support substrate. | 2011-05-05 |
| 20110101414 | LIGHT EMITTING DIODES WITH ZINC OXIDE CURRENT SPREADING AND LIGHT EXTRACTION LAYERS DEPOSITED FROM LOW TEMPERATURE AQUEOUS SOLUTION - A method for fabricating a Light Emitting Diode (LED) with increased light extraction efficiency, comprising providing a III-Nitride based LED structure comprising a light emitting active layer between a p-type layer and an n-type layer; growing a Zinc Oxide (ZnO) layer epitaxially on the p-type layer by submerging a surface of the p-type layer in a low temperature aqueous solution, wherein the ZnO layer is a transparent current spreading layer; and depositing a p-type contact on the ZnO layer. The increase in efficiency may be more than 93% with very little or no increase in cost. | 2011-05-05 |
| 20110101415 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises: a first conductive type semiconductor layer; an active layer on the first conductive type semiconductor layer; an undoped semiconductor layer on the active layer; a first delta-doped layer on the undoped semiconductor layer; and a second conductive type semiconductor layer on the first delta-doped layer. | 2011-05-05 |
| 20110101416 | BIPOLAR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided. | 2011-05-05 |
| 20110101417 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers. | 2011-05-05 |
| 20110101418 | Method for improving transistor performance through reducing the salicide interface resistance - An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption. | 2011-05-05 |
| 20110101419 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND OPTICAL APPARATUS - This semiconductor device includes a substrate, an underlayer formed on a main surface of the substrate, a first semiconductor layer and a second semiconductor layer. Unstrained lattice constants of the underlayer and the second semiconductor layer in a second direction are larger than a lattice constant of the substrate in the second direction in an unstrained state. Lattice constants of the underlayer and the second semiconductor layer in the second direction in a state of being formed on the main surface are larger than the lattice constant of the substrate in the second direction. | 2011-05-05 |
| 20110101420 | INCREASING FULL WELL CAPACITY OF A PHOTODIODE USED IN DIGITAL PHOTOGRAPHY - A CMOS pixel circuit and timing for use in digital photography where the photodiode has increased full well. The circuit includes the photodiode, a reset transistor, a first transfer gate to move a charge from the photodiode to a floating diffusion node, a source follower transistor, a row select transistor, a second transfer gate located between the photodiode and the first transfer, and a capacitor located between the first and second transfer gates. | 2011-05-05 |
| 20110101421 | METHOD OF FORMING EPI FILM IN SUBSTRATE TRENCH - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation. | 2011-05-05 |
| 20110101422 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased. | 2011-05-05 |
| 20110101423 | JUNCTION FIELD EFFECT TRANSISTOR - A field effect transistor having a drain, a gate and a source, where the drain and source are formed by semiconductor regions of a first type, and in which a further doped region is provided intermediate the gate and the drain. Field gradients around the drain are thereby reduced. | 2011-05-05 |
| 20110101424 | JUNCTION FIELD EFFECT TRANSISTOR - A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping. | 2011-05-05 |
| 20110101425 | SEMICONDUCTOR DEVICE WITH INCREASED SNAPBACK VOLTAGE - Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region. | 2011-05-05 |
| 20110101426 | SEMICONDUCTOR DEVICE COMPRISING REPLACEMENT GATE ELECTRODE STRUCTURES WITH AN ENHANCED DIFFUSION BARRIER - In sophisticated semiconductor devices, the integrity of the device level may be enhanced after applying a replacement gate approach by providing an additional diffusion barrier layer, such as a silicon nitride layer, thereby obtaining a similar degree of diffusion blocking capabilities as in semiconductor devices without performing a replacement gate approach. | 2011-05-05 |
| 20110101427 | TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SUPERIOR IMPLANTATION MASKING EFFECT - When forming a sophisticated high-k metal gate stack in an early manufacturing stage, the dielectric cap layer may be efficiently removed without unduly affecting the drain and source extension regions. To this end, a specifically designed sidewall spacer structure may be used, such as a silicon dioxide spacer element in combination with a silicon nitride etch stop liner. The spacer structure may thus enable the removal of the dielectric cap layer while still maintaining the functions of an implantation mask and a silicidation mask during the further processing. | 2011-05-05 |
| 20110101428 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semiconductor substrate adjacent to the gate electrode to a first depth to the semiconductor substrate, the impurity diffusion region containing impurity, an inert substance containing region formed in the area of the semiconductor substrate to a second depth deeper than the first depth, the inert substance containing region containing an inert substance, and a diffusion suppressing region formed in the area of the semiconductor substrate to a third depth deeper than the second depth, the diffusion suppressing region containing a diffusion suppressing substance suppressing diffusion of the impurity. | 2011-05-05 |
| 20110101429 | SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FIN STRUCTURES AND ELECTRONIC DEVICE - Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-PET devices. Electronic systems including such fin-FET devices are also disclosed. | 2011-05-05 |
| 20110101430 | CMOS IMAGE SENSOR - A CIS and a method of manufacturing the same, the CIS including a substrate having a first surface and second surface opposite thereto, the substrate including an APS array region including a photoelectric transformation element and a peripheral circuit region; an insulating interlayer on the first surface of the substrate and including metal wirings electrically connected to the photoelectric transformation element; a light blocking layer on the peripheral circuit region of the second surface of the substrate, exposing the APS array region, and including a plurality of metal wiring patterns spaced apart from one another to form at least one drainage path along a boundary region between the APS array region and the peripheral circuit region; a color filter layer on the second surface of the substrate covering the APS array region and the light blocking layer; and a microlens on the color filter layer on the APS array region. | 2011-05-05 |
| 20110101431 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technology capable of improving the property of an MRAM in a semiconductor device containing the MRAM. | 2011-05-05 |
| 20110101432 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a capacitor, the capacitor includes a lower electrode, which includes platinum, provided above a semiconductor substrate; a first ferroelectric film, which includes lead zirconate titanate added with La, provided on the lower electrode; a second ferroelectric film, which includes lead zirconate titanate added with La, Ca, and Sr, provided directly on the first ferroelectric film, the second ferroelectric film having a thickness smaller than that of the first ferroelectric film and includes amounts of Ca and Sr greater than amounts of Ca and Sr that may be present in the first ferroelectric film; and an upper electrode, which includes a conductive oxide, provided on the second ferroelectric film. | 2011-05-05 |
| 20110101433 | UNIT BLOCK CIRCUIT OF SEMICONDUCTOR DEVICE - A unit block circuit of a semiconductor device includes a first well, a first pickup unit configured to form a closed loop over the first well, a first transistor including a first gate and a first active region, and formed within the first pickup unit, and a first reservoir capacitor formed in a spare within the first pickup unit and arranged in a major-axis direction of the first gate of the first transistor, wherein the first reservoir capacitor comprises a second active region and a second gate, the second gate being formed over the second active region. | 2011-05-05 |
| 20110101434 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region. | 2011-05-05 |
| 20110101435 | BURIED BIT LINE PROCESS AND SCHEME - The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer. | 2011-05-05 |
| 20110101436 | SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A substrate for a semiconductor device includes: a base substrate; a semiconductor layer that has a source region, a drain region, a plurality of channel regions, and at least one intermediate region; a source electrode being in contact with the source region; a drain electrode being in contact with the drain region; a gate electrode that overlaps the plurality of channel regions, the intermediate region, and each of a part of the source electrode and a part of the drain electrode; and a floating electrode being in contact with the intermediate region. The size of an area where the floating electrode and the gate electrode overlap each other is smaller than the sum of the size of an area where the source electrode and the gate electrode overlap each other and the size of an area where the drain electrode and the gate electrode overlap each other. | 2011-05-05 |
| 20110101437 | METHOD OF FORMING NONVOLATILE MEMORY DEVICE HAVING FLOATING GATE AND RELATED DEVICE - A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region. | 2011-05-05 |
| 20110101438 | Nonvolatile Memory Devices Having Gate Structures Therein with Improved Blocking Layers - Nonvolatile memory devices include a tunnel insulating layer on a substrate and a charge storing layer on the tunnel insulating layer. A charge transfer blocking layer is provided on the charge storing layer. The charge transfer blocking layer is formed as a composite of multiple layers, which include a first oxide layer having a thickness of about 1 Å to about 10 Å. This first oxide layer is formed directly on the charge storing layer. The charge transfer blocking layer includes a first dielectric layer on the first oxide layer. The charge transfer blocking layer also includes a second oxide layer on the first dielectric layer and a second dielectric layer on the second oxide layer. The first and second dielectric layers have a higher dielectric constant relative to the first and second oxide layers, respectively. The memory cell includes an electrically conductive electrode on the charge transfer blocking layer. | 2011-05-05 |
| 20110101439 | INTERCONNECTION STRUCTURES FOR SEMICONDCUTOR DEVICES - An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug. | 2011-05-05 |
| 20110101440 | TWO PFET SOI MEMORY CELLS - A CMOS device includes a silicon substrate and an electrical insulator formed over the silicon substrate. The device also includes an access pFET formed over the electrical insulator and a first gate stack and a storage pFET formed over the electrical insulator, the storage pFET including a second source region that is co-formed with the first drain region, a second channel region, and a second drain region. The device also includes a second gate stack including a second dielectric layer formed above the second channel region and a floating gate electrode formed above the second gate dielectric layer. | 2011-05-05 |
| 20110101441 | SELECT GATES FOR MEMORY - Methods of forming memory and memory devices are disclosed, such as a memory device having a memory cell with a floating gate formed from a first conductor, a control gate formed from a second conductor, and a dielectric interposed between the floating gate and the control gate. For example, a select gate may be coupled in series with the memory cell and has a first control gate portion formed from the first conductor and a second control gate portion formed from a third conductor. A contact may be formed from the third conductor and coupled in series with the select gate. Other methods and devices are also disclosed. | 2011-05-05 |
| 20110101442 | Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control - A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed. | 2011-05-05 |
| 20110101443 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern. | 2011-05-05 |
| 20110101444 | ELECTROSTATIC PROTECTION DEVICE - An apparatus including an electrostatic discharge (ESD) protection device comprising a semiconductor having first, second and third regions arranged to form a transistor, wherein the first region is doped with a first impurity of a first conductivity type and is separated from the second region which is doped with a second impurity of a second conductivity type opposite the first type, and wherein a dimensional constraint of the regions defines an operational threshold of the ESD protection device. In one example, the separation between a collector and an emitter of a bipolar transistor defines a trigger voltage to cause the electrostatic discharge protection device to become conducting. In another example, a width of a bipolar transistor base controls a holding voltage of the electrostatic discharge protection device. | 2011-05-05 |
| 20110101445 | SUBSTRATE STRUCTURES INCLUDING BURIED WIRING, SEMICONDUCTOR DEVICES INCLUDING SUBSTRATE STRUCTURES, AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate structure including a first substrate and a second substrate, and a buried wiring interposed between the first substrate and the second structure, where the buried wiring is in direct contact with the second substrate. The semiconductor device further includes a vertical transistor located in the second substrate of the substrate structure. The vertical transistor includes a gate electrode and a semiconductor pillar, and the buried wiring is one of source electrode or a drain electrode of the vertical transistor | 2011-05-05 |
| 20110101446 | STAGGERED COLUMN SUPERJUNCTION - A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer. | 2011-05-05 |
| 20110101447 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having trenches, buried bit lines formed in the substrate, and including a metal silicide layer and a metallic layer, wherein the metal silicide layer contacts sidewalls of the trenches and the metallic layer is formed over the sidewalls of the trenches and contacts the metal silicide layer. | 2011-05-05 |
| 20110101448 | VERTICAL TRANSISTOR AND MANUFACTURING METHOD THEREOF - A vertical transistor includes: a substrate, a bottom-oxide layer, an epitaxial silicon layer, an insulating oxide layer, two gate-oxide films and a gate-stacked layer. The bottom-oxide layer is disposed on the substrate, and the bottom-oxide layer has a gate recess concavely formed thereof. The substrate has a first doped area in an upper part corresponding to the gate recess. The epitaxial silicon layer is formed on the gate recess, and the epitaxial silicon layer has a second doped area in an upper part. The insulating oxide layer is disposed on the epitaxial silicon layer. The gate-oxide films are respectively formed on two opposite sides of the epitaxial silicon layer. The gate-stacked layer is formed on the two gate-oxide layers and the bottom-oxide layer. Whereby, the lateral area of transistor is reduced, and the integration and the performance of the device are improved. | 2011-05-05 |
| 20110101449 | ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD - Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (R | 2011-05-05 |
| 20110101450 | SEMICONDUCTOR DEVICE WITH BURIED GATES AND BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a plurality of first trenches formed inside a plurality of active regions; a plurality of buried gates configured to partially fill insides of the plurality of the first trenches; a plurality of second trenches formed to be extended in a direction crossing the plurality of the buried gates; and a plurality of buried bit lines configured to fill the plurality of the second trenches. | 2011-05-05 |
| 20110101451 | SEMICONDUCTOR COMPONENT STRUCTURE WITH VERTICAL DIELECTRIC LAYERS - A semiconductor component having a semiconductor body having a first and a second side, an edge and an edge region adjacent to the edge in a lateral direction is described. | 2011-05-05 |
| 20110101452 | TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A trench-gate semiconductor device configuration is provided which is suitable for incorporation in integrated circuits, together with methods for its manufacture. A self-aligned drain region ( | 2011-05-05 |
| 20110101453 | LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR - The invention provides a lateral double-diffused metal oxide semiconductor (LDMOS). The pre-metal dielectric layer (PMD) of the LDMOS is a silicon rich content material. Additionally, the inter-layer dielectric layer (ILD), inter-metal dielectric layer (IMD), or protective layer of the LDMOS may be formed of a silicon rich content material. | 2011-05-05 |
| 20110101454 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A P type semiconductor substrate includes a P type body region, an N type drift region formed away from the P type body region in a direction parallel to a substrate surface, an N type drain region formed in a region separated by a field oxide film in the N type drift region so as to have a concentration higher than the N type drift region, an N type source region formed in the P type body region so as to have a concentration higher than the N type drift region. A P type buried diffusion region having a concentration higher than the N type drift region is formed of a plurality of parts each of which is connected to a part of the bottom surface of the P type body region and extends parallel to the substrate surface and its tip end reaches the inside of the drift region. | 2011-05-05 |
| 20110101455 | FINFET SPACER FORMATION BY ORIENTED IMPLANTATION - A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack. | 2011-05-05 |
| 20110101456 | STRAIN ENGINEERING IN THREE-DIMENSIONAL TRANSISTORS BASED ON GLOBALLY STRAINED SEMICONDUCTOR BASE LAYERS - Non-planar transistors, such as FINFETs, may be formed on the basis of a globally strained semiconductor material, thereby preserving a high uniaxial strain component in the resulting semiconductor fins. In this manner, a significant performance enhancement may be achieved without adding process complexity when implementing FINFET transistors. | 2011-05-05 |
| 20110101457 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is that the method of manufacturing the semiconductor device including a first process of implanting a first impurity of a first conductivity type in a source and drain region having an elevated structure, with a concentration equal to or less than 1E14 atoms/cm | 2011-05-05 |
| 20110101458 | SOI type semiconductor device having a protection circuit - An SOI type semiconductor device having a silicon substrate and a buried oxide layer formed on the silicon substrate includes an internal circuit formed in a first region having at least one FD type transistor having a SOI structure, the internal circuit performing a function of the semiconductor device and a protection circuit formed in a second region having at least one PD type transistor having a SOI structure, the protection circuit protecting the internal circuit from electro static damage. | 2011-05-05 |
| 20110101459 | Thin Film Transistors and Fabrication Methods Thereof - Thin film transistors and fabrication methods thereof. A gate is formed overlying a portion of a substrate. A first vanadium oxide layer formed overlying the gate and the substrate. A gate-insulating layer is formed overlying the first vanadium oxide layer. A semiconductor layer is formed on a portion of the gate-insulating layer. A source and a drain are formed on a portion of the semiconductor layer. | 2011-05-05 |
| 20110101460 | SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES - In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment. | 2011-05-05 |
| 20110101461 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention presupposes a MIPS electrode in which a gate electrode of a MISFET is made up of a stacked film of a metal film and a polysilicon film. Then, by a first characteristic point that a gate contact hole is formed to have an opening diameter larger than a gate length of the gate electrode of the MIPS electrode and a second characteristic point that a concave portion is formed in a side surface of the metal film constituting the gate electrode, the further reduction of the gate resistance (parasitic resistance) and the improvement of the connection reliability between the gate electrode and the gate plug can be achieved. | 2011-05-05 |
| 20110101462 | METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE INCLUDING STRESS FILMS - A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region. | 2011-05-05 |
| 20110101463 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device includes a first device and a second device, which are implemented laterally next to each other in a substrate. A recombination zone is implemented in the substrate between the first device and the second device, so that diffusing charge carriers recombine between the first device and the second device. | 2011-05-05 |
| 20110101464 | METHOD AND RESULTING STRUCTURE DRAM CELL WITH SELECTED INVERSE NARROW WIDTH EFFECT - A shallow trench isolation structure for integrated circuits includes a semiconductor substrate having a trench and a buffered oxide layer overlying the semiconductor substrate. A pad nitride layer is overlying the buffered oxide layer. An implanted region is formed around a perimeter of the trench. The trench has a bottom width of less than 0.13 microns and an upper width of less than 0.13 microns. A rounded edge is surrounding a periphery of the trench. The rounded edge has a radius of curvature greater than about 0.02 um. A planarized high density plasma fill material is formed within the trench. The structure has a P-well region within the semiconductor substrate and bordering a vicinity of the trench region. A channel region is within the P-well region within the semiconductor substrate. The implanted region has an impurity concentration of more than double an amount of impurities in the channel region. | 2011-05-05 |
| 20110101465 | CMOS DEVICE STRUCTURES - Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd). | 2011-05-05 |
| 20110101466 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 2011-05-05 |
| 20110101467 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor device includes a first gate structure formed on a substrate, a first insulating interlayer covering the first gate structure on the substrate, a first active pattern formed through and on the first insulating interlayer and contacting the substrate, a second gate structure formed on the first active pattern and the first insulating interlayer, a buffer layer covering the second gate structure on the first active pattern and the first insulating interlayer, a second insulating interlayer formed on the buffer layer, and a contact plug formed through the first and second insulating interlayers, which contacts with the substrate and is insulated from the second gate structure by the buffer layer. Operation failures of a transistor in the stacked semiconductor device can be reduced because the buffer layer prevents a word line from being electrically connected to the contact plug. | 2011-05-05 |
| 20110101468 | Method of manufacturing semiconductor device and semiconductor device - A semiconductor device according to the embodiments comprises a gate insulator formed on a substrate, the gate insulator including a high-dielectric film in whole or part, a reaction film including a first metal on the gate insulator; a metal film including a second metal on the reaction film; and a film including Si formed on the metal film. | 2011-05-05 |
| 20110101469 | STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CORNER ROUNDING AT THE TOP OF THE GATE ELECTRODE - In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage. | 2011-05-05 |
| 20110101470 | HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS IN TRANSISTORS OF DIFFERENT CONDUCTIVITY TYPE - In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence. | 2011-05-05 |
| 20110101471 | METHOD OF FORMING A NANOCLUSTER-COMPRISING DIELECTRIC LAYER AND DEVICE COMPRISING SUCH A LAYER - A method of forming a dielectric layer on a further layer of a semiconductor device is disclosed. The method comprises depositing a dielectric precursor compound and a further precursor compound over the further layer, the dielectric precursor compound comprising a metal ion from the group consisting of Yttrium and the Lanthanide series elements, and the further precursor compound comprising a metal ion from the group consisting of group IV and group V metals; and chemically converting the dielectric precursor compound and the further precursor compound into a dielectric compound and a further compound respectively, the further compound self-assembling during said conversion into a plurality of nanocluster nuclei within the dielectric layer formed from the first dielectric precursor compound. The nanoclusters may be dielectric or metallic in nature. Consequently, a dielectric layer is formed that has excellent charge trapping capabilities. Such a dielectric layer is particularly suitable for use in semiconductor devices such as non-volatile memories. | 2011-05-05 |
| 20110101472 | STRUCTURE AND METHOD TO FORM A THERMALLY STABLE SILICIDE IN NARROW DIMENSION GATE STACKS - An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height. | 2011-05-05 |
| 20110101473 | Junction deveice - This invention relates to a junction device, especially a p-n junction device. This invention also relates to a backward current decoupler which is also a good sensor. An induced backward current by forward current input can be decoupled by the backward current decoupler. The new p-n junction device has built-in damper and better capacitive property so that less power is consumed. The new sensor can be interactable with thermal, magnetic, optical, force or electrical fields. | 2011-05-05 |
| 20110101474 | METHOD FOR PROTECTING ENCAPSULATED SENSOR STRUCTURES USING STACK PACKAGING - A method of protecting a micro-mechanical sensor structure embedded in a micro-mechanical sensor chip, in which the micro-mechanical sensor structure is fabricated with a protective membrane, the micro-mechanical sensor chip is arranged so that a surface of the protective membrane faces toward a second chip, and the micro-mechanical sensor chip is secured to the second chip. | 2011-05-05 |
| 20110101475 | CMOS INTEGRATED MICROMECHANICAL RESONATORS AND METHODS FOR FABRICATING THE SAME - The present invention is directed to a CMOS integrated micromechanical device fabricated in accordance with a standard CMOS foundry fabrication process. The standard CMOS foundry fabrication process is characterized by a predetermined layer map and a predetermined set of fabrication rules. The device includes a semiconductor substrate formed or provided in accordance with the predetermined layer map and the predetermined set of fabrication rules. A MEMS resonator device is fabricated in accordance with the predetermined layer map and the predetermined set of fabrication rules. The MEMS resonator device includes a micromechanical resonator structure having a surface area greater than or equal to approximately 20 square microns. At least one CMOS circuit is coupled to the MEMS resonator member. The at least one CMOS circuit is also fabricated in accordance with the predetermined layer map and the predetermined set of fabrication rules. | 2011-05-05 |
