| 18th week of 2012 patent applcation highlights part 78 |
| Patent application number | Title | Published |
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| 20120110324 | METHOD AND APPARATUS FOR SENDING A KEY ON A WIRELESS LOCAL AREA NETWORK - A method and an apparatus for sending a key on a Wireless Local Area Network (WLAN) is provided. In a scenario where an Access Server is separate from an Access Controller, the Access Controller may send a master key of a specified WLAN station to the AC and trigger the AC to agree with the station on a transient key. The method includes: when receiving the master key of the WLAN station sent from an AAA server, searching a station information table for an IP address of an AC associated with the station; sending a message to the AC to instruct the AC to perform a 4-way handshake with the station to agree on a transient key, where the third message carries the master key of the station, a 4-way handshake triggering bit, and a MAC address of the WLAN station. | 2012-05-03 |
| 20120110325 | METHOD, DEVICE AND MOBILE TERMINAL FOR CHALLENGE HANDSHAKE AUTHENTICATION PROTOCOL AUTHENTICATION - A method, apparatus and mobile terminal for a Challenge Handshake Authentication Protocol (CHAP) authenticating in a CDMA Evolution to packet Data Optimized (EVDO) network are provided in the present invention. It makes the authentication process of EVDO network be successful, even though an authentication server does not support the Message Digest 5 (MD5) authentication method. The CHAP authentication method includes: receiving a CHAP authentication request which contains a first key value and is sent by an authentication server; when confirming that an identifier supporting MD5 authentication method is stored in the user identify module, calling MD5 authentication method to calculate a first authentication key value with the first key value, and sending the first authentication key value to the authentication server to authenticate; when receiving a CHAP re-authentication request which contains a second key value and is returned by the authentication server according to the first authentication key value after the authentication is failure, calling the Cellular Authentication and Voice Encryption (CAVE) authentication method to calculate a second authentication key value with the second key value, and sending the second authentication key value to the authentication server to authenticate. | 2012-05-03 |
| 20120110326 | ENHANCED CRYPTOGRAPHCIALLY GENERATED ADDRESSES FOR SECURE ROUTE OPTIMIZATION IN MOBILE INTERNET PROTOCOL - Enhanced cryptographically generated addresses (ECGAs) for MIPv6 incorporate a built-in backward key chain and offer support to bind multiple logically-linked CGAs together. Enhanced CGAs may be used to implement a secure and efficient route optimization (RO) for MIPv6. | 2012-05-03 |
| 20120110327 | EVENT-DRIVEN PROVISION OF PROTECTED FILES - A system may include reception of a request for an encryption key pair including a first private encryption key and a first public encryption key, the encryption key pair associated with a future event, generation of the encryption key pair, transmission of the first public encryption key to a second device, reception, from the second device, of a file encrypted using the first public encryption key and using a second public encryption key of an intended recipient, transmission of the file to a third device associated with the intended recipient, detection of the future event, and, in response to the detection of the future event, transmission of the first private encryption key to the third device. | 2012-05-03 |
| 20120110328 | System and Method For Secure Storage of Virtual Machines - A virtual file system is described that is implemented in a virtualization platform as a stackable file system layer that intercepts file operations between a hypervisor and a physical file system. The virtual file system encrypts (at least in part) VM files to be stored, organizes the encrypted VM files into VM sets, and then maps and stores the encrypted VM sets into storage pools. Storage and access to files within the VM sets is controlled through the use of administrator-determined policies governing storage, security, access control, authentication, and auditing. The system and method described herein allow a seamless integration between a data center (e.g., a private cloud) and computing resources served across the internet and supported by cloud service providers (e.g., public clouds) while ensuring that the security needs of customers and cloud service providers are met. | 2012-05-03 |
| 20120110329 | TECHNIQUES FOR MOBILE DEVICE AUTHENTICATION - A user authenticates a mobile device (MD) to a network-based service (NBS) for initial authentication. Policy is pushed from the NBS to the MD and the MD automatically obtains details about devices and attributes that are near or accessible to the MD in accordance with the policy. The details are pushed as a packet from the MD to the NBS and multifactor authentication is performed based on the details and the policy. If the multifactor authentication is successful, access privileges are set for the MD for accessing the NBS and perhaps for accessing local resources of the MD. | 2012-05-03 |
| 20120110330 | AUTOMATIC USER CREDENTIALS FOR REMOTE SUPPORT - Various embodiments herein include at least one of systems, methods, and software to receive and process credential requests for remote support of computer applications. One embodiment includes receiving a credentials request in a first environment from a second environment in response to an incident in the first environment. This embodiment further includes processing the received credentials request within the first environment by approving the request, activating credentials, and sending the credentials to the second environment. This embodiment may further include receiving, within the first environment, a message indicating the incident is resolved and deactivating the credentials. | 2012-05-03 |
| 20120110331 | METHOD FOR ACTIVATING A NETWORK NODE - In a method for activating a destination network node (SN) to be woken up in a wireless network ( | 2012-05-03 |
| 20120110332 | Secure Messaging with Automatic Recipient Enrollment - A public-key based secure messaging system with automatic receiver enrollment is disclosed. A sender in the system first determines whether a receiver has a public key. If the receiver has a public key, the messages will be sent to the receiver using a standard public-key based encryption. If the receiver does not have a public key, the first message will be sent to the receiver using a delivery method that does not require the receiver to have a pair of public and private keys prior to sending the message. However, when the receiver accesses the first message, a pair of public and private keys will be automatically generated at the receiver and the public key will be made available for encrypting subsequent messages sent to the receiver. | 2012-05-03 |
| 20120110333 | SOFTWARE SECURITY - An apparatus with at least one secure memory area comprising a plurality of pre-installed public keys for verifying software authenticity. The apparatus is caused to receive an indication that a software package signed with a private key according to public key infrastructure has been received; check from the secure memory area, whether a public key associated with the private key with which the software package has been signed, is disabled; and if the public key associated with the private key is disabled, prevent execution of the received software package, and otherwise, proceed to verify authenticity of the received software package using the public key associated with the private key. | 2012-05-03 |
| 20120110334 | SECURE ROUTE OPTIMIZATION IN MOBILE INTERNET PROTOCOL USING TRUSTED DOMAIN NAME SERVERS - A trusted domain name server is introduced to provide a secure route optimization procedure for MIPv6. A trusted authority registers network addresses of a mobile node with corresponding fully qualified domain names. The trusted domain name server can later be queried to compare the domain of a network address for a mobile node with the domain of a network address for another network node. | 2012-05-03 |
| 20120110335 | Secure Association of Metadata with Content - A method and system for associating metadata with an encrypted content item, the method including receiving metadata for association with a content item, receiving an entitlement control packet (ECP) associated with the content item, applying a cryptographic hash function to the ECP, thereby generating an ECP hash value, combining the ECP hash value with the metadata, thereby creating a data control object, performing a cryptographic operation on the data control object, thereby generating cryptographic integrity data, and joining the cryptographic integrity data to the data control object after the cryptographic operation, wherein usage of the content by the recipient is dependent on both a validation of the ECP hash value and a validation of the cryptographic integrity data. Related apparatus and methods are also described. | 2012-05-03 |
| 20120110336 | DATA VERIFICATION METHOD - (EN)An electronic system ( | 2012-05-03 |
| 20120110337 | METHOD AND SYSTEM FOR RESTRICTING EXECUTION OF VIRTUAL APPLICATIONS TO A MANAGED PROCESS ENVIRONMENT - Methods and systems for restricting the launch of virtual application files. In one embodiment, a launching application is signed with a digital signature. When the launching application launches a runtime engine and instructs it to execute an application file, the runtime engine determines whether an entity identifier associated with the launching application identifies an authorized entity. If the entity identifier identifies an authorized entity and the digital signature is valid, the runtime engine executes the application file. In another embodiment, a ticket is transmitted to the launching application along with an instruction to launch the application file. The ticket includes a digital signature and an expiration date. The launching application communicates the ticket to the runtime engine, which will execute the application file only if the digital signature is valid and a current date is not later than the expiration date. | 2012-05-03 |
| 20120110338 | Protecting the Integrity and Privacy of Data with Storage Leases - Storage leases specify access restrictions and time periods, restricting access to their associated data during the storage lease time period. Storage leases may be assigned to individual data storage blocks or groups of data storage blocks in a data storage device. A data storage device may include any arbitrary number of different storage leases assigned to different portions of its data storage blocks. Storage lease-enabled devices may provide security certificates to verify that data access operations have been performed as requested and that their storage leases are being enforced. Storage lease-enabled devices compare storage lease information for data units with the current time using a clock isolated from access by storage clients or time certificates from one or more trusted time servers. Storage leases may be used in combination with backup applications, file systems, database systems, peer-to-peer data storage, and cloud storage systems. | 2012-05-03 |
| 20120110339 | Security Software For Vector File Format Data - Systems and/or methods where a file requires an associated token to be accessed (see DEFINITIONS section) by the software used to access the file and that the token effectively requires that: (i) a particular authorized copy (or subset of authorized copies) of the software is being used to access the file; and (ii) that the authorized software is being run on an authorized hardware set (for example, organizational server computer). In at least some preferred embodiments, the files are specifically vector file format data files (“vffdf's”). In at least some preferred embodiments: (i) the token associated with the file is called a public token; (ii) the authorized software copy includes a private token; (iii) the file is encrypted; and (iv) the public and private tokens must sufficiently correspond in order for the file to be decrypted and thereby accessed. In at least some preferred embodiments, files that have an associated token cannot be accessed unless each licensing condition of a set of licensing (see DEFINITION of “license”) conditions, including at least one licensing condition is met, such that the use of the software on the file bearing the token is considered to be authorized. If the licensing conditions are not all met, then the software may or may not still be allowed to process files that do not bear a token according to the present invention. | 2012-05-03 |
| 20120110340 | SYSTEM, PORTABLE DEVICE AND METHOD FOR DIGITAL AUTHENTICATING, CRYPTING AND SIGNING BY GENERATING SHORT-LIVED CRYPTOKEYS - A system for authentication, encryption and/or signing, as well as corresponding devices and methods, that use temporary but repeatable encryption keys uniquely connected to the user and generated from a unique set of input parameters. The system comprises an input device designed to extract predetermined characteristic values from value input by the user, which value is specific to the user, by means of a given algorithm, which algorithm is designed to remove the natural variation in the characteristic values in order to yield an identical set of characteristic values upon input of the same value, and a device designed to generate at least one user specific encryption key comprising said characteristic values. | 2012-05-03 |
| 20120110341 | Mobile Device Transaction Using Multi-Factor Authentication - The following is a system in which a person may use a Cellular (Mobile) Telephone, a PDA or any other handheld computer to make a purchase. This is an example only. The process may entail any type of transaction which requires authentication, such as any financial transaction, any access control (to account information, etc.), and any physical access scenario such as doubling for a passport or an access key to a restricted area (office, vault, etc.). It may also be used to conduct remote transactions such as those conducted on the Internet (E-Commerce, account access, etc.). In the process, a multi-factor authentication is used. | 2012-05-03 |
| 20120110342 | Methods and Systems for Migrating Content Licenses - A system can comprise a processor and a memory embodying an application. The application can comprise code that causes the processor to identify a client key embedded or hard-coded in the application (i.e., included as part of the code comprising the application). Additional code causes the processor to identify data to be accessed according to an encrypted license accessible through use of a machine key. The application can maintain the machine key in an encrypted state using the client key. The application can include code that causes the processor to determine if an encrypted version of the machine key accessible by the processor can actually be decrypted using the client key. If so, the client key can be used to access the machine key. If not, the processor can request a differently-encrypted version of the machine key from a migration service. | 2012-05-03 |
| 20120110343 | Trustworthy timestamps on data storage devices - Secure timestamps created by a data storage device are described. Metadata timestamp is created for each recorded unit of data (such as a sector) The HDD performs the time-stamping in a secure manner. The timestamp is made secure by performing a secure operation (i.e. one that can only be performed by the HDD) using the data and timestamp. The secure operation uses a secure key that is built-in to the storage device and is not readable outside of the device. In some embodiments the secure operation is encryption using the secure key. In other embodiments the secure operation is a hash code function (such as a Hash-based Message Authentication Code (HMAC) function) that uses the secure key to generate a hash code using at least the recorded data and the timestamp as input. The hash code is then included in the metadata that is recorded for the data unit. | 2012-05-03 |
| 20120110344 | Reporting of Intra-Device Failure Data - Methods and a computing device are disclosed. A computing device may include a managed device having embedded firmware. When a failure occurs with respect to the managed device, drivers within the computing device may collect failure data from a driver stack of the computing device and from the managed device. The computing device may send the collected failure data to one or more second computing devices to be stored and analyzed. The computing device may include a health monitor for periodically collecting telemetry data from the computing device and the managed device. When the health monitor becomes aware of conditions indicative of a possible impending failure, the health monitor may trigger collection of sickness telemetry data from the computing device and the managed device. Collected data from the managed device may be made available to a vendor of the managed device. | 2012-05-03 |
| 20120110345 | METHOD AND SYSTEM FOR SECURING DATA OF A MOBILE COMMUNICATIONS DEVICE - A method and system for securing data of a mobile communications device. The method includes: determining that first application data is data associated with a first server; encrypting the first application data with an encryption key stored in the mobile communications device; storing the encrypted first application data on a memory; receiving a request to access the first application data from an application or a service implemented from the mobile communications device; determining that the application or service is authorized to access the first application data; and in response to said determining, decrypting the first application data with the encryption key. | 2012-05-03 |
| 20120110346 | STORING DATA INTEGRITY INFORMATION UTILIZING DISPERSED STORAGE - A method begins by a processing module generating an integrity check value for each encoded data slice of a set of encoded data slices to produce a set of integrity check values. The method continues with the processing module encoding the set of integrity check values to produce encoded integrity check values. The method continues with the processing module sending the encoded integrity check values for storage in a memory system. | 2012-05-03 |
| 20120110347 | METHOD OF RANDOMLY AND DYNAMICALLY CHECKING CONFIGURATION INTEGRITY OF A GAMING SYSTEM - In a gaming environment, a method of periodically downloading dynamically generated executable modules at random intervals that perform system configuration integrity checks in a secure and verifiable manner is disclosed. The dynamically generated executable module returns the signature to a server from which it was downloaded and deletes itself from the system being checked. The next time such an executable module is downloaded, it will contain a different randomly chosen subset of hashing and encryption algorithms. The server that is performing the system configuration integrity check maintains a database of expected system configurations and performs subset of hashing and encryption algorithms as contained in the dynamically generated executable module. The result returned by the downloaded executable module is compared to that computed locally, and an error condition is raised if they do not match. | 2012-05-03 |
| 20120110348 | Secure Page Tables in Multiprocessor Environments - A system comprises a memory module configured to store signed page table data and a selected processing element coupled to the memory module. The selected processing element is one of a plurality of processing elements, which together comprise a portion of a multiprocessor system. The selected processing element is configured to authenticate page table management code and, based on authenticated page table management code, to sign page table data that is subsequently stored in the memory module, and to verify signed page table data that is read from the memory module. | 2012-05-03 |
| 20120110349 | METHOD FOR OBFUSCATING A COMPUTER PROGRAM - The invention relates to a method for obfuscating a computer program. | 2012-05-03 |
| 20120110350 | POWER SUPPLY GRID SWITCH - Examples relate to a grid switch adapted for use with a power supply, wherein the grid switch selects an operational power grid from first and second power grids if one of power grids has failed, and selects between the first and second grids based on a policy if both the first and second power grids are operational. | 2012-05-03 |
| 20120110351 | POWER MANAGEMENT FOR DIGITAL DEVICES - In a digital device, activity of (or load on) one or more processors, peripherals and memory buses are measured. A power management framework operated in the digital device bases power settings in the digital device on the measured loads, and accordingly issues power management commands to change power consumption states of one or more of the processors, peripherals and memory buses. Some user applications (termed power aware applications) in the digital device provide a number identifying their application type to the power management framework, which thereby determines the resources required by the application. The power management commands issued by the power management framework ensure provision of the corresponding resources to the application, while also targeting minimization of power consumption in the digital device. In an embodiment, the digital device corresponds to a mobile phone. | 2012-05-03 |
| 20120110352 | METHOD AND APPARATUS FOR THERMAL CONTROL OF PROCESSING NODES - An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold. | 2012-05-03 |
| 20120110353 | Debugger Recovery on Exit from Low Power Mode - A device is configured with components to enable debugging of the device's entry into and exit from a low power mode. The device includes: core logic, debug components, and a power management module (PMM). When the device exits a low power mode in which the states of the debug components are lost, the PMM prevents the core logic from resuming processing operations until the debug components have been re-configured to their prior states. The PMM either holds the core logic in reset or alternatively withholds power to the core logic. Reconfiguration of the debug components is initiated by a connected debugger, which can set one or more control and status (CS) register values within the device. The CS register values determine when the PMM prevents the core logic processing from resuming and when the PMM enables core logic processing to resume following the device's return from low power mode. | 2012-05-03 |
| 20120110354 | HOLDER WITH SOLAR MODULE FOR HOLDING PORTABLE ELECTRONIC DEVICES - One embodiment of a holder for holding portable electronic devices includes a main support body being a rectangular rigid plate; a main support member hingedly secured to a rear end of the main support body, the main support member being a rectangular rigid plate and comprising two spaced hinge housings proximate to a top edge distal the main support body; and two parallel support legs hingedly secured to a back of the main support member; and a rectangular solar panel comprising two pivots at two top corners respectively, each pivot pivotably secured to the hinge housing so that an angle of the solar panel with respect to the main support member can be adjusted for orienting toward the sun. | 2012-05-03 |
| 20120110355 | Power Supply Circuit and Power Supply Method - Provided is a power supply circuit capable of suppressing a power supply voltage to be input to an integrated circuit device to low level. A power supply circuit ( | 2012-05-03 |
| 20120110356 | PROVIDING POWER OVER ETHERNET WITHIN A VEHICULAR COMMUNICATION NETWORK - A power distribution system within a vehicle operates to provide power over Ethernet to a plurality of network node modules coupled to a vehicular communication network of the vehicle. | 2012-05-03 |
| 20120110357 | COMMUNICATION APPARATUS, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - A communication apparatus that is capable of communicating with network nodes more properly even when a control unit thereof shifts to a power-saving state. An NIC communicates with the network nodes via a network. The controller communicates with the network nodes via the communication unit. The controller stores node information on a network node that has transmitted data satisfying a predetermined condition, determines whether or not a shift condition for shifting the controller to a power-saving state is satisfied, and notifies the communication unit of the stored node information when it is determined that the shift condition is satisfied. The NIC stores node information notified by the controller, and executes communication processing based on the stored node information when the controller is in the power-saving state. | 2012-05-03 |
| 20120110358 | POWER CONTROL OF SECONDARY COPY STORAGE BASED ON JOURNAL STORAGE USAGE AND ACCUMULATION SPEED RATE - Arrangements having multiple second storage systems which each include a restore control unit for controlling restoration processing, in which a data element in a journal stored in a journal storage area is written into a secondary logical volume, and a storage device control unit for controlling a storage device in the second storage system. The restore control unit is provided with a function for suspending the restoration processing. A first value indicating the usage condition of the journal storage area in the second storage system is obtained, and the restore control unit suspends the restoration processing in accordance with the obtained first value. The storage device control unit then executes power saving on a storage device relating to the secondary logical volume. | 2012-05-03 |
| 20120110359 | AUTOMATICALLY DETERMINING OPERATING PARAMETERS OF A POWER MANAGEMENT DEVICE - Automatically determining operating parameters of a power management device is described. | 2012-05-03 |
| 20120110360 | APPLICATION-SPECIFIC POWER MANAGEMENT - An application-specific power management technique may establish a separate power-down interval for one or more applications based on user interaction with the one or more applications. In some implementations, during use of a particular application, when a management component determines that a period of user inactivity has become greater than or equal to the particular power-down interval established for the particular application, the management component may initiate a power down of one or more components, such as a display. | 2012-05-03 |
| 20120110361 | Device For Controlling The Power Supply Of A Computer - The invention relates to a device for controlling a computer ( | 2012-05-03 |
| 20120110362 | APPARATUS THAT PREVENT A MALFUNCTION OF THE CIRCUIT AND REDUCE POWER CONSUMPTION - An interface circuit provided with a first input/output unit and a second input/output unit which respectively access external apparatuses to which electric power is supplied from power sources via different electric power supply lines includes an acquisition unit configured to acquire information whether electric power is supplied to the respective external apparatuses based on a command from the outside; a selection circuit configured to select an input/output unit corresponding to an external apparatus to which electric power is supplied, from the first input/output unit and the second input/output unit based on the information acquired by the acquisition unit; and a control circuit configured to output an instruction corresponding to the command, to the external apparatus to which electric power is supplied, via the input/output unit selected by the selection circuit. | 2012-05-03 |
| 20120110363 | METHOD AND SYSTEM FOR POWER-EFFICIENT AND NON-SIGNAL-DEGRADING VOLTAGE REGULATION IN MEMORY SUBSYSTEMS - Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate. | 2012-05-03 |
| 20120110364 | APPARATUS AND METHOD FOR DECOUPLING ASYNCHRONOUS CLOCK DOMAINS - A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent read and write to counters so that write signals from the fast clock domain can be directly used in the slower clock domain when the counters are not toggling. This feature removes the need for sampling and holding the data on the fast clock, which would require consume additional power and require additional circuit area. | 2012-05-03 |
| 20120110365 | METHOD FOR LOCKING FREQUENCY OF USB DEVICE AND USB FREQUENCY LOCKING DEVICE - A method for locking the frequency of a USB device includes the following steps. Receive a USB data signal and generate multiple reference clock signals. Compare the frequency of the reference clock signals with a bit rate of the USB data signal to generate a control signal. Adjust the operating frequency of an output clock of the USB device according to the control signal. | 2012-05-03 |
| 20120110366 | CLOCK CONTROL DEVICE, CLOCK CONTROL METHOD, CLOCK CONTROL PROGRAM AND INTEGRATED CIRCUIT - An instruction detecting section ( | 2012-05-03 |
| 20120110367 | Architecture and Method for Eliminating Store Buffers in a DSP/Processor with Multiple Memory Accesses - A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions. | 2012-05-03 |
| 20120110368 | DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA - Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal. | 2012-05-03 |
| 20120110369 | Data Recovery in a Cross Domain Environment - A method for recovering data when corrupted data from a source is detected includes identifying data corrupted as a result of using the corrupted data by tracing propagation of the corrupted data to provide identified corrupted data, and repairing the identified corrupted data to provide repaired data. The propagation of the corrupted data is traced from one domain to another. Data in both domains is repaired. A wrapper is provided for the source. Calls into and out of the source are intercepted by the wrapper. Calls of a plurality of different domains are intercepted by the wrapper. A wrapper is provided for a process. External service calls of the process are intercepted by the wrapper. The wrapper recreates a process flow followed by the process in accordance with the corrupted data. A wrapper is provided for a database. Accesses of the database are intercepted by the wrapper. | 2012-05-03 |
| 20120110370 | HIGHLY AVAILABLE FILE SYSTEM IN A DIRECTLY ATTACHED STORAGE - A method and system to provide a highly available file system in a directly attached storage (DAS). The storage is directly attached to a computer system that has an inactive operating system. A hardware module in the computer system receives a network command to access the file system. The hardware module determines a physical location of data blocks to be accessed in the storage. According to the network command, the hardware module accesses the data blocks in the storage. | 2012-05-03 |
| 20120110371 | SELF-RESTARTING NETWORK DEVICES - A method and apparatus for self-monitoring to identify an occurrence of a threshold and rebooting in response to the occurrence of the threshold is provided. In an embodiment, a data processing apparatus comprises one or more processors; logic coupled to the one or more processors and comprising one or more stored sequences of instructions which, when executed by one or more processors, cause the one or more processors to obtain a threshold associated with the apparatus; self-monitor the apparatus to identify an occurrence of the threshold; and self-reboot the apparatus responsive to the occurrence of the threshold. | 2012-05-03 |
| 20120110372 | RELIABLE MESSAGING USING REDUNDANT MESSAGE STREAMS IN A HIGH SPEED, LOW LATENCY DATA COMMUNICATIONS ENVIRONMENT - A method includes receiving active application messages that are part of an active message stream in a subscribing client device from an active feed adapter. Each active application message is characterized by an active source stream identifier, an active source stream sequence number, and an active message sequence number. The method includes receiving, in response to a failover from the active feed adapter to a backup feed adapter, backup application messages in the subscribing client device from the backup feed adapter. Each backup application message is characterized by a backup source stream identifier, a backup source stream sequence number, and a backup message sequence number. The method includes administering, by the subscribing client device, the backup application messages in dependence upon the active stream source identifier, the active stream source sequence number, the backup stream source identifier, and the backup stream source sequence number. | 2012-05-03 |
| 20120110373 | COMMUNICATION NETWORK AND METHOD FOR SAFETY-RELATED COMMUNICATION IN TUNNEL AND MINING STRUCTURES - A communication network in an underground system comprises a ring network computers which is connected to an aboveground central system computer unit, each computer having an overview of the overall structure of the ring network and an allocated network status. Plural network computers are configured to, in the event of a connection interruption between networked nodes, seek an alternative communication path in order to maintain the communications. Plural network computers are coupled to at least one sensor in order to pick up information relating to the environment and are configured to pass it on to other network computers of the ring network and/or to the aboveground central system. In normal operation, the network computers pass on current information relating to the environment to the aboveground central system and to other network computers. In a network island arising as a result of one or more connection interruptions, the network status of a multiplicity of the network computers changes from normal operation to emergency operation. | 2012-05-03 |
| 20120110374 | Methods and Systems for Measuring I/O Signals - Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal. | 2012-05-03 |
| 20120110375 | MACRO AND COMMAND EXECUTION FROM MEMORY ARRAY - Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation. | 2012-05-03 |
| 20120110376 | Systems and Methods for Managing End of Life in a Solid State Drive - Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block. | 2012-05-03 |
| 20120110377 | PERFORMING DATA WRITES IN PARITY PROTECTED REDUNDANT STORAGE ARRAYS - A first and a second physical disk identifier, a physical Logical Block Address (LBA), a data length, and a span identifier are calculated from a data write operation. A first request command frame is created for retrieving the existing data block from the storage array, the first request command frame including at least one of the calculated parameters. At least one second request command frame is created for retrieving the at least one existing parity data block from the storage array, the at least one second request command frame including the calculated at least one second physical disk identifier and at least one of the calculated parameters. At least one new parity data block is calculated utilizing the existing data block, the new data block, and the at least one existing parity data block. | 2012-05-03 |
| 20120110378 | FIRMWARE RECOVERY SYSTEM AND METHOD OF BASEBOARD MANAGEMENT CONTROLLER OF COMPUTING DEVICE - A firmware recovery method of a baseboard management controller (BMC) of a computing device detects whether a firmware of a default firmware memory of the BMC is damaged by sending a detection command to the BMC at a regular interval. When the firmware of the default firmware memory of the BMC is damaged, the method recovers the firmware according to firmware data of a backup firmware memory of the BMC. | 2012-05-03 |
| 20120110379 | FIRMWARE RECOVERY SYSTEM AND METHOD - A firmware recovery system includes a baseboard management controller (BMC) module, a south bridge, a basic input and output system (BIOS) module, a multiplexer and a storage module. The BIOS module is connected to the BMC module by the south bridge and determines whether a firmware file of the BMC module is corrupt. The multiplexer selectively connects the BIOS module or the BMC module to the south bridge. The storage module stores a new firmware file. When the firmware file of the BMC module is corrupt, the BIOS module controls the multiplexer to select the BMC module to connect to the south bridge. The BIOS module reads the new firmware file from the storage module to recover the corrupt firmware file from the BMC module. | 2012-05-03 |
| 20120110380 | INFORMATION HANDLING SYSTEM FORCED ACTION COMMUNICATED OVER AN OPTICAL INTERFACE - A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal. | 2012-05-03 |
| 20120110381 | INFORMATION HANDLING SYSTEM FORCED ACTION COMMUNICATED OVER AN OPTICAL INTERFACE - A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal. | 2012-05-03 |
| 20120110382 | COMPUTING DEVICE AND METHOD FOR MANAGING MOTHERBOARD TEST - A system and method for managing a test of a motherboard can create a first test data consisting of test items. In the first test data, one or more selected test items to perform can be identified. A second test data is obtained by performing a logical NOR operation on the test bits corresponding to the selected test items. After performing the test items, a third test data is created by setting the test bits corresponding to the selected test items that pass the test to the test bits of the selected test items in the first test data, and by setting the test bits corresponding to the selected test items that fail the test to the test bits of the test items that have not been selected in the first test data. By comparing the third with the test data, a test result of the motherboard is obtained. | 2012-05-03 |
| 20120110383 | Method and apparatus for off-line analyzing crashed programs - In a method for off-line analyzing crashed programs, a simulator of a debugger is made to enter into a running state, and set breakpoints in the running state. Register and memory signals are separated from a dump signal outputted by a platform during crash. The debugger is used to replace, at the breakpoints, register and memory signals of the simulator originally in the running state with the register and memory signals separated from the dump signal. A debugging signal in the running state is replaced with a debugging signal during crash. The debugger is used to analyze reasons of crash based on the debugging, register, and memory signals after replacement. By separating the register and memory signals from the dump signals outputted by the platform during crash without involving any OS signal, there is no need to modify the platform and the GDB debugger when analyzing the reasons of crash. | 2012-05-03 |
| 20120110384 | Source Identification of Compliance Errors in a Web Page with Custom Widgets - A mechanism is provided to automate the mapping so that custom widgets that cause compliance errors in the Web page can be identified automatically. The mechanism dynamically creates and inserts debug directives into the HTML code generated from a custom widget in a Web page so that a compliance error found in the generated code can be traced back to the custom widget that caused the error. | 2012-05-03 |
| 20120110385 | MULTIPLE FUNCTIONALITY IN A VIRTUAL STORAGE AREA NETWORK DEVICE - In one aspect of the present description, a connection between a predetermined input port and a predetermined output port is created in a partition of a VSAN switch, in which the connection is a destination address independent physical layer connection conforming to the physical layer of a communication protocol. Another connection between a plurality of input ports and a plurality of output ports may be created in another partition of the VSAN switch, in which the connection is a multi-layer connection which includes a network layer connection conforming to the network layer of the communication protocol. Other features and aspects may be realized, depending upon the particular application. | 2012-05-03 |
| 20120110386 | AUTOMATED EMERGENCY POWER SUPPLY TEST USING VARIABLE LOAD BANK STAGES - An automated emergency power supply system (EPSS) and testing solution that records generator load values and engine exhaust temperature values to evaluate whether an EPSS test satisfies legislated test criteria. The EPSS test is carried out under software control, which initiates a test by instructing an automatic transfer switch (ATS) to change its status to a test status, causing the essential loads to be powered by a generator instead of a main utility power source. Power monitors record the ATS and generator status during the test as well as electrical parameter data from the ATS and generator and exhaust temperature data and other engine parameter data from the generator. When the test is concluded, the ATS is instructed to return the status to normal so that power delivery is resumed from the main power source. The electrical and engine parameter data is analyzed and compared against legislated test criteria to determine a pass/fail result of the EPSS test. | 2012-05-03 |
| 20120110387 | TRACE SYNCHRONIZATION - A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. A controller is coupled to the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator. In this way, the downstream behavior of the data processing apparatus can be made to influence the rate and timing of insertion of synchronization markers into a trace data stream. | 2012-05-03 |
| 20120110388 | Watch-Dog Timer with Support for Multiple Masters - A time-out period is established for a watchdog timer. The time-out period is restarted each time a designated key value is received when each key value is received in a proper sequence. An error is indicated if set of key values is received in an incorrect sequence. A time-out is indicated if a correct sequence of key values is not received within the time-out period. | 2012-05-03 |
| 20120110389 | METHOD FOR OBTAINING STORAGE DEVICE STATE SIGNAL BY USING BMC - A method for obtaining a storage device state signal by using a Baseboard Management Controller (BMC) includes defining a sensor monitored by the BMC, in which the value of the sensor indicates the state of a storage device; converting the storage device state signal generated by a storage device controller into an electric signal by using a hardware coding method; and reading the electric signal and appointing the read value of the electric signal as the value of the sensor. | 2012-05-03 |
| 20120110390 | UPDATING A SET OF MEMORY DEVICES IN A DISPERSED STORAGE NETWORK - A method begins by a processing module determining a memory usability indication for a set of memory devices, wherein the set of memory devices stores data as first dispersed storage error coded data using first dispersed storage error coding parameters. The method continues with the processing module comparing the memory usability indication to a memory usability level threshold. The method continues with the processing module adding one or more memory devices to the set of memory devices to produce an updated set of memory devices when the memory usability indication compares unfavorably to the memory usability level threshold. The method continues with the processing module storing the data as second dispersed storage error coded data using second dispersed storage error coding parameters in the updated set of memory devices. | 2012-05-03 |
| 20120110391 | SYSTEM AND METHOD FOR DETERMINING FAULT DIAGNOSABILITY OF A HEALTH MONITORING SYSTEM - Methods and apparatus are provided for determining the fault diagnosability of a health monitoring software application for a complex system. The method includes extracting data from the software application containing a relationship between one or more failure modes of the complex system and one or more evidence items of the complex system, the a priori probabilities of each failure mode occurring, and the a priori probability of each evidence item occurring. The method also includes creating one or more matrices relating the one or more FMs to the one or more evidence items. The method further includes analyzing the one or more matrices and the a priori probabilities to determine the diagnosability of each FM. | 2012-05-03 |
| 20120110392 | MISALIGNMENT PREDICTOR - In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory. | 2012-05-03 |
| 20120110393 | METHOD AND APPARATUS PROVIDING FAILOVER FOR A POINT TO POINT TUNNEL FOR WIRELESS LOCAL AREA NETWORK SPLIT-PLANE ENVIRONMENTS - A method, apparatus and computer program product for providing failover for a point to point tunnel for wireless local area network split-plane environments is presented. A second network switch learns first data associated with a third network switch and the second network switch terminates a tunnel. The third network switch learns second data associated with the second network switch. The first and second data are synchronized between the second network switch and the third network switch. The second network switch and the third network switch load sharing tunnel data packets. The third network switch forwards tunnel control packets received by the third network switch to the second network switch. A failure relating to the second network switch is detected and a new tunnel is established with the third network switch. | 2012-05-03 |
| 20120110394 | SELF-UPDATING NODE CONTROLLER FOR AN ENDPOINT IN A CLOUD COMPUTING ENVIRONMENT - Embodiments of the present invention provide a self-updating node controller (e.g., for an endpoint/node such as a cloud node). In general, the node controller will autonomously and automatically obtain program code (e.g., scripts) from a central repository. Among other things, the program code enables the node controller to: receive a request message from a cloud node queue associated with the endpoint; process a request corresponding to the request message; automatically update the program code as needed (e.g., when requests cannot be processed/fulfilled); place a state message indicating a state of fulfillment of the request in a cloud manager queue associated with a cloud manager from which the request message was received; update an audit database to reflect the state of fulfillment; and/or place a failure message in a triage queue if the request cannot be processed by the node controller. | 2012-05-03 |
| 20120110395 | MESSAGE COMPOSITION MANAGEMENT FOR FATIGUED COMPOSERS - Embodiments of the present invention provide a method, system and computer program product for message composition management for fatigued composers of electronic messages. In an embodiment of the invention, a method for message composition management for fatigued composers of electronic messages includes detecting a request by a message composer to transmit a message to a designated recipient in a messaging client executing in memory of a computer. The method also includes computing a fatigue quotient for the message composer. Finally the method includes diverting the message to a drafts folder instead of transmitting the message if the fatigue quotient exceeds a threshold value. | 2012-05-03 |
| 20120110396 | Error handling mechanism for a tag memory within coherency control circuitry - A data processing system | 2012-05-03 |
| 20120110397 | DATA TRANSMISSION SYSTEM, STORAGE MEDIUM AND DATA TRANSMISSION PROGRAM - A system has a processor configured to be capable of read and write to a main memory, a storage configured to transmit stored data per block on an I/O bus, and a protocol processing apparatus connected to the I/O bus and configured to perform a communication protocol process on behalf of the processor. The processor includes a specifying part configured to specify data per block to be transmitted from the storage, and an indicating part configured to indicate data transfer from the storage to the protocol processing apparatus by specifying address information of the protocol processing apparatus. The protocol processing apparatus includes a receiving part configured to directly receive data transferred per block from the storage to the I/O bus, without relaying the main memory, and a network processing part configured to transmit the data received per block by the receiving part over a network per packet. | 2012-05-03 |
| 20120110398 | DATA ERROR CHECK CIRCUIT, DATA ERROR CHECK METHOD, DATA TRANSMISSION METHOD USING DATA ERROR CHECK FUNCTION, SEMICONDUCTOR MEMORY APPARATUS AND MEMORY SYSTEM USING DATA ERROR CHECK FUNCTION - Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input/output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read/write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups. | 2012-05-03 |
| 20120110399 | ERROR SCANNING IN FLASH MEMORY - Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed. | 2012-05-03 |
| 20120110400 | Method and Apparatus for Performing Memory Interface Calibration - A universal memory interface on an integrated circuit includes an external memory interface unit operable to perform data rate conversion for a data signal between a first rate associated with the integrated circuit and a second rate associated with a memory system. The universal memory interface also includes a sequencer unit operable to calibrate at least one of a delay for the data signal and a delay for a strobe for the data signal by executing a calibration procedure instruction. | 2012-05-03 |
| 20120110401 | SYSTEM AND METHOD OF SENSING DATA IN A SEMICONDUCTOR DEVICE - A semiconductor memory apparatus includes: a first data counting unit configured to count respective programming levels of a plurality of input data and output a plurality of first data counting codes having a code value corresponding to the number of respective programming levels; a data read unit configured to sense data stored in a memory block having the plurality of input data programmed therein, based on a voltage level of a plurality of read bias signals, and output the sensed result as a plurality of output data; a second data counting unit configured to count respective programming levels of the plurality of output data and output a plurality of second data counting codes having a code value corresponding to the number of respective programming levels; a read bias control unit configured to compare the plurality of first data counting codes with the plurality of second data counting codes and output a bias control code having a code value corresponding to the comparison result; and a read bias generating unit configured to generate the plurality of read bias signals whose voltage levels are adjusted based on the code value of the bias control code. | 2012-05-03 |
| 20120110402 | METHOD AND APPARATUS FOR TESTING 3D INTEGRATED CIRCUITS - A method and apparatus for testing a scan-based 3D integrated circuit (3DIC) using time-division demultiplexing/multiplexing allowing for high-data-rate scan patterns applied at input/output pads converting into low-data-rate scan patterns applied to each embeddded module in the 3DIC. A set of 3D design guidelines is proposed to reduce the number of test times and the number of through-silicon vias (TSVs) required for both pre-bond testing and post-bond testing. The technique allows reuse of scan patterns developed for pre-bond testing of each die (layer) for post-bond testing of the whole 3DIC. It further reduces test application time without concerns for I/O pad count limit and risks for fault coverage loss. | 2012-05-03 |
| 20120110403 | Error Correction Scheme for Facsimile Over a Packet Switched Network - A method for correcting at least one error in a facsimile transmission over a packet switched communications network includes the steps of: detecting, by a first gateway coupled to the communications network, at least one missing data packet in a sequence of data packets transmitted from a second gateway coupled to the communications network during the facsimile transmission; transmitting, from the first gateway, a request for retransmission of the missing data packet to the second gateway; determining whether the missing data packet is available for retransmission; and, when the missing data packet is available, retransmitting the missing data packet to the first gateway. | 2012-05-03 |
| 20120110404 | METHOD AND APPARATUS FOR PERFORMING NON REAL TIME SERVICE IN DIGITAL BROADCAST SYSTEM - Disclosed herein is a non real-time broadcast receiving system. The system includes: a non real-time service decoder dividing received non real-time service content into a transmission block according to a protocol; a service content manager monitoring whether the receive of the non real-time service content stops and acknowledging a schedule regarding whether a portion with errors in the non real-time service content is retransmitted; a memory storing a portion without errors in the non real-time service content; a file checker checking whether errors are produced during the receive of the non real-time service contents and determining whether the portion with errors in the non real-time service content is retransmitted; a retransmission request signal generator generating a retransmission request signal; a return channel transmitter transmitting the retransmission request signal; and a return channel receiver receiving data corresponding the portion with error. | 2012-05-03 |
| 20120110405 | COMMUNICATION DEVICE - According to one exemplary embodiment, a communication device includes: a receiver which receives a frame including data, a first error detection code for detecting an error of the data, a sequence number of the data, and a second error detection code for detecting an error of the sequence number; a first detector which detects the error of the data using the first error detection code; a second detector which detects the error of the sequence number using the second error detection code; a generator which generates an acknowledgement frame having maximum sequence number information regarding a maximum sequence number in a frame for which the error of the sequence number is not detected, and acknowledgement information representing whether there is an error for data in each frame of which the sequence number being equal to or less than the maximum sequence number; and a transmitter which transmits the acknowledgement frame. | 2012-05-03 |
| 20120110406 | RATE MATCHING METHOD AND DEVICE - The present invention discloses a rate matching method and device. The method includes that: an information bit sequence is coded and interleaved to obtain a mother code codeword with a length N | 2012-05-03 |
| 20120110407 | DECODING DEVICE AND METHOD, AND PROGRAM - Disclosed herein is a decoding device including: an extracting section, a storing section, an allocating section, and a decoding section. The extracting section acquires data containing plural code words and information other than the plural code words in one frame, and extracts the plural code words from the data every one code word. The storing section at least stores the one code word extracted by the extracting section. The allocating section sets time obtained by dividing time for the one frame by the number of code words contained in the one frame as time allocated to decoding of one code word. The decoding section decodes the code word within the time allocated by the allocating section. | 2012-05-03 |
| 20120110408 | LOW COMPLEXITY DECODING OF LOW DENSITY PARITY CHECK CODES - An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes. | 2012-05-03 |
| 20120110409 | ERROR-CORRECTING ENCODING METHOD WITH TOTAL PARITY BITS, AND METHOD FOR DETECTING MULTIPLE ERRORS - An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H·V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k>k1>2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method. | 2012-05-03 |
| 20120110410 | METHODS AND SYSTEMS FOR ENCODING AND DECODING IN TRELLIS CODED MODULATION SYSTEMS - Systems and methods for encoding and decoding for communications or storage systems utilizing coded modulation are provided. A first portion of data is encoded with a first at least one encoding scheme. A second portion of the data id encoded with a second encoding scheme. A coset is selected from a plurality of cosets based at least in part on the encoded first portion of the data, where the plurality of cosets corresponds to a partition of a signal constellation. A signal vector is selected within the selected coset based at least in part on the encoded second portion of the data. | 2012-05-03 |
| 20120110411 | Content Addressable Memory (CAM) Parity And Error Correction Code (ECC) Protection - A memory system including a content addressable memory (CAM) array and a non-CAM array. The non-CAM array, which may share word lines with the CAM array, stores one or more error detection bits associated with each row of the CAM array. A state machine reads entries of the CAM array and corresponding error detection bits of the non-CAM array during idle cycles of the CAM array. Error detection logic identifies errors in the entries read from CAM array (using the retrieved error detection bits). If these errors are correctable, the error detection logic corrects the entry, and writes the corrected entry back to the CAM array (an updated set of error detection bits are also written to the non-CAM array). If these errors are not correctable, an interrupt is generated, which causes correct data to be retrieved from a shadow copy of the CAM array. | 2012-05-03 |
| 20120110412 | DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN DIGITAL BROADCASTING SYSTEM - A digital broadcasting system and a method for controlling the same are disclosed. A method for controlling a digital broadcast receiving system includes the steps of receiving a broadcast signal having mobile service data and main service data multiplexed therein, extracting transmission parameter channel (TPC) signaling information and fast information channel (FIC) signaling information from a data group within the received mobile service data, by using the extracted fast information channel (FIC) signaling information, acquiring a program table describing virtual channel information and service of an ensemble, the ensemble being a virtual channel group of the received mobile service data, by using the acquired program table, detecting a descriptor defining basic information required for accessing the received service, and, by using the detected descriptor, controlling the receiving system to enable access to the corresponding service. | 2012-05-03 |
| 20120110413 | METHOD FOR CODING AND DECODING DIGITAL DATA, PARTICULARLY DATA PROCESSED IN A MICROPROCESSOR UNIT - The invention relates to a method for encoding digital data, in particular of data processed in a microprocessor unit. In the method according to the invention for a respective data word (A, B, C) of a series of data words to be encoded subsequently a parity code (P(A), P(B), P(C)) is computed on the basis of the data of the respective data word (A, B, C). Further the respective data word (A, B, C) is altered with the aid of the data word (A, B, C) preceding it in the series, wherein the altered data word (Aa, Ba, Ca) and the parity code (P(A), P(B), P(C)) represent the encoded data word (Ac, Bc, Cc) and the encoded data word (Ac, Bc, Cc) can be decoded with the aid of the data word (A, B, C) preceding it in the series. | 2012-05-03 |
| 20120110414 | Memory-Module Controller, Memory Controller and Corresponding Memory Arrangement, and Also Method for Error Correction - A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module. | 2012-05-03 |
| 20120110415 | DECODING APPARATUS, METHOD, AND PROGRAM - The present disclosure provides a decoding apparatus including, a storage section configured to store a reception value, a detection section configured to detect an error in the reception value, an error correction section configured to correct an error detected by the detection section with respect to the reception value, and a control section configured to control reading of the reception value from the storage section, wherein the control section controls first reading such that the reception value is read into the detection section and, after detection of an error by the detection section, second reading such that substantially the same reception value as that in the first reading is read into the error correction section. | 2012-05-03 |
| 20120110416 | DATA STORAGE APPARATUS WITH ENCODER AND DECODER - According to one embodiment, an encoder/decoder apparatus includes an encoder module, a decoder module, and a transposing module. The encoder module is configured to generate a Hamming code from the input data, in accordance with a check matrix having a specific regularity. The decoder module is configured to detect an error position in the output data composed of the Hamming code, in accordance with the check matrix. The transposing module is configured to perform a transposing process of transposing some of the columns of the check matrix, while maintaining the regularity of the check matrix, and to change the error position in accordance with the transposing process, during the decoding process. | 2012-05-03 |
| 20120110417 | HYBRID ERROR CORRECTION CODING TO ADDRESS UNCORRECTABLE ERRORS - A method in a memory device includes receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. An ECC operation is initiated to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data, a first sub-block ECC operation is initiated to process the first sub-block of data using the first ECC data. | 2012-05-03 |
| 20120110418 | Advanced Data Encoding With Reduced Erasure Count For Solid State Drives - Technologies are generally described herein for encoding a message. Technologies are also generally described herein for decoding an encoded message. The message may be encoded and/or decoded according to a mapping rule. The mapping rule may enable multiple messages to be successively written to the same block in a solid state drive without an erasure operation. | 2012-05-03 |
| 20120110419 | Data Structure for Flash Memory and Data Reading/Writing Method Thereof - A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively. | 2012-05-03 |
| 20120110420 | UNIVERSAL PACKET LOSS RECOVERY FOR DELIVERY OF REAL-TIME STREAMING MULTIMEDIA CONTENT OVER PACKET-SWITCHED NETWORKS - The Universal Packet Loss Recovery System (UPLRS) is capable of recovering end-to-end network packet losses to obtain reliable end-to-end network delivery of multimedia streaming content over IP networks where packet losses appear above the transport layer. The UPLRS incorporates the use of Packet Forward Error Correction Coding (FEC) with packet interleaving processing prior to transport. Packet FEC is an error correction coding method at the packet level to improve link transmission reliability. At the source end of the packet-switching network, the Packet FEC scheme encodes a stream of transport multimedia content packets by including redundant packets in the stream to allow for the recovery of lost packets by the Packet FEC decoder at the user end of the packet-switching network. Since lost packets appear only above the transport layer in the IP network protocol stack, Packet FEC can be viewed as a transport layer or an application layer coding method. | 2012-05-03 |
| 20120110421 | TECHNIQUES TO PERFORM FORWARD ERROR CORRECTION FOR AN ELECTRICAL BACKPLANE - Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed | 2012-05-03 |
| 20120110422 | TRANSMISSION DEVICE - A transmission device in a communication system where a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deletion of the dummy bits from the results of the systematic encoding is transmitted. The transmission device inserts dummy bits into information bits based on an interleaving pattern of an interleaving portion in a turbo encoder; performs systematic encoding of the information bits into which the dummy bits are inserted, and then deletes the dummy bits from the results of the systematic encoding to generate a systematic code; and transmits the systematic code. By considering the interleaving pattern, original bit positions, which, after interleaving, exists within the ranges of stipulated numbers of bits at the beginning and at the end, are determined in advance, and the dummy bit insertion portion executes control so as not to insert dummy bits into the original bit positions. | 2012-05-03 |
| 20120110423 | COMMAND CONTROL CIRCUIT, INTEGRATED CIRCUIT HAVING THE SAME, AND COMMAND CONTROL METHOD - A command control circuit includes a command decoder configured to decode a command and generate an internal command, an error check unit configured to detect an error in the command and an address by using check data and generate an error check signal in response to the detection, and a blocking unit configured to block or pass the internal command in response to first and second states of the error check signal. | 2012-05-03 |
