| 18th week of 2012 patent applcation highlights part 77 |
| Patent application number | Title | Published |
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| 20120110224 | DATA PROCESSING APPARATUS AND IMAGE PROCESSING APPARATUS - A data processing apparatus may include a buffer unit, a data write control unit, a data read control unit, and a buffer area determination unit. The data write control unit may write the input data to the storage area determined by the buffer area determination unit, and output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may read the data from the storage area determined by the buffer area determination unit, and output a data read completion signal indicating that the reading of the data is completed when the output of the output data generated based on the read data is completed. | 2012-05-03 |
| 20120110225 | Method and communication system for determining the time of an event in an IO device - A method and communication system that provide an inexpensive approach that enables the times of events that are detected in IO device to be determined in a higher-level controller. The higher-level controller has a system clock and is connected to an IO link device to which multiple first IO devices are able to be connected. In addition, a second IO device is connected to the IO link device. The clock of the second IO device is synchronized by a synchronization device with the system clock of the higher-level controller. The status data that are provided by at least one of the first IO devices and the current time data that the second IO device supplies are transmitted simultaneously to the IO link device. The IO link device assigns the status data received to the received current time data, then transmits these data to the higher-level controller. | 2012-05-03 |
| 20120110226 | MEDICAL DATA COLLECTION APPARATUS - A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit. | 2012-05-03 |
| 20120110227 | Device for transmitting data between a serial data bus and working modules such as actuator modules and/or I/O modules - The invention concerns a device for transmitting data between a serial data bus and working modules, wherein the data bus is connected to a bus node in a bus module having at least two serial communication ports which are connected to ports of a hub connected to or integrated with the bus node, wherein the communication ports are designed for the connection and for the power supply of the working modules and wherein at least one of the working modules is designed as an actuator and/or I/O module comprising a serial-to-parallel converter for the parallel connection of actuators and/or I/O interfaces provided on or connected to the respective working module. | 2012-05-03 |
| 20120110228 | Medical Data Collection Apparatus - A physiological data collection device obtains physiological data from a subject interface on a subject. The physiological data collection device includes a data connector such as a USB connector for connecting directly to a computer. When the physiological data collection device is connected to the computer, the physiological data is uploaded to a remote data processing center for computer-based analysis and review by a medical professional. A report can be provided to the subject based on the analysis and review. When the subject interface is physically connected to the physiological data collection device, the data connector is prevented from being connected to an external device such as the computer. | 2012-05-03 |
| 20120110229 | SELECTIVE SWITCHING OF A MEMORY BUS - A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate. | 2012-05-03 |
| 20120110230 | DEVICE FOR ARBITRATING BUS ACCESSES AND METHOD FOR CONTROLLING SAME - In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits at least one of the bus-access requests of the plurality of submodules to the first arbiter. | 2012-05-03 |
| 20120110231 | HOME STORAGE SYSTEM - In general, embodiments of the present invention provide a home storage system and method of production. Specifically, in a typical embodiment, the home storage system includes a main controller that is coupled to a display controller, an external memory controller, an external interface, and a PCI-Express-based hybrid RAID controller. Further, a set of semiconductor storage device (SSD) memory units and a set of hard disk drive (HDD/Flash) memory units are coupled to the hybrid RAID controller. The external interface allows the storage system to establish network connectivity, while the external memory controller allows the storage device to be coupled to different types of external memory devices. | 2012-05-03 |
| 20120110232 | MULTI-DESTINATION DIRECT MEMORY ACCESS TRANSFER - An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location. | 2012-05-03 |
| 20120110233 | I/O SYSTEM, DOWNSTREAM PCI EXPRESS BRIDGE, INTERFACE SHARING METHOD, AND PROGRAM - Fault tolerance is improved, a functional limitation at the time of start-up of an I/O system is avoided, and a start-up time is shortened. A downstream PCI Express bridge sets a PCI Express device connected to the downstream PCI Express bridge itself, among a plurality of single root-compatible PCI Express devices shared by a plurality of root complexes connected to a plurality of upstream PCI Express bridges that exchange data with the downstream PC Express bridge itself through a network, controls and monitors a state of a physical link with the PCI Express device connected to the downstream PCI Express bridge itself, and performs monitoring and notification of an error of the PCI Express device connected to the downstream PCI Express bridge itself. | 2012-05-03 |
| 20120110234 | MULTI-PROTOCOL BUS INTERFACE DEVICE - A bus interface device is configured to receive data from one or more devices via a bus. The bus interface device is also configured to process first data received via the bus according to a transport protocol of the bus. The bus interface device is further configured to process second data received via the bus according to a native coding/decoding (CODEC) protocol that is distinct from the transport protocol. | 2012-05-03 |
| 20120110235 | WIRE CONTROL DEVICE AND ELECTRONIC DEVICE USING THE SAME - A wire control device for wired remotely controlling an electronic device. The wire control device includes a USB connector and a control switch, and the control switch generates control signals. The electronic device includes a USB port and a process unit. When the USB port is connected to the USB connector of the wire control device, the process unit receives the control signals via the USB port and executes corresponding functions. | 2012-05-03 |
| 20120110236 | System and Method to Prioritize Large Memory Page Allocation in Virtualized Systems - The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization. | 2012-05-03 |
| 20120110237 | METHOD, APPARATUS, AND SYSTEM FOR ONLINE MIGRATING FROM PHYSICAL MACHINE TO VIRTUAL MACHINE - A method, an apparatus, and a system for online migrating from a physical machine to a virtual machine are provided. The method including: after a target virtual machine is created, started, and suspended by a virtualization platform VMM Host, initially synchronizing data of a memory page from a source physical machine to the target virtual machine at a second time point; monitoring the operation of updating the memory page since the second time point; incrementally synchronizing data of the updated memory page in the source physical machine to the target virtual machine, and stopping monitoring when an increment value of the updated memory page in the source physical machine is less than a first threshold; and calling the virtualization platform VMM Host to resume the target virtual machine to a running state. The effect of smoothly switching services from the source physical machine to the target virtual machine is achieved. | 2012-05-03 |
| 20120110238 | DATA SECURITY IN SOLID STATE MEMORY - The invention concerns data security in solid state memory. The solid state memory contains at least one specific area directed to storing sensitive information. The invention is for handling security relevant data in solid state memories and to protect the data from unauthorized access. According to the invention, the solid state memory includes a security element for deleting the specific memory area at start up. | 2012-05-03 |
| 20120110239 | Causing Related Data to be Written Together to Non-Volatile, Solid State Memory - A first write request that is associated with a first logical address is received via a collection of write requests targeted to a non-volatile, solid state memory. It is determined whether the logical address is related to logical addresses of one or more other write requests of the collection that are not proximately ordered with the first write request in the collection. In response to this determination, the first write request and the one or more other write requests are written together to the memory. | 2012-05-03 |
| 20120110240 | Method and System for Memory Controller Calibration - A method for calibration of a memory controller may include determining if an unused memory location exists in memory. The method may include writing a first pattern to the unused memory location in response to a determination that the unused memory location exists. The method may include determining if a second pattern exists in the memory in response to a determination that the unused memory location does not exist. The method may include iteratively modifying a first delay of a first delay control module among a plurality of delay values. The method may include reading from a memory location including the first pattern or the second pattern for each iteration of modification of the first delay. The method may include modifying one or more second delays, each second delay associated with one of one or more second delay control modules, based on the results of reading from the memory location. | 2012-05-03 |
| 20120110241 | SYSTEM FOR NAND FLASH PARAMETER AUTO-DETECTION - A system comprising a NAND flash memory device having a multiplicity of parameters; a flash controller configured to perform a NAND flash memory parameter automatic detection process including reading a device identifier of the NAND flash memory device and proceeding if a valid device identifier value is returned, detecting an address cycle and a block type of the NAND flash memory device, detecting a page size of the NAND flash memory device, detecting a spare size of the NAND flash memory device, detecting a memory size of the NAND flash memory device, and detecting a block size of the NAND flash memory device. | 2012-05-03 |
| 20120110242 | PROGRAMMABLE MEMORY CONTROLLER - A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device. | 2012-05-03 |
| 20120110243 | DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A data writing method for a rewritable non-volatile memory module is provided, the rewritable non-volatile memory module has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, a portion of the physical blocks are mapped to a plurality of logical blocks, and each of the logical blocks has a plurality of logical pages. The data writing method includes receiving data, and the data has a plurality of data bits and belongs to one of the logical pages. The data writing method also includes determining whether each of the data bits is a specific value. The data writing method further includes not writing the data into the physical pages when each of the data bits is the specific value. Thereby, the performance of a memory storage apparatus is improved. | 2012-05-03 |
| 20120110244 | COPYBACK OPERATIONS - Methods and systems for copyback operations are described. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the memory device, and programming the data to a second memory unit of the memory device. | 2012-05-03 |
| 20120110245 | Data writing method and writing device for an electronic erasable read only dynamic memory - A data writing method for an EEPROM in an electronic device is performed by a writing device. The electronic device includes a system unit generating a system voltage and a write-protection voltage. The writing device includes a processor stored with data to be written, and connected electrically to a connector with the same interface as that of an expansion connector of the electronic device. When the connector is connected electrically to the expansion connector, the processor generates a write-enable voltage greater than the system voltage upon receipt of the system voltage from the electronic device, and outputs the write-enable voltage to the system unit. The system unit raises the system voltage in response to the write-enable voltage such that the write-protection voltage is smaller than the raised system voltage to thereby enable the EEPROM to operate in a write state, where the processing unit writes the data into the EEPROM. | 2012-05-03 |
| 20120110246 | EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY - Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device. | 2012-05-03 |
| 20120110247 | MANAGEMENT OF CACHE MEMORY IN A FLASH CACHE ARCHITECTURE - A method for managing cache memory in a flash cache architecture. The method includes providing a storage cache controller, at least a flash memory comprising a flash controller, and at least a backend storage device, and maintaining read cache metadata for tracking on the flash memory cached data to be read, and write cache metadata for tracking on the flash memory data expected to be cached. | 2012-05-03 |
| 20120110248 | ELECTRONIC FLASH MEMORY EXTERNAL STORAGE METHOD AND DEVICE - An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system. | 2012-05-03 |
| 20120110249 | MEMORY SYSTEM, DATA STORAGE DEVICE, USER DEVICE AND DATA MANAGEMENT METHOD THEREOF - A data management method of a data storage device having a data management unit different from a data management unit of a user device receives information regarding a storage area of a file to be deleted, from the user device, selects a storage area which matches with the data management unit of the data storage device, from among the storage area of the deleted file, and performs an erasing operation on the selected storage area which matches with the data management unit. | 2012-05-03 |
| 20120110250 | MEETHOD, SYSTEM AND COMPUTER READABLE MEDIUM FOR COPY BACK - Systems, computer readable media and methods for updating a flash memory device involve procedures for transferring, from a flash memory device to an external controller, only a portion of a data entity; and determining, by the external controller, based upon the portion of the data entity, whether to complete a copy back operation of the data entity or to correct errors of the data entity. If it is determined to correct errors of the data entity, then the procedure includes (a) completing a transfer of the data entity to the external controller; (b) error correcting the data entity to provide an amended data entity; and (c) writing the amended data entity to the flash memory device. If, however, it is determined to complete the copy back operation then the procedures includes completing the copy back operation of the data entity by transferring the data entity within the flash memory device. | 2012-05-03 |
| 20120110251 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages. | 2012-05-03 |
| 20120110252 | System and Method for Providing Performance-Enhanced Rebuild of a Solid-State Drive (SSD) in a Solid-State Drive Hard Disk Drive (SSD HDD) Redundant Array of Inexpensive Disks 1 (Raid 1) Pair - The present invention is a method for implementing a storage system. The storage system may include a disk array having a disk drive pair which includes a solid-state disk drive and a hard disk drive. The method may include the step of copying a data subset of a data set from the hard disk drive to a spare solid-state disk drive during a solid-state disk drive rebuild process. The data subset includes a first amount of data and the data set includes a second amount of data, where the first amount of data is less than the second amount of data. The method may further include the step of receiving a read request from a host server requesting the data subset. The method further includes the step of directing the read command to the spare solid-state disk drive. | 2012-05-03 |
| 20120110253 | COMBINED MEMORY AND STORAGE DEVICE IN AN APPARATUS FOR DATA PROCESSING - The invention concerns an apparatus for data processing comprising a central processing unit and a non volatile random access memory. The central processing unit and the non volatile random access memory are connected via a memory bus. The data related to an operating system for running said apparatus is at least partly stored in said non volatile random access memory and the memory used by the operating system for operating said apparatus is at least partly said non volatile memory. | 2012-05-03 |
| 20120110254 | OBJECT PERSISTENCY - There is provided a method and computer system for object persistency that includes: running a program; storing an object of the program into a random access memory in response to determining that the object is a non-persistent object; and storing the object into a phase change memory in response to determining that the object is a persistent object. The method and computer system of the present disclosure do not need separate persistency layers, such that the programming model is light weighted, the persistency of object data is more simple and fast, and implicit transaction process is supported, thereby a great deal of development and runtime costs are saved. | 2012-05-03 |
| 20120110255 | METHOD AND APPARATUS FOR SENDING DATA FROM MULTIPLE SOURCES OVER A COMMUNICATIONS BUS - In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed. | 2012-05-03 |
| 20120110256 | LOW POWER CONTENT-ADDRESSABLE MEMORY AND METHOD - Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparison signal is provided to comparator circuitry that uniquely represents the stored binary values. A match signal is input to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair. In one example, a transistor is operated to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair. In that example, no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs. | 2012-05-03 |
| 20120110257 | VIRTUAL TAPE DEVICE AND METHOD FOR SELECTING PHYSICAL TAPE - A virtual tape device being located between a host and a tape library and storing data as a virtual logical volume in a storage, has a calculator that calculates a time period in which a robot moves, from a cell to a drive device, the physical tape in accordance with an instruction when the instruction is issued to recall the target logical volume redundantly stored on the physical tapes stored in two or more cells included in different tape libraries or in the same tape library and to store the target logical volume, a calculator that calculates a time period for tape positioning, and a unit that calculates a time period on the basis of the time period in which the robot moves from the cell to the drive device and the time period for the tape positioning, and that selects a physical tape corresponding to the shortest time period. | 2012-05-03 |
| 20120110258 | STORAGE DEVICE CACHE - Implementations described and claimed herein provide a method and system for comparing a storage location related to a new write command on a storage device with storage locations of a predetermined number of write commands stored in a first table to determine frequency of write commands to the storage location. If the frequency is determined to be higher than a first threshold, the data related to the write command is stored in a write cache. | 2012-05-03 |
| 20120110259 | TIERED DATA STORAGE SYSTEM WITH DATA MANAGEMENT AND METHOD OF OPERATION THEREOF - A method of operation of a data storage system includes: enabling a system interface for receiving host commands; updating a mapping register for monitoring transaction records of a logical block address for the host commands including translating a host virtual block address to a physical address for storage devices; accessing by a storage processor, the mapping register for comparing the transaction records with a tiering policies register; and enabling a tiered storage engine for transferring host data blocks by the system interface and concurrently transferring between a tier zero, a tier one, or a tier two if the storage processor determines the transaction records exceed the tiering policies register. | 2012-05-03 |
| 20120110260 | AUTOMATED STORAGE PROVISIONING WITHIN A CLUSTERED COMPUTING ENVIRONMENT - Embodiments of the present invention provide an approach for automatic storage planning and provisioning within a clustered computing environment (e.g., a cloud computing environment). Specifically, embodiments of the present invention will receive planning input for a set of storage area network volume controllers (SVCs) within the clustered computing environment, the planning input indicating a potential load on the SVCs and its associated components. Along these lines, analytical models (e.g., from vendors) can be also used that allow for a load to be accurately estimated on the storage components. Regardless, configuration data for a set of storage components (i.e., the set of SVCs, a set of managed disk (Mdisk) groups associated with the set of SVCs, and a set of backend storage systems) will also be collected. Based on this configuration data, the set of storage components will be filtered to identify candidate storage components capable of addressing the potential load. Then, performance data for the candidate storage components will be analyzed to identify an SVC and an Mdisk group to address the potential load. This allows for storage provisioning planning to be automated in a highly accurate fashion. | 2012-05-03 |
| 20120110261 | HOME STORAGE DEVICE AND SOFTWARE - In general, embodiments of the present invention provide a home storage system. Specifically, in a typical embodiment, the home storage system includes a graphical user interface for graphically accessing features of the home storage system; an internal storage management and monitoring module for managing and monitoring a set of semiconductor storage device (SSD) memory units and a set of hard disk drive (HDD) memory units within the home storage system; an external interface management and monitoring module for managing and monitoring network connectivity of the home storage system; and a portable storage management and monitoring module for managing and monitoring at least one type of external memory coupled to the home storage system. | 2012-05-03 |
| 20120110262 | Systems and methods for remote raid configuration in an embedded environment - Remote RAID system configuration may be implemented in an embedded and out-of-band manner using an information handling system configured, for example, as a RAID server. The remote RAID configuration may be implement, for example, on a RAID server system in the condition as it is supplied directly out-of-the-box to a user without requiring downloading of any additional software or firmware, without requiring presence of a management framework and plug in, and/or in a manner that is operating system (OS)-independent or that requires no OS to be present on the server. The RAID server may then be remotely reconfigured one or more times thereafter | 2012-05-03 |
| 20120110263 | MANAGEMENT METHOD OF PERFORMANCE HISTORY AND A MANAGEMENT SYSTEM OF PERFORMANCE HISTORY - A performance history management method and system are disclosed, in which the time-series performance history such as a volume included in a storage device is managed as one time-series performance history at the time of data rearrangement or device change. The data-oriented performance history providing the logical place of storage of the data stored in the volume is generated using the storage performance monitor program based on the rearrangement history information providing the information on the history of transfer of the data stored in the rearrangement history table and the volume of the storage device by the storage structure information acquisition program, the storage structure information stored in the storage structure information table and the performance history of each volume stored in the storage performance history table by the storage performance information acquisition program. The performance history can be displayed or the performance change detected to display an alert. | 2012-05-03 |
| 20120110264 | SELECTIVELY UTILIZING A PLURALITY OF DISPARATE SOLID STATE STORAGE LOCATIONS - A method for selectively utilizing a plurality of disparate solid state storage locations is disclosed. The technology initially receives class types for a plurality of disparate solid state storage locations. The characteristics of the received data are determined. The received data is then allocated to one of the plurality of disparate solid state storage locations based upon the determined characteristics of the received data. | 2012-05-03 |
| 20120110265 | SECURISATION OF A REMOTE EXECUTABLE CODE USING A FOOTPRINT OF THE COMPUTER RECIPIENT - Method of securing exchanges between two electronic devices, by using an imprint of at least one of the two devices. This imprint is obtained on the basis of all or part of the electronic components of which this device is composed. This imprint will serve, either to protect the confidentiality of the data exchanged, or to attest to the identity of the device issuing the data. | 2012-05-03 |
| 20120110266 | DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS - Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed. | 2012-05-03 |
| 20120110267 | METHOD AND APPARATUS FOR PROVIDING EFFICIENT CONTEXT CLASSIFICATION - A method for providing context classification may include causing selection of a single core in a multi-core processor as a context core in a user terminal, configuring cache memory associated with the context core to enable the context core to process context information for the user terminal, and causing execution of prediction and control functions related to user interface interactions based on the context information processed at the context core. Corresponding apparatuses are also provided. | 2012-05-03 |
| 20120110268 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The data processing apparatus according to an embodiment of the present invention includes: a first processor; a second processor; and an external RAM to/from which the first processor writes/reads data, the first processor including a cache memory for storing data used in the first processor in association with an address on the external RAM, and the data being written to the cache memory by the second processor not through the external RAM. | 2012-05-03 |
| 20120110269 | PREFETCH INSTRUCTION - Techniques are disclosed relating to prefetching data from memory. In one embodiment, an integrated circuit may include a processor containing an execution core and a data cache. The execution core may be configured to receive an instance of a prefetch instruction that specifies a memory address from which to retrieve data. In response to the instance of the instruction, the execution core retrieves data from the memory address and stores it in the data in the data cache, regardless of whether the data corresponding to that particular memory address is already stored in the data cache. In this manner, the data cache may be used as a prefetch buffer for data in memory buffers where coherence has not been maintained. | 2012-05-03 |
| 20120110270 | DATA PROCESSING SYSTEM HAVING SELECTIVE INVALIDATION OF SNOOP REQUESTS AND METHOD THEREFOR - A data processing system includes a system interconnect, a processor coupled to the system interconnect, and a cache coherency manager (CCM) coupled to the system interconnect. The processor includes a cache. A method includes generating, by the CCM, one or more snoop requests to the cache of the processor; storing the one or more snoop requests to the cache of the processor into a snoop queue; setting a cache enable indicator to indicate that the cache of the processor is to be disabled; in response to setting the cache enable indicator to indicate that the cache of the processor is to be disabled, selectively invalidating the one or more snoop requests to the cache of the processor, wherein the selectively invalidating is performed based on an invalidate snoop queue indicator of the processor; and disabling the cache. | 2012-05-03 |
| 20120110271 | MECHANISM TO SPEED-UP MULTITHREADED EXECUTION BY REGISTER FILE WRITE PORT REALLOCATION - Various systems and processes may be used to speed up multi-threaded execution. In certain implementations, a system and process may include the ability to write results of a first group of execution units associated with a first register file into the first register file using a first write port of the first register file and write results of a second group of execution units associated with a second register file into the second register file using a first write port of the second register file. The system, apparatus, and process may also include the ability to connect, in a shared register file mode, results of the second group of execution units to a second write port of the first register file and connect, in a split register file mode, results of a part of the first group of execution units to the second write port of the first register file. | 2012-05-03 |
| 20120110272 | CROSS PROCESS MEMORY MANAGEMENT - A method for efficiently managing memory resources in a computer system having a graphics processing unit that runs several processes simultaneously on the same computer system includes using threads to communicate that additional memory is needed. If the request indicates that termination will occur then the other processes will reduce their memory usage to a minimum to avoid termination but if the request indicates that the process will not run optimally then the other processes will reduce their memory usage to 1/N where N is the count of the total number of running processes. The apparatus includes a computer system using a graphics processing unit and processes with threads that can communicate directly with other threads and with a shared memory which is part of the operating system memory. | 2012-05-03 |
| 20120110273 | TRANSPARENT HYPERVISOR PINNING OF CRITICAL MEMORY AREAS IN A SHARED MEMORY PARTITION DATA PROCESSING SYSTEM - Transparent hypervisor pinning of critical memory areas is provided for a shared memory partition data processing system. The transparent hypervisor pinning includes receiving at a hypervisor a hypervisor call initiated by a logical partition to register a logical memory area of the logical partition with the hypervisor. Responsive to this hypervisor call, the hypervisor transparently determines whether the logical memory is a critical memory area for access by the hypervisor. If the logical memory area is a critical memory area, then the hypervisor automatically pins the logical memory area to physical memory of the shared memory partition data processing system, thereby ensuring that the memory area will not be paged-out from physical memory to external storage, and thus ensuring availability of the logic memory area to the hypervisor. | 2012-05-03 |
| 20120110274 | Operating System Image Management - In a data processing system including multiple logical partitions (LPARs), an application executes on a first logical partition (LPAR) of the multiple LPARs, where the application uses a first operation system stored in a first memory partition of a shared pool memory of the data processing system. A virtualization management component (a) initiates an update process that quiesces operations of the first LPAR, (b) pages in, via a virtual input/output server coupled to a first paging device, a first image of a second operating system from the first paging device to the shared pool memory; (c) changes one or more pointers associated with the application to point to one or more portions of the second operating system, such that the application uses the second operating system, when resumed; and (b) resumes execution the application. | 2012-05-03 |
| 20120110275 | Supporting Virtual Input/Output (I/O) Server (VIOS) Active Memory Sharing in a Cluster Environment - A method, system, and computer program product provide a shared virtual memory space via a cluster-aware virtual input/output (I/O) server (VIOS). The VIOS receives a paging file request from a first LPAR and thin-provisions a logical unit (LU) within the virtual memory space as a shared paging file of the same storage amount as the minimum required capacity. The VIOS also autonomously maintains a logical redundancy LU (redundant LU) as a real-time copy of the provisioned/allocated LU, where the redundant LU is a dynamic copy of the allocated LU that is autonomously updated responsive to any changes within the allocated LU. Responsive to a second VIOS attempting to read a LU currently utilized by a first VIOS, the read request is autonomously redirected to the logical redundancy LU. The redundant LU can be utilized to facilitate migration of a client LPAR to a different computing electronic complex (CEC). | 2012-05-03 |
| 20120110276 | MANAGING MIGRATION OF A SHARED MEMORY LOGICAL PARTITION FROM A SOURCE SYSTEM TO A TARGET SYSTEM - Migration management is provided for a shared memory logical partition migrating from a source system to a target system. The management approach includes managing migration of the logical partition from the source system to the target system by: transferring a portion of logical partition state information for the migrating logical partition from the source system to the target system by copying at the source system contents of a logical page of the migrating logical partition into a state record buffer for forwarding to the target system; forwarding the state record buffer to the target system; and determining whether the migrating logical partition is suspended at the source system, and if not, copying at the target system contents of the state record buffer to paging storage of the target system, the paging storage being external to physical memory managed by a hypervisor of the target system. | 2012-05-03 |
| 20120110277 | METHOD AND SYSTEM FOR STORAGE-SYSTEM MANAGEMENT - One example of the present invention is directed to a data-storage system comprising a plurality of data-storage devices, one or more communications connections through which the data-storage system receives management and data-access commands and sends responses to received commands, and one or more processors. The one or more processors execute controller functionality that controls command and response exchanges through the communications connections, accesses the data-storage devices, and provides a data-storage-system interface that includes a management-interface portion that provides access to management functionality, a data-interface portion that provides access to data-access functionality, and a management-interface tunnel that provides alternative access to management functionality through the data-interface portion of the data-storage-system interface. | 2012-05-03 |
| 20120110278 | REMAPPING OF INOPERABLE MEMORY BLOCKS - Inoperable phase change memory (PCM) blocks in a PCM device are remapped to one or more operable PCM blocks, e.g. by maintaining an inoperable block table that includes an entry for each inoperable PCM block and an address of a remapped PCM block. Alternatively, the PCM blocks may be remapped by storing the address of the remapped block in the block itself, and setting a remapping bit that indicate the block has been remapped. Where the remapping is performed by a processor, an inoperable block bit may be set in a translation look aside buffer that indicates whether a virtual memory page is associated with an inoperable or remapped PCM block. When a request to access a virtual memory page is received, the processor references the inoperable block bit associated with the virtual memory page to determine whether to check for remapped PCM blocks in the inoperable block table. | 2012-05-03 |
| 20120110279 | METHOD AND SYSTEM FOR NON-DISRUPTIVE MIGRATION - Method and system for migrating a virtual storage system from a source storage system having access to a source storage device to a destination storage system having access to a destination storage device is provided. A processor executable management application estimates a likelihood of success for a migration operation before the migration operation enters a cut-over duration during which client access to the source storage system and the destination storage system is restricted. The migration operation enters the cut-over duration if there is high likelihood of success for completing the migration during the cut-over duration or aborted, if there is a low likelihood of success for completing the migration during the cut-over duration. | 2012-05-03 |
| 20120110280 | OUT-OF-ORDER LOAD/STORE QUEUE STRUCTURE - The present invention provides a method and apparatus for supporting embodiments of an out-of-order load/store queue structure. One embodiment of the apparatus includes a first queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes one or more additional queues for storing memory operation in response to completion of a memory operation. The embodiment of the apparatus is configured to remove the memory operation from the first queue in response to the completion. | 2012-05-03 |
| 20120110281 | VIRTUALIZATION AND OFFLOAD READS AND WRITES - Aspects of the subject matter described herein relate to virtualization and offload reads and writes. In aspects, an offload read allows a requestor to obtain a token that represents data while an offload write allows the requestor to request that the data (or a part thereof) represented by a token be logically written. Offload reads and writes may be used to perform various actions for virtual environments. | 2012-05-03 |
| 20120110282 | SYSTEMS AND METHODS FOR MANAGING INFORMATION OBJECTS IN DYNAMIC DATA STORAGE DEVICES - According to one aspect, a system for managing information objects in dynamic data storage devices including a first data storage device having a plurality of information objects, a second data storage device operatively connectable to an output device for providing at least some of the information objects to at least one user, and at least one processor operatively coupled to the first data storage device and the second data storage device. The at least one processor is configured to automatically divide the plurality of information objects in the first data storage device to form at least one data subdivision based on division criteria, and repeatedly, in response to a dynamic operating condition determine a relevance value of at least one of the data subdivisions in the first data storage device and the second data storage device indicative of the relevance of those data subdivision to the user, and based on the relevance value, perform at least one of loading those data subdivision to the second data storage, or unloading those data subdivision from the second data storage. | 2012-05-03 |
| 20120110283 | DATA PROCESSING APPARATUS AND IMAGE PROCESSING APPARATUS - A data processing apparatus may include a plurality of buffer units that stores data, a data write control unit that writes input data to any one of the plurality of buffer units by exclusively controlling the plurality of buffer units, and a data read control unit that reads data to be output from any one of the plurality of buffer units by exclusively controlling the plurality of buffer units. The data write control unit may output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may output a data read completion signal indicating that the reading of the data is completed when the reading of the data to be output is completed. | 2012-05-03 |
| 20120110284 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND PROGRAM - The present invention relates to a data processing apparatus, a data processing method, and a program that are configured to prevent (or lower) the increase in scale and cost of the apparatus. | 2012-05-03 |
| 20120110285 | INFORMATION STORAGE MEDIUM, RECORDING/REPRODUCING APPARATUS, AND RECORDING/REPRODUCING METHOD - A recording/reproducing apparatus is configured to record a replacement block by logical overwrite (LOW) for updating data recorded on an information storage medium in a first area of the medium, record a replacement block for replacing a defect block generated on the medium in a second area of the medium, and record a second replacement block for replacement by defect of a first replacement block in the second area if the defect is detected while the first replacement block is being recorded in the first area to perform the logical overwrite of an original block recorded in a predetermined area of the medium, generate a defect list (DFL) entry including location information of the original block and location information of the second replacement block in order to indicate the replacement state, and move location information of the first replacement block in the second replacement block. | 2012-05-03 |
| 20120110286 | Image processing apparatus, power-saving recovery control method, and computer program product - An image processing apparatus including: a first storage unit; a second storage unit that has a higher storage capacity than that of the first storage unit and a longer start-up time than that of the first storage unit; and a control unit that, after shifting to a power-saving mode in which power consumption is reduced by shutting off power supply at least to the second storage unit, starts a recovery process from the power-saving mode upon occurrence of a recovery request from the power-saving mode to perform a processing operation using the second storage unit, starts the processing operation with the first storage unit as a data storing destination when the first storage unit is ready for use, and switches the data storing destination from the first storage unit to the second storage unit when the second storage unit is ready for use. | 2012-05-03 |
| 20120110287 | SNAPSHOTS IN A HYBRID STORAGE DEVICE COMPRISING A MAGNETIC DISK AND A SOLID STATE DISK - One or more snapshots of data stored over a period of time are maintained in a hybrid storage device comprising a magnetic disk and a solid state disk, wherein a selected snapshot stores information that allows recovery of data that is stored in the hybrid storage device at a selected point in time of the period of time. The hybrid storage device receives an input/output (I/O) command from a computational device. A category of a plurality of categories to which the I/O command belongs is determined, wherein the plurality of categories comprise writing to an unused block, writing to a used block, reading from an unused block, and reading from a used block. In response to determining the category to which the I/O command belongs, the I/O command is handled by one of the magnetic disk and the solid state disk based on the determined category. | 2012-05-03 |
| 20120110288 | TEMPORARY VTOC LOCKING DURING DEFRAGMENTATION - Various embodiments for defragmentation of a storage volume in a computing storage environment by a processor device are provided. A volume table of contents (VTOC) is serialized for a volume scan operation. At least one dummy data set in the storage volume is allocated, to be subsequently filled with actual data pursuant to a degragmentation operation. The serialization of the VTOC is released, allowing access to the storage volume. Input/output (I/O) operations are allowed to occur. | 2012-05-03 |
| 20120110289 | DATA BACKUP SYSTEM AND METHOD FOR VIRTUAL INFRASTRUCTURE - Systems for backing up the data of an IT system by utilizing server or storage virtualization technology to create and move logical IT infrastructures dynamically. A virtualized IT system provides a server resource pool and a storage resource pool composed from multiple physical devices either within a datacenter or a globally located plurality of datacenters. The virtual server and the storage volume provisioned from those pools will be paired to form the virtual infrastructure. In other words, the virtual infrastructure becomes a logical IT environment build with the required computing and storage resources needed in order to execute specific applications. The virtual infrastructure can also be migrated within/among datacenter sites. | 2012-05-03 |
| 20120110290 | METHOD AND APPARATUS FOR INCREASING AN AMOUNT OF MEMORY ON DEMAND WHEN MONITORING REMOTE MIRRORING PERFORMANCE - A method and storage system for increasing an amount of memory in a queuing area on. The storage system includes first and second storage subsystems connected to each other via a path. A primary volume in the first storage subsystem and a remote secondary volume in the second storage subsystem are mirrored and operated in the asynchronous mode. A queuing area having memory is provided in the second storage subsystem for temporarily storing data transferred to the second storage subsystem from the first storage subsystem in response to a write input/output (I/O) issued by a host to write data in the primary volume. Data temporarily stored in the memory is retrieved and stored in the remote secondary volume. An unused area of the queuing area is monitored and the memory increased if the unused area becomes less than a predetermined amount. | 2012-05-03 |
| 20120110291 | SYSTEM AND METHOD FOR I/O COMMAND MANAGEMENT - Systems and methods for input/output command management. In embodiments of the invention an input/output command fully executes after a lock has been obtained for the command on all storage segments relating to the command, in a predetermined order. Some embodiments of the invention allow overlapping access to storage and/or to individual storage segments by a plurality of input/output commands. In some embodiments of the invention, prioritization of commands is facilitated through the usage of a sharing policy and/or wakeup policy. | 2012-05-03 |
| 20120110292 | METHOD FOR ACCESSING A PORTABLE DATA STORAGE MEDIUM WITH AUXILIARY MODULE AND PORTABLE DATA STORAGE MEDIUM - The invention describes a method for accessing a portable storage data carrier ( | 2012-05-03 |
| 20120110293 | METHOD AND SYSTEM FOR MANAGING VIRTUAL MACHINE STORAGE SPACE AND PHYSICAL HOST - A method for managing Virtual Machine (VM) storage space is provided. In the method, a Storage Balloon Agent (SBA) module deployed in a VM is adopted to directly acquire virtual storage free block information and deliver the acquired virtual storage free block information to a Storage Balloon Daemon (SBD) module deployed in a Virtual Machine Monitor (VMM) layer; and the SBD module releases a part or all of physical storage space corresponding to the virtual storage free block information, and marks virtual storage blocks corresponding to the released physical storage space as unavailable. A corresponding system and a physical host are further provided in the present invention. Through the method of an embodiment of the present invention, use condition of virtual storage space can be acquired in real time, and a large number of read and write operations of a storage system can be avoided. | 2012-05-03 |
| 20120110294 | METHOD OF MEMORY MANAGEMENT FOR SERVER-SIDE SCRIPTING LANGUAGE RUNTIME SYSTEM - A method of memory management includes allocating a portion of a memory as a memory heap including a plurality of segments, each segment having a segment size; performing one or more memory allocations for objects in the memory heap; creating a free list array and class-size array in a metadata section of the memory heap, the class-size array being created such that each element of the size-class array is related a particular one of the plurality of segments and the free list array being created such that each element of the free list array is related to a different size class; and initializing the heap when it is determined that the heap may be destroyed, initializing including clearing the free list array. | 2012-05-03 |
| 20120110295 | Keeping File Systems or Partitions Private in a Memory Device - Disclosed is a method and apparatus for allowing a user to select, from a plurality of partitions on a memory device, which partitions may be visible to hosts connecting to the memory device. | 2012-05-03 |
| 20120110296 | ELECTRONIC APPARATUS - A diagnostic tool sends a request format designating a virtual address, which is different from a real address for an EEPROM. When a microcomputer determines that an address designated by the received request format is a virtual address assigned to the EEPROM, the microcomputer executes a process, which is designated by the received request format, with respect to the virtual address assigned to the EEPROM. | 2012-05-03 |
| 20120110297 | SECURE PARTITIONING WITH SHARED INPUT/OUTPUT - A soft partitioning system for allowing multiple virtual system environments to execute on a single platform may include I/O service partitions (IOSPs). The IOSPs operating in a separate virtual memory space on the platform and service disk and network requests from multiple guests. The IOSPs provide translation from virtual addresses to physical addresses such that from the point of view of the guest the virtual addresses used by the guest appear to be physical addresses. The IOSP may be implemented in a Linux kernel. The address space of the IOSP may be extended to include DMA memory sections such that the Linux kernel does not include all of the guest's memory. The IOSP may operate on hardware that does or does not support virtualization technology for directed I/O. | 2012-05-03 |
| 20120110298 | MEMORY ACCESS CONTROL DEVICE AND COMPUTER - To virtualize a system without having to incorporate a special mechanism into software and with increases in overhead suppressed, by controlling memory accesses made by processors using hardware. | 2012-05-03 |
| 20120110299 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 2012-05-03 |
| 20120110300 | DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring logical units for mapping to the physical units of the data area and writing update data belonging to the logical pages of the logical units orderly into the physical pages of physical units gotten from the free area. The method further includes configuring root units for the logical pages, configuring an entry chain for each of the root units and building entries on the entry chains for recording update information of the updated logical pages, wherein each of the logical pages corresponds to a root unit. Accordingly, the table size for storing the update information is effectively reduced and the time for searching valid data is effectively shortened. | 2012-05-03 |
| 20120110301 | METHOD OF CREATING A VIRTUAL ADDRESS FOR A DAUGHTER SOFTWARE ENTITY RELATED TO THE CONTEXT OF A MOTHER SOFTWARE ENTITY - A process for creates a virtual address for a software entity called a “daughter” belonging to the context of a software entity called the “mother.” This virtual address includes a series of fields allowing retrieval of the series of fields of the virtual address of the mother software entity and a field unique in the context of the mother software entity. Each series of fields is associated with a single software entity which it defines completely. | 2012-05-03 |
| 20120110302 | Accelerating Generic Loop Iterators Using Speculative Execution - A method, a system and a computer program product for effectively accelerating loop iterators using speculative execution of iterators. An Efficient Loop Iterator (ELI) utility detects initiation of a target program and initiates/spawns a speculative iterator thread at the start of the basic code block ahead of the code block that initiates a nested loop. The ELI utility assigns the iterator thread to a dedicated processor in a multi-processor system. The speculative thread runs/executes ahead of the execution of the nested loop and calculates indices in a corresponding multidimensional array. The iterator thread adds all the precomputed indices to a single queue. As a result, the ELI utility effectively enables a multidimensional loop to be replaced by a single dimensional loop. At the beginning of (or during) each iteration of the iterator, the ELI utility “dequeues” an entry from the queue to use the entry to access the array upon which the ELI utility iterates. The ELI utility performs concurrent iterations on the array by using the queue entries. | 2012-05-03 |
| 20120110303 | Method for Process Synchronization of Embedded Applications in Multi-Core Systems - A system and method for process synchronization in a multi-core computer system. A separate non-caching memory enables a method to synchronize processes executing on multiple processor cores. Since only a very small amount (a few number of bytes), is needed for the synchronization, it is possible to extend the method for inter-processor core message passing by allocating dedicated address space of the on-chip memory for each processor with exclusive write access. Each of the multiple processor cores maintains a dedicated cache while maintaining coherency with the non-cache shared memory. | 2012-05-03 |
| 20120110304 | PIPELINED SERIAL RING BUS - The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations. | 2012-05-03 |
| 20120110305 | Register Renamer that Handles Multiple Register Sizes Aliased to the Same Storage Locations - A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry. | 2012-05-03 |
| 20120110306 | TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR - A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated. | 2012-05-03 |
| 20120110307 | COMPRESSED INSTRUCTION PROCESSING DEVICE AND COMPRESSED INSTRUCTION GENERATION DEVICE - A compressed instruction processing device has: a compressed instruction expanding circuit which expands a compressed instruction code that include a difference code between an instruction code being a compression object and a reference instruction code and which outputs an expanded instruction code; an instruction buffer storing the instruction code expanded by the compressed instruction expanding circuit; and an execution section executing the instruction code expanded by the compressed instruction expanding circuit, wherein the compressed instruction expanding circuit outputs the expanded instruction code by inputting the instruction code in the instruction buffer as the reference instruction code and adding the reference instruction code and the difference code in the compressed instruction code. | 2012-05-03 |
| 20120110308 | METHOD FOR CONTROLLING BMC HAVING CUSTOMIZED SDR - A Baseboard Management Controller (BMC) controlling method includes the steps of dividing a memory of a BMC into an original region and customized region, in which the original region includes at least one original sensor data record (SDR) and original platform event filter (PEF) corresponding to each other; providing an instruction set to at least one external system, in which the external system manages at least one customized SDR and customized PEF corresponding to each other in the customized region through the instruction set; polling the original SDR in the original region and the customized SDR in the customized region; determining whether values of the SDRs obtained through polling conform to a plurality of critical values individually corresponding to the SDRs; and obtaining a processing policy according to the corresponding PEF when at least one value of the SDR does not conform to the corresponding critical value. | 2012-05-03 |
| 20120110309 | Data Output Transfer To Memory - Methods, systems, and computer readable media for improved transfer of processing data outputs to memory are disclosed. According to an embodiment, a method for transferring outputs of a plurality of threads concurrently executing in one or more processing units to a memory includes: forming, based upon one or more of the outputs, a combined memory export instruction comprising one or more data elements and one or more control elements; and sending the combined memory export instruction to the memory. The combined memory export instruction can be sent to memory in a single clock cycle. Another method includes: forming, based upon outputs from two or more of the threads, a memory export instruction comprising two or more data elements; embedding at least one address representative of the two or more of the outputs in a second memory instruction; and sending the memory export instruction and the second memory instruction to the memory. | 2012-05-03 |
| 20120110310 | MICROPROCESSOR WITH PIPELINE BUBBLE DETECTION DEVICE - A microprocessor includes a pipeline microarchitecture and a pipeline bubble detection device. The pipeline bubble detection device has a minimum execution clock cycle ascertainment unit for ascertaining a minimum or optimum number of execution clock cycles for one or more program commands which pass through the pipeline microarchitecture or are handled by the pipeline microarchitecture. | 2012-05-03 |
| 20120110311 | CUSTOMIZED KIOSK MODES OF OPERATION - Techniques for customized kiosk modes of operation are provided. A kiosk is configured to recognize periods of operation that are slow, moderate, or busy. A number of factors can be used to automatically recognize these periods and change the periods on demand. For each type of period (slow, moderate, or busy), the kiosk uses a different customized mode of operation so as to optimally use the kiosk for the benefit of the kiosk owner, customers interfacing with the kiosk, and marketers selling advertisements via the kiosk. | 2012-05-03 |
| 20120110312 | System and Method for an Access Controller Assisted Boot - Systems and methods for reducing problems and disadvantages associated with network boots are disclosed. In accordance with an embodiment of the present disclosure, an information handling system comprises a processor, a memory communicatively coupled to the processor, and an access controller communicatively coupled to the processor. The access controller has stored thereon a general pre-boot file and configured to receive boot configuration information from a management server. The access controller further configured to generate a boot script according to the boot configuration information and generate a specific pre-boot file based on the general pre-boot file and the boot script. The access controller is further configured to configure the information handling system to boot to a target based on the specific pre-boot file. | 2012-05-03 |
| 20120110313 | ENHANCED REBOOT COMMAND - A method and system allows a computer system to perform a network reboot in response to an enhanced reboot command. The computer system receives a command to load an operating system and interprets the command to determine whether a physical machine or a virtual machine is to be rebooted. In response to a determination that the command indicates the use of a network option, the computer system loads the operating system from a networked server, and perform rebooting according to the interpreted command with the use of the operating system. | 2012-05-03 |
| 20120110314 | BOOTING ACCESS METHOD AND MEMORY DEVICE OF EMBEDDED SYSTEM - A booting access method and a storage device of an embedded system are provided. The booting access method of the embedded system is applied to the storage device which includes a master boot record (MBR) section, a hidden section and a public section to improve access precision of embedded memory data. The access method includes: using the MBR section to access data of the public section when a normal booting signal is received; using a boot loader in the hidden section to update the MBR section and then accessing data of the public section when a trigger update signal is received. | 2012-05-03 |
| 20120110315 | MOBILE TERMINAL AND CONTROLLING METHOD THEREOF - A method and system for controlling a mobile terminal provided with at least two operating systems. The method includes: displaying an application on a dedicated screen of a first OS (Operating System) among the at least two OSs (Operating Systems); determining that an execution command for the application is input to the dedicated screen of the first OS; determining whether the application is executable in the first OS if the execution command for the application is determined to have been input to the dedicated screen of the first OS; finding, among the at least two OSs in the memory, a second OS capable of executing the application if the first OS is determined not to be able to execute the application; activating the second OS; and executing the application via the activated second OS. | 2012-05-03 |
| 20120110316 | Intelligent Data Storage and Processing Using FPGA Devices - A re-configurable logic device such as a field programmable gate array (FPGA) can be used to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations, wherein the pipeline comprises a multi-functional pipeline, and wherein the re-configurable logic device is further configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. | 2012-05-03 |
| 20120110317 | CONTENT DOWNLOAD MANAGER - A system is configured to receive input to define one or more download policies from a group of available download policies, including one or more network restriction policies, one or more time restriction policies, one or more event restriction policies, and one or more location restriction policies. The system is further configured to receive an instruction to download particular content, determine that the one or more download policies permit the particular content to be downloaded, download the particular content when the one or more download policies permit the particular content to be downloaded, and generate a notification that the particular content is available to be accessed. | 2012-05-03 |
| 20120110318 | SYSTEM AND METHOD FOR CONTROLLING STATE TOKENS - The system and method for controlling state tokens described herein may secure sensitive application state tokens, link one application state token to other state tokens that represent certain identities or communication sessions, and maintain application state tokens to integrate various different systems or applications. In particular, the system and method described herein may provide a mechanism to override scheme that applications use to manage state information and thereby enforce policies that provide fine-grained control over any semantics the applications otherwise use to manage state information. Furthermore, a first application state token may be linked to another state token representing a session or identity to validate whether the session or identity represented therein created the first application state token, and state tokens that represent active communication sessions may be copied from browser processes to various external clients to integrate or otherwise share state information across the various external clients. | 2012-05-03 |
| 20120110319 | FAILURE RECOGNITION - A system and method for failure recognition is disclosed. The technology initially establishes a security association (SA) between a client and a first server on a network. In addition, an active reference count of a number of connections in the SA between the client and the first server is maintained. The SA is evaluated when the active reference count returns less than two connections within the SA between the client and the first server. | 2012-05-03 |
| 20120110320 | Automatic Secure Client Access - Providing secure network access in a networked client device. A client device is provided with a secure connection adapter. In operation, the secure connection adapter detects the network environment of the client device and determines of the network environment is trusted or untrusted. If the client device is operating in an untrusted network environment, the secure connection adapter establishes a secure connection to an enterprise host using a secure tunnel such as IPSec, SSL, or other secure connection. Programs executing on the client device now operate in the secure network environment, with all network activity routed through the secure connection to the enterprise. Optionally, a split tunnel mechanism may be used to direct some network traffic directly to the Internet from the client device. | 2012-05-03 |
| 20120110321 | DATA COMMUNICATION USING PORTABLE TERMINAL - In a method in a portable end device ( | 2012-05-03 |
| 20120110322 | SYSTEM AND METHOD OF DELIVERING CONFIDENTIAL ELECTRONIC FILES - A private document delivery system and method includes a sending computer configured to transmit an electronic document over a computer network, a dynamically established encrypted line to traverse the computer network from a receiving computer to the sending computer where the delivery address of the receiving computer is resolved a at the time of transmission of the private message such that no third parties to the message receive a permanent copy of the message. The system and method also includes a signaling mechanism configured to notify the receiving computer that the electronic document is waiting for delivery. The system and method includes a verification agent configured to verify the receiving computer's identity with a protocol specified by the sending computer and to provide access instructions to the receiving computer with which the receiving computer locates the sending computer via the dynamically established encrypted line and receives the transmitted electronic document. | 2012-05-03 |
| 20120110323 | METHODS FOR PROCESSING PRIVATE METADATA - According to one aspect of the invention, a file received from a first user is stored in a storage device, where the file includes private metadata encrypted by a secret key associated with a second user. A private metadata identifier is stored in a predetermined storage location, indicating that private metadata of the file has not been decrypted and indexed. In response to an inquiry subsequently received from the second user, the predetermined storage location is scanned to identify the private metadata identifier based on the inquiry. The encrypted metadata identified by the private metadata identifier is transmitted to the second user for decryption. In response to the metadata that has been decrypted by the second user, the decrypted metadata is indexed for the purpose of subsequent searches of at least one of the metadata and the file. | 2012-05-03 |
