| 18th week of 2012 patent applcation highlights part 37 |
| Patent application number | Title | Published |
|---|
| 20120106216 | AC-DC CONVERTER WITH UNITY POWER FACTOR - A method for construction of voltage or current power sources receiving an AC input, the power sources based on inclusion of a buffer stage feeding a converter operating with an output driver to a load. The buffer stage includes a buffer capacitance and a control means, such that the consumed input current from the AC input is proportional to the AC input voltage to the power source. The buffer capacitance functions as a charge buffer, enabling maintenance of the consumed input current over the entire period of the AC input voltage, and acting to separate the load from the consumed input current. | 2012-05-03 |
| 20120106217 | CURRENT CONTROLLED POWER CONVERTER - A current controlled power converter includes a converting part configured to convert a three-phase ac voltage into a dc voltage or converts a dc voltage into a three-phase ac voltage, ac side current detection portions configured to detect an ac side current of the converting part, dc side current detection portions configured to detect a dc side current of the converting part, and a control section configured to control the converting part by pulse-width modulation using a spatial vector modulation method based on the ac side current detected by the ac side current detection portions and the dc side current detected by the dc side current detection portions. The control section corrects an amplitude error of the ac side current detected by the ac side current detection portions, and an offset error of the ac side current detected by the ac side current detection portions. | 2012-05-03 |
| 20120106218 | POWER CONVERSION APPARATUS - In order to widen an operational input voltage range of a power conversion apparatus and obtain a maximum efficiency value comparable to that in a case where the operational input voltage range is not widened by changing software but not hardware, provided is a power conversion apparatus, in which a control section ( | 2012-05-03 |
| 20120106219 | SEMICONDUCTOR DEVICE FOR WIRELESS COMMUNICATION - Provided is a semiconductor device for wireless communication which achieves a reduction in leakage power and allows an improvement in power efficiency. For example, to external terminals, an antenna driver section for driving an antenna and a rectifying section for rectifying input power from the antenna are coupled. The antenna driver section includes pull-up PMOS transistors and pull-down NMOS transistors. In the rectifying section, a power supply voltage generated by a full-wave rectifying circuit is boosted by a voltage boosting circuit. For example, when a supply of a power supply voltage from a battery is stopped, a power supply voltage resulting from the boosting by the voltage boosting circuit is supplied to the bulk of each of the pull-up PMOS transistors. | 2012-05-03 |
| 20120106220 | SWITCHING MODULE - A switching module includes a series-connected unit of a first flowing restriction element and a second flowing restriction element, the first flowing restriction element having an opening and closing function of opening and closing a flowing path of current, and the second flowing restriction element having at least one of a rectifying function of restricting the direction in which current flows and the opening and closing function, and a snubber circuit connected to the series-connected unit in parallel. A first wiring line connecting between the first flowing restriction element and the snubber circuit, a second wiring line connecting between the second flowing restriction element and the snubber circuit, a third wiring line connecting between the first flowing restriction element and the second flowing restriction element, the first flowing restriction element, the second flowing restriction element, and the snubber circuit are formed substantially integrally with each other by using an insulator. | 2012-05-03 |
| 20120106221 | ELECTRIC POWER CONVERTER APPARATUS - An electric power converter apparatus includes an inverter circuit having a plurality of upper arm elements and a plurality of lower arm elements, a feedback controlling module calculating a voltage command value in order to control an output from the inverter circuit in a feedback control manner and a compensating module compensating the voltage command value with a compensation amount and outputting a compensated voltage command value. Each of the plurality of upper arm elements and the plurality of lower arm elements is operated to switch over based on a control signal that is set according to the compensated voltage command value and a dead time. The compensation amount is set by the compensating module in order to compensate a fluctuation in the output current due to the dead time. | 2012-05-03 |
| 20120106222 | METHOD OF OPERATING AN INVERTER BY TURNING OFF THE SWITCHING AROUND A ZERO TRANSITION OF THE ALTERNATING OUTPUT CURRENT - A method of operating an inverter for converting direct voltage into alternating voltage. The inverter has direct-voltage terminals and alternating-voltage terminals and a plurality of power switching elements that are clocked at high-frequency connected between the d.c. and a.c. terminals. The high-frequency clocking of the power switching elements of the inverter is switched off around a zero transition of the alternating current or the alternating voltage for a period which depends on the direct voltage present at the direct-voltage terminals of the inverter and/or the output power of the inverter. No current is generated during time intervals with a poor efficiency. | 2012-05-03 |
| 20120106223 | CIRCUIT FOR CONVERTING POWER BETWEEN A THREE-PHASE GRID AND A SINGLE-PHASE GRID - Described is a circuit for converting electric power between a three-phase grid and a single-phase grid. The circuit includes, in at least one embodiment, a first transformer that is connected to the three-phase grid, a number of first converter stages assigned to the first transformer, the associated DC intermediate circuits and the associated second converter stages. The second converter stages are connected to each other at the alternating-current side outputs with the aid of a series connection. | 2012-05-03 |
| 20120106224 | NONVOLATILE MEMORY APPARATUS, REPAIR CIRCUIT FOR THE SAME, AND METHOD FOR READING CODE ADDRESSABLE MEMORY DATA - A nonvolatile memory apparatus includes: a memory cell array including a plurality of planes and configured to store a plurality of code addressable memory (CAM) data in independent planes. A redundancy cell array is configured to replace the memory cell array and a CAM data read unit is configured to read the plurality of CAM data from the respective planes in parallel, in response to a CAM data read command, and store the read data. | 2012-05-03 |
| 20120106225 | Array-Based Integrated Circuit with Reduced Proximity Effects - An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array. | 2012-05-03 |
| 20120106226 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor. | 2012-05-03 |
| 20120106227 | INTEGRATED CIRCUIT - An integrated circuit includes a normal data storage unit configured to store normal data and output the stored normal data in response to a write command, a read command, and an address signal in a normal operation mode, a test data storage unit configured to store the address signal as test data in response to the write command in a test operation mode, and output the stored test data in response to the read command, and a connection selection unit configured to selectively connect a data input/output terminal of the normal data storage unit or a data output terminal of the test data storage unit to a global line based on whether the integrated circuit is in a first or second one of the normal operation mode and the test operation mode, respectively. | 2012-05-03 |
| 20120106228 | METHOD AND APPARATUS FOR OPTIMIZING DRIVER LOAD IN A MEMORY PACKAGE - An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect. | 2012-05-03 |
| 20120106229 | Semiconductor device - To include stacked plural core chips, each of which includes a first through silicon via for transferring write data and a second through silicon via for transferring read data, and an interface chip commonly connected to the core chips. The interface chip includes a data input/output terminal, an input buffer provided between the data input/output terminal and the first through silicon via, and an output buffer provided between the data input/output terminal and the second through silicon via. With this configuration, the write data and the read data are transferred through the different through silicon vias, whereby the collision of data is not caused even when continuous accesses are made to different ranks. | 2012-05-03 |
| 20120106230 | SEMICONDUCTOR MEMORY DEVICE - The memory cell array has memory cells each positioned at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The resistance element may have at least a first resistance value ant a second resistance value higher than the first resistance value. The contact arrangement portion is formed to arrange a plurality of contacts on a plane. The contacts are connected to the first wirings or the second wirings. The probe can move along the plane to electrically contact with either of the contacts. | 2012-05-03 |
| 20120106231 | LOW-PIN-COUNT NON-VOLATILE MEMORY INTERFACE - A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. In one embodiment, the low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. Since the clock signal can be derived and shared from the system clock of the integrated circuit, the NVM memory need only have one external control pin for I/O transactions to realize a low-pin-count interface. | 2012-05-03 |
| 20120106232 | Memory Cells, Methods of Programming Memory Cells, and Methods of Forming Memory Cells - Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer. | 2012-05-03 |
| 20120106233 | REDUCED SWITCHING-ENERGY MAGNETIC ELEMENTS - A system includes a continuous thin-film ferromagnetic layer, N magnetic tunnel junction (MTJ) devices, and N write structures. The continuous thin-film ferromagnetic layer includes N modified regions. Each of the N modified regions is configured to stabilize a magnetic domain wall located in the continuous thin-film ferromagnetic layer. Each of the N MTJ devices includes one of N portions of the continuous thin-film ferromagnetic layer. Adjacent MTJ devices of the N MTJ devices are separated by one of the N modified regions. Each of the N write structures is configured to receive current and generate a magnetic field that magnetizes a different one of the N portions of the continuous thin-film ferromagnetic layer. N is an integer greater than 2. | 2012-05-03 |
| 20120106234 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating - Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described. | 2012-05-03 |
| 20120106235 | IMPLEMENTING PHYSICALLY UNCLONABLE FUNCTION (PUF) UTILIZING EDRAM MEMORY CELL CAPACITANCE VARIATION - A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor and a second EDRAM memory cell including a memory cell complement storage capacitor. The memory cell true storage capacitor and the memory cell complement storage capacitor include, for example, trench capacitors or metal insulator metal capacitors (MIM caps). A random variation of memory cell capacitance is used to implement the physically unclonable function. Each memory cell is connected to differential inputs to a sense amplifier. The first and second EDRAM memory cells are written to zero and then the first and second EDRAM memory cells are differentially sensed and the difference is amplified to consistently read the same random data. | 2012-05-03 |
| 20120106236 | TFET BASED 6T SRAM CELL - Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines. | 2012-05-03 |
| 20120106237 | BOOST CIRCUIT FOR GENERATING AN ADJUSTABLE BOOST VOLTAGE - A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost phase to generate a boost voltage. In this case, the boost voltage is applied to a driver circuit of the device only during the boost phase and at least one of the first and second voltages is adjustable, thereby making the boost voltage adjustable. | 2012-05-03 |
| 20120106238 | STATIC RANDOM-ACCESS CELL, ACTIVE MATRIX DEVICE AND ARRAY ELEMENT CIRCUIT - A static random-access memory (SRAM) cell which includes: a sampling switch and a feedback switch; and a first inverter and a second inverter connected in series whereby an output of the first inverter is connected to an input of the second inverter. An input of the first inverter is connected to a data input of the SRAM cell via the sampling switch, and to a data output of the SRAM cell independent of the feedback switch, an output of the second inverter is connected to the input of the first inverter via the feedback switch, and first and second clock inputs of the SRAM cell are configured to control the sampling switch and the feedback switch, respectively. | 2012-05-03 |
| 20120106239 | Magnetic Memory Element With Multi-Domain Storage Layer - An apparatus and method for enhancing data writing and retention to a magnetic memory element, such as in a non-volatile data storage array. In accordance with various embodiments, a programmable memory element has a reference layer and a storage layer. The reference layer is provided with a fixed magnetic orientation. The storage layer is programmed to have a first region with a magnetic orientation antiparallel to said fixed magnetic orientation, and a second region with a magnetic orientation parallel to said fixed magnetic orientation. A thermal assist layer may be incorporated into the memory element to enhance localized heating of the storage layer to aid in the transition of the first region from parallel to antiparallel magnetic orientation during a write operation. | 2012-05-03 |
| 20120106240 | COMPOUND CELL SPIN-TORQUE MAGNETIC RANDOM ACCESS MEMORY - A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals. | 2012-05-03 |
| 20120106241 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ METHOD - A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. | 2012-05-03 |
| 20120106242 | MEMORY APPARATUS HAVING STORAGE MEDIUM DEPENDENT ON TEMPERATURE AND METHOD FOR DRIVING THE SAME - A memory apparatus includes a temperature detection block configured to detect temperature of an internal circuit and output a temperature detection signal, a current control block configured to receive the temperature detection signal and generate a pulse control signal, and a write driver configured to provide a program pulse having a compensated level and width to a memory cell in response to the pulse control signal. | 2012-05-03 |
| 20120106243 | CURRENT CONTROL APPARATUS AND PHASE CHANGE MEMORY HAVING THE SAME - A current control apparatus of a phase change memory includes a temperature sensing block having an output voltage level which varies depending on temperature of an internal circuit and a write driver configured to control an amount of program current provided to a memory cell in response to the output voltage level of the temperature sensing block. | 2012-05-03 |
| 20120106244 | PHASE-CHANGE MEMORY DEVICE - A phase-change memory device and its firing method are provided. The firing method of the phase-change memory device includes applying a writing current to phase-change memory cells, identifying a state of the phase-change memory cells after applying the writing current, and applying a firing current, in which an additional current is added to the writing current, to the phase-change memory cells in accordance with the state. | 2012-05-03 |
| 20120106245 | THERMALLY ASSISTED MAGNETIC RANDOM ACCESS MEMORY ELEMENT WITH IMPROVED ENDURANCE - The present disclosure concerns a magnetic memory element suitable for a thermally-assisted switching write operation, comprising a current line in electrical communication with one end of a magnetic tunnel junction, the magnetic tunnel junction comprising: a first ferromagnetic layer having a fixed magnetization; a second ferromagnetic layer having a magnetization that can be freely aligned at a predetermined high temperature threshold; and a tunnel barrier provided between the first and second ferromagnetic layer; the current line being adapted to pass a heating current through the magnetic tunnel junction during the write operation; wherein said magnetic tunnel junction further comprises at least one heating element being adapted to generate heat when the heating current is passed through the magnetic tunnel junction; and a thermal barrier in series with said at least one heating element, said thermal barrier being adapted to confine the heat generated by said at least one heating element within the magnetic tunnel junction. | 2012-05-03 |
| 20120106246 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD OF WRITING THE SAME, AND SEMICONDUCTOR DEVICE - A control circuit is configured to be able to perform a rough write process, a foggy write process, and a fine write process. The rough write process moves, for a memory cell to be provided with a plurality of second threshold voltage distributions, a first threshold voltage distribution in the positive direction to generate a third threshold voltage distribution. The foggy write process does not move, for a memory cell finally to be provided with first data, the third threshold voltage distribution, and moves, for a memory cell finally to be provided with second data different from the first data, the first threshold voltage distribution or the third threshold voltage distribution in the positive direction to generate a plurality of fourth threshold voltage distributions. The fine write process moves the fourth threshold voltage distributions in the positive direction to generate the second threshold voltage distributions. | 2012-05-03 |
| 20120106247 | FLASH MEMORY DEVICE INCLUDING FLAG CELLS AND METHOD OF PROGRAMMING THE SAME - Provided is a flash memory device and a method of programming the same. The flash memory device includes a memory cell array, a first judgment circuit and a second judgment circuit. The memory cell array includes multiple main cells and multiple flag cells. The first judgment circuit judges program pass of the main cells, and the second judgment circuit judges program pass of the flag cells by applying a more strict judgment reference than the first judgment circuit. | 2012-05-03 |
| 20120106248 | NON-VOLATILE MULTILEVEL MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states. | 2012-05-03 |
| 20120106249 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL - Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. | 2012-05-03 |
| 20120106250 | METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES - Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching. | 2012-05-03 |
| 20120106251 | FLASH MEMORY DEVICE CONFIGURED TO SWITCH WORDLINE AND INITIALIZATION VOLTAGES - Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal. | 2012-05-03 |
| 20120106252 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A nonvolatile semiconductor memory device includes a first region, a second region, and a plurality of word lines. The first region includes a plurality of electrically-rewritable memory transistors. The second region is located around the first region. The plurality of word lines are connected to the gates of the plurality of memory transistors respectively. The plurality of word lines includes interconnection portions and connection portions respectively. The interconnection portions extend in a first direction to head from the first region to the second region and are arrayed in a second direction orthogonal to the first direction with a first distance therebetween. The connection portions are extending from the interconnection portions, located in the second region, and electrically connected to contacts, respectively. The ends of the plurality of connection portions are formed along straight lines extending in the second direction. | 2012-05-03 |
| 20120106253 | THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED ARRAY LINE MEMORY ARRAY - A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased. | 2012-05-03 |
| 20120106254 | MEMORY SYSTEM - According to one embodiment, a memory system includes a NAND flash memory, a first unit, and an second unit. Memory cells capable of holding data and management data as a first control signal. Memory cells are arranged in a matrix in the NAND flash memory. The first unit holds a second and a third signal. The second signal is made variable in accordance with an output frequency. The third signal is made variable. The second unit outputs the data to an outside in accordance with the first to third signals. The second unit includes a buffer unit including first to third transistors. The output frequency includes a first frequency and a second frequency. If the first to third transistors output the data to the outside in synchronization with the second frequency, the first to third transistors may be turned on regardless of a value of the first control signal. | 2012-05-03 |
| 20120106255 | VOLTAGE GENERATION CIRCUIT WHICH IS CAPABLE OF REDUCING CIRCUIT AREA - According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first boost circuit outputs a first voltage in first and second operation modes. The first output circuit is connected to the first boost circuit, and outputs the first voltage as a second voltage in the first operation mode. The rectifying circuit is connected to the first boost circuit, and outputs a third voltage which is lower than the first voltage in the first operation mode. The second output circuit short-circuits the rectifying circuit in the second operation mode, and outputs the first voltage as a fourth voltage. The detection circuit detects the second and fourth voltages which are supplied from the first and second output circuits. | 2012-05-03 |
| 20120106256 | ELECTRONIC CIRCUIT WITH A FLOATING GATE TRANSISTOR AND A METHOD FOR DEACTIVATING A FLOATING GATE TRANSISTOR TEMPORARILY - An electronic circuit includes a floating gate transistor with a floating gate capacitor. The floating gate transistor can be programmed to be in an ON or an OFF state by charging the floating gate capacitor. The circuit further includes a deactivation capacitor adapted to store a charge sufficient for deactivating the floating gate transistor temporarily. The deactivation capacitor is connectable in series to the floating gate capacitor. A method for deactivating a floating gate transistor temporarily is provided, wherein the floating gate transistor includes a floating gate capacitor. A deactivation capacitor is charged with a charge sufficient for changing the state of the floating gate transistor temporarily. The deactivation capacitor is connected in series to the floating gate capacitor for deactivating the floating gate transistor. | 2012-05-03 |
| 20120106257 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage. | 2012-05-03 |
| 20120106258 | READOUT CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - A readout circuit has a sense amplifier to compare a cell current which changes according to whether a memory cell is on or off with a reference current, to output a comparison signal of a first logic upon detecting that the cell current is smaller than the reference current, and to output a comparison signal of a second logic upon detecting that the cell current is greater than the reference current, the readout circuit outputting a data output signal depending upon an output of the sense amplifier. The reference current is set to be greater than a middle value between a first cell current which flows when the memory cell is in an off-state and a second cell current which flows when the memory cell is in an on-state and which is greater than the first cell current, and to be smaller than the second cell current. Unless the sense amplifier detects that the cell current is smaller than the reference current as a result of comparison made between the cell current and the reference current, the sense amplifier outputs the comparison signal of the second logic regardless of whether the sense amplifier detects that the cell current is greater than the reference current. | 2012-05-03 |
| 20120106259 | Adaptive Control of Programming Currents for Memory Cells - A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed in the first programming operation; and performing a second programming operation on the failed memory cells. Passed memory cells successfully programmed in the first programming operation are not programmed in the second programming operation. | 2012-05-03 |
| 20120106260 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells. | 2012-05-03 |
| 20120106261 | SYSTEMS AND METHODS FOR ERASING A MEMORY - Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase voltage, such as to tighten an erase distribution. Faster erasing cells have their erasing throttled using a positive bias on their access line once a particular number of cells coupled to the access line are erased to the intermediate erase voltage. | 2012-05-03 |
| 20120106262 | PROGRAMMING METHOD FOR NONVOLATILE MEMORY APPARATUS - Provided is a method for programming a nonvolatile memory apparatus which includes a bit line selector coupled to first and second bit lines and a page buffer including a main data transmission switch coupled to the bit line selector, a first latch coupled to the main data transmission switch, a temporary data transmission switch coupled to the bit line selector, and a second latch coupled between the temporary data transmission switch and the first latch. In the programming when the first bit line is precharged to a power supply voltage level, a main data transmission switch and a temporary data transmission switch are simultaneously turned on to set up a voltage of the second bit line depending on data levels stored in the first and second latches. | 2012-05-03 |
| 20120106263 | INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME - A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and configured to control input/output of signals between the controller and the semiconductor memory apparatus, wherein the input/output device operates in a normal mode which corresponds to the input/output of the signals between the controller operating at the first speed and the semiconductor memory apparatus and a test mode which corresponds to the input/output of the signals between the controller operating at the second speed and the semiconductor memory apparatus. | 2012-05-03 |
| 20120106264 | WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES - Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device. | 2012-05-03 |
| 20120106265 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a memory block configured to store a data inputted/outputted through a data transfer line, a data output block configured to output the data loaded on the data transfer line in response to a source clock, wherein the data output block is controlled to be coupled with the data transfer line in response to a write operation signal, a write operation signal generation block configured to generate the write operation signal in response to an operation selection signal and a reference clock lagging behind the source clock by a set time, and a data input block configured to load the data on the data transfer line in response to the write operation signal. | 2012-05-03 |
| 20120106266 | Apparatus For Measuring Data Setup/Hold Time - An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a flag signal generating unit for generating flag signals according to the internal clock signal and the data signals, and a counter for producing the counting signals in response to the flag signals. | 2012-05-03 |
| 20120106267 | CIRCUIT FOR GENERATING REFERENCE VOLTAGE OF SEMICONDUCTOR MEMORY APPARATUS - A reference voltage generating circuit in a semiconductor memory apparatus comprises a driving control signal generating unit configured to generate a driving control signal according to a temperature variation, wherein the driving control signal generating unit is enabled in response to a power-up signal, a driving unit configured to control a voltage level, which is applied to a voltage transfer node, in response to the power-up signal and the driving control signal, and a reference voltage generating unit configured to generate a reference voltage when a voltage level on the voltage transfer node is higher than a predetermined voltage level. | 2012-05-03 |
| 20120106268 | SYNCHRONOUS TYPE SEMICONDUCTOR STORAGE DEVICE AND DRAM - A synchronous type semiconductor storage device includes an array unit which includes a cell array and sense amplifiers. The synchronous type semiconductor storage device includes a read/write pulse generator which generates a read pulse signal and a write pulse signal according to a clock signal, the clock signal defining one cycle time of a read operation and a write operation with respect to the array unit as one cycle. The synchronous type semiconductor storage device includes a secondary amplifier which is activated according to the read pulse signal to read out data stored in the sense amplifiers through the read/write line. The synchronous type semiconductor storage device includes a write driver which is activated according to the write pulse signal to write data in the sense amplifiers through the read/write line. | 2012-05-03 |
| 20120106269 | MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME - The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver. | 2012-05-03 |
| 20120106270 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes first and second memory groups that each comprise memory cells and redundancy memory cells; first main page buffers assigned to the first memory group and second main page buffers assigned to the second memory group; first main page buffers and a first redundancy page buffer coupled between the first memory group and first internal data lines and configured to store data for the program or read operation of the memory cells and the redundancy memory cells; and a data transfer circuit configured to transfer data from a first main page buffer of the first main page buffers that corresponds to the defective column of the first memory group to the at least one second redundancy page buffer before the program operation and transfer data of the at least one second redundancy page buffer to the first main page buffer. | 2012-05-03 |
| 20120106271 | SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a redundancy signal generation unit configured to compare mat information set by fuse cutting with address information inputted from outside and generate a plurality of redundancy signals; a mat designation signal generation unit configured to generate a plurality of mat designation signals in response to the plurality of redundancy signals and a plurality of mat address signals; and a mat control signal generation group configured to enable one of the mat control signals in response to the plurality of mat designation signals. | 2012-05-03 |
| 20120106272 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a pattern data generator configured to generate certain pattern data in a training operation mode, and an output driver configured to drive the pattern data to output training data with a slew rate corresponding to an external command in the training operation mode. | 2012-05-03 |
| 20120106273 | SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a column control signal generator configured to generate a column control signal for a pair of bit lines corresponding to a data mask during a data mask operation; and a bit line sense amplifier configured to sense and amplify a voltage difference between the pair of bit lines and electrically couple the pair of bit lines to a pair of segment input/output lines in response to the column control signal. | 2012-05-03 |
| 20120106274 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a fourth delayed data strobe signal, and generate a data strobe enable signal in response to a CAS write signal, a CAS write latency signal and the first to fourth delayed data strobe signals, a latch control signal generation block configured to output the data strobe signal as a latch control signal during an enable period of the data strobe enable signal, and a data latch block configured to latch data in response to the latch control signal and output latched data. | 2012-05-03 |
| 20120106275 | RINGBACK CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A circuit for a semiconductor memory device includes: a filtering control signal generation unit configured to synchronize a seed signal activated in a pre-amble period of a data strobe signal with the data strobe signal and sequentially generate a plurality of filtering control signals in response to the seed signal; and a filtering signal output unit configured to generate a filtering signal for filtering the data strobe signal in response to the plurality of filtering control signals and a plurality of burst length (BL) control signals. | 2012-05-03 |
| 20120106276 | DATA STROBE SIGNAL GENERATION CIRCUIT - A data strobe signal generation circuit includes: an enable signal generation unit configured to decode a test signal and generate an enable signal; an internal clock generation unit configured to generate a rising clock signal and a falling clock signal in response to the test signal; and a data strobe signal output unit configured to selectively buffer first and second powers in response to the rising clock signal and the falling clock signal, and output a data strobe signal. | 2012-05-03 |
| 20120106277 | REFRESH OPERATION CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND REFRESH OPERATION CONTROL METHOD - A semiconductor memory device includes a bank including a first cell region and a second cell region, an active signal generation unit configured to generate a first row active signal and a second row active signal having different activation periods from each other in response to a refresh command, and an address counting unit configured to count the refresh command and generate a row address, wherein a word line of the first cell region designated by the row address is activated when the first row active signal is activated, and a word line of the second cell region designated by the row address is activated when the second row active signal is activated. | 2012-05-03 |
| 20120106278 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a plurality of banks, a clock input unit configured to receive an external data clock, an internal data clock generation unit configured to receive the external data clock from the clock input unit and generate an internal data clock by delaying the external data clock by a delay amount which changes in correspondence to the number of banks activated among the plurality of banks, and a data buffer unit configured to buffer a data signal in response to the internal data clock. | 2012-05-03 |
| 20120106279 | SEMICONDUCTOR MEMORY APPARATUS, MEMORY SYSTEM, AND PROGRAMMING METHOD THEREOF - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus includes a core block configured to receive and store external input data, a control unit configured to activate a control signal in response to a test mode signal and a command, when the external input data has a predetermined value, and a fuse circuit configured to perform fuse programming when the control signal is activated. | 2012-05-03 |
| 20120106280 | SELF-ADAPTIVE SENSING DESIGN - A clock signal having a clock pulse width duration is received. A delay time is received. A first relationship and a second relationship between the clock pulse width duration and the delay time are determined. A new clock is generated that has a first new clock pulse width duration determined by the first relationship and the delay time and a second new clock pulse width duration determined by the second relationship and the clock pulse width duration. Switching between the first new clock pulse width duration and the second new clock pulse width duration is automatic based on the first relationship and the second relationship. | 2012-05-03 |
| 20120106281 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR MEMORY SYSTEMS - A semiconductor memory device includes at least one memory cell block and at least one connection unit. The at least one memory cell block has a first region including at least one first memory cell connected to a first bit line, and a second region including at least one second memory cell connected to a second bit line. The at least one connection unit is configured to selectively connect the first bit line to a corresponding bit line sense amplifier based on a first control signal, and configured to selectively connect the second bit line to the corresponding bit line sense amplifier via a corresponding global bit line based on a second control signal. | 2012-05-03 |
| 20120106282 | PATTERN LAYOUT IN SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch. An interval between the line in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below. | 2012-05-03 |
| 20120106283 | Row Address Control Circuit Semiconductor Memory Device Including The Same And Method Of Controlling Row Address - A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided. | 2012-05-03 |
| 20120106284 | MEMORY POWER SUPPLY CIRCUIT - A memory power supply circuit includes a memory module, a micro control unit (MCU), a phase switch circuit, and a multi-phase pulse-width modulation (PWM) controller. The MCU is operable to determine required current to be supplied to the memory module and output corresponding phase switch signals to the phase switch circuit. The PWM controller includes a number of phase pins connected to the phase switch circuit. The phase switch circuit controls enable states of the phase pins of the PWM controller according to the phase switch signals. | 2012-05-03 |
| 20120106285 | CIRCUITS AND METHODS FOR REDUCING MINIMUM SUPPLY FOR REGISTER FILE CELLS - A register file employing a shared supply structure to improve the minimum supply voltage. | 2012-05-03 |
| 20120106286 | MEMORY CIRCUIT HAVING DECODING CIRCUITS AND METHOD OF OPERATING THE SAME - The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals. | 2012-05-03 |
| 20120106287 | Memory Arrangement for Accessing Matrices - A memory arrangement is provided having a plurality of memory elements, the elements being associated with a memory space that can be addressed in a row and column fashion during a write or a read access. The memory arrangement further includes a first macro bank comprising a first plurality of memory cells comprising a first subset of the memory elements and a second macro bank comprising a second plurality of memory cells comprising a second subset of the memory elements. The memory arrangement further includes an address resolution stage for addressing the memory cells in the respective macro banks. The memory cells are arranged so that the memory space is partitioned into a plurality of non-overlapping basic matrices, whereby each basic matrix is mapped to a given macro bank and wherein the memory cells are arranged logically so that the memory space is partitioned into a plurality of non-overlapping logic matrices of a given size, each logic matrix being of a size equal or larger than a basic matrix. | 2012-05-03 |
| 20120106288 | VACUUM KNEADING AND DEAERATING DEVICE - Disclosed is a vacuum kneading and deaerating device capable of conducting an uniform and sufficient kneading treatment and a sufficient deaerating treatment with a high efficiency for a paste material contained in a cylindrical paste container. | 2012-05-03 |
| 20120106289 | CASSETTE SYSTEM INTEGRATED APPARATUS - A cassette integrated system. The cassette integrated system includes a mixing cassette, a balancing cassette, a middle cassette fluidly connected to the mixing cassette and the balancing cassette and at least one pod. The mixing cassette is fluidly connected to the middle cassette by at least one fluid line and the middle cassette is fluidly connected to the balancing cassette by at least one fluid line. The at least one pod is connected to at least two of the cassettes wherein the pod is located in an area between the cassettes. | 2012-05-03 |
| 20120106290 | STATIC MIXER COMPRISING A STATIC MIXING ELEMENT, METHOD OF MIXING A FLUID IN A CONDUIT AND A FORMULA FOR DESIGNING SUCH A STATIC MIXING ELEMENT - Using the Mapping Method different designs of SMX motionless mixers are analyzed and optimized. The three design parameters that constitute a specific SMX design are: the number of cross-bars over the width of channel, Nx, the number of parallel cross-bars per element, Np, and the angle between opposite cross-bars θ. Optimizing Nx, somewhat surprisingly reveals that in the standard design with Np=3, Nx=6 is the optimum using both energy efficiency as well as compactness as criteria. Increasing Nx results in under-stretching and decreasing Nx leads to over-stretching of the interface. Increasing Np makes interfacial stretching more effective by co-operating vortices. Comparing realized to optimal stretching, we find the optimum series for all possible SMX(n) designs to obey the universal design rule Np=(⅔)Nx−1, for Nx=3, 6, 9, 12, . . . | 2012-05-03 |
| 20120106291 | METHOD FOR FUNCTIONAL TESTING OF AN ULTRASONIC SENSOR ON A MOTOR VEHICLE, METHOD FOR OPERATING AN ULTRASONIC SENSOR ON A MOTOR VEHICLE, AND DISTANCE MEASURING DEVICE HAVING AT LEAST ONE ULTRASONIC SENSOR FOR USE IN A MOTOR VEHICLE - In a method for functional testing of an ultrasonic sensor on a motor vehicle, the ultrasonic sensor is controlled in such a way that it emits an ultrasonic signal having a frequency of a secondary mode of the ultrasonic sensor, the ultrasonic signal is reflected by a surface in the region around the vehicle, and at least one transmission path or one transmitting unit of the ultrasonic sensor is classified as functional if the reflected signal is received by the ultrasonic sensor itself or by another ultrasonic sensor on the motor vehicle. | 2012-05-03 |
| 20120106292 | RESERVOIR MAPPING WITH FRACTURE PULSE SIGNAL - A method and system includes determining a subsurface fluid seismic attribute comprising recording a signal at a wellhead related to pumping fracture stimulation fluid to obtain a pressure pulse pump signal. A deconvolution operator is determined from the obtained pressure pulse pump signal. Seismic data are acquired from a plurality of sensors. Travel time differences are computed for the seismic data between the plurality of sensor locations and the subsurface position. Seismic data are deconvolved with the deconvolution operator to obtain a plurality of deconvolution coefficients associated with the subsurface position. The computed travel time differences are used to sum the plurality of deconvolution coefficients associated with the subsurface position to obtain a subsurface fluid seismic attribute at the subsurface position. | 2012-05-03 |
| 20120106293 | IMAGE BASED EFFECTIVE MEDIUM MODELING OF THE NEAR SURFACE EARTH FORMATION - This disclosure presents a method that utilizes the seismic image of the near-surface formation to estimate an effective velocity field equivalent to the unknown true velocity field of the soil column, such that the statics shifts derived from the effective velocity field are essentially the same as the statics shifts that would have been computed using the unknown true velocity field. The effective velocity field derived statics shifts can be used to correct distortions caused by the near-surface formation and restore the sesimic image of the subsurface formation. | 2012-05-03 |
| 20120106294 | Optimization Approach to Q-Factor Estimation From VSP Data - A zero-offset VSP survey is carried out with spaced apart receivers located in a vertical wellbore. Spectra of the signals at the receivers following wavefield separation are estimated. An absorption coefficient is estimated using differences in spectra between all pairs of receivers. | 2012-05-03 |
| 20120106295 | SEISMIC DATA VISUALIZATIONS - Embodiments of various technologies for a method for processing seismic data are disclosed. In one embodiment, a first portion of a record of pre-stack seismic data may be displayed in a three-dimensional XYZ (3-D XYZ) space. A selection may be received of a second portion of the record of the pre-stack seismic data within the first portion. One or more attributes may be determined that define the second portion. One or more regions may be identified within the record of the pre-stack seismic data having the attributes that define the second portion. | 2012-05-03 |
| 20120106296 | SEISMIC DATA ACQUISITION SYSTEM COMPRISING MODULES ASSOCIATED WITH UNITS CONNECTED TO SENSORS, THE MODULES BEING AUTONOMOUS WITH RESPECT TO POWER SUPPLY, SYNCHRONISATION AND STORAGE - A module for operation in a seismic data acquisition system is described. The seismic data acquisition system includes a cabled network with a plurality of acquisition lines having electronic units assembled in series along a telemetry cable. Each electronic unit is associated with at least one seismic sensor and processes signals transmitted by the sensor(s). The module is designed to be associated with at least one of the electronic units to provide power supply and synchronization to the electronic unit(s). The module includes: autonomous synchronization means; bidirectional and autonomous power supply means to power at least one electronic unit upstream and/or downstream from the module; and means for storing and processing the signals processed by the electronic units, the storage means being bidirectional to store the signals from at least one electronic unit upstream and/or downstream from the module. | 2012-05-03 |
| 20120106297 | DOWNHOLE APPARATUS, DEVICE, ASSEMBLY AND METHOD - A downhole assembly includes an apparatus for generating a fluid pressure pulse downhole. A disclosed apparatus for generating a fluid pressure pulse downhole includes an elongate, generally tubular housing defining an internal fluid flow passage and having a housing wall. The apparatus also includes a device for selectively generating a fluid pressure pulse, the device having a cartridge which can be releasably mounted entirely within a space provided in the wall of the tubular housing. The internal fluid flow passage defined by the tubular housing is a primary fluid flow passage. A secondary fluid flow passage has an inlet which communicates with the primary fluid flow passage. The cartridge houses a valve actuable to control fluid flow through the secondary fluid flow passage to selectively generate a fluid pressure pulse. Data relating to a measured downhole parameter or parameters can be transmitted to surface via the pressure pulses. | 2012-05-03 |
| 20120106298 | GESTURE RECOGNITION APPPARATUS AND METHOD - The disclosure provides a gesture recognition apparatus and method. The gesture recognition apparatus includes an ultrasound transmitter, an ultrasound receiver, a dividing module, a computing module, a gesture library, and a recognition module. The dividing module is configured to divide reflected ultrasound signals into a plurality of frames according to time intervals. The computing module is configured to obtain an eigenvalue of each frame. The classifying module is configured to filter the eigenvalues to obtain gesture eigenvalues, and to obtain a matrix of probabilities of the gesture eigenvalues. The recognition module is configured to search reference matrices of probabilities from the gesture library for matching with the matrix of probabilities, and to recognize the gesture eigenvalues as a reference gesture corresponding to the reference matrix of probabilities if the reference matrix of probabilities is found. | 2012-05-03 |
| 20120106299 | MULTI FREQUENCY 2D PHASED ARRAY TRANSDUCER - Improved two-dimensional planar array transducer and beamformer apparatus and methods. In one embodiment, the two-dimensional planar array transducer is capable of simultaneously or sequentially forming multiple acoustic beams in two axes and at two or more widely separated acoustic frequencies from a single flat planar array transducer. The transducer planar array consists of two or more electrically and acoustically independent two dimensional planar transducer array structures operating at different frequencies that are physically integrated onto a single multi frequency configuration. In an exemplary embodiment, a second higher frequency transducer array is positioned within the aperture area of a lower frequency planar array transducer. Methods of using the aforementioned two-dimensional planar array transducer and beamformer are also disclosed. | 2012-05-03 |
| 20120106300 | DOWNSCAN IMAGING SONAR - A sonar transducer assembly for mounting to a surface watercraft includes a rectangular first transducer configured to produce a first beam defining a fan-shape and extending generally in a first plane. The assembly further includes a rectangular second transducer configured to produce a second beam defining a fan-shape and extending generally in a second plane. The first transducer and the second transducer are oriented such that the respective first and second beams insonify different first and second areas each extending laterally with respect to a running direction of the surface watercraft, and such that the first beam is outside of the second plane of the second beam, the resulting planar separation of the first and second planes of the first and second beams reducing interference between the first and second transducers. | 2012-05-03 |
| 20120106301 | CALENDAR DISPLAY DEVICE AND CALENDAR WATCH - A calendar display device for a mechanical watch piece, including a first disk, the disk of days, carrying multiple series of inscriptions symbolizing the seven days of the week, a second disk, the disk of dates, carrying inscriptions symbolizing the date of the month, a third disk, the disk of months, carrying 12 inscriptions symbolizing the months of the year. One of the disk of days and the disk of dates acts as a dial by being fixed, whereas the other acts as a rotary disk by being arranged concentrically and rotatably in relation to the dial. The dial includes an aperture making it possible to see the inscription of the current month. A hand indicates simultaneously the date and the day of the week; and a direct kinematic link between the disk of months and the rotary disk provides automatic indexing. | 2012-05-03 |
| 20120106302 | CALENDAR DISPLAY DEVICE AND CALENDAR WATCH - A calendar display device for a mechanical watch piece including a first disk, the disk of days, carrying multiple series of inscriptions symbolizing the seven days of the week, a second disk, the disk of dates, carrying inscriptions symbolizing the date of the month, a third disk, the disk of months, carrying 12 inscriptions symbolizing the months of the year. One of the disk of days and the disk of dates acts as a dial by being fixed, whereas the other acts as a rotary disk by being arranged concentrically and rotatably in relation to the dial. The dial includes an aperture making it possible to see the inscription of the current month on the disk of months. A hand indicates simultaneously the date and the day of the week. The device includes a correction mechanism cooperating at least with a gear train bidirectionally driving the disk of months. | 2012-05-03 |
| 20120106303 | SPIRAL SPRING - A spiral spring ( | 2012-05-03 |
| 20120106304 | SYSTEM, METHOD AND APPARATUS FOR HOLDING MULTIPLE DEVICES - A consumer electronic system for concurrently holding and providing power to several consumer electronic devices has several cradles in a staggered configuration. At least one of the cradles is positioned behind at least one other of the cradles. Thereby the cradle positioned behind the at least one other cradles is capable of supporting a larger consumer electronic device without blocking the at least one other cradle. The support walls of the at least one other cradles provides a surface that supports the larger consumer electronic device, keeping the larger consumer electronic device from sliding forward. | 2012-05-03 |
| 20120106305 | Multilevel Recording Method and System Thereof - The present invention discloses a multilevel recording method and system thereof. The multilevel recording method applied to a recording media comprises the following steps. At First, a plurality of beams are provided to a recording layer of the recording media, and the recording layer has a first structure and a second structure. Then, a first polarized reflected light of the first structure and a second polarized reflected light of the second structure are detected by a detecting unit. Then, a corresponding table is stored by a storing unit. The corresponding table comprises a relationship between the different angle of the polarized reflected light and a level of multilevel recording. Finally, the processing unit looks up the corresponding table to process multilevel recording. | 2012-05-03 |
| 20120106306 | INTEGRATED CIRCUIT AND OPTICAL DISC APPARATUS - An integrated circuit is provided in an optical disc apparatus for drawing a visible image on an optical disc including a discoloration layer which is discolored by heat or light by irradiating the optical disc with laser light. The integrated circuit includes a tracking direction displacement section configured to execute, when the visible image is drawn, oscillation control to oscillate a position irradiated with the laser light in a radial direction of the optical disc, and a laser modulation section configured to change, when the visible image is drawn, an intensity of the laser light so that the higher a displacement rate of the position irradiated with the laser light in the radiation direction is, the higher the intensity of the laser light becomes. | 2012-05-03 |
| 20120106307 | OPTICAL DISC APPARATUS AND DEFOCUS CORRECTING METHOD - An optical disc apparatus in which a bias of a focusing error signal is changed to a value according to a recording power at timing corresponding to a predetermined address position before starting the recording and a defocus of an opposite polarity is preliminarily caused so as to set off a defocus which occurs at the start of the recording. | 2012-05-03 |
| 20120106308 | OPTICAL RECORDING MEDIUM AND RECORDING DEVICE - An optical recording medium in which recording is performed by a recording device that is configured such that tracking servo control of recording light is performed by irradiating the recording light and ATS light for an adjacent track servo and by an adjacent track servo based on reflected light of the ATS light, wherein while a recording layer in which a mark is formed according to an irradiation of the recording light is included, a mark row is formed in advance by a pitch that is twice a distance between an irradiation spot of the recording light and an irradiation spot of the ATS light or greater in the recording layer. | 2012-05-03 |
| 20120106309 | ELIMINATION OF DUPLICATE WRITTEN RECORDS - A storage device includes first and second buffers. A request to write a new record from a host is received. A hash value (new S) of the new record is calculated. The hash value (new S) of the new record is checked to determine if the hash value exists in a second buffer. If the new S exists in the second buffer, the new record is compared with a record stored in the second buffer corresponding to the new S to check if the new record and the stored record in the second buffer match each other. If the new record and the stored record match each other, a pointer (a record number) is written as write data of the new record to the recording medium. The pointer points to the record already stored in any one of a recording medium and the second buffer. | 2012-05-03 |
| 20120106310 | OPTICAL HEAD DEVICE AND OPTICAL DISC DEVICE - An optical head device mounted in an optical disc device. The optical head device is provided with a diffractive optical element and a photodetector. The diffractive optical element has: a primary diffraction region at a location on which the positive and negative first-order components and some of the zero-order component of a reflectively diffracted light beam are incident; and secondary diffraction regions at locations on which the rest of the zero-order component but none of the positive or negative first-order components of the reflectively diffracted light beam are incident. A main light-receiving section of the photodetector receives the zero-order component of a transmissively diffracted light beam that has passed through the primary diffraction region and the secondary diffraction regions. Secondary light-receiving sections receive the positive first-order component and/or the negative first-order component of the transmissively diffracted light beam that has passed through the secondary diffraction regions. | 2012-05-03 |
| 20120106311 | COMPATIBLE OPTICAL PICKUP AND OPTICAL INFORMATION STORAGE MEDIUM APPARATUS USING THE SAME - An optical pickup and an information storage medium system using the same. The optical pickup includes a light source that emits light having a plurality of different wavelengths. The optical pickup includes a diffraction device having a plurality of diffraction patterns corresponding to the plurality of different wavelengths to divide the light incident from the light source unit into main light and sub light. The optical pickup further includes a photo-detector having a first main light reception unit that receives the main light and a first sub light reception unit that receives the sub light so as to detect an information signal and/or an error signal by receiving reflected light. The first sub light reception unit of the photo-detector is shaped so as to reduce reception of noise sub light due to diffraction based on an undesired diffraction pattern of sub light generated the diffraction device. | 2012-05-03 |
| 20120106312 | OPTICAL PICKUP DEVICE - A first laser light source emits first laser light of a predetermined wavelength, and a second laser light source emits second laser light of a wavelength different from the wavelength of the first laser light. Reflected light of the first and second laser light is entered into an astigmatism portion. The astigmatism portion generates first and second focal lines. A light separating portion separates light fluxes of the reflected light of the first and second laser light from each other, the light fluxes obtained by dividing the reflected light of the first and second laser light into four light fluxes. The light separating portion is constituted of at least one prism having plural slopes, and the photodetector is provided with a common sensor portion which receives the light fluxes of the reflected light of the first and second laser light. | 2012-05-03 |
| 20120106313 | Optical Disk Device and Optical Disk Discriminating Method - An optical disk discriminating method and an optical disk device which can detect reflected rays for making discrimination among kinds of optical disks with high accuracies. By switching a plurality of lasers and moving a spherical aberration corrector while moving an objective lens to cause it to approach or keep away from an optical disk, rays reflected light from the optical disk can be detected with high accuracies. Discrimination among the kinds of a plurality of optical disks can be made on the basis of signals generated from the detected reflected rays. This ensures that the kind of an optical disk can be determined through one operation of sweeping. | 2012-05-03 |
| 20120106314 | HIGH DENSITY DATA STORAGE MEDIUM, METHOD AND DEVICE - A composition of matter for the recording medium of nanometer scale thermo-mechanical information storage devices and a nanometer scale thermo-mechanical information storage device. The composition includes: one or more polyaryletherketone polymers, each of the one or more polyaryletherketone polymers having two terminal ends, each terminal end having two or more phenylethynyl moieties. The one or more polyaryletherketone polymers are thermally cured and the resulting cross-linked polyaryletherketone resin used as the recording layers in atomic force data storage devices. | 2012-05-03 |
| 20120106315 | Efficient Generation of Compensated Signals for Crosstalk Control in a Communication System - An access node of a communication system is configured to control crosstalk between channels of the system. Vectoring circuitry in the access node estimates crosstalk between channels of the system, generates a compressed representation of the crosstalk estimates, and generates compensated signals based on the compressed representation of the crosstalk estimates. The compressed representation comprises a value array and an index array, with the value array comprising selected values from each of a plurality of rows of a matrix representation of the crosstalk estimates, and the index array identifying locations of the selected values in the matrix representation of the crosstalk estimates. The compensated signals may be pre-compensated signals or post-compensated signals. | 2012-05-03 |
