| 18th week of 2012 patent applcation highlights part 20 |
| Patent application number | Title | Published |
|---|
| 20120104514 | Semiconductor Devices and Methods of Manufacturing the Same - Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer. | 2012-05-03 |
| 20120104515 | TRANSISTORS AND SEMICONDUCTOR DEVICES WITH OXYGEN-DIFFUSION BARRIER LAYERS - Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material. | 2012-05-03 |
| 20120104516 | METAL SILICIDE FORMATION - Techniques for forming metal silicide contact pads on semiconductor devices are disclosed, and in one exemplary embodiment, a method may comprise depositing a metal layer on and between a plurality of raised silicon-based features formed on a semiconductor substrate, the metal layer comprising metal capable of reacting with external silicon-based portions of the features to form a metal silicide. In addition, such a method may also include depositing a cap layer on the metal layer deposited on and between the plurality of raised silicon-based features, wherein a thickness of the cap layer on the metal layer between the raised features is greater than or equal to a thickness of the cap layer on the metal layer on the raised features. Furthermore, such a method may also include annealing the structure to cause portions of the metal layer to react with portions of the external silicon-based portions of the features to form metal silicide pads on and between the raised features. | 2012-05-03 |
| 20120104517 | PACKAGE STRUCTURE WITH MICRO-ELECTROMECHANICAL ELEMENT AND MANUFACTURING METHOD THEREOF - A package structure includes a micro-electromechanical element having a plurality of electrical contacts; a package layer enclosing the micro-electromechanical element and the electrical contacts, with a bottom surface of the micro-electromechanical element exposed from a lower surface of the package layer; a plurality of bonding wires embedded in the package layer, each of the bonding wires having one end connected to one of the electrical contacts, and the other end exposed from the lower surface of the package layer; and a build-up layer structure provided on the lower surface of the package layer, the build-up layer including at least one dielectric layer and a plurality of conductive blind vias formed in the dielectric layer and electrically connected to one ends of the bonding wires. The package structure is easier to accurately control the location of an external electrical contact, and the compatibility of the manufacturing procedures is high. | 2012-05-03 |
| 20120104518 | PRESSURE SENSOR - A pressure sensor has a sensor body at least partly formed with an electrically insulating material, particularly a ceramic material, defining a cavity facing on which is a diaphragm provided with an electric detector element, configured for detecting a bending of the diaphragm. The sensor body supports a circuit arrangement, including, a plurality of circuit components, among which is an integrated circuit, for treating a signal generated by the detection element. The circuit arrangement includes tracks made of electrically conductive material directly deposited on a surface of the sensor body made of electrically insulating material. The integrated circuit is made up of a die made of semiconductor material directly bonded onto the surface of the sensor body and the die is connected to respective tracks by means of wire bonding, i.e. by means of thin connecting wires made of electrically conductive material. | 2012-05-03 |
| 20120104519 | MEMS DEVICE HAVING A MOVABLE ELECTRODE - A microelectromechanical system (MEMS) device includes a semiconductor substrate, a MEMS including a fixed electrode and a movable electrode formed on the semiconductor substrate through an insulating layer, and a well formed in the semiconductor substrate below the fixed electrode. The well is one of an n-type well and a p-type well. The p-type well applies a positive voltage to the fixed electrode while the n-type well applies a negative voltage to the fixed electrode. | 2012-05-03 |
| 20120104520 | MEMS SENSOR - An MEMS sensor includes: a functional layer having a sensor section; a wiring substrate disposed facing the functional layer and having a conduction pathway for the sensor section; a first metal layer provided on the surface of the sensor section which faces the wiring substrate; and a second metal layer provided on the surface of the wiring substrate which faces the sensor section, wherein the first and second metal layers are joined to each other, a space is formed between a movable portion of the sensor section and the wiring substrate, and a stopper which is composed of a third metal layer being the same film as the first metal layer formed on the functional layer side and a contact portion formed on the wiring substrate side which come into contact with each other is formed between the functional layer and the wiring substrate. | 2012-05-03 |
| 20120104521 | METHOD AND SYSTEM FOR ETCHING A DIAPHRAGM PRESSURE SENSOR - A method for etching a diaphragm pressure sensor based on a hybrid anisotropic etching process. A substrate with an epitaxial etch stop layer can be etched utilizing an etching process in order to form a diaphragm at a selective portion of the substrate. The diaphragm can be oriented at an angle (e.g., 45 degree) with respect to the substrate in order to avoid an uncertain beveled portion in a stress/strain field of the diaphragm. The diaphragm can be further etched utilizing an etch finishing process to create an anisotropic edge portion on the major areas of the diaphragm and optimize the thickness and size of the diaphragm. Such an approach provides an enhanced diaphragm structure with respect to a wide range of pressure sensor applications. | 2012-05-03 |
| 20120104522 | MAGNETIC TUNNEL JUNCTION CELLS HAVING PERPENDICULAR ANISOTROPY AND ENHANCEMENT LAYER - A magnetic tunnel junction cell that includes a ferromagnetic free layer; an enhancement layer having a thickness of at least about 15 Å; an oxide barrier layer; and a ferromagnetic reference layer, wherein the enhancement layer and the oxide barrier layer are positioned between the ferromagnetic reference layer and ferromagnetic free layer and the oxide barrier layer is positioned adjacent the ferromagnetic reference layer, and wherein the ferromagnetic free layer, the ferromagnetic reference layer, and the enhancement layer all have magnetization orientations that are out-of-plane | 2012-05-03 |
| 20120104523 | Solid-state imaging device manufacturing method of solid-state imaging device, and electronic apparatus - A solid-state imaging device includes a substrate, a photodiode region which is formed in the substrate and generates a signal charge using photoelectric conversion of light which is incident from a back surface side of the substrate, a wiring layer which is formed on a front surface side of the substrate which is a side opposite to a light incidence surface, a light-blocking wiring which is formed in the wiring layer and is formed in a region which covers at least a portion of the photodiode region, and a connection portion which supplies a predetermined voltage from the light-blocking wiring to the photodiode region. | 2012-05-03 |
| 20120104524 | Wiring Substrate, Imaging Device and Imaging Device Module - A imaging device includes a first insulating substrate having a through hole, a connection electrode and a first wiring conductor, a second insulating substrate having outside terminals and a second wiring conductor, and an imaging element including a light-receiving portion arranged at a center portion on an upper surface thereof and a connection terminal arranged at an outer peripheral portion thereof, at least one of the lower surface of the first insulating substrate and the upper surface of the second insulating substrate including a recess portion, the through hole being located on an inner side thereof, the imaging element being arranged below the first insulating substrate such that the light-receiving portion is located within the through hole, the connection terminal being electrically connected to the connection electrode, the imaging element being accommodated inside the recess portion, outer peripheral portions of the first insulating substrate and the second insulating substrate being electrically connected to each other. | 2012-05-03 |
| 20120104525 | IMAGE SENSOR WITH COLOR PIXELS HAVING UNIFORM LIGHT ABSORPTION DEPTHS - An example image sensor includes first, second, and third micro-lenses. The first micro-lens is in a first color pixel and has a first curvature and a first height. The second micro-lens is in a second color pixel and has a second curvature and a second height. The third micro-lens is in a third color pixel and has a third curvature and a third height. The first curvature is the same as both the second curvature and the third curvature and the first height is greater than the second height and the second height is greater than the third height, such that light absorption depths for the first, second, and third color pixels are the same. | 2012-05-03 |
| 20120104526 | IMAGER MODULE OPTICAL FOCUS AND ASSEMBLY METHOD - An imager apparatus and methods are described. An embodiment of an imager module includes a plurality of groups of optical lenses, a lens frame, and at least one associated lens barrel configured to position and hold the plurality of groups of optical lenses. At least one of the groups of optical lenses is movable with respect to at least one other group of optical lenses for achieving optical focus. The imager module includes an integrated circuit (IC) imager die in proximity to the plurality of lenses, the imager die containing at least one image capture microelectronic device. | 2012-05-03 |
| 20120104527 | SEMICONDUCTOR IMAGING INSTRUMENT AND MANUFACTURING METHOD THEREOF, AND CAMERA AND MANUFACTURING METHOD THEREOF - A semiconductor imaging instrument is disclosed, including a prescribed substrate, an imaging device array provided on the substrate and having plural semiconductor imaging devices and electrodes for outputting a signal charge upon photoelectric conversion of received light, and a color filter layer provided on the imaging device array, with an infrared light absorbing dye being contained in the color filter layer. | 2012-05-03 |
| 20120104528 | WAFER-LEVEL PACKAGED MICROELECTRONIC IMAGERS AND PROCESSES FOR WAFER-LEVEL PACKAGING - The following disclosure describes several embodiments of (1) methods for wafer-level packaging of microelectronic imagers, (2) methods of forming electrically conductive interconnects in microelectronic imagers, (3) methods for forming optical devices for microelectronic imagers, and (4) microelectronic imagers that have been packaged using wafer-level packaging processes. Wafer-level packaging of microelectronic imagers is expected to significantly enhance the efficiency of manufacturing microelectronic imagers because a plurality of imagers can be packaged simultaneously using highly accurate and efficient processes developed for packaging semiconductor devices. Moreover, wafer-level packaging of microelectronic imagers is expected to enhance the quality and performance of such imagers because the semiconductor fabrication processes can reliably align an optical device with an image sensor and space the optical device apart from the image sensor by a desired distance with a higher degree of precision. | 2012-05-03 |
| 20120104529 | COLORED COMPOSITION FOR LIGHT-SHIELDING FILM, LIGHT-SHIELDING PATTERN, METHOD FOR FORMING THE SAME, SOLID-STATE IMAGE SENSING DEVICE, AND METHOD FOR PRODUCING THE SAME - The present invention provides a colored composition for a light-shielding film including at least one selected from titanium atom-containing black titanium pigments and at least one organic pigment selected from the group consisting of a red organic pigment, a yellow organic pigment, a violet organic pigment, and an orange color organic pigment, which has a maximum value of the transmittance of light having a wavelength of 400 to 700 nm of 1.5% or less when a film is formed such that the light transmittance at a wavelength of 650 nm is 0.2%, has a wavelength showing the maximum transmittance at 400 to 550 nm, and has a light transmittance at a wavelength of 400 nm of 0.1% or more. | 2012-05-03 |
| 20120104530 | SUBSTRATE FOR DISPLAY PANEL, AND DISPLAY DEVICE - A display panel substrate includes a plurality of pixels, a pixel in the display panel substrate including a PIN diode for conducting therethrough a different electric current in accordance with an amount of light received by the light receiving element, a first inorganic insulating film formed on the PIN diode, a line formed on or above the first inorganic insulating film and electrically connected to the PIN diode, an organic insulating film formed on or above the line, a transparent pixel electrode formed on the organic insulating film, and a transparent cover electrode provided at such a position that the transparent electrode is located between the organic insulating film and the first inorganic insulating film and formed to cover at least a part of an I-layer of the PIN diode. | 2012-05-03 |
| 20120104531 | AVALANCHE PHOTODIODES AND METHODS OF FABRICATING THE SAME - Provided are an avalanche photodiode and a method of fabricating the same. The method of fabricating the avalanche photodiode includes sequentially forming a compound semiconductor absorption layer, a compound semiconductor grading layer, a charge sheet layer, a compound semiconductor amplification layer, a selective wet etch layer, and a p-type conductive layer on an n-type substrate through a metal organic chemical vapor deposition process. | 2012-05-03 |
| 20120104532 | LOW CROSSTALK, FRONT-SIDE ILLUMINATED, BACK-SIDE CONTACT PHOTODIODE ARRAY - The present application is directed to novel front side illuminated, back side contact photodiodes and arrays thereof. In one embodiment, the photodiode has a substrate with at least a first and a second side and a plurality of electrical contacts physically confined to the second side. The electrical contacts are in electrical communication with the first side through a doped region of a first type and a doped region of a second type, each of the regions substantially extending from the first side through to the second side. In another embodiment, the photodiode comprises a wafer with at least a first and a second side; and a plurality of electrical contacts physically confined to the second side, where the electrical contacts are in electrical communication with the first side through a diffusion of a p+ region through the wafer and a diffusion of an n+ region through the wafer. | 2012-05-03 |
| 20120104533 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk) so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate. | 2012-05-03 |
| 20120104534 | IMAGE SENSOR INCLUDING GUARD RING AND NOISE BLOCKING AREA TO BLOCK NOISE AND METHOD OF MANUFACTURING THE SAME - An image sensor including a deep guard ring and a noise blocking area and a method of manufacturing the same. The image sensor includes the deep guard ring and a deep P well surrounding the noise blocking area, thereby preventing crosstalk between adjacent pixels. In addition, an ion implantation layer is divided by the noise blocking area, so that substrate crosstalk is effectively eliminated. | 2012-05-03 |
| 20120104535 | PHOTODETECTOR - A photodetector includes a substrate, a first electrode layer, a first light absorbing layer, a second electrode layer, a second light absorbing layer, and a third electrode layer that are laminated on the substrate, a first electrode wire that intercouples the first electrode layer and the second electrode layer, a second electrode wire that intercouples the second electrode layer and the third electrode layer, a first diode formed at a place where the second electrode layer and the first electrode wire are mutually brought into contact, and a second diode formed at a place where the second electrode layer and the second electrode wire are mutually brought into contact. | 2012-05-03 |
| 20120104536 | Imaging device package, method of manufacturing the imaging device package, and electronic apparatus - An imaging device package includes: an imaging device chip; a substrate on which the imaging device chip is mounted; a wire that electrically connects the imaging device chip and the substrate at a peripheral edge of the substrate around the imaging device chip; a supporting body that supports an optical member with respect to the substrate; and a bonding section that bonds the supporting body to the substrate while sealing the wire and a bonding terminal of the wire at the peripheral edge of the substrate. | 2012-05-03 |
| 20120104537 | Semiconductor Device and a Method for Manufacturing a Semiconductor Device - A semiconductor device and a method for forming a semiconductor device are provided. The semiconductor device includes a semiconductor body with a first semiconductor region and a second semiconductor region spaced apart from each other. A first metallization is in contact with the first semiconductor region. A second metallization is in contact with the second semiconductor region. An insulating region extends between the first semiconductor region and the second semiconductor region. A semi-insulating region having a resistivity of about 10 | 2012-05-03 |
| 20120104538 | DAMASCENE METHOD OF FORMING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE WITH MULTIPLE FIN-SHAPED CHANNEL REGIONS HAVING DIFFERENT WIDTHS - Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET. | 2012-05-03 |
| 20120104539 | TRENCHES WITH REDUCED SILICON LOSS - An isolation trench in a substrate of a semiconductor device includes a first shallow portion with a dielectric sidewall and a second deeper portion without a dielectric sidewall. The isolation trench is formed by forming a first shallow portion of the trench, forming dielectric sidewalls on the first shallow portion, and then etching the substrate below the first shallow portion to form the second deeper portion. Shallow isolation trenches may be formed simultaneously with the etching of the second deeper portion. | 2012-05-03 |
| 20120104540 | TRENCH WITH REDUCED SILICON LOSS - An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on the first shallow portion, and then etching the second deeper portion. | 2012-05-03 |
| 20120104541 | SEAL RING STRUCTURE WITH POLYIMIDE LAYER ADHESION - The present disclosure provides a semiconductor device, including a substrate having a seal ring region and a circuit region, a seal ring structure disposed over the seal ring region, a first passivation layer disposed over the seal ring structure, the first passivation layer having a first passivation layer aperture over the seal ring structure, and a metal pad disposed over the first passivation layer, the metal pad coupled to the seal ring structure through the first passivation layer aperture and having a metal pad aperture above the first passivation layer aperture. The device further includes a second passivation layer disposed over the metal pad, the second passivation layer having a second passivation layer aperture above the metal pad aperture, and a polyimide layer disposed over the second passivation layer, the polyimide layer filling the second passivation layer aperture to form a polyimide root at an exterior tapered edge of the polyimide layer. | 2012-05-03 |
| 20120104542 | Semiconductor Structure With Contact Structure and Manufacturing Method of the Same - The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface. | 2012-05-03 |
| 20120104543 | HIGH-SPEED MEMORY SOCKETS AND INTERPOSERS - High-speed memory systems that consume a reduced amount of board space, have a low height or profile, or both. This reduction in board space and height may result in shorter signal paths from a board to a memory device, thereby improving the high-speed performance of the high-speed memory system. One example may provide a space-efficient memory system that consumes a reduced amount of board space. Space efficiency may gained by arraying memory devices on an interposer that mates with a socket attached to a board. Another example may provide a memory system that has a reduced height or profile. This reduced height may be achieved by employing a socket that accepts an interposer in a lateral or rotational direction. | 2012-05-03 |
| 20120104544 | SEMICONDUCTOR DEVICE - A semiconductor device adapted such that written information cannot be analyzed even by using a method of analyzing the presence or absence of electric charge, accumulated on a gate electrode, in which a substrate is a first conduction type, for example, p-type semiconductor substrate (for example, silicon substrate), an antifuse has a gate electrode and a second conduction type diffusion layer, the second conduction type diffusion layer is formed in the substrate and has, for example, an n-conduction type, a first contact is connected to the gate electrode, second contacts are formed in a layer identical with the first contact and connected to a region of the substrate in which the second conduction type diffusion layer is not formed, and the second contact is adjacent to the first contact. | 2012-05-03 |
| 20120104545 | Anti-Fuse Element - An anti-fuse element that includes a capacitance unit having an insulation layer and at least a pair of electrode layers formed on upper and lower surfaces of the insulation layer. The capacitance unit has a protection function against electrostatic discharge. Because the capacitance unit has a protection function against electrostatic discharge, an anti-fuse element can be provided which is less likely to cause insulation breakdown due to electrostatic discharge at the time of, for example, mounting a component. | 2012-05-03 |
| 20120104546 | STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME - Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical. | 2012-05-03 |
| 20120104547 | LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure. | 2012-05-03 |
| 20120104548 | Semiconductor Capacitor with Large Area Plates and a Small Footprint that is Formed with Shadow Masks and Only Two Lithography Steps - A semiconductor capacitor with large area plates and a small footprint is formed on a semiconductor wafer by forming an opening in the wafer, depositing a first metal atoms through a first shadow mask that lies spaced apart from the wafer to form a first metal layer in the opening, a dielectric layer on the first metal layer, and a second metal atoms through a second shadow mask that lies spaced apart from the wafer to form a second metal layer on the dielectric layer. | 2012-05-03 |
| 20120104549 | MEMORY DEVICE AND FABRICATION THEREOF - The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate surface and a word line coupling the capacitor. In an embodiment, the C-shaped capacitor is a stack capacitor. Both inner edge and outer edge of the C-shaped capacitor can be used for providing capacitance. | 2012-05-03 |
| 20120104550 | HIGH ASPECT RATIO CONTACTS - A contact formed in accordance with a process for etching a insulating material to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating material to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an aspect ratio of less than 15:1. Secondly, the insulating material is exposed to a first plasma of a first gaseous etchant having at least fifty percent helium (He) to etch the opening having an aspect ratio of at least 15:1, thereby increasing the aspect ratio to greater than 15:1, | 2012-05-03 |
| 20120104551 | EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE - Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with independent electrode contacts. In the method, a series of capacitors are formed by forming a plurality of insulator layers and a plurality of electrodes in a trench structure, where each electrode is formed in an alternating manner with each insulator layer. The method further includes planarizing the electrodes to form contact regions for a plurality of capacitors. | 2012-05-03 |
| 20120104552 | Capacitors in Integrated Circuits and Methods of Fabrication Thereof - In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line. | 2012-05-03 |
| 20120104553 | Semiconductor device - A semiconductor device in which only the trigger voltage can be controlled without change in the hold voltage. In the semiconductor device, a protection device includes a lower doped collector layer, a sinker layer, a highly-doped collector layer, an emitter layer, a highly-doped base layer, a base layer, a first conductivity type layer, and a second conductivity type layer. The second conductivity type layer is formed in the lower doped collector layer and located between the base layer and first conductivity type layer. The second conductivity type layer has a higher impurity concentration than the lower doped collector layer. | 2012-05-03 |
| 20120104554 | FLEXIBLE AND ON WAFER HYBRID PLASMA-SEMICONDUCTOR TRANSISTORS - Preferred embodiment flexible and on wafer hybrid plasma semiconductor devices have at least one active solid state semiconductor region; and a plasma generated in proximity to the active solid state semiconductor region(s). Doped solid state semiconductor regions are in a thin flexible solid state substrate, and a flexible non conducting material defining a microcavity adjacent the semiconductor regions. The flexible non conducting material is bonded to the thin flexible solid state substrate, and at least one electrode is arranged with respect to said flexible substrate to generate a plasma in said microcavity, where the plasma will influence or perform a semiconducting function in cooperation with said solid state semiconductor regions. A preferred on-wafer device is formed on a single side of a silicon on insulator wafer and defines the collector (plasma cavity), emitter and base regions on a common side, which provides a simplified and easy to manufacture structure. A preferred embodiment array of flexible hybrid plasma transistors of the invention is an n+pn PBJT fabricated between two flexible sheets. One or both of the flexible sheets is transparent. The overall array structure is planar, and the planarized structure is sealed between the two flexible sheets. Visible or ultraviolet light is emitted during operation by plasma collectors in the array. In preferred embodiments, individual PBJTs in the array serve as sub-pixels of a full-color display. | 2012-05-03 |
| 20120104555 | Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances - This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode. | 2012-05-03 |
| 20120104556 | POWER DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present power device includes a metal-made support substrate, and a group III nitride conductive layer, a group III nitride active layer and an electrode successively formed on one main surface side of the metal-made support substrate. In addition, the present method for manufacturing a power device includes the steps of preparing a conductive-layer-joined metal-made support substrate in which a group III nitride conductive layer is joined to a metal-made support substrate, forming a group III nitride active layer on the group III nitride conductive layer, and forming an electrode on the group III nitride active layer. Thus, an inexpensive power device low in on-resistance and a method for manufacturing the same can be provided. | 2012-05-03 |
| 20120104557 | Method for manufacturing a group III nitride crystal, method for manufacturing a group III nitride template, group III nitride crystal and group III nitride template - A method for manufacturing a group III nitride crystal includes a step of mixing a group III source material and ammonia in a reactor including quartz, and growing a group III nitride crystal on a support substrate by a vapor deposition. The group III source material is an organic metal source material containing Al. The organic metal source material is mixed with a hydrogen halide gas and the mixture of the organic metal source material and the hydrogen halide gas is supplied to the reactor. | 2012-05-03 |
| 20120104558 | III NITRIDE SEMICONDUCTOR SUBSTRATE, EPITAXIAL SUBSTRATE, AND SEMICONDUCTOR DEVICE - In a semiconductor device | 2012-05-03 |
| 20120104559 | Semiconductor Device Having Island Type Support Patterns - A semiconductor device includes a plurality of cylindrical structures arranged in a first direction and a second direction, and a plurality of unit regions formed in the first direction and the second direction, each of the plurality of unit regions including an island type support pattern supporting the plurality of cylindrical structures contacting side surfaces of the plurality of cylindrical structures and an open region exposing the side surfaces of the plurality of cylindrical structures. | 2012-05-03 |
| 20120104560 | SEMICONDUCTOR DEVICE HAVING A THROUGH ELECTRODE - A semiconductor device | 2012-05-03 |
| 20120104561 | Structures for Preventing Cross-talk Between Through-Silicon Vias and Integrated Circuits - A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring. | 2012-05-03 |
| 20120104562 | Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die - A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer. | 2012-05-03 |
| 20120104563 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a second oxide film and a pad electrode on a first oxide film that is formed on a front surface of a semiconductor substrate, a contact electrode and a first barrier layer formed in the second oxide film and connected to the pad electrode, a silicide portion formed between the contact electrode and a through-hole electrode layer and connected to the contact electrode and the first barrier layer, a via hole extending from a back surface of the semiconductor substrate to reach the silicide portion and the second oxide film, a third oxide film formed on a sidewall of the via hole and on the back surface of the semiconductor substrate, and a second barrier layer and a rewiring layer formed inside the via hole and on the back surface of the semiconductor substrate and connected to the silicide portion. | 2012-05-03 |
| 20120104564 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent. | 2012-05-03 |
| 20120104565 | EPITAXIAL WAFER AND METHOD FOR PRODUCING THE SAME - When a mixed gas of trichlorosilane and dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 1000 to 1100° C., preferably, 1040 to 1080° C. When dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 900 to 1150° C., preferably, 1000 to 1150° C. According to this, a silicon epitaxial wafer, which has low haze level, excellent flatness (edge roll-off), and reduced orientation dependence of epitaxial growth rate, and is capable of responding to the higher integration of semiconductor devices, can be obtained, and this epitaxial wafer can be used widely in production of semiconductor devices. | 2012-05-03 |
| 20120104566 | PASSIVATION LAYER STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a passivation layer structure of a semiconductor device for disposed on a semiconductor substrate is provided, which includes a passivation layer structure disposed on the semiconductor substrate, wherein the passivation layer structure includes a halogen-doped aluminum oxide layer. According to an embodiment of the invention, a method for forming a passivation structure of a semiconductor device is provided. | 2012-05-03 |
| 20120104567 | IIIOxNy ON REO/Si - An insulative layer on a semiconductor substrate and a method of fabricating the structure includes the steps of depositing a single crystal layer of rare earth oxide on a semiconductor substrate to provide electrical insulation and thermal management. The rare earth oxide is crystal lattice matched to the substrate. A layer of single crystal IIIO | 2012-05-03 |
| 20120104568 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently processed to manufacture an SOI substrate, so that an area of a semiconductor device can be increased and a semiconductor device can be manufactured with improved efficiency. In specific, a series of processes is performed using a tray with which a plurality of semiconductor substrates can be concurrently processed. Here, the tray is provided with at least one depression for holding single crystal semiconductor substrates. Further, deterioration of characteristics of a manufactured semiconductor element is prevented by providing an insulating layer serving as a barrier layer against an impurity element which may affect characteristics of the semiconductor element. | 2012-05-03 |
| 20120104569 | INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF - An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges. | 2012-05-03 |
| 20120104570 | SEMICONDUCTOR PACKAGE MODULE - There is provided a semiconductor package module allowing a shield of a semiconductor package to be easily grounded and securing bonding reliability between the shield and a ground pattern. The semiconductor package module includes a semiconductor package having a shield formed on an upper surface thereof and side surfaces thereof; a main substrate having at least one ground electrode formed on a surface thereof and having the semiconductor package mounted thereon; and a bonding part bonding the ground electrode to the shield to electrically connect the ground electrode to the shield. | 2012-05-03 |
| 20120104571 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes. | 2012-05-03 |
| 20120104572 | SEMICONDUCTOR PACKAGE MODULE - There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate. | 2012-05-03 |
| 20120104573 | Semiconductor Device and Method of Shielding Semiconductor Die from Inter-Device Interference - A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion of the gap. An insulating material is deposited in the gap and over the semiconductor die. A portion of the insulating material in the gap is removed to form a recess between each semiconductor die extending to the conductive material. A shielding layer is formed over the insulating material and in the recess to contact the conductive material. The shielding layer isolates the semiconductor die from inter-device interference. A substrate is formed as a build-up structure on the semiconductor die adjacent to the conductive material. The conductive material electrically connects to a ground point in the substrate. The gap is singulating to separate the semiconductor die. | 2012-05-03 |
| 20120104574 | INTEGRATED ANTENNAS IN WAFER LEVEL PACKAGE - A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package. | 2012-05-03 |
| 20120104575 | Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes - A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips. | 2012-05-03 |
| 20120104576 | INTERCONNECT STRUCTURE FOR HIGH FREQUENCY SIGNAL TRANSMISSIONS - A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects. | 2012-05-03 |
| 20120104577 | SEMICONDUCTOR PACKAGE AND ELECTRONIC COMPONENT PACKAGE - A semiconductor package includes an IC chip including a pad array having at least four pads, the pads including a voltage input pad and a voltage output pad disposed at edges of the pad array, a driver transistor disposed between the voltage input pad and the voltage output pad to receive an input voltage from the voltage input pad and output an output voltage to the voltage output pad, disposed in contact with an outer edge of the element arrangement region; and at least four leads on which the IC chip is mounted by flip chip bonding, disposed corresponding to the pads, formed in a lead array, the leads including a voltage input lead electrically connected to the voltage input pad and a voltage output lead electrically connected to the voltage output pad, disposed at edges of the lead array. | 2012-05-03 |
| 20120104578 | Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. | 2012-05-03 |
| 20120104579 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK - An integrated circuit package system includes an external interconnect having a lead tip and a lead body, including a recess in the lead body including a first recess segment, having an orientation substantially parallel to the lengthwise dimension of the lead body, and a second recess segment intersecting and perpendicular to the first recess segment along a lead body top surface of the lead body, the first recess segment at a bottom portion of the second recess segment; an internal interconnect between an integrated circuit die and the external interconnect; and an encapsulation to cover the external interconnect with the recess filled. | 2012-05-03 |
| 20120104580 | SUBSTRATELESS POWER DEVICE PACKAGES - A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed. | 2012-05-03 |
| 20120104581 | Semiconductor package device with a heat dissipation structure and the packaging method thereof - The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism. | 2012-05-03 |
| 20120104582 | High Power Ceramic on Copper Package - According to an embodiment of a high power package, the package includes a heat sink containing enough copper to have a thermal conductivity of at least 350 W/mK, an electrically insulating attached to the heat sink with an epoxy and a semiconductor chip attached to the heat sink on the same side as the lead frame with an electrically conductive material having a melting point of 280° C. or greater. | 2012-05-03 |
| 20120104583 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING SAME - A semiconductor device includes a lead frame that has a die interconnect portion and at least first and second die pads. The die interconnect portion is isolated from the die pads. The device also includes a first die and a second die attached to the first and second die pads and electrically connected to each other by way of the die interconnect portion. The first die is encapsulated in a first medium and the second die is encapsulated in a second medium, the first medium being different from the second medium. | 2012-05-03 |
| 20120104584 | SEMICONDUCTOR DEVICE PACKAGES WITH PROTECTIVE LAYER AND RELATED METHODS - A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads. | 2012-05-03 |
| 20120104585 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming signal contacts; forming a power bar having a power bar terminal, the power bar terminal formed in a staggered position relative to the signal contacts; depositing a terminal pad on the power bar terminal; depositing a contact pad on one of the signal contacts; coupling an integrated circuit die to the power bar terminal and the signal contacts; and forming a package body on the integrated circuit die. | 2012-05-03 |
| 20120104586 | Direct Contact Flip Chip Package with Power Transistors - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 2012-05-03 |
| 20120104587 | Direct Contact Semiconductor Package with Power Transistor - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 2012-05-03 |
| 20120104588 | METHOD FOR MANUFACTURING LEADFRAME, PACKAGING METHOD FOR USING THE LEADFRAME AND SEMICONDUCTOR PACKAGE PRODUCT - A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads. | 2012-05-03 |
| 20120104589 | Deposition-free sealing for Micro- and Nano-fabrication - A method for sealing through-holes in a material via material diffusion, without the deposition of a sealant material, is disclosed. The method is well suited to the fabrication and packaging of microsystems technology-based devices and systems. In some embodiments, the method comprises forming sacrificial material release through-holes through a structural layer, removing the sacrificial material via an etch that etches the sacrificial material through the release through-holes, and sealing of the release through-holes via material diffusion. | 2012-05-03 |
| 20120104590 | Semiconductor Device and Method of Forming Penetrable Film Encapsulant Around Semiconductor Die and Interconnect Structure - A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconductor die and bumps. The penetrable film encapsulant layer is pressed over the semiconductor die and bumps to embed the semiconductor die and bumps within the first and second adhesive layers. The first adhesive layer and second adhesive layer are separated to remove the base layer and first adhesive layer and leave the second adhesive layer around the semiconductor die and bumps. The bumps are exposed from the second adhesive layer. The carrier is removed. An interconnect structure is formed over the semiconductor die and second adhesive layer. A conductive layer is formed over the second adhesive layer electrically connected to the bumps. | 2012-05-03 |
| 20120104591 | Systems and methods for improved heat dissipation in semiconductor packages - Today's high speed semiconductor chips offer high performance at the expense of increase heat generation. A heat spreader can be build into a mold compound covering a semiconductor die in a semiconductor package by forming holes in the mold compound and filling the holes with a thermally conductive material such as thermally conductive adhesive. This heat dissipation capability can further be enhanced by a layer of thermally conductive material on the surface of the mold compound and optionally by an external metal layer or heat sink. | 2012-05-03 |
| 20120104592 | SEMICONDUCTOR MODULE HAVING A SEMICONDUCTOR CHIP STACK AND METHOD - A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film. | 2012-05-03 |
| 20120104593 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device according to the invention includes: a substrate; an MEMS structure formed above the substrate; and a covering structure defining a cavity in which the MEMS structure is arranged, wherein the covering structure has a first covering layer covering from above the cavity and having a through-hole in communication with the cavity and a second covering layer formed above the first covering layer and closing the through-hole, the first covering layer has a first region located above at least the MEMS structure and a second region located around the first region, the first covering layer is thinner in the first region than in the second region, and a distance between the substrate and the first covering layer in the first region is longer than a distance between the substrate and the first covering layer in the second region. | 2012-05-03 |
| 20120104594 | GROUNDED SEAL RING STRUCTURE IN SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having a seal ring region and a circuit region, at least one corner bump disposed in the circuit region, a seal ring structure disposed in the seal ring region, and a connector electrically coupling a metal layer of the seal ring structure to the at least one corner bump. The at least one corner bump is configured to be coupled to a signal ground. A method of fabricating a semiconductor device includes providing a substrate having a seal ring region and a circuit region, providing at least one corner bump in a triangular corner bump zone in the circuit region, providing a seal ring structure in the seal ring region, electrically coupling a metal layer of the seal ring structure to the at least one corner bump, and electrically coupling the at least one corner bump to a signal ground. | 2012-05-03 |
| 20120104595 | NO FLOW UNDERFILL - A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element. | 2012-05-03 |
| 20120104596 | FLIP CHIP BUMP ARRAY WITH SUPERIOR SIGNAL PERFORMANCE - An integrated circuit ( | 2012-05-03 |
| 20120104597 | CHIP-ON-CHIP STRUCTURE AND MANUFACTURING METHOD THEROF - According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property. | 2012-05-03 |
| 20120104598 | PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented. | 2012-05-03 |
| 20120104599 | Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor - A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps. | 2012-05-03 |
| 20120104600 | STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE AND PACKAGING THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided. | 2012-05-03 |
| 20120104601 | Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring - A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV. | 2012-05-03 |
| 20120104602 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND CIRCUIT DEVICE USING SEMICONDUCTOR DEVICE - [Problem] A semiconductor device which achieves a fine pitch, a high throughput and a high connection reliability, especially in flip-chip mounting is provided. A method for manufacturing the semiconductor device and a circuit device using the semiconductor device are also provided. | 2012-05-03 |
| 20120104603 | INTERCONNECT ASSEMBLIES AND METHODS OF MAKING AND USING SAME - The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween. | 2012-05-03 |
| 20120104604 | CRACK ARREST VIAS FOR IC DEVICES - An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ±30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads. | 2012-05-03 |
| 20120104605 | Chip Design having Integrated Fuse and Method for the Production Thereof - A chip design ( | 2012-05-03 |
| 20120104606 | BALL GRID ARRAY SEMICONDUCTOR DEVICE AND ITS MANUFACTURE - A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts. | 2012-05-03 |
| 20120104607 | STACKED SEMICONDUCTOR PACKAGES AND RELATED METHODS - The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer. | 2012-05-03 |
| 20120104608 | WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF - In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability. | 2012-05-03 |
| 20120104609 | DISCRETE CIRCUIT COMPONENT HAVING COPPER BLOCK ELECTRODES AND METHOD OF FABRICATION - A discrete circuit component has copper block electrodes and that utilizes a simple copper substrate as the basis for the component. The component is made by providing an electrode separation hole preformed in the main substrate. The electrode separation hole results in a simple fabrication for the construction of the discrete component product. With the presence of the electrode separation hole, two solid blocks of copper automatically come into shape for each fabricated device at the final phase of production when each device is cut loose from the main production matrix. | 2012-05-03 |
| 20120104610 | INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY - An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided. | 2012-05-03 |
| 20120104611 | SEMICONDUCTOR STRUCTURE WITH INSULATED THROUGH SILICON VIA - Techniques described herein generally relate to laminated semiconductor structures. In some examples, method of forming a polyimide film are described. An example method may include forming a through hole in a laminated semiconductor structure that includes multiple stacked semiconductor layers. An inner wall of the laminated semiconductor structure can define the through hole. The inner wall can be exposed to a solution including a salt of polyamic acid and/or a polyamic acid that can be precipitated on the inner wall. The precipitated polyamic acid on the inner wall can be transformed into a polyimide film substantially coating the inner wall. | 2012-05-03 |
| 20120104612 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device has: a semiconductor substrate; and an upper surface electrode laminated on an upper surface of the semiconductor substrate, wherein at least one portion of the upper surface electrode includes a first layer formed on an upper surface side of the semiconductor substrate, a second layer formed on an upper surface side of the first layer, a third layer in contact with the upper surface of the second layer, and a fourth layer formed on an upper surface side of the third layer. The first layer is a barrier metal layer. The second layer is an Al (aluminum) layer. The third layer is one of an Al—Si (aluminum-silicon alloy) layer, an Al—Cu (aluminum-copper alloy) layer and an Al—Si—Cu (aluminum-silicon-copper alloy) layer. The fourth layer is a solder joint layer. | 2012-05-03 |
| 20120104613 | BONDING WIRE FOR SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 μm in thickness. | 2012-05-03 |
