| 18th week of 2012 patent applcation highlights part 19 |
| Patent application number | Title | Published |
|---|
| 20120104414 | MINIATURE PACKAGING FOR DISCRETE CIRCUIT COMPONENTS - A miniature packaging for a discrete circuit component that comprises a core dice for the circuit component fabricated on a semiconductor substrate. The core dice has at least a pair of metallization electrodes formed on the same or different surfaces of the semiconductor substrate. An end electrode covers a corresponding side surface of the core dice and electrically connects to a corresponding one of the pair of metallization electrodes. The end electrode extends toward the center of the core dice on both the top and bottom surface of the core dice. | 2012-05-03 |
| 20120104415 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an emitter electrode formed of a silicide film, and provided on a semiconductor layer; an insulating film provided on the emitter electrode; and an electrode pad made of Al, and provided on the insulating film. | 2012-05-03 |
| 20120104416 | BIPOLAR JUNCTION TRANSISTOR GUARD RING STRUCTURES AND METHOD OF FABRICATING THEREOF - Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer. | 2012-05-03 |
| 20120104417 | SILICON CARBIDE SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING THE SAME, AND SILICON CARBIDE DEVICE - A silicon carbide semiconductor element and a manufacturing method thereof are disclosed in which a low contact resistance is attained between an electrode film and a wiring conductor element, and the wiring conductor element is hardly detached from the electrode film. In the method, a nickel film and a nickel oxide film are laminated in this order on a surface of an n-type silicon carbide substrate or an n-type silicon carbide region of a silicon carbide substrate, followed by a heat treatment under a non-oxidizing condition. The heat treatment transforms a portion of the nickel film into a nickel silicide film. Then, the nickel oxide film is removed with hydrochloric acid solution, and subsequently, a nickel aluminum film and an aluminum film are laminated in this order on a surface of the nickel silicide film. | 2012-05-03 |
| 20120104418 | LIGHT-EMITTING MODULE AND ALTERNATING CURRENT LIGHT-EMITTING DEVICE - A light-emitting module is provided, including a heat sink and a plurality of insulating layers disposed over the heat sink. A plurality of light-reflective layers is disposed over one of the insulating layers, respectively, wherein the light-reflective layers comprise a plurality of light-reflective inclined surfaces. A plurality of conductive layers is disposed over one of the light-reflective layers, respectively. A light-emitting diode (LED) chip is disposed over the heat sink. A plurality of bonding wires is provided, connecting the LED chip with the conductive layers. A transparent housing is disposed over the LED chip. A phosphor layer is disposed over a surface of the transparent housing facing the heat sink, and does not physically contact the LED chip. | 2012-05-03 |
| 20120104419 | TRANSISTOR ARRAY SUBSTRATE - A transistor array substrate includes a substrate, plural pads, plural shorting bars, at least one pixel array, plural first wires, and plural second wires. The substrate has at least one panel region and a peripheral circuit region surrounding the panel region. The pads and the shorting bars are disposed in the peripheral circuit region. The pixel array, the first wires, and the second wires are disposed in the panel region. The panel region has a pair of first edges and a pair of second edges. The first edges are connected between the second edges. The shorting bars are connected to the pads. The first wires and the second wires are electrically connected to the pixel array. The first wires are connected to some shorting bars through one of the first edges. The second wires are connected to the other shorting bars through at least one second edge | 2012-05-03 |
| 20120104420 | DISPLAY DEVICE AND ORGANIC LIGHT EMITTING DIODE DISPLAY - A display device includes a substrate, a display unit formed on the substrate, a sealing substrate bonded to the substrate by a bonding layer surrounding the display unit, the sealing substrate comprising a complex member and an insulating member, wherein the complex member has a resin matrix and a plurality of carbon fibers and the insulator is connected to an edge of the complex member and comprises a penetration hole, a metal layer disposed at one side of the sealing substrate wherein the one side faces the substrate, and a conductive connection unit filling in the penetration hole and contacting the metal layer. The complex member and the insulator may be coupled by tongue and groovecoupling along a thickness direction of the sealing substrate where the protrusion-groove coupling structure is top-to-bottom symmetric and the insulator may have a thickness identical to that of the complex member. | 2012-05-03 |
| 20120104421 | LEADFRAME PACKAGE WITH RECESSED CAVITY FOR LED - An LED package includes a die pad having a bottom surface, an upper surface and a centrally located recessed cavity. The recessed cavity has a chip attach surface between the bottom surface and upper surface and sidewalls that extend from the recessed chip attach surface to the upper surface. The package additionally has leads arranged on opposing sides of the die pad. The leads have a bottom surface that is coextensive with the bottom surface of the die pad and an upper surface coextensive with the upper surface of the die pad. An LED chip is attached to the chip attach surface. The package further includes a package body having an encapsulant which fills space between the die pad and leads forming a bottom encapsulant surface that is coextensive with the bottom surfaces of the die pad and leads. | 2012-05-03 |
| 20120104422 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display and a method of manufacturing the same. The organic light-emitting display is a transparent display where one can see through the display to view an image on the other side of the display. Each pixel of the display has a first region that includes an organic light emitting diode and a thin film transistor, and a larger second region that is transparent. The second region is made of either transparent layers or ultra thin layers so that light is not blocked. A second electrode of the display may include magnesium and may be produced by a selective deposition process, so that use of a fine metal mask may be avoided. | 2012-05-03 |
| 20120104423 | ORGANIC LIGHT-EMITTING ELEMENT, ORGANIC LIGHT-EMITTING DEVICE, ORGANIC DISPLAY PANEL, ORGANIC DISPLAY DEVICE, AND METHOD OF MANUFACTURING AN ORGANIC LIGHT-EMITTING ELEMENT - An organic light-emitting element includes a reflective anode, a first functional layer, an organic light-emitting layer that emits blue light, a second functional layer, a transparent cathode, and a coating layer. An optical thickness of the first functional layer is greater than 0 nm but not greater than 316 nm. A difference in refractive index between the transparent cathode and either a layer adjacent to the transparent cathode within the second functional layer or a layer adjacent to the transparent cathode within the coating layer is from 0.1 to 0.7 inclusive. The transparent cathode has a physical thickness greater than 0 nm but not greater than 70 nm, a refractive index from 2.0 to 2.4 inclusive, and an optical thickness greater than 0 nm but not greater than 168 nm. | 2012-05-03 |
| 20120104424 | LIGHT EMITTING DEVICE HAVING PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND METHOD OF FABRICATING THE SAME - Disclosed are a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. This method comprises preparing a first substrate of sapphire or silicon carbide having an upper surface with an r-plane, an a-plane or an m-plane. The first substrate has stripe-shaped anti-growth patterns on the upper surface thereof, and recess regions having sidewalls of a c-plane between the anti-growth patterns. Nitride semiconductor layers are grown on the substrate having the recess regions, and the nitride semiconductor layers are patterned to form the light emitting cells separated from one another. Accordingly, there is provided a light emitting device having non-polar light emitting cells with excellent crystal quality. | 2012-05-03 |
| 20120104425 | Method of Driving A Light Emitting Device - The present invention is characterized in that a transistor with its L/W set to 10 or larger is employed, and that |V | 2012-05-03 |
| 20120104426 | WHITE CERAMIC LED PACKAGE - The present invention is directed to leadless LED packages and LED displays utilizing white ceramic casings and thin/low profile packages with improved color mixing and structural integrity. In some embodiments, the improved color mixing is provided, in part, by the white ceramic package casing, which can help reflect light emitted from each LED in many directions away from the device. The non-linear arrangement of the LEDs can also contribute to improved color-mixing. The improved structural integrity can be provided by various features in the bond pads that cooperate with the casing for a stronger package structure. Moreover, in some embodiments the thinness/low profile of each package is attributed to its leadless structure, with the bond pads and electrodes electrically connected via through-holes. In some embodiments, the structural integrity of the package can also be attributed to indentations along its sides, which do not enable as much plating material to accumulate at the sides and helps package cutting processes during manufacture. The indentations can also contribute to displays having more tightly and densely packed LED arrays. | 2012-05-03 |
| 20120104427 | MINIATURE SURFACE MOUNT DEVICE WITH LARGE PIN PADS - One embodiment of the surface mount LED package includes a lead frame and a plastic casing at least partially encasing the lead frame. The lead frame includes a plurality of electrically conductive chip carriers. There is an LED disposed on each one of the plurality of electrically conductive chip carriers. A profile height of the surface mount LED package is less than about 1.0 mm. | 2012-05-03 |
| 20120104428 | SIDE VIEW SURFACE MOUNT LED - A light emitting diode is disclosed. The diode includes a package support and a semiconductor chip on the package support, with the chip including an active region that emits light in the visible portion of the spectrum. Metal contacts are in electrical communication with the chip on the package. A substantially transparent encapsulant covers the chip in the package. A phosphor in the encapsulant emits a frequency in the visible spectrum different from the frequency emitted by the chip and in response to the wavelength emitted by the chip. A display element is also disclosed that combines the light emitting diode and a planar display element. The combination includes a substantially planar display element with the light emitting diode positioned on the perimeter of the display element and with the package support directing the output of the diode substantially parallel to the plane of the display element. | 2012-05-03 |
| 20120104429 | ORGANIC EL ELEMENT, METHOD FOR MANUFACTURING THE SAME, AND ORGANIC EL DISPLAY DEVICE - An organic EL element includes a substrate | 2012-05-03 |
| 20120104430 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display is disclosed. In one embodiment, the OLED display includes i) a substrate having first and second surfaces opposing each other and ii) an organic light emitting diode (OLED) formed over the substrate, wherein the OLED is closer to the first surface than the second surface of the substrate. The display may also include i) a light scattering layer formed between the first surface of the substrate and the organic light emitting diode and ii) a light absorbing layer formed between the first surface of the substrate and the light scattering layer or on the second surface of the substrate. | 2012-05-03 |
| 20120104431 | LIGHT EMITTING ELEMENT - According to one embodiment, a light emitting element includes a light emitting layer, a cladding layer, a current spreading layer, a second layer, and an electrode. The light emitting layer is capable of emitting emission light. The current spreading layer includes a surface processed layer and a first layer. The surface processed layer has a surface including convex portions and bottom portions provided adjacent to the convex portions. The first layer is provided between the surface processed layer and the cladding layer. The second layer is provided between the surface processed layer and the cladding layer and includes a region having an impurity concentration higher than an impurity concentration of the current spreading layer. The electrode is provided in a region of the surface of the surface processed layer where the convex portions and the bottom portions are not provided. | 2012-05-03 |
| 20120104432 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a semiconductor light emission stacked body including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer positioned between the first and second conductive semiconductor layers; and a highly conductive transparent electrode formed on at least one of the first and second conductive semiconductor layers and including a transparent electrode layer formed of at least one of a transparent conductive oxide layer and a transparent conductive nitride and a graphene layer allowing light within the visible spectrum to be transmitted therethrough, the transparent electrode layer and the graphene layer being stacked. | 2012-05-03 |
| 20120104433 | GROUP III NITRIDE SEMICONDUCTOR ELEMENT AND EPITAXIAL WAFER - A primary surface | 2012-05-03 |
| 20120104434 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are a light emitting device and a method for manufacturing the same. The light emitting device comprises a first conductive type semiconductor layer, an active layer, a second conductive type semiconductor layer, and a light extraction layer. The active layer is formed on the first conductive type semiconductor layer. The second conductive type semiconductor layer is formed on the active layer. The light extraction layer is formed on the second conductive type semiconductor layer. The light extraction layer has a refractive index smaller than or equal to a refractive index of the second conductive type semiconductor layer. | 2012-05-03 |
| 20120104435 | REFRACTIVE INDEX TUNING OF WAFER LEVEL PACKAGE LEDS - Two or more molded ellipsoid lenses are formed on a packaged LED die by injecting a glue material into a mold over the LED die and curing the glue material. After curing, the refractive index of the lens in contact with the LED die is greater than the refractive index of the lens not directly contacting the LED die. At least one phosphor material is incorporated into the glue material for at least one of the lenses not directly contacting the LED die. The lens directly contacting the LED die may also include one or more phosphor material. A high refractive index coating may be applied between the LED die and the lens. | 2012-05-03 |
| 20120104436 | LIGHT EMITTING PACKAGE WITH A MECHANICAL LATCH - A surface mount light emitting device package with mechanical latching means for locking a lens on to the package is provided. The surface mount light emitting package may include an encapsulation layer or a lens, a lead frame, at least one lead, a body, a die, and a layer of transparent gel encapsulant material. The lead frame may include at least one protrusion which is bent upward to from at least one latch for engaging the lens. | 2012-05-03 |
| 20120104437 | OPTIC ASSEMBLY UTILIZING QUANTUM DOTS - An optic assembly is provided. The assembly includes a housing having an upstream end and a downstream end. An LED is positioned in the upstream end of the housing. The LED is configured to generate excitation light therefrom. The excitation light has a first wavelength. An optic is positioned in the downstream end of the housing. The optic is positioned remotely from the LED so that a cavity is formed between the LED and the optic. The excitation light generated from the LED passes downstream through the cavity to the optic. Quantum dots are positioned on the optic. The excitation light excites the quantum dots so that the quantum dots produce emitted light having a second wavelength that is different than the first wavelength of the excitation light. | 2012-05-03 |
| 20120104438 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - An LED package structure includes a substrate, a first electrical portion and a second electrical portion formed on the substrate, and an LED chip mounted on a first surface of the first electrical portion. The first and second electrical portions are electrically insulated from each other. The LED chip includes a first electrode connected with the first electrical portion and a second electrode connected with the second electrical portion through a connecting wire. The LED chip has a top surface for supporting the second electrode. The connecting wire has a highest point. A distance between the highest point and the top surface is less than a half of a distance between the first surface of the first electrical portion and the top surface of the LED chip. | 2012-05-03 |
| 20120104439 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a light emission structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; and a wavelength conversion layer formed on at least a portion of a light emission surface of the light emission structure, made of a light-transmissive material including phosphor particles, and having a void therein. A semiconductor light emitting device includes: a light emission structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; and a wavelength conversion layer formed on at least a portion of a light emission surface of the light emission structure, made of a light-transmissive material including phosphor particles or quantum dots, and having a void therein. | 2012-05-03 |
| 20120104440 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device comprising, a substrate and a first transition stack formed on the substrate comprising a first transition layer formed on the substrate having a hollow component formed inside the first transition layer, a second transition layer formed on the first transition layer, and a reflector rod formed inside the second transition layer. | 2012-05-03 |
| 20120104441 | METHOD OF MANUFACTURING COLOR FILTER SUBSTRATE, SEMI-TRANSMISSIVE LIQUID CRYSTAL DISPLAY USING THE SAME, AND MANUFACTURING METHOD THEREOF - A manufacturing method of a color filter substrate, a semi-transmissive LCD using the same, and a manufacturing method thereof are disclosed. In one embodiment, the manufacturing method of the color filter substrate includes preparing a first substrate which comprises a reflection region and a transmission region. Then, a color resist on the first substrate is formed. A mask, including a semi-transmission mask corresponding to the reflection region, is provided on the color resist. An exposure process is provided for the color resist with the mask to form a color filter layer on the first substrate. The color filter layer is formed by removing a portion of the color resist of the reflection region. | 2012-05-03 |
| 20120104442 | LED AND MANUFACTURING METHOD - An LED includes a substrate, an LED chip setting on the substrate and a reflection cup surrounding the LED chip on the substrate. The LED chip electrically connects with two electrodes setting on the substrate. The reflection cup is filled with an encapsulating material. A fluorescent layer is formed by heating the encapsulating material and deposits on an end of the encapsulation away from the LED chip. The fluorescent layer is used for converting light from the LED chip into a specific wavelength. | 2012-05-03 |
| 20120104443 | IIIOxNy ON SINGLE CRYSTAL SOI SUBSTRATE AND III n GROWTH PLATFORM - A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIO | 2012-05-03 |
| 20120104444 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: first and second conductive type semiconductor layers; an active layer disposed between the first and second conductive type semiconductor layers; and first and second electrodes disposed on one surface of each of the first and second conductive type semiconductor layers, respectively, wherein at least one of the first and second electrodes includes a pad part and a finger part formed to extend from the pad part, and the end of the finger part has an annular shape. Because a phenomenon in which current is concentrated in a partial area of the finger part is minimized, tolerance to electrostatic discharge (ESD) can be strengthened and light extraction efficiency can be improved. | 2012-05-03 |
| 20120104445 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a substrate having a surface; a first conducting layer located on the surface; a second conducting layer located on the surface, wherein the first conducting layer and the second conducting layer are electrically insulated from each other; a first reflective layer conformally located on the first conducting layer and at least partially covering a side of the first conducting layer; a second reflective layer conformally located on the second conducting layer and at least partially covering a side of the second conducting layer; and a chip disposed on the surface of the substrate and having at least a first electrode and a second electrode, wherein the first electrode is electrically connected to the first conducting layer, and the second electrode is electrically connected to the second conducting layer. | 2012-05-03 |
| 20120104446 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A method for manufacturing a light emitting device, includes: forming a first multilayer body including a first substrate, a first semiconductor layer provided on the first substrate and having a light emitting layer, and a first metal layer provided on the first semiconductor layer; forming a second multilayer body including a second substrate having a thermal expansion coefficient different from a thermal expansion coefficient of the first substrate, and a second metal layer provided on the second substrate; a first bonding step configured to heat the first metal layer and the second metal layer being in contact with each other; removing the first substrate after the first bonding step; and a second bonding step configured to perform, after the removing, heating at a temperature higher than a temperature of the first bonding step. | 2012-05-03 |
| 20120104447 | LIGHT EMITTING DEVICE PACKAGE - Disclosed is a light emitting device package. The light emitting device package includes a substrate comprising a recess, a light emitting chip on the substrate and a first conductive layer electrically connected to the light emitting chip. And the first conductive layer includes at least one metal layer electrically connected to the light emitting chip on an outer circumference of the substrate. | 2012-05-03 |
| 20120104448 | LIGHT-EMITTING DEVICE - A semiconductor light-emitting device that is high in luminous efficiency and that emits light which is high in color rendering property includes a semiconductor light-emitting element that emits blue light; a green fluorescent substance that absorbs the blue light and emits green light; and an orange fluorescent substance that absorbs the blue light and emits orange light, fluorescence emitted by the green fluorescent substance and the orange fluorescent substance having an emission spectrum that has a peak wavelength of not less than 540 nm and not more than 565 nm and that satisfies the relation of 0.70>PI(90)/PI(MAX)>0.55, where PI(MAX) represents an emission intensity at the peak wavelength, and PI(90) represents an emission intensity at a wavelength 90 nm longer than the peak wavelength. | 2012-05-03 |
| 20120104449 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a first conductive semiconductor layer including first and second areas; an active layer disposed on the second area; a second conductive semiconductor layer disposed on the active layer; first and second electrode branches disposed on the first and second conductive semiconductor layers, respectively; a first electrode pad electrically connected to the first electrode branch and disposed on the first electrode branch; and a second electrode pad electrically connected to the second electrode branch and disposed on the second electrode branch. | 2012-05-03 |
| 20120104450 | LIGHT EMITTING DIODE OPTICAL EMITTER WITH TRANSPARENT ELECTRICAL CONNECTORS - An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching. | 2012-05-03 |
| 20120104451 | ORGANIC LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting device and a method for manufacturing the same are provided. The organic light emitting device comprises: a substrate; a first electrode disposed on the substrate; a hole function layer disposed on the first electrode; a first emission layer disposed on the hole function layer; a second emission layer disposed on the first emission layer; an electron function layer disposed on the second emission layer; and a second electrode disposed on the electron function layer, wherein the hole function layer and the first emission layer are melted. | 2012-05-03 |
| 20120104452 | LIGHT EMITTING APPARATUS AND PRODUCTION METHOD THEREOF - A light emitting apparatus comprises an electrically insulating base member; a pair of electrically conductive pattern portions formed on an upper surface of the base member; at least one light emitting device that is electrically connected to the pair of electrically conductive pattern portions; and a resin portion that surrounds at least a side surface of the at least one light emitting device and partially covers the pair of electrically conductive pattern portions. Each of the pair of electrically conductive pattern portions extends toward a periphery of the base member from resin-covered parts of the electrically conductive pattern portions. At least the resin-covered parts of each of the electrically conductive pattern portions has at least one elongated through hole extending in a direction in which the electrically conductive pattern portions extend from the resin-covered parts, wherein the resin portion contacts the base member via the through holes. | 2012-05-03 |
| 20120104453 | NITRIDE LIGHT EMITTING DEVICE OF USING SUBSTRATE DECOMPOSITION PREVENTION LAYER AND MANUFACTURING METHOD OF THE SAME - A light-emitting device is provided with a substrate decomposition prevention layer using as a matrix at least one selected from the group consisting of boron nitride (B—N), silicon carbide (Si—C), and silicon carbon nitride (Si—C—N), and patterned into a predetermined shape; an n-type nitride clad layer formed on the substrate decomposition prevention layer; a nitride active layer formed on the n-type nitride clad layer; a p-type nitride clad layer formed on the nitride active layer; a p-type ohmic contact layer formed on the p-type nitride clad layer; a p-type electrode pad formed on the p-type ohmic contact layer; an n-type ohmic contact layer electrically connected to the n-type nitride clad layer by means of a patterned region of the substrate decomposition prevention layer; and an n-type electrode pad formed beneath the n-type ohmic contact layer. | 2012-05-03 |
| 20120104454 | OPTICAL DEVICE, PROCESS FOR FABRICATING IT AND AN ELECTRONIC PACKAGE COMPRISING THIS OPTICAL DEVICE - An optical device includes at least one optical die ( | 2012-05-03 |
| 20120104455 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device includes a substrate and a first transition stack formed on the substrate including at least a first transition layer formed on the substrate and having at least one hollow component formed inside the first transition layer, and a second transition layer wherein the second transition layer is an unintentional doped layer or an undoped layer formed on the first transition layer. | 2012-05-03 |
| 20120104456 | Fast Recovery Reduced P-N Junction Rectifier - A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily p-type doped thin film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate. | 2012-05-03 |
| 20120104457 | POWER SWITCHING ASSEMBLY HAVING A ROBUST GATE CONNECTION - A structurally robust power switching assembly, that has a power transistor, comprising a thin and delicate layer of metal oxide, and a major surface of the layer of metal oxide being substantially coincident with a major surface of the power transistor, the major surface of the power transistor defining both an emitter and a gate. Also, dielectric material is placed over a portion of the emitter, so that it abuts the gate and a highly conductive pillar is constructed out of a relatively soft material, supported by the gate and the dielectric material, so that it has a larger area than would be possible if it was supported only by the gate. | 2012-05-03 |
| 20120104458 | ISOLATED SCR ESD DEVICE - The present invention discloses an isolated SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a first high density doped region located in the first well and having a second conductivity type; a second well nearby the first well and having the second conductivity type; a second high density doped region located in the second well and having the second conductivity type; and a third high density doped region located in the second well and having the first conductivity type, wherein the first high density doped region is for electrical connection with a pad, and wherein the first well is not provided with a high density doped region having the first conductivity type for connection with the pad. | 2012-05-03 |
| 20120104459 | BI-DIRECTIONAL SCR ESD DEVICE - The present invention discloses a bi-directional SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a second well and a third well both located in the first well and both having a second conductivity type, the second well and the third well being separated from each other; a first high density doped region of the first conductivity type and a second high density doped region of the second conductivity type located in the second well; and a third high density doped region of the first conductivity type and a fourth high density doped region of the second conductivity type located in the third well. | 2012-05-03 |
| 20120104460 | OPTOELECTRONIC DEVICES INCLUDING HETEROJUNCTION - Embodiments of the invention generally relate to optoelectronic semiconductor devices such as photovoltaic devices including solar cells. In one aspect, an optoelectronic semiconductor device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device, the emitter layer made of a different material than the absorber layer and having a higher bandgap than the absorber layer. A heterojunction formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. The p-n junction causes a voltage to be generated in the device in response to the device being exposed to light at a front side of the device. | 2012-05-03 |
| 20120104461 | Semiconductor Heterostructures Having Reduced Dislocation Pile-Ups and Related Methods - Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein. | 2012-05-03 |
| 20120104462 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE - A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom selected such that the Fermi level of the second semiconductor containing both the first and second impurity atoms is closer to the Fermi level of the second semiconductor containing neither the first impurity atom nor the second impurity atom, than the Fermi level of the second semiconductor containing the first impurity atom is. For example, the majority carrier of the second semiconductor is an electron, and the Fermi level of the second semiconductor containing the first and second impurity atoms is lower than the Fermi level of the second semiconductor containing the first impurity atom. | 2012-05-03 |
| 20120104463 | DEVICES AND MEMORY ARRAYS INCLUDING BIT LINES AND BIT LINE CONTACTS - Each of the first bit lines of a device has an upper surface and a lower surface, with the upper surface being more outwardly located over a semiconductor surface than the lower surface. A second bit line of the device has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the semiconductor surface than the lower surface. The upper surface of the second bit line is more outwardly located over the semiconductor surface than the upper surfaces of the first bit lines. The first bit lines are each adjacent to the second bit line and the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled. The second bit line does not overlap any of the first bit lines. | 2012-05-03 |
| 20120104464 | P-PIXEL CMOS IMAGERS USING ULTRA-THIN SILICON ON INSULATOR SUBSTRATES (UTSOI) - A CMOS image sensor is disclosed. The CMOS image sensor includes a semiconductor substrate having a surface. An epitaxial layer is grown on the surface. A p-type CMOS pixel formed substantially in the epitaxial layer. In one version of the CMOS image sensor, there exists a net n-type dopant concentration profile in the semiconductor substrate and the epitaxial layer which has a maximum value at a predetermined distance from the surface and which decreases monotonically on both sides of the profile from the maximum value within the semiconductor substrate and the epitaxial layer. In another version of the CMOS image sensor, there exists a net n-type dopant concentration profile in the semiconductor substrate and the epitaxial layer which has a maximum value at the surface and which decreases monotonically with increasing distance from the surface within the semiconductor substrate and the epitaxial layer. | 2012-05-03 |
| 20120104465 | IMAGE SENSOR - An image sensor including: a substrate that includes a first surface onto which light is irradiated, a second surface opposite to the first surface, and a light receiving device disposed adjacent to the second surface; a transistor that includes a source region, a drain region, and a gate electrode disposed between the source region and the drain region, wherein the transistor is disposed on the second surface of the substrate; a wiring line that is disposed on the second surface of the substrate; and a plurality of contact plugs that are disposed on the source region, the drain region, or the gate electrode, wherein at least one of the plurality of contact plugs is connected to the wiring line. | 2012-05-03 |
| 20120104466 | METHOD FOR FABRICATING CONTACT ELECTRODE AND SEMICONDUCTOR DEVICE - The invention provides a semiconductor device comprising: a substrate; a gate, which is formed on the substrate; a source and a drain, which are located on opposite sides of the gate, respectively; a contact, which contacts with the source and/or the drain, wherein the contact has an enlarged end at an end which is in contact with the source and/or the drain. In the present invention, since the contact area of the contact is increased on the interface in contact with the source/the drain, the contact resistance can be reduced, and thus the performances of the semiconductor device can be guaranteed/improved. The present invention further provides a method of fabricating the semiconductor device (especially the contact therein) as previously described. | 2012-05-03 |
| 20120104467 | SELF-ALIGNED CONTACT STRUCTURE TRENCH JFET - According to one embodiment, a self-aligned trench structure junction gate field-effect transistor (JFET) includes a silicon substrate, two or more trenches having a P-type polysilicon gate region near a bottom portion of the trench and an interlayer dielectric layer (ILDL) above the P-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, an N+ source region above the channel region extending between a top of each trench, and a source metal above the N+ source region. In another embodiment, a self-aligned trench structure JFET includes a silicon substrate, two or more trenches having an N-type polysilicon gate region near a bottom portion of the trench and an ILDL above the N-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, a P+ source region above the channel region extending between a top of each trench, and a source metal above the P+ source region. | 2012-05-03 |
| 20120104468 | FABRICATING HIGH VOLTAGE TRANSISTORS IN A LOW VOLTAGE PROCESS - Fabricating high voltage transistors includes forming a buried p-type implant on a p-substrate for each transistor, the transistor having a source side and a drain side, wherein the p-type implant is positioned adjacent the source and is configured to extend under a gate region; depositing a low doping epitaxial layer on the p-substrate and the p-type implant for each high voltage transistor, the low doping epitaxial layer extending from the source to the drain; forming an N-Well in the low doping epitaxial layer for each transistor, wherein the N-Well corresponds to a low voltage transistor N-Well fabricated using a low voltage transistor fabrication process; and forming a p-top diffusion region in or on the N-Well for each transistor, wherein the p-top diffusion region is configured to compensate for a dopant concentration of the N-Well at or near a surface of the N-Well opposing the substrate. | 2012-05-03 |
| 20120104469 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 2012-05-03 |
| 20120104470 | REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN - A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor. | 2012-05-03 |
| 20120104471 | CONTACT STRUCTURE FOR REDUCING GATE RESISTANCE AND METHOD OF MAKING THE SAME - A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material. | 2012-05-03 |
| 20120104472 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material. | 2012-05-03 |
| 20120104473 | TRANSISTOR AND METHOD FOR FORMING THE SAME - The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations. | 2012-05-03 |
| 20120104474 | TRANSISTOR AND METHOD FOR FORMING THE SAME - The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer. | 2012-05-03 |
| 20120104475 | FIELD EFFECT TRANSISTORS (FETS) AND METHODS OF MANUFACTURE - An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a storage capacitance of the finFET. The enhancement can be by either adding a storage capacity to the finFET or altering a portion of the finFET after formation of a fin body of the finFET. | 2012-05-03 |
| 20120104476 | ELECTRONIC DEVICE WITH ASYMMETRIC GATE STRAIN - The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode. | 2012-05-03 |
| 20120104477 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process. | 2012-05-03 |
| 20120104478 | SOLID STATE IMAGING DEVICE - An island-shaped semiconductor constituting a pixel includes a first semiconductor N | 2012-05-03 |
| 20120104479 | SOLID-STATE IMAGING DEVICE, METHOD OF PRODUCING THE SAME, AND IMAGING DEVICE - A solid-state imaging device includes a semiconductor substrate including a pixel portion having a photoelectric conversion portion and a peripheral circuit portion; a first sidewall composed of a sidewall film and disposed on each sidewall of gate electrodes of MOS transistors in the pixel portion; a second sidewall composed of the sidewall film and disposed on each sidewall of gate electrodes of MOS transistors in the peripheral circuit portion; a first silicide blocking film composed of the sidewall film and disposed on the photoelectric conversion portion and a part of the MOS transistors in the pixel portion; and a second silicide blocking film disposed on the MOS transistors in the pixel portion so as to overlap with a part of the first silicide blocking film, wherein the MOS transistors in the pixel portion are covered with the first and second silicide blocking films. | 2012-05-03 |
| 20120104480 | STORAGE DEVICE - A storage device in which stored data can be held even when power is not supplied, and stored data can be read at high speed without turning on a transistor included in a storage element is provided. In the storage device, a memory cell having a transistor including an oxide semiconductor layer as a channel region and a storage capacitor is electrically connected to a capacitor to form a node. The voltage of the node is boosted up in accordance with stored data by capacitive coupling through a storage capacitor and the potential is read with an amplifier circuit to distinguish data. | 2012-05-03 |
| 20120104481 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion. | 2012-05-03 |
| 20120104482 | SEMICONDUCTOR DEVICES HAVING A CONTROL GATE ELECTRODE INCLUDING A METAL LAYER FILLING A GAP BETWEEN ADJACENT FLOATING GATES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a device isolation layer defining a plurality of active regions of a semiconductor substrate, floating gates and a control gate electrode in which the lowermost part of the electrode is constituted by a metal layer. The control gate electrode crosses over the active regions. The floating gates are disposed between the control gate electrode and the active regions. The tops of the floating gates are disposed at a level above the level of the top of the device isolation layer such that a gap is defined between adjacent ones of the floating gates. A region of the gap is filled with the metal layer of the control gate electrode. | 2012-05-03 |
| 20120104483 | NON-VOLATILE MEMORY AND LOGIC CIRCUIT PROCESS INTEGRATION - A method of making a logic transistor in a logic region of a substrate and a non-volatile memory cell in an NVM region of the substrate includes forming a gate dielectric layer on the substrate. A first polysilicon layer is formed on the gate dielectric. The first polysilicon layer is formed over the NVM region and removing the first polysilicon layer over the logic region. A dielectric layer is formed over the NVM region including the first polysilicon layer and over the logic region. A protective layer is formed over the dielectric layer. The dielectric layer and the protective layer are removed from the logic region to leave a remaining portion of the dielectric layer and a remaining portion of the protective layer over the NVM region. A high-k dielectric layer is formed over the logic region and the remaining portion of the protective layer. A first metal layer is formed over the high K dielectric layer. The first metal layer, the high K dielectric, and the remaining portion of the protective layer are removed over the NVM region to leave a remaining portion of the first metal layer and a remaining portion of the high K dielectric layer over the logic region. A conductive layer is deposited over the remaining portion of the dielectric layer and over the first metal layer. The NVM cell and the logic transistor are formed and this includes patterning the conductive layer. | 2012-05-03 |
| 20120104484 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device includes a substrate, a stacked structure with conductive materials and first insulating materials and the conductive materials and the first insulating materials are alternately stacked on the substrate, and a plurality of pillars in contact with the substrate and the pillars extend through the stacked structure in a direction perpendicular to the substrate. The device also includes information storage layers between the conductive materials and the first insulating materials, and second insulating materials between the first insulating materials and the pillars. | 2012-05-03 |
| 20120104485 | Nonvolatile Memory Devices And Methods Of Manufacturing The Same - A method of manufacturing a nonvolatile memory device includes forming a tunnel dielectric layer, a charge storage layer, and a hard mask layer on a substrate in sequential order. Active portions are defined by forming trenches in the substrate. A tunnel dielectric pattern, a preliminary charge storage pattern, and a hard mask pattern are formed on each of the active portions in sequential order by sequentially patterning the hard mask layer, the charge storage layer, the tunnel dielectric layer, and the substrate. A capping pattern is formed covering an upper surface of the trenches such that a first void remains in a lower portion of the trenches, the capping pattern including etch particles formed by etching the hard mask pattern through a sputtering etch process. | 2012-05-03 |
| 20120104486 | TRANSISTOR AND METHOD FOR FORMING THE SAME - The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein only the source region comprises at least one dislocation. The method for forming a transistor according to the present invention comprises forming a mask layer on a semiconductor substrate on which a gate has been formed so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer to only expose at least a portion of a source region; performing a first ion implantation to the exposed portion of the source region; and annealing the semiconductor substrate so as to form a dislocation in the exposed portion of the source region. | 2012-05-03 |
| 20120104487 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, a transistor and a contact plug pillar of an impurity-diffused semiconductor. The transistor includes a semiconductor channel pillar having a vertical channel; and a first diffusion region adjacent to a lower portion of the semiconductor channel pillar. The contact plug pillar of an impurity-diffused semiconductor is coupled to the first diffusion region. | 2012-05-03 |
| 20120104488 | DATA CELLS AND CONNECTIONS TO DATA CELLS - Disclosed are devices, among which is a device that includes a transistor and a contact. The transistor includes two terminals that may be formed in respective legs. The contact includes a first portion extending vertically, and a second portion extending perpendicularly with respect to the first portion. The second portion is wider than the first portion. | 2012-05-03 |
| 20120104489 | SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate; a plurality of active pillars formed over the substrate; bulb-type trenches, each of the bulb-type trenches formed inside the substrate between the active pillars; buried bit lines, each of the buried bit lines being formed on a sidewall of a respective one of the bulb-type trenches; and vertical gates, each of the vertical gates being formed to surround a sidewall of a respective one of the active pillars. | 2012-05-03 |
| 20120104490 | Trench-Gate Field Effect Transistors and Methods of Forming the Same - A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region. | 2012-05-03 |
| 20120104491 | Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells - A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed. | 2012-05-03 |
| 20120104492 | LOW ON-RESISTANCE RESURF MOS TRANSISTOR - The present invention relates to a low on-resistance RESURF MOS transistor, comprising: a drift region; two isolation regions formed on the drift region; a first-doping-type layer disposed between the two isolation regions; and a second-doping-type layer disposed below the first-doping-type layer. | 2012-05-03 |
| 20120104493 | LATERAL SUPERJUNCTION EXTENDED DRAIN MOS TRANSISTOR - An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer. | 2012-05-03 |
| 20120104494 | SEMICONDUCTOR DEVICE - A field-effect transistor ( | 2012-05-03 |
| 20120104495 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention adjusts a threshold voltage with a common contact, which has a portion outside the source or drain region extending to the back-gate region and provides an electrical contact of the source or drain region and the back-gate region, which leads to a simple manufacturing process, an increased integration level and a lowered manufacture cost. Moreover, the asymmetric design of the back-gate structure further increases the threshold voltage and improves the performance of the device. | 2012-05-03 |
| 20120104496 | SOI RADIO FREQUENCY SWITCH WITH ENHANCED ELECTRICAL ISOLATION - At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced. | 2012-05-03 |
| 20120104497 | HIGH VOLTAGE DRAIN EXTENSION ON THIN BURIED OXIDE SOI - An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel). | 2012-05-03 |
| 20120104498 | Semiconductor device having localized extremely thin silicon on insulator channel region - A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed. | 2012-05-03 |
| 20120104499 | SEMICONDUCTOR DEVICE FOR PREVENTING PLASMA INDUCED DAMAGE - A semiconductor device including a well, at least a first transistor region formed over the well, a gate electrode formed over the transistor region, a well guard disposed to include an open region while surrounding the transistor region, a diode disposed in the open region, and a metal line configured to electrically connect the gate electrode and the diode. | 2012-05-03 |
| 20120104500 | SHALLOW TRENCH ISOLATION RECESS REPAIR USING SPACER FORMATION PROCESS - A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subjected to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and a horizontal fill portion of the spacer layer remains in one more recesses present in the STI regions so as to substantially planarize the STI region prior to subsequent material deposition thereon. | 2012-05-03 |
| 20120104501 | Semiconductor apparatus and method of manufacturing semiconductor apparatus - A semiconductor apparatus includes: an MOS type field effect transistor formed on a semiconductor substrate and having a first gate electrode set at a predetermined impurity concentration; and a charge modulation device formed on the semiconductor substrate and having a second gate electrode set at a predetermined impurity concentration lower than the impurity concentration of the first gate electrode. | 2012-05-03 |
| 20120104502 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Disclosed is a method of producing a semiconductor device, able to form a source/drain of a Schottky junction (FET) with simple steps and able to improve the device characteristics. A gate is formed on an element region defined in a silicon substrate layer by element isolation regions (first step), the silicon substrate is etched by self-alignment using the gate and the element isolation regions as masks (second step), and an insulating film is formed on the side surfaces of the gate (third step). Then, a metal film acting as the source/drain is selectively formed on the etching region of the silicon substrate by electroless plating (fourth step). | 2012-05-03 |
| 20120104503 | TRANSISTOR STRUCTURE WITH SILICIDED SOURCE AND DRAIN EXTENSIONS AND PROCESS FOR FABRICATION - A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch. | 2012-05-03 |
| 20120104504 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer. | 2012-05-03 |
| 20120104505 | STRUCTURE AND METHOD FOR USING HIGH-K MATERIAL AS AN ETCH STOP LAYER IN DUAL STRESS LAYER PROCESS - A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device. | 2012-05-03 |
| 20120104506 | CMOSFET DEVICE WITH CONTROLLED THRESHOLD VOLTAGE CHARACTERISTICS AND METHOD OF FABRICATING THE SAME - There is provided a CMOSFET device with threshold voltage controlled by means of interface dipoles and a method of fabricating the same. A cap layer, for example a very thin layer of poly-silicon, amorphous silicon, or SiO | 2012-05-03 |
| 20120104507 | METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW - A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses. | 2012-05-03 |
| 20120104508 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region. | 2012-05-03 |
| 20120104509 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor. | 2012-05-03 |
| 20120104510 | CMOS PROCESS TO IMPROVE SRAM YIELD - An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. | 2012-05-03 |
| 20120104511 | DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS - The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices. | 2012-05-03 |
| 20120104512 | SEALED AIR GAP FOR SEMICONDUCTOR CHIP - A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact. | 2012-05-03 |
| 20120104513 | FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE - The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge. | 2012-05-03 |
