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18th week of 2013 patent applcation highlights part 17
Patent application numberTitlePublished
20130105897Nanowire FET and FINFET Hybrid Technology2013-05-02
20130105898Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices2013-05-02
20130105899INPUT/OUTPUT ELECTROSTATIC DISCHARGE DEVICE WITH REDUCED JUNCTION BREAKDOWN VOLTAGE2013-05-02
20130105900Methods of Forming PFET Devices With Different Structures and Performance Characteristics2013-05-02
20130105901SEMICONDUCTOR DEVICE WITH METAL GATE ELECTRODE AND HIGH-K DIELECTRIC MATERIAL AND METHOD FOR FABRICATING THE SAME2013-05-02
20130105902NONVOLATILE SEMICONDUCTOR MEMORY DEVICE2013-05-02
20130105903SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF2013-05-02
20130105904RADIATION HARDENED INTEGRATED CIRCUIT2013-05-02
20130105905SEMICONDUCTOR DEVICE WITH METAL GATE AND HIGH-K DIELECTRIC LAYER, CMOS INTEGRATED CIRCUIT, AND METHOD FOR FABRICATING THE SAME2013-05-02
20130105906CMOS Device Having Dual Metal Gates and Method of Manufacturing the Same2013-05-02
20130105907MOS DEVICE AND METHOD OF MANUFACTURING THE SAME2013-05-02
20130105908SEMICONDUCTOR DEVICE2013-05-02
20130105909HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE2013-05-02
20130105910Remote Doped High Performance Transistor Having Improved Subthreshold Characteristics2013-05-02
20130105911SEMICONDUCTOR DEVICE2013-05-02
20130105912SEMICONDUCTOR DEVICE2013-05-02
20130105913Current Control Semiconductor Element and Control Device Using the Same2013-05-02
20130105914STRUCTURE OF FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE AND FABRICATING METHOD THEREOF2013-05-02
20130105915METAL OXIDE SEMICONDUCTOR DEVICE HAVING A PREDETERMINED THRESHOLD VOLTAGE AND A METHOD OF MAKING2013-05-02
20130105916HIGH SELECTIVITY NITRIDE ETCH PROCESS2013-05-02
20130105917Methods of Epitaxially Forming Materials on Transistor Devices2013-05-02
20130105918SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF2013-05-02
20130105919SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME2013-05-02
20130105920SEMICONDUCTOR STRUCTURE2013-05-02
20130105921MICROSYSTEM DEVICE AND METHODS FOR FABRICATING THE SAME2013-05-02
20130105922SEMICONDUCTOR PRESSURE SENSOR AND METHOD OF MANUFACTURING SEMICONDUCTOR PRESSURE SENSOR2013-05-02
20130105923DEEP WELL PROCESS FOR MEMS PRESSURE SENSOR2013-05-02
20130105924SOLID-STATE IMAGING APPARATUS AND MANUFACTURING METHOD OF SOLID-STATE IMAGING APPARATUS2013-05-02
20130105925Integrated Die-Level Cameras And Methods Of Manufacturing The Same2013-05-02
20130105926BACK SIDE ILLUMINATION IMAGE SENSOR AND MANUFACTURING METHOD THEREOF2013-05-02
20130105927PHOTOELECTRIC CONVERSION ELEMENT2013-05-02
20130105928BACKSIDE-THINNED IMAGE SENSOR USING Al2O3 SURFACE PASSIVATION2013-05-02
20130105929RESIN COMPOSITION2013-05-02
20130105930METHOD FOR MAKING SEMICONDUCTOR LIGHT DETECTION DEVICES2013-05-02
20130105931SOLID-STATE IMAGING APPARATUS2013-05-02
20130105932METHOD FOR MOLECULAR ADHESION BONDING AT LOW PRESSURE2013-05-02
20130105933SEMICONDUCTOR APPARATUS2013-05-02
20130105934SEMICONDUCTOR DEVICE2013-05-02
20130105935SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING THE SAME2013-05-02
20130105936SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING IMPROVED INTERCONNECT ACCURACY NEAR CELL BOUNDARIES2013-05-02
20130105937SIMPLIFIED PITCH DOUBLING PROCESS FLOW2013-05-02
20130105938DEVICE MATCHING LAYOUT AND METHOD FOR IC2013-05-02
20130105939SEMICONDUCTOR DEVICE2013-05-02
20130105940SEMICONDUCTOR DEVICE HAVING A FUSE ELEMENT2013-05-02
20130105941SEMICONDUCTOR DEVICE INCLUDING IN WAFER INDUCTORS, RELATED METHOD AND DESIGN STRUCTURE2013-05-02
20130105942FINFET DEVICES2013-05-02
20130105943PACKAGING SUBSTRATE HAVING EMBEDDED CAPACITORS AND FABRICATION METHOD THEREOF2013-05-02
20130105944METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION2013-05-02
20130105945MULTI-JUNCTION PHOTODIODE IN APPLICATION OF MOLECULAR DETECTION AND DISCRIMINATION, AND METHOD FOR FABRICATING THE SAME2013-05-02
20130105946SEMICONDUCTOR DEVICE INCLUDING GROUP III-V COMPOUND SEMICONDUCTOR LAYER, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE2013-05-02
20130105947HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE2013-05-02
20130105948PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS2013-05-02
20130105949LAMINATED SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME2013-05-02
201301059503D CHIP PACKAGE WITH SHIELDED STRUCTURES2013-05-02
20130105951BLOCK POWER SWITCH WITH EMBEDDED ELECTROSTATIC DISCHARGE (ESD) PROTECTION AND ADAPTIVE BODY BIASING2013-05-02
20130105952SHIELDED ENCAPSULATING STRUCTURE AND MANUFACTURING METHOD THEREOF2013-05-02
20130105953POWER MODULE PACKAGE2013-05-02
20130105954SEMICONDUCTOR PACKAGE2013-05-02
20130105955SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGE MODULE HAVING THE SAME2013-05-02
20130105956POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME2013-05-02
20130105957LEAD FRAME SEMICONDUCTOR DEVICE2013-05-02
20130105958Compact Wirebonded Power Quad Flat No-Lead (PQFN) Package2013-05-02
20130105960Low Stray Inductance Power Module2013-05-02
20130105961LOW INDUCTANCE POWER MODULE2013-05-02
20130105962THERMAL DISSIPATION IN CHIP2013-05-02
20130105963Semiconductor Device and Method of Forming Thermal Interface Material and Heat Spreader Over Semiconductor Die2013-05-02
20130105964Semiconductor Device2013-05-02
20130105965CHIP2013-05-02
20130105966THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION2013-05-02
20130105967Semiconductor Die and Method of Forming Sloped Surface in Photoresist Layer to Enhance Flow of Underfill Material Between Semiconductor Die and Substrate2013-05-02
20130105968TSV Backside Processing Using Copper Damascene Interconnect Technology2013-05-02
20130105969SOLDER BONDING PROCESS FORMING A SEMICONDUCTOR CHIP IN MULTIPLE STAGES ON A 3-DIMENSIONAL STACKED ASSEMBLY2013-05-02
20130105970Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe2013-05-02
20130105971Solder Interconnect Pads with Current Spreading Layers2013-05-02
20130105972STACKED PACKAGES USING LASER DIRECT STRUCTURING2013-05-02
20130105973EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE2013-05-02
20130105974SEMICONDUCTOR PACKAGE FEATURING FLIP-CHIP DIE SANDWICHED BETWEEN METAL LAYERS2013-05-02
20130105975SEMICONDUCTOR CHIP DEVICE WITH THERMAL INTERFACE MATERIAL FRAME2013-05-02
20130105976METHOD TO ALIGN MASK PATTERNS2013-05-02
20130105977Electronic Device and Method for Fabricating an Electronic Device2013-05-02
20130105978SILICON SUBMOUNT FOR LIGHT EMITTING DIODE AND METHOD OF FORMING THE SAME2013-05-02
20130105979Package on Package Devices and Methods of Packaging Semiconductor Dies2013-05-02
20130105980SINTERABLE BONDING MATERIAL USING COPPER NANOPARTICLES, PROCESS FOR PRODUCING SAME, AND METHOD OF BONDING ELECTRONIC COMPONENT2013-05-02
20130105981FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING2013-05-02
20130105982LAND GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE2013-05-02
20130105983SEMICONDUCTOR DEVICE AND METHOD FORMING PATTERNS WITH SPACED PADS IN TRIM REGION2013-05-02
20130105984SEMICONDUCTOR DEVICE PACKAGE ADAPTER2013-05-02
20130105985SEMICONDUCTOR DEVICE2013-05-02
20130105986SEMICONDUCTOR DEVICE WITH VIAS ON A BRIDGE CONNECTING TWO BUSES2013-05-02
20130105987LAMINATE INTERCONNECT HAVING A COAXIAL VIA STRUCTURE2013-05-02
20130105988SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP WITH THROUGH OPENING2013-05-02
20130105989Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect2013-05-02
20130105990SEMICONDUCTOR DEVICE2013-05-02
20130105991EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE2013-05-02
20130105992SEMICONDUCTOR COMPONENT HAVING A STACK OF SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING THE SAME2013-05-02
20130105993SEMICONDUCTOR DEVICE INTERCONNECT2013-05-02
20130105994HEATSINK ATTACHMENT MODULE2013-05-02
20130105995SEMICONDUCTOR DEVICE STRUCTURES AND THEIR FABRICATION2013-05-02
20130105996LOW ENERGY ETCH PROCESS FOR NITROGEN-CONTAINING DIELECTRIC LAYER2013-05-02
20130105997SILICONE RESIN COMPOSITION, SILICONE RESIN SHEET, OPTICAL SEMICONDUCTOR ELEMENT DEVICE, AND PRODUCING METHOD OF SILICONE RESIN SHEET2013-05-02
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