| 18th week of 2014 patent applcation highlights part 17 |
| Patent application number | Title | Published |
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| 20140117348 | Active-matrix Panel Display Device, TFT and Method for Forming the Same - The present invention discloses an active-matrix panel display device, a TFT and a method for forming the same The method includes that arranging a first insulating layer on a gate, stacking an oxide semiconductor layer and a buffer layer in order on the first insulating layer, arranging as source on the oxide semiconductor layer and a drain on the buffer layer, and plasma processing or heating in oxygen atmosphere the buffer layer which does not directly contact the source and the drain. Therefore, the present invention is capable of preventing the oxide semiconductor layer from damage in follow-up processes to assure stability of the TFT and display quality of the active-matrix panel display device. | 2014-05-01 |
| 20140117349 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING METAL OXIDE - A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer. | 2014-05-01 |
| 20140117350 | DISPLAY DEVICE AND ELECTRONIC DEVICE - To improve the reliability of a transistor as well as to inhibit fluctuation in electric characteristics. A display device includes a pixel portion and a driver circuit portion outside the pixel portion; the pixel portion includes a pixel transistor, a first insulating film covering the pixel transistor and including an inorganic material, a second insulating film including an organic material over the first insulating film, and a third insulating film including an inorganic material over the second insulating film; and the driver circuit portion includes a driving transistor to supply a signal to the pixel transistor, the first insulating film covering the driving transistor, and the second insulating film over the first insulating film, and further includes a region in which the third insulating film is not formed over the second insulating film or a region in which the second insulating film is not covered with the third insulating film. | 2014-05-01 |
| 20140117351 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPLIANCE - The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor. | 2014-05-01 |
| 20140117352 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented. | 2014-05-01 |
| 20140117353 | SEMICONDUCTOR DEVICE - A semiconductor device includes an antenna functioning as a coil, a capacitor electrically connected to the antenna in parallel, a passive element forming a resonance circuit with the antenna and the capacitor by being electrically connected to the antenna and the capacitor in parallel, a first field effect transistor controlling whether the passive element is electrically connected to the antenna and the capacitor in parallel or not, and a memory circuit. The memory circuit includes a second field effect transistor which includes an oxide semiconductor layer where a channel is formed and in which a data signal is input to one of a source and a drain. The gate voltage of the first field effect transistor is set depending on the voltage of the other of the source and the drain of the second field effect transistor. | 2014-05-01 |
| 20140117354 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first semiconductor package including a first terminal and a second terminal provided on a surface different from a surface on which the first terminal is formed, and a second semiconductor package including a third terminal connected to the first terminal, wherein the surface on which the first terminal is formed faces a surface on which the third terminal is formed. | 2014-05-01 |
| 20140117355 | Display Device - A display device includes a substrate having a display region with signal lines within the display region connected to respective terminals in a terminal group outside the display region via terminal wires, and an IC driver having bumps facing and connected to the terminals via an isotropic conductive film. The terminal wires have first, second, third and fourth terminal wires, and the terminals have a first terminal connected to the first terminal wire, a second terminal connected to the second terminal wire, a third terminal connected to the third terminal wire, and a fourth terminal connected to the fourth terminal wire. The first terminal and the second terminal are staggered with respect to each other, the second terminal and the third terminal are staggered with respect to each other, and the third terminal and the fourth terminal are staggered with respect to each other. | 2014-05-01 |
| 20140117356 | SEMICONDUCTOR STRUCTURE FOR IMPROVED OXIDE FILL IN - A semiconductor device includes a substrate, a semiconductor layer, and a material layer. The semiconductor layer is formed over the substrate. The material layer is formed over the semiconductor layer. The semiconductor layer and the material layer have a tapered profile in a vertical direction extending from the substrate. | 2014-05-01 |
| 20140117357 | LIGHT EMITTING DEVICE PACKAGE - Embodiments provide a light emitting device package including a package body having a top-opened cavity disposed in at least a portion thereof, a first electrode layer and a second electrode layer electrically isolated from the package body with an insulating layer interposed therebetween, the first electrode layer and the second electrode layer being electrically isolated from each other at a bottom surface of the cavity, a light emitting device placed on the bottom surface of the cavity configured to emit light through the open region of the cavity, and a sensor placed on at least a portion of the package body at the outside of the cavity configured to measure output of the light emitting device. | 2014-05-01 |
| 20140117358 | ELECTRO-OPTICAL DEVICE, SHIFT REGISTER CIRCUIT, AND SEMICONDUCTOR DEVICE - An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver. | 2014-05-01 |
| 20140117359 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - The present invention relate to a display device, an array substrate and a method for manufacturing the same. The array substrate includes a substrate and a thin film transistor and a pixel electrode which are formed on the substrate, the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes and is overlaid with a passivation layer, the active layer of the thin film transistor is of an oxide semiconductor, and the passivation layer comprises at least one layer of inorganic insulating thin film or organic insulating thin film. With this array substrate, the oxide semiconductor can be effectively avoided from being affected by hydrogen-containing groups, so that stability of the whole TFT device is enhanced to a great extent, and yield of final products is increased. | 2014-05-01 |
| 20140117360 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area. | 2014-05-01 |
| 20140117361 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side. | 2014-05-01 |
| 20140117362 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A display panel is provided, which includes a transparent substrate, a first thin film transistor (TFT), a second TFT, a transparent bottom electrode, a capacitance layer, a transparent top electrode, an opposite substrate and a display medium layer. The transparent substrate has a display region and a peripheral region. The display region has sub-pixel regions, and at least one sub-pixel region at least includes a capacitance region and a transistor region. The first and the second TFTs are disposed on the transistor region of the transparent substrate. The transparent bottom electrode, the capacitance layer and the transparent top electrode are sequentially disposed on the capacitance region of transparent substrate, in which the transparent bottom electrode is connected to a source/drain electrode of the first TFT, and the transparent top electrode is connected to a source/drain electrode of the second TFT. | 2014-05-01 |
| 20140117363 | DISPLAY PANEL DEVICE AND METHOD OF MANUFACTURING DISPLAY PANEL DEVICE - A display panel device includes: a gate electrode above a substrate; a gate insulator above the gate electrode; a first source electrode and a first drain electrode above the gate insulator; a second source electrode and a second drain electrode above the first source electrode and the first drain electrode respectively; a first partition wall part having an opening in which the second source electrode and the second drain electrode are exposed; a semiconductor layer in the opening; an insulation layer above the semiconductor layer; a lower electrode above the insulation layer; and a contact hole in the insulation layer, for connecting the lower electrode and the second drain electrode or the second source electrode, wherein a film structure of each of the second source electrode and the second drain electrode is sparser than a film structure of each of the first source electrode and the first drain electrode. | 2014-05-01 |
| 20140117364 | Semiconductor Device and Manufacturing Method Thereof - By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer. | 2014-05-01 |
| 20140117365 | DISPLAY DEVICE - In view of the problem that a reduced thickness of an EL film causes a short circuit between an anode and a cathode and malfunction of a transistor, the invention provides a display device that has a light emitting element including an electrode and an electroluminescent layer, a wire electrically connected to the electrode of the light emitting element, a transistor provided with an active layer including a source, a drain and a channel forming region, and a power supply line electrically connected to one of the source and the drain of the transistor, wherein the wire is electrically connected to the other of the source and the drain of the transistor, and the width of a part of the electrode in the vicinity of a portion where the electrode is electrically connected to the wire is smaller than that of the electrode in the other portion. | 2014-05-01 |
| 20140117366 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes an underlying layer and a plurality of transistors. The underlying layer includes a first region and a second region provided adjacently to the first region. The transistors are arranged in a plane parallel to an upper surface of the underlying layer. Each transistor includes a channel allowing a current to flow in a first direction intersecting the plane. The plurality of transistors includes a first transistor provided on the first region and a second transistor provided on the second region, a first channel of the first transistor having a first crystal orientation, and a second channel of the second transistor having a second crystal orientation different from the first crystal orientation. | 2014-05-01 |
| 20140117367 | DEVICES, STRUCTURES, AND METHODS USING SELF-ALIGNED RESISTIVE SOURCE EXTENSIONS - Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region. | 2014-05-01 |
| 20140117368 | BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS - A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. | 2014-05-01 |
| 20140117369 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer. | 2014-05-01 |
| 20140117370 | ARRAY SUBSTRATE, DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an arrayed substrate is disclosed, in which ion-doping is performed by using photoresist as a barrier layer instead of using a gate electrode, which process can reduces the short channel effect that is caused by diffusion of doped ions toward a channel region, and meanwhile decrease the coupling capacitance between the gate electrode and the source-drain electrodes, thereby improving the performance of the prepared TFT. | 2014-05-01 |
| 20140117371 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - Embodiments of the present invention relate to an array substrate, a manufacturing method thereof and a display device. The manufacturing method of the array substrate comprises: preparing a base substrate; forming a gate electrode pattern on the base substrate; forming a gate insulating layer pattern on the base substrate with the gate electrode pattern formed thereon; and forming an active layer pattern, a pixel electrode pattern and source and drain patterns above the gate insulating layer pattern through a three-gray-tone mask process in one patterning process, wherein the gate electrode pattern, the active layer pattern, the source pattern and the drain pattern constitute a thin film transistor. | 2014-05-01 |
| 20140117372 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND PRODUCING METHOD THEREOF - Disclosed are a thin film transistor array substrate and a producing method thereof in the embodiments of the present invention, the producing method comprising: forming an active layer thin film and a conductive layer thin film on a substrate; depositing a source/drain electrode layer thin film on the conductive layer thin film, treating the conductive layer thin film and the source/drain electrode layer thin film using gray tone or half tone masking process, to form at least two data lines, a pixel electrode and source/drain electrodes of the thin film transistor (TFT); after depositing an insulating layer thin film covered the active layer thin film, the source/drain electrodes, the data lines and the pixel electrode, forming a through hole and a gate insulating layer of the TFT on the insulating layer, to form an active layer of the TFT; forming a gate electrode of the TFT and at least two gate scanning lines cross with the data wires. | 2014-05-01 |
| 20140117373 | SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including: a source electrode formed on one side of an N-type AlGaN layer; N-type and P-type AlGaN layers formed on the other side of the P-type AlGaN layer and formed in a direction perpendicular to the source electrode; a gate electrode formed on one side of the N-type and P-type AlGaN layers; and a drain electrode formed on the other side of the N-type and P-type AlGaN layers. | 2014-05-01 |
| 20140117374 | SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including: a base substrate; a first nitride semiconductor layer formed on the base substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer; a cathode electrode formed on one side of the second nitride semiconductor layer; an anode electrode having one end and the other end, one end being recessed at the other side of the second nitride semiconductor layer up to a predetermined depth, and the other end being spaced apart from the cathode electrode and formed to be extended up to an upper portion of the cathode electrode; and an insulating film formed on the second nitride semiconductor layer between the anode electrode and the cathode electrode so as to cover the cathode electrode. | 2014-05-01 |
| 20140117375 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first electrode, a second electrode, a control electrode, and a third electrode. The second semiconductor layer is provided on the first semiconductor layer and has a band gap narrower than that of the first semiconductor layer. The second semiconductor layer includes a first portion and a second portion which is provided together with the first portion and contains an activated acceptor. The third semiconductor layer is provided on the first portion and has a band gap wider than or equal to the band gap of the second semiconductor layer. The first and the second electrodes are provided on the third semiconductor layer. The control electrode is provided between the first electrode and the second electrode. The third electrode is provided on the second portion. | 2014-05-01 |
| 20140117376 | Nitride Semiconductor Element and Method of Manufacturing the Same - A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n | 2014-05-01 |
| 20140117377 | OXYGEN-DOPED GALLIUM NITRIDE SINGLE CRYSTAL SUBSTRATE - Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. Oxygen-doped {20-21}, {1-101}, {1-100}, {11-20} or {20-22} surface n-type gallium nitride crystals are obtained. | 2014-05-01 |
| 20140117378 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device and a method of manufacturing the same are disclosed. The light emitting device includes a buffer layer formed on a substrate, a nitride semiconductor layer including a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially stacked on the buffer layer, a portion of the first semiconductor layer being exposed to the outside by performing mesa etching from the second semiconductor layer to the portion of the first semiconductor layer, and at least one nanocone formed on the second semiconductor layer. | 2014-05-01 |
| 20140117379 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes sequentially forming an n− type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate, and forming a trench through the first n+ region and the p type epitaxial layer, wherein the forming of the trench includes forming a photosensitive layer pattern on the first n+ region, etching the first n+ region and the p type epitaxial layer by using the photosensitive layer pattern as a mask, forming a buffer layer by using amorphous carbon on the first n+ region after the photosensitive layer pattern is removed, forming a buffer layer pattern by etching the buffer layer, etching using the buffer layer pattern as the mask, isotropically etching to form a second portion of the trench, and removing the buffer layer pattern. | 2014-05-01 |
| 20140117380 | FLAT SIC SEMICONDUCTOR SUBSTRATE - Methods for manufacturing silicon carbide wafers having superior specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR). The resulting SiC wafer has a mirror-like surface that is fit for epitaxial deposition of SiC. The specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR) of the wafer are preserved following the addition of the epitaxy layer. | 2014-05-01 |
| 20140117381 | Epitaxial Wafer, Method for Fabricating the Same, and Semiconductor Device Including the Same - Disclosed is an epitaxial wafer including a substrate and an epitaxial structure disposed on the substrate, wherein the epitaxial structure is doped with an n-type or p-type dopant and has a doping uniformity of 10% or less. | 2014-05-01 |
| 20140117382 | Epitaxial Wafer, Method for Fabricating the Wafer, and Semiconductor Device Including the Wafer - Disclosed is an epitaxial wafer including a substrate, and an epitaxial structure disposed on the substrate, wherein the epitaxial structure includes a first epitaxial layer, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed between the first epitaxial layer and the second epitaxial layer, the third epitaxial layer having a first doping concentration around a first boundary adjacent to the first epitaxial layer and a second doping concentration different from the first doping concentration around a second boundary adjacent to the second epitaxial layer. | 2014-05-01 |
| 20140117383 | Optocoupler Having Lens Layer - An optocoupler having optical lens layer is disclosed. The optocoupler may comprise an optical emitter, an optical receiver, an isolation layer, a lens layer and a substantially transparent encapsulant. The lens layer may be integrally formed within the optical receiver. Alternatively, the lens layer may be formed integrally with the isolation layer, or the lens layer may be an optical film attached on the optical receiver. The substantially transparent encapsulant may encapsulate at least partially the optical emitter, the optical receiver and the isolation layer. The isolation layer may be inserted to the substantially transparent encapsulant, making the substantially transparent encapsulant into two compartments. In another embodiment, an electronic system having optocoupler is disclosed. | 2014-05-01 |
| 20140117384 | METHOD OF AND DEVICE FOR MANUFACTURING LED ASSEMBLY USING LIQUID MOLDING TECHNOLOGIES - A method of and a system for making LED comprising concurrently forming multiple dam structures on a whole silicon wafer using a liquid transfer mold, attaching dies to the silicon wafer inside each of the dam structure, performing flux reflow, cleaning flux, performing wire bonding, dispensing phosphor, curing the phosphor, concurrently forming dome structures by using a liquid transfer mold on all of the dam structures, mounting wafer, and using a saw for single or multiple LED(s) singulation. | 2014-05-01 |
| 20140117385 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device including a base substrate, a pixel disposed on the base substrate, and a color filter part disposed between the base substrate and the pixel. The color filter part includes a color filter corresponding to the pixel and a black matrix disposed at at least a side of the color filter. The pixel includes a cover layer defining a tunnel-shaped cavity on the base substrate, an image display part disposed in the tunnel-shaped cavity, and first and second pixel electrodes and a common electrode applying an electric field to the image display part. The tunnel-shaped cavity is formed by forming a sacrificial layer and wet-etching the sacrificial layer. | 2014-05-01 |
| 20140117386 | TILTED EMISSION LED ARRAY - The present disclosure is directed to LED components, and systems using such components, having a light emission profile that may be controlled independently of the lens shape by varying the position and/or orientation of LED chips with respect to one or both of an overlying lens and the surface of the component. For example, the optical centers of the LED emitting surface and the lens, which are normally aligned, may be offset from each other to generate a controlled and predictable emission profile. The LED chips may be positioned to provide a peak emission shifted from a perpendicular centerline of the lens base. The use of offset emitters allows for LED components with shifted or tilted emission patterns, without causing output at high angles of the components. This is beneficial as it allows a lighting system to have tilted emission from the LED component and primary optics. | 2014-05-01 |
| 20140117387 | PHOSPHOR LAYER CONTAINING TRANSPARENT PARTICLES OVER BLUE LED - LED dies are suspended in an ink and printed on a first support substrate to form a light emitting layer having a light emitting surface emitting primary light, such as blue light. A mixture of a transparent binder, phosphor powder, and transparent glass beads is formed as an ink and printed over the light emitting surface. The mixture forms a wavelength conversion layer when cured. The beads are preferably sized so that the tops of the beads protrude completely through the conversion layer. Some of the primary light passes through the beads with virtually no attenuation or backscattering, and some of the primary light is converted by the phosphor to secondary light. The combination of the secondary light and the primary light passing though the beads may form white light. The overall color is highly controllable by controlling the percentage weight of the beads. | 2014-05-01 |
| 20140117388 | LIGHT-EMITTING SEMICONDUCTOR PACKAGES AND RELATED METHODS - Light-emitting semiconductor packages and related methods. The light-emitting semiconductor package includes a central barrier, a plurality of leads, a light-emitting device, a first encapsulant, a package body, and a second encapsulant. The light-emitting device is disposed in the interior space defined by the central barrier and is electrically connected to the leads surrounding the central barrier. The light-emitting device includes upper and lower light-emitting surfaces. The first encapsulant and the second encapsulant cover the upper and lower light-emitting surfaces, respectively. The package body encapsulates portions of the central barrier, portions of each of the leads, and the first encapsulant. The light-emitting semiconductor package can emit light from both the upper and lower sides thereof. | 2014-05-01 |
| 20140117389 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device including a light emitting structure comprising a first semiconductor layer, an active layer and a second semiconductor layer, a phosphor plate disposed on the second semiconductor layer, a first electrode portion disposed on the phosphor plate, and a plurality of bonding portions disposed between the light emitting structure and the phosphor plate, the bonding portions bonding the phosphor plate to the light emitting structure, wherein each bonding portion includes at least one first bonding portion electrically connected to the first electrode portion. | 2014-05-01 |
| 20140117390 | LIGHT EMITTING DIODE PACKAGE - An LED package includes a first electrode and a second electrode electrically insulating from the first electrode, an LED chip, two electrically insulating connecting layers, and a reflector. Top surfaces of the first electrode and the second electrode are recessed to define a first receiving space and a second receiving space therein. The LED chip is mounted on the top surface of the first electrode and electrically connects the first electrode and the second electrode. The electrically insulating connecting layers are respectively received in the first receiving space and the second receiving space. The reflector is mounted on top surfaces of the connecting layers and enclosing the LED chip therein. | 2014-05-01 |
| 20140117391 | LED LENS AND LED PACKAGE USING THE SAME - An LED lens includes a recess disposed in a quadrangular bottom surface of the LED lens and configured to have a light source disposed therein, wherein an internal surface of the recess, including lateral surfaces and top surfaces, is a light incident surface. The LED lens further includes a top surface forming a light exit surface, having a size greater than that of the bottom surface, and having a quadrangular shape; and lateral surfaces of the LED lens, disposed between the top and bottom surfaces of the LED lens, forming a reflective surface, and guiding light incident to the LED lens through the light incident surface to the light exit surface. The top surfaces of the light incident surface form an inverted quadrangular pyramid. | 2014-05-01 |
| 20140117392 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor light emitting device includes forming an isolation pattern on a semiconductor single crystal growth substrate. A first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer are sequentially grown in one chip unit region of the semiconductor single crystal growth substrate defined by the isolation pattern, and a reflective metal layer is formed to cover the light emitting structure and the isolation pattern. A support substrate is formed on the reflective metal layer, and the semiconductor single crystal growth substrate is removed from the light emitting structure. The support substrate is then cut into individual light emitting devices. | 2014-05-01 |
| 20140117393 | LIGHT EMITTING DIODE DEVICES, METHOD OF MANUFACTURE, USES THEREOF - A light emitting diode lighting device contains a light emitting diode and a lighting device component, wherein the device component comprises a polycarbonate composition comprising a bisphenol A polycarbonate; and 2,2′-(1,4-phenylene)bis(4H-3,1-benzoxazin-4-one) in an amount effective to provide a composition wherein a molded sample of the composition has a UL94 rating of V-2 or better at a thickness of 0.9 mm; an absorbance of less than 2 a.u. in the region of 370 to 380 nanometers; and an increase in yellowness index (ΔYI) of 12 or less at 2.5 mm thickness after heat aging at 130° C. for 5,000 hours. | 2014-05-01 |
| 20140117394 | LENS AND LIGHT EMITTING MODULE FOR SURFACE ILLUMINATION - An exemplary embodiment of the present invention discloses a light-emitting module including a circuit board, a light-emitting device disposed on the circuit board, and a lens disposed on the circuit board and configured to distribute light emitted from the light emitting device. The lens includes a concave portion having an incidence surface configured to receive incident light emitted from the light-emitting device, and the light emitting device is disposed within the concave portion of the lens. | 2014-05-01 |
| 20140117395 | LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Provided are a light emitting diode (LED) and a method of fabricating the same. The LED includes a unit chip. The unit chip includes a substrate, and a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer which are sequentially stacked on the substrate. A concavo-convex structure having the shape of irregular vertical lines is disposed in a side surface of the unit chip. | 2014-05-01 |
| 20140117396 | OPTOELECTRONIC SEMICONDUCTOR CHIP, OPTOELECTRONIC SEMICONDUCTOR COMPONENT, AND A METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT - An optoelectronic semiconductor chip includes a semiconductor body that emits primary light, and a luminescence conversion element that emits secondary light by wavelength conversion of at least part of the primary light, wherein the luminescence conversion element has a first lamina fixed to a first partial region of an outer surface of the semiconductor body, the outer surface emitting primary light, and leaves free a second partial region of the outer surface, the luminescence conversion element has a second lamina fixed to a surface of the first lamina facing away from the semiconductor body and spaced apart from the semiconductor body, the first lamina is at least partly transmissive to the primary radiation, a section of the second lamina covers at least the second partial region, and at least the section of the second lamina is designed to be absorbent and/or reflective and/or scattering for the primary radiation. | 2014-05-01 |
| 20140117397 | MOLD HAVING AN UNEVEN SURFACE STRUCTURE, OPTICAL ARTICLE, MANUFACTURING METHOD THEREFOR, TRANSPARENT SUBSTRATE FOR SURFACE LIGHT EMITTER AND SURFACE LIGHT EMITTER - The invention relates to a mold having an irregularly uneven surface structure in which an average inclination angle is from 20 to 80 degrees; an optical article having an irregularly uneven surface structure in which an average inclination angle is from 20 to 80 degrees; a method for manufacturing an optical article having an irregularly uneven surface structure by transferring an uneven structure of a mold; a transparent substrate for a surface light emitter which uses an optical article having an irregularly uneven surface structure; and a surface light emitter having a transparent substrate for a surface light emitter. | 2014-05-01 |
| 20140117398 | Epitaxial Substrate, Light-Emitting Diode, and Methods for Making the Epitaxial Substrate and the Light-Emitting Diode - An epitaxial substrate includes: a base member; and a plurality of spaced apart light-transmissive members, each of which is formed on and tapers from an upper surface of the base member, and each of which is made of light-transmissive material having a refractive index lower than that of the base member. A light-emitting diode having the epitaxial substrate, and methods for making the epitaxial substrate and the light-emitting diode are also disclosed. | 2014-05-01 |
| 20140117399 | LIGHT EMITTING DEVICE - A light emitting device may be provided that includes a conductive support member, a first conductive layer, a second conductive layer, an insulation layer between the first conductive layer and the second conductive layer, and a light emitting structure that includes a second semiconductor layer on the second conductive layer, a first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer. The first conductive layer may include at least one conductive via that passes through the second conductive layer, the second semiconductor layer and the active layer. A top surface of the at least one conductive via is provided into the first semiconductor layer. The insulation layer may substantially surround a side wall of the conductive via. | 2014-05-01 |
| 20140117400 | LIGHT EMITTING DEVICE - A light emitting device may be provided that includes a conductive support member, a first conductive layer, a second conductive layer, an insulation layer between the first conductive layer and the second conductive layer, and a light emitting structure that includes a second semiconductor layer on the second conductive layer, a first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer. The first conductive layer may include at least one conductive via that passes through the second conductive layer, the second semiconductor layer and the active layer. A top surface of the at least one conductive via is provided into the first semiconductor layer. The insulation layer may substantially surround a side wall of the conductive via. | 2014-05-01 |
| 20140117401 | Nanowire LED Structure and Method for Manufacturing the Same - A method for ablating a first area of a light emitting diode (LED) device which includes an array of nanowires on a support with a laser is provided. The laser ablation exposes a conductive layer of the support that is electrically connected to a first conductivity type semiconductor nanowire core in the nanowires, to form a first electrode for the LED device. In embodiments, the nanowires are aligned at least 20 degrees from the plane of the support. A light emitting diode (LED) structure includes a first electrode for contacting a first conductivity type nanowire core, and a second electrode for contacting a second conductivity type shell enclosing the nanowire core, where the first electrode and/or at least a portion of the second electrode are flat. | 2014-05-01 |
| 20140117402 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - A semiconductor light emitting element ( | 2014-05-01 |
| 20140117403 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT EMITTING DEVICE - The light emitting device package has a lengthwise direction as viewed from above and a lateral or widthwise direction perpendicular to the lengthwise direction, and is provided with two lead-frames lined-up in the lengthwise direction and molded resin formed as a single unit with the two lead-frames. The package is characterized in that each of the two lead-frames has a first thin region that is thinned by establishing a recess in the lower surface and/or the upper surface of the lead-frame, and that recess is covered with molded resin. Further, each lead-frame has an extension that narrows as it extends towards the opposite lead-frame. Both extensions are entirely within first thin regions, and as viewed from above, at least parts of the opposing extensions are positioned opposite each other in the lateral direction. | 2014-05-01 |
| 20140117404 | LIGHT-EMITTING DEVICE WITH IMPROVED ELECTRODE STRUCTURES - A light-emitting device includes first and second semiconductor layers and a light-emitting layer between the first and second semiconductor layers. The light-emitting device also includes an improved electrode structures. | 2014-05-01 |
| 20140117405 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed on one surface of the first semiconductor region; a third semiconductor region having a first conductivity type and formed on one surface of the second semiconductor region; a gate electrode formed in a trench penetrating through the second semiconductor region and the third semiconductor region to reach an interior of the first semiconductor region; and a hole injection unit formed between the gate electrode and the first semiconductor region. | 2014-05-01 |
| 20140117406 | REVERSE BLOCKING MOS SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A reverse blocking IGBT is disclosed in which a lifetime control region formed by helium ion irradiation is selectively provided in a region within a range approximately corresponding to the planar pattern of a p-type base region in the direction along the principal surface of a silicon semiconductor substrate of n-type and within a range from the upward vicinity to the downward vicinity of the p-n junction on the bottom of the p-type base region in the direction of the depth of the silicon semiconductor substrate. This can provide a reverse blocking MOS semiconductor device capable of further decreasing a reverse leakage current less than the current in a previous device while making the influence on an on-state current small. | 2014-05-01 |
| 20140117407 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction. | 2014-05-01 |
| 20140117408 | UNIT POWER MODULE AND POWER MODULE PACKAGE COMPRISING THE SAME - Disclosed herein is a unit power module including: a first semiconductor chip having one surface on which a 1-1-th electrode and a 1-2-th electrode spaced apart from the 1-1-th electrode are formed and the other surface on which a 1-3-th electrode is formed, a second semiconductor chip having one surface on which a 2-1-th electrode is formed and the other surface on which a 2-2-th electrode is formed, a first metal plate contacting the 1-1-th electrode of the first semiconductor chip and the 2-1-th electrode of the second semiconductor chip, a second metal plate contacting the 1-2-th electrode of the first semiconductor chip and spaced apart from the first metal plate, a third metal plate contacting the 1-3-th electrode of the first semiconductor chip and the 2-2-th electrode of the second semiconductor chip, and a sealing member formed to surround the first metal plate, the second metal plate, and the third metal plate. | 2014-05-01 |
| 20140117409 | METHOD AND STRUCTURE FOR BODY CONTACTED FET WITH REDUCED BODY RESISTANCE AND SOURCE TO DRAIN CONTACT LEAKAGE - A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body having a body contact region and an abutting switching region; a bridged gate over the semiconductor body, the bridged gate having a bridge gate portion and an abutting gate portion, the bridge gate portion comprising a multilayer first gate stack and the gate portion comprising a multilayer second gate stack comprising the gate dielectric layer on the semiconductor body; first and second source/drains formed in the switching region on opposite sides of the channel; and wherein a first work function difference between the bridge portion and the body contact region is different from a second work function difference between the gate portion and the channel region. | 2014-05-01 |
| 20140117410 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer formed on a substrate and formed of a nitride-based semiconductor; a second semiconductor layer formed on a surface of the first semiconductor layer and formed of a nitride-based semiconductor having a wider band-gap than the first semiconductor layer; first and second electrodes formed on a surface of the second semiconductor layer; an inter-electrode insulator film that is formed between the first and second electrodes on the surface of the second semiconductor layer; and a dielectric constant adjustment layer formed on the inter-electrode insulator film and formed of an electric insulator. The first electrode has a field plate portion formed so as to ride on the inter-electrode insulator film, and the dielectric constant adjustment layer has a first layer that contacts a lateral end portion of the field plate portion and a second layer formed on the first layer. | 2014-05-01 |
| 20140117411 | MONOLITHIC INTEGRATED CIRCUIT - A monolithic integrated circuit includes: a substrate having a diode region and a transistor region; a first semiconductor layer on the substrate in the diode region and in the transistor region; a second semiconductor layer on the first semiconductor layer in the diode region and in the transistor region; a third semiconductor layer on the second semiconductor layer in the transistor region, but not located in the diode region; a first electrode in the diode region and connected to the first semiconductor layer; a second electrode in the diode region and connected to the second semiconductor layer; and a source electrode, a gate electrode, and a drain electrode which are on the third semiconductor layer. | 2014-05-01 |
| 20140117412 | Heterojunction Transistor and Manufacturing Method Therefor - A heterojunction transistor including a semiconductor body is provided. The semiconductor body includes: a base region of a semiconductor material having a first band-gap, the base region being of a first conductivity type; a collector region of a semiconductor material having a second band-gap which is larger than the first band-gap by at least about 1 eV, the collector region being of a second conductivity type and forming a first heterojunction with the base region; and an emitter region of a semiconductor material having a third band-gap which is larger than the first band-gap by at least about 1 eV, the emitter region being of the second conductivity type and forming a second heterojunction with the base region. Further, a method for producing a heterojunction transistor is provided. | 2014-05-01 |
| 20140117413 | PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS - A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array. | 2014-05-01 |
| 20140117414 | SEMICONDUCTOR DEVICE HAVING A TRIPLE GATE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. | 2014-05-01 |
| 20140117415 | JUNCTION FIELD EFFECT TRANSISTORS AND ASSOCIATED FABRICATION METHODS - A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region. | 2014-05-01 |
| 20140117416 | SEMICONDUCTOR DEVICE AND ASSOCIATED METHOD FOR MANUFACTURING - A semiconductor device having a trench-gate MOSFET and a vertical JFET formed in a semiconductor layer. In the semiconductor device, a gate region of the vertical JFET may be electrically coupled to a source region of the trench-gate MOSFET, and a drain region of the vertical JFET and a drain region of the trench-gate MOSFET may share a common region in the semiconductor layer. | 2014-05-01 |
| 20140117417 | PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING A GRADED EMBEDDED STRAIN-INDUCING SEMICONDUCTOR REGION WITH ADAPTED ANGLES WITH RESPECT TO THE SUBSTRATE SURFACE - In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity. | 2014-05-01 |
| 20140117418 | THREE-DIMENSIONAL SILICON-BASED TRANSISTOR COMPRISING A HIGH-MOBILITY CHANNEL FORMED BY NON-MASKED EPITAXY - Three-dimensional transistors may be formed on the basis of high mobility semiconductor materials, which may be provided locally restricted in the channel region by selective epitaxial growth processes without using a mask material for laterally confining the growing of the high mobility semiconductor material. That is, by controlling process parameters of the selective epitaxial growth process, the cross-sectional shape may be adjusted without requiring a mask material, thereby reducing overall process complexity and providing an additional degree of freedom for adjusting the transistor characteristics in terms of threshold voltage, drive current and electrostatic control of the channel region. | 2014-05-01 |
| 20140117419 | FIN ETCH AND FIN REPLACEMENT FOR FINFET INTEGRATION - A method and device are provided for etching and replacing silicon fins in connection with a FinFET integration process. Embodiments include providing a first plurality and a second plurality of silicon fins on a silicon wafer with an oxide between adjacent silicon fins; forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween; etching the second plurality of silicon fins, forming trenches; removing the first nitride liner; depositing a second nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches; removing the second nitride liner down to the upper surface of the first plurality of silicon fins; and recessing the oxide. | 2014-05-01 |
| 20140117420 | SEMICONDUCTOR STRUCTURE INCORPORATING A CONTACT SIDEWALL SPACER WITH A SELF-ALIGNED AIRGAP AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE - Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts. | 2014-05-01 |
| 20140117421 | SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE - A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material. | 2014-05-01 |
| 20140117422 | FIN FIELD EFFECT TRANSISTORS HAVING A NITRIDE CONTAINING SPACER TO REDUCE LATERAL GROWTH OF EPITAXIALLY DEPOSITED SEMICONDUCTOR MATERIALS - A fin field effect transistor including a plurality of fin structures on a substrate, and a shared gate structure on a channel portion of the plurality of fin structures. The fin field effect transistor further includes an epitaxial semiconductor material having a first portion between adjacent fin structures in the plurality of fin structures and a second portion present on outermost sidewalls of end fin structures of the plurality of fin structures. The epitaxial semiconductor material provides a source region and at drain region to each fin structure of the plurality of fin structures. A nitride containing spacer is present on the outermost sidewalls of the second portion of the epitaxial semiconductor material. | 2014-05-01 |
| 20140117423 | INSULATIVE CAP FOR BORDERLESS SELF-ALIGNING CONTACT IN SEMICONDUCTOR DEVICE - An apparatus comprises: a semiconductor device on a base substrate, the semiconductor device having a core metal positioned proximate a source and a drain in the base substrate; a work function metal on a portion of the core metal; a dielectric liner on a portion of the work function metal; a metal gate in electrical communication with one of the source and the drain; and an insulator film implanted into the core metal, the insulator film forming an insulative barrier across the metal gate and between the core metal and the source or the drain. | 2014-05-01 |
| 20140117424 | SEMICONDUCTOR DEVICE - A semiconductor device is provided that includes a substrate including a device region and a peripheral region surrounding the device region, a first interconnection including one or more first conductive lines extending in a first direction, a second interconnection including one or more second conductive lines extending in the first direction, the second interconnection spaced apart from the first interconnection, a first conductive plate and a second conductive plate spaced apart from each other, the first conductive plate corresponding to the first interconnection and the second conductive plate corresponding to the second interconnection, one or more first vias connecting the first conductive lines to the first conductive plate and overlapping the device region and one or more second vias connecting the second conductive lines to the second conductive plate, the second vias overlapping the device region and arranged in a staggered, alternating configuration with the one or more first vias. | 2014-05-01 |
| 20140117425 | INTERLAYER DIELECTRIC FOR NON-PLANAR TRANSISTORS - The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor. | 2014-05-01 |
| 20140117426 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided. The semiconductor device comprising a substrate, a first fin formed on the substrate, and an isolation film formed on the substrate and coming in contact with a part of the first fin, wherein the first fin includes a first region that is in contact with the isolation film, a second region that is in non-contact with the isolation film, and a boundary line between the first region and the second region, the first region has a slope that is at right angles with respect to the boundary line, and the second region has a slope that is an acute angle with respect to the boundary line. | 2014-05-01 |
| 20140117427 | STACKED STRUCTURE, SPIN TRANSISTOR, AND RECONFIGURABLE LOGIC CIRCUIT - A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer. | 2014-05-01 |
| 20140117428 | Image Sensor - Disclosed is an image sensor including a photodiode region on a first conductive type semiconductor substrate; a first floating diffusion region having a second conductive type, separate from the photodiode region; a second floating diffusion region having the second conductive type, separate from the first floating diffusion region; a first gate on the semiconductor substrate between the photodiode region and the first floating diffusion region; and a second gate on the semiconductor substrate between the first floating diffusion region and the second floating diffusion region, wherein the semiconductor substrate and the first floating diffusion region forms a junction area that is larger than that of the semiconductor substrate and the second floating diffusion region. | 2014-05-01 |
| 20140117429 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer. | 2014-05-01 |
| 20140117430 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate. | 2014-05-01 |
| 20140117431 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped charge storage layer arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the charge storage layer and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the charge storage layer in such a manner that an insulating film is interposed between the control gate and the charge storage layer. The insulating film is arranged so as to be interposed between the charge storage layer and the upper, lower, and inner side surfaces of the control gate. | 2014-05-01 |
| 20140117432 | NONVOLATILE MEMORY DEVICE, METHOD FOR FABRICATING THE SAME, AND METHOD FOR OPERATING THE SAME - A nonvolatile memory device includes bit and source lines alternately arranged parallel to each other and even strings and odd strings alternately arranged between the bit lines and the source lines and each including drain selection transistors, memory transistors, and a source selection transistor. The drain selection transistors include a first drain selection transistor with the same structure as the memory transistors and a second drain selection transistor with the same structure as the source selection transistor. The nonvolatile memory device further includes an even drain selection line connected to the first drain selection transistors of the even strings and the second drain selection transistors of the odd strings and an odd drain selection line connected to the second drain selection transistors of the even strings and the first drain selection transistors of the odd strings. | 2014-05-01 |
| 20140117433 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film. | 2014-05-01 |
| 20140117434 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit. | 2014-05-01 |
| 20140117435 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 2014-05-01 |
| 20140117436 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench. | 2014-05-01 |
| 20140117437 | Super Junction Semiconductor Device Comprising a Cell Area and an Edge Area - A super junction semiconductor device may include one or more doped zones in a cell area. A drift layer is provided between a doped layer of a first conductivity type and the one or more doped zones. The drift layer includes first regions of the first conductivity type and second regions of a second conductivity type, which is the opposite of the first conductivity type. In an edge area that surrounds the cell area, the first regions may include first portions separating the second regions in a first direction and second portions separating the second regions in a second direction orthogonal to the first direction. The first and second portions are arranged such that a longest second region in the edge area is at most half as long as a dimension of the edge area parallel to the longest second region. | 2014-05-01 |
| 20140117438 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device is at least partially formed in a semiconductor substrate, the substrate including first and second opposing main surfaces. The semiconductor device includes a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, the cell field portion including at least a transistor. The contact area includes a connection substrate portion insulated from other substrate portions and including a part of the semiconductor substrate, an electrode adjacent to the second main surface and in contact with the connection substrate portion, and a metal layer disposed over the first main surface, the connection substrate portion being electrically coupled to the metal layer to form an ohmic contact between the electrode and metal layer. The connection substrate portion is not electrically coupled to a component of the cell field portion by a conductive material disposed between the first and second main surfaces. | 2014-05-01 |
| 20140117439 | MOS-Gated Power Devices, Methods, and Integrated Circuits - MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances. | 2014-05-01 |
| 20140117440 | SEMICONDUCTOR DEVICE WITH IMPURITY REGION WITH INCREASED CONTACT AREA - A semiconductor device includes a semiconductor substrate, an impurity region in the semiconductor substrate, and a conductive layer contacting a top surface of the impurity region and at least a side surface of the impurity region. | 2014-05-01 |
| 20140117441 | POWER DEVICE STRUCTURES AND METHODS - Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling. | 2014-05-01 |
| 20140117442 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source. | 2014-05-01 |
| 20140117443 | DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance. | 2014-05-01 |
| 20140117444 | Lateral MOSFET - A lateral MOSFET comprises a plurality of isolation regions formed in a substrate, wherein a first isolation region is of a top surface lower than a top surface of the substrate. The lateral MOSFET further comprises a gate electrode layer having a first gate electrode layer formed over the first isolation region and a second gate electrode layer formed over the top surface of the substrate, wherein a top surface of the first gate electrode layer is lower than a top surface of the second gate electrode layer. | 2014-05-01 |
| 20140117445 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer. | 2014-05-01 |
| 20140117446 | LDMOS Device with Minority Carrier Shunt Region - A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region. | 2014-05-01 |
| 20140117447 | DUAL GATE FINFET DEVICES - A device comprises: a first plurality of fins on a semiconductor substrate, the first plurality of fins including a semiconductor material and extending perpendicular from the semiconductor substrate; a second plurality of fins on the semiconductor substrate, the second plurality of fins including a semiconductor material and extending perpendicular from the semiconductor substrate; a chemox layer deposited on lower portions of the fins of the first plurality of fins; and a dielectric layer deposited on the fins of the second plurality of fins. The dielectric layer is thicker than the chemox layer. | 2014-05-01 |
