18th week of 2020 patent applcation highlights part 71 |
Patent application number | Title | Published |
20200135740 | Memory Devices with Gate All Around Transistors - A memory structure and a system-on chip (SOC) device are provided. A memory structure according to the present disclosure includes a first static random access memory (SRAM) macro comprising first gate-all-around (GAA) transistors and a second SRAM macro comprising second GAA transistors. The first GAA transistors of the first SRAM macro each includes a first plurality of channel regions each having a first channel width (W1) and a first channel thickness (T1). The second GAA transistors of the second SRAM macro each comprises a second plurality of channel regions each having a second channel width (W2) and a second channel thickness (T2). W2/T2 is greater than W1/T1. | 2020-04-30 |
20200135741 | SRAM Structure and Connection - A semiconductor structure includes SRAM cells, bit-line edge cells, and word-line edge cells, wherein the SRAM cells are arranged in an array, bordered by the bit-line edge cells and the word-line edge cells, each of the SRAM cells including two inverters cross-coupled together and a pass gate coupled to the two inverters, and the pass gate includes a FET; a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to a drain feature of the FET; a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer; and a second bit-line of a third metal material, electrically connected to the first bit-line, and disposed in a third metal layer. The first metal material and the third metal material are different from each other in composition. | 2020-04-30 |
20200135742 | MEMORY DEVICE AND MANUFACTURING METHOD - A static random access memory device includes a write circuit, a read port circuit, and a substrate. The write port circuit includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass-gate transistor coupled to the first inverter, and a second pass-gate transistor coupled to the second inverter. The read port circuit includes a read pull-down transistor and a read pass-gate transistor that are coupled in series to each other. The substrate includes a standard threshold voltage (STV) region and a low threshold voltage (LVT) region abutting the STV region. The write port circuit is formed within the STV region, and the read port circuit is formed within the LVT region. The LVT region has a first boundary at an edge of a gate of the first pass-gate transistor, or approaching the edge of the gate of the first pass-gate transistor. | 2020-04-30 |
20200135743 | MANUFACTURING METHOD OF STATIC RANDOM ACCESS MEMORY CELL - A method for manufacturing a SRAM cell includes forming a first p-well in a semiconductor substrate; forming a first semiconductor fin extending within the first p-well; forming a first mask layer over the first semiconductor fin; patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer; with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant; after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin. | 2020-04-30 |
20200135744 | SRAM Cell with Balanced Write Port - A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors; and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first, second, and fifth gates are electrically connected, and wherein one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the third gate, and the fourth gate are electrically connected. | 2020-04-30 |
20200135745 | Memory Arrays, and Methods of Forming Memory Arrays - Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies. | 2020-04-30 |
20200135746 | ANTI-FUSE CELL AND CHIP HAVING ANTI-FUSE CELLS - An anti-fuse cell includes a control device and an anti-fuse element is introduced. The control device includes a source node, a drain node and a gate node, wherein the gate node is electrically coupled to a word line and the drain node is electrically coupled to a bit line. The anti-fuse element includes a first conductive layer, a second conductive layer and a dielectric layer, wherein the dielectric layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer of the anti-fuse element is physically stacked upon a conductive layer and electrically connected to the source node of the control device, and first conductive layer is electrically coupled to a program line through a via. An anti-fuse cell having multiple anti-fuse elements and a chip having a plurality of anti-fuse cells are also introduced. | 2020-04-30 |
20200135747 | STACKED FINFET READ ONLY MEMORY - A stacked FinFET mask-programmable read only memory (ROM) is provided. The stacked FinFET mask-programmable ROM includes a fin structure extending upward from an insulator layer. The fin structure includes, from bottom to top, a first semiconductor fin portion, an insulator fin portion, and a second semiconductor fin portion. A lower gate structure having a first threshold voltage contacts a sidewall of the first semiconductor fin portion, and an upper gate structure having a second threshold voltage contacts a sidewall of the second semiconductor fin portion. | 2020-04-30 |
20200135748 | MEMORY CELL PILLAR INCLUDING SOURCE JUNCTION PLUG - Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug. | 2020-04-30 |
20200135749 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction. | 2020-04-30 |
20200135750 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction. | 2020-04-30 |
20200135751 | Integrated Assemblies Which Include Stacked Memory Decks, and Methods of Forming Integrated Assemblies - Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies. | 2020-04-30 |
20200135752 | STRUCTURE OF 3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME - A structure of 3D NAND memory device and manufacturing method are provided. The structure of 3D NAND memory device includes a substrate, a first stack layer on the substrate, a second stack layer on the first stack layer, a block layer between the first stack layer and the second stack layer, and a channel structure extending through the first stack layer, the block layer and the second stack layer, wherein the channel structure comprises a function layer and a channel layer surrounding by the functional layer. | 2020-04-30 |
20200135753 | THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF - A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a temporary top selective gate cut in an upper portion of the alternating dielectric stack and extending along a lateral direction; forming a plurality of channel holes penetrating the alternating dielectric stack; removing the temporary top selective gate cut; and forming, simultaneously, a plurality of channel structures in the plurality of channel holes and a top selective gate cut structure. | 2020-04-30 |
20200135754 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided herein may be a method of manufacturing a semiconductor device including the step of replacing sacrificial layers of a stack with line patterns through slits that pass through the stack and have different depths. | 2020-04-30 |
20200135755 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure. | 2020-04-30 |
20200135756 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - A 3D semiconductor memory device includes an electrode structure on a substrate, the electrode structure including gate electrodes stacked in a first direction perpendicular to a top surface of the substrate, a vertical semiconductor pattern penetrating the electrode structure and connected to the substrate, and a data storage pattern between the electrode structure and the vertical semiconductor pattern. The data storage pattern includes first, second and third insulating patterns sequentially stacked. Each of the first to third insulating patterns includes a horizontal portion extending in a second direction parallel to the top surface of the substrate. The horizontal portions of the first, second and third insulating patterns are sequentially stacked in the first direction. At least one of the horizontal portions of the first and third insulating patterns protrudes beyond a sidewall of the horizontal portion of the second insulating pattern in the second direction. | 2020-04-30 |
20200135757 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes conductive lines on a substrate, first and second semiconductor patterns, first and second pads, first and second electrodes, a third electrode, and a first division pattern. The conductive lines are stacked in a vertical direction and extend in a first direction. The first and second semiconductor patterns extend through the conductive lines in the vertical direction. The first and second pads are formed on the first and second semiconductor patterns. The first and second electrodes are electrically connected to the first and second pads. The third electrode is electrically connected to a first conductive line of the conductive lines. The first division pattern extends in a second direction, and extends through and divides the first conductive line. In a plan view, the first and second semiconductor patterns and the first conductive line are disposed at one side of the first division pattern. | 2020-04-30 |
20200135758 | NONVOLATILE MEMORY DEVICE, VERTICAL NAND FLASH MEMORY DEVICE AND SSD DEVICE INCLUDING THE SAME - A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region. | 2020-04-30 |
20200135759 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A hole is formed to pass through preliminary first mold layers and preliminary second mold layers to form first mold layers and mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure. The first mold layers are partially etched along a side surface of the hole to form recess regions and recessed first mold layers. Third mold layers are formed in the recess regions to form interlayer insulation layers so that each of the interlayer insulation layers includes a corresponding third mold layer and a corresponding recessed first mold layer that are positioned at the same level in the vertical direction. A first dielectric layer is formed in the hole to cover the third mold layers and the second mold layers stacked on each other. Information storage patterns are formed on the first dielectric layer. | 2020-04-30 |
20200135760 | METHODS OF MANUFACTURING A VERTICAL MEMORY DEVICE - A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode. | 2020-04-30 |
20200135761 | SEMICONDUCTOR MEMORY DEVICE HAVING A CHANNEL STRUCTURE VERTICALLY PASSING THROUGH A PLURALITY OF MEMORY LAYERS AND HAVING MEMORY CELL BLOCKS AND DUMMY MEMORY CELL BLOCKS - A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate. | 2020-04-30 |
20200135762 | SEMICONDUCTOR STRUCTURE - Semiconductor structures are provided. Each of the transistors includes a first source/drain region over a semiconductor fin extending in a first direction, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction perpendicular to the first direction. In a first transistor of the transistors, a first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors, A second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate extending in the second direction. A first contact of the first source/drain region is narrower than a second contact of the second source/drain region along the first direction. | 2020-04-30 |
20200135763 | ARRAY SUBSTRATE AND DISPLAY PANEL - An array substrate and a display panel are provided. The array substrate comprises a display area including a first and a second display area parallelly arranged along a first direction, wherein the second display area includes a first edge portion extending along a second direction; a non-display area including a first and a second non-display area, wherein in the second direction, the first non-display area is disposed at one side of the display area and includes a first sub-non-display area and a second sub-non-display area; at least one notch formed by recessing the first edge portion toward an inside of the second display area; data lines; and at least one driving chip. An orthogonal projection of the at least one driving chip onto the array substrate is at least partially located in the second sub-non-display area. The second non-display area is disposed at perimeter of the at least one notch. | 2020-04-30 |
20200135764 | DISPLAY PANEL INCLUDING LINK LINES - A display panel includes: a display area including: a curved boundary in plan view, and a pixel array including pixel rows, and a non-display area in a periphery of the display area, and including: a curved boundary in plan view, a plurality of gate blocks arranged along the curved boundary of the non-display area, and at least one dummy block among the gate blocks, and a plurality of link lines configured to connect the gate blocks to the pixel rows, at least one of the link lines being multi-segmented to include a plurality of segments oriented in different directions in plan view. | 2020-04-30 |
20200135765 | TRANSISTOR DISPLAY PANEL - A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view. | 2020-04-30 |
20200135766 | MONOLITHIC INTEGRATION OF GAN HEMT AND SI CMOS - A CMOS process is disclosed for manufacturing an integrated circuit including both MOSFETS and GaN HEMT devices. Each GaN HEMT device resides within an oxidized window that exposes a silicon substrate having a <111> crystal lattice orientation. | 2020-04-30 |
20200135767 | METHOD FOR FABRICATING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY - A method for fabricating an array substrate, after the wet etching process of the source-drain metal layer ( | 2020-04-30 |
20200135768 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin. | 2020-04-30 |
20200135769 | Metal Oxide Thin Film Semiconductor Device Monolithically Integrated With Dissimilar Device on the Same Wafer - A monolithically integrated circuit comprising a semiconducting wafer, a metal oxide thin film semiconductor device disposed adjacent a first region of the semiconducting wafer, and a dissimilar semiconductor device disposed adjacent a second region of the semiconducting wafer and fabrication methods thereof. | 2020-04-30 |
20200135770 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCTION SYSTEM - A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film. | 2020-04-30 |
20200135771 | TRANSISTOR AND ELECTRONIC DEVICE - An electronic device comprises a panel, a driving circuit configured to drive the panel, and a transistor disposed in the panel. The transistor includes a first insulation film on a substrate, an active layer disposed on the first insulation film, a second insulation film disposed on the active layer and the first insulation film to cover the active layer, the second insulation film having a thickness smaller than a thickness of the first insulation film, a source electrode disposed on the second insulation film and spaced apart from the active layer by the second insulation film, the source electrode overlapping an end of the active layer, and a drain electrode disposed on the second insulation film and spaced apart from the active layer by the second insulation film, the drain electrode overlapping another end of the active layer. | 2020-04-30 |
20200135772 | DISPLAY DEVICE COMPRISING A PLURALITY OF THIN FILM TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME - A display device can include a pixel driver disposed on a substrate; and a display element electrically connected with the pixel driver, in which the pixel driver includes a first thin film including a first semiconductor layer, a first gate electrode, at least a part of the first gate electrode overlapping with the first semiconductor layer, and a first source electrode and a first drain electrode respectively connected with the first semiconductor layer; and a second thin film including a second semiconductor layer, a second gate electrode, at least a part of the second gate electrode overlapping with the second semiconductor layer, and a second source electrode and a second drain electrode respectively connected with the second semiconductor layer, in which the first semiconductor layer and the second semiconductor layer are disposed in different layers, and the first source electrode, the first drain electrode, the second gate electrode, the second source electrode, and the second drain electrode are disposed in a same layer. | 2020-04-30 |
20200135773 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE HAVING THE SAME - A change in electrical characteristics can be inhibited and reliability can be improved in a semiconductor device including an oxide semiconductor. The semiconductor device including an oxide semiconductor film includes a first insulating film, the oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, and a third insulating film over the second insulating film. The second insulating film includes oxygen and silicon, the third insulating film includes nitrogen and silicon, and indium is included in a vicinity of an interface between the second insulating film and the third insulating film. | 2020-04-30 |
20200135774 | INVERTER CIRCUIT STRUCTURE, GATE DRIVING CIRCUIT AND DISPLAY PANEL - Provided are an inverter circuit structure, a gate driving circuit and a display panel. The inverter circuit structure includes a PMOS transistor and an NMOS transistor, and further includes a first active layer, a gate layer, a second active layer, a first insulating layer between the gate layer and the first active layer, and a second insulating layer between the gate layer and the second active layer. An orthographic projection of the gate on the first active layer is a first region, and a portion of the first active layer in the first region has substantially a same thickness. An orthographic projection of the gate on the second active layer is a second region, and a portion of the second active layer in the second region has substantially a same thickness. | 2020-04-30 |
20200135775 | DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - Embodiments of the present disclosure provide a display substrate, a method for manufacturing a display substrate, and a display device. The method for manufacturing the display substrate includes: providing a seed layer on a first carrier substrate and forming a base substrate covering the seed layer; forming a first connection terminal on a side of the base substrate away from the first carrier substrate, the first connection terminal electrically connecting to the seed layer; removing the first carrier substrate to expose the seed layer; and forming a second connection terminal electrically connecting to the seed layer. | 2020-04-30 |
20200135776 | HIGH QUANTUM EFFICIENCY GEIGER-MODE AVALANCHE DIODES INCLUDING HIGH SENSITIVITY PHOTON MIXING STRUCTURES AND ARRAYS THEREOF - A photodetector device includes a semiconductor material layer and at least one photodiode in the semiconductor material layer. The at least one photodiode is configured to be biased beyond a breakdown voltage thereof to generate respective electrical signals responsive to detection of incident photons. The respective electrical signals are independent of an optical power of the incident photons. A textured region is coupled to the semiconductor material layer and includes optical structures positioned to interact with the incident photons in the detection thereof by the at least one photodiode. Two or more photodiodes may define a pixel of the photodetector device, and the optical structures may be configured to direct the incident photons to any of the two or more photodiodes of the pixel. | 2020-04-30 |
20200135777 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH THREE-DIMENSIONAL TRANSISTOR STRUCTURE AND FORMING METHOD THEREOF - A method for forming a backside illuminated image sensor with a three-dimensional transistor structure is provided, where forming a gate of the three-dimensional transistor structure includes: forming a source follower transistor and/or a reset transistor with a three-dimensional transistor structure, wherein the source follower transistor and/or the reset transistor correspond to a protruding structure; and forming an insulating sidewall around the protruding structure, forming a groove between the insulating sidewall and a channel region of a transistor corresponding to the protruding structure, and forming a gate of the transistor in the groove, wherein the gate of the transistor is isolated by the insulating sidewall. | 2020-04-30 |
20200135778 | LENS MODULE - A lens module includes a circuit board, a hollow mounting bracket, a photosensitive chip, a lens base, and a lens. The photosensitive chip is mounted within the hollow mounting bracket on a surface of the circuit board. The lens base is mounted on a surface of the mounting bracket opposite to the circuit board. The lens base axially defines a through hole. The lens is mounted within the lens base. The lens base includes a screw thread formed along an inner wall of the through hole. The lens includes mating threads formed along a periphery of the lens contacting the inner wall of the through hole. The mating threads define at least one thread slot which defines a gap with the screw threads of the inner wall of the through hole. | 2020-04-30 |
20200135779 | IMAGING DEVICE WITH UNIFORM PHOTOSENSITVIE REGION ARRAY - Various embodiments of the present disclosure are directed towards a pixel sensor including a first and second pair of photodetectors. The pixel sensor includes the first and second pair of photodetectors in a semiconductor substrate. The first pair of photodetectors are reflection symmetric with respect to a first line positioned at a midpoint between the first pair of photodetectors. The second pair of photodetectors are reflection symmetric with respect to a second line that intersects the first line at a center point. A first plurality of transistors overlying the semiconductor substrate laterally offset the first pair of photodetectors. A second plurality of transistors overlying the semiconductor substrate laterally offset the first plurality of transistors. The first and second pair of photodetectors are laterally between the first and second plurality of transistors. The first and second plurality of transistors are point symmetric with respect to the center point. | 2020-04-30 |
20200135780 | RADIATION IMAGING APPARATUS, RADIATION IMAGING METHOD, AND STORAGE MEDIUM - A radiation imaging apparatus in which a pixel for obtaining an image based on radiation and a light shielded pixel which is shielded from light are arranged in an array, comprises: a setting unit configured to set a region including a plurality of pixels for obtaining the image based on the radiation and cause pixel values based on the plurality of pixels in the region to be output; and a correction unit configured to determine whether the light shielded pixel is included in the region, and correct the pixel values based on the plurality of pixels in the region if the light shielded pixel is included in the region. | 2020-04-30 |
20200135781 | SOLID-STATE IMAGING ELEMENT AND ELECTRONIC APPARATUS - To enhance a charge transfer efficiency in a transfer gate having a vertical gate electrode. A solid-state imaging element includes a photoelectric conversion section, a charge accumulating section, and a transfer gate. The photoelectric conversion section is formed in a depth direction of a semiconductor substrate, and generates charges corresponding to a quantity of received light. The charge accumulating section accumulates the charges generated by the photoelectric conversion section. The transfer gate transfers the charges generated by the photoelectric conversion section to the charge accumulating section. The transfer gate includes a plurality of vertical gate electrodes which is filled to a predetermined depth from an interface of the semiconductor substrate, and at least a part of a diameter is different in the depth direction of the semiconductor substrate. | 2020-04-30 |
20200135782 | PHOTOSENSITIVE ASSEMBLY AND FORMATION METHODS THEREOF, LENS MODULE, AND ELECTRONIC DEVICE - The present disclosure provides a method for forming a photosensitive assembly. The method includes providing a transparent cover plate; providing a photosensitive chip, including a photosensitive region and a peripheral region surrounding the photosensitive region; and bonding the transparent cover plate to the photosensitive chip through a bonding layer located in the peripheral region of the photosensitive chip. The transparent cover plate, the bonding layer, and the photosensitive chip enclose a cavity that accommodates the photosensitive region. The method further includes forming an encapsulation layer to at least cover the sidewall of the bonding layer and the sidewall of the transparent cover plate. | 2020-04-30 |
20200135783 | IMAGE SENSOR HAVING TWO-COLORED COLOR FILTERS SHARING ONE PHOTODIODE - Disclosed is an image sensor having a plurality of groups of pixels, each group of pixels including: first to third image detection color filter sets and a phase difference detection color filter set, which are arranged in a matrix with rows and columns. The phase difference detection color filter set comprises first to fourth phase difference detection color filter pairs arranged in a matrix with rows and columns. The first to fourth phase difference detection color filter pairs comprise first to fourth left phase difference detection color filters positioned on the left of each of the first to fourth phase difference detection color filter pairs and first to fourth right phase difference detection color filters positioned on the right of each of the first to fourth phase difference detection color filter pairs, respectively. | 2020-04-30 |
20200135784 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate, a barrier layer disposed over the substrate, a grid disposed over the barrier layer, and a first color filter disposed over the barrier layer. The semiconductor structure also includes a second color filter disposed over the substrate and laterally surrounded by and contacting the grid. The semiconductor structure further includes a dielectric layer disposed between the barrier layer and the substrate. The barrier layer includes an upper surface overlapping the grid and the first color filter and a bottom surface substantially level with a bottom surface of the second color filter. The dielectric layer includes a first portion overlapping a bottom surface of the first color filter and a second portion overlapping a bottom surface of the second color filter, wherein non-visible light is allowed to pass from the second color filter to the substrate through the second portion of the dielectric layer. | 2020-04-30 |
20200135785 | IMAGE SENSOR AND METHOD OF MAKING - An image sensor includes a substrate and a first photodiode (PD) having a first size in the substrate. The image sensor further includes a second PD having a second size in the substrate, wherein the first size is different from the second size. The image sensor further includes a first buffer layer over the substrate. The image sensor further includes a shield layer over the first buffer, wherein the first buffer layer and the shield layer define a first recess aligned with the first PD and a second recess aligned with the second PD. The image sensor further includes a flicker reduction layer in the first recess, wherein the second recess is free of the flicker reduction layer. | 2020-04-30 |
20200135786 | PHOTOELECTRIC CONVERSION APPARATUS HAVING METAL PORTION, IMAGING SYSTEM, MOVABLE BODY, AND SEMICONDUCTOR CHIP FOR STACKING - A photoelectric conversion apparatus includes a semiconductor substrate, a floating diffusion, an amplifying transistor, first and second contact plugs, a wire, and a metal portion. The semiconductor substrate has a first plane and a second plane to be entered by light, and includes a photoelectric conversion element. The amplifying transistor includes a first gate electrode. The first contact plug is connected to the floating diffusion. The second contact plug is connected to the first gate electrode. The wire is configured to electrically connect the first gate electrode and the floating diffusion to each other. The metal portion, which is arranged between the first plane and a third plane, covers at least a part of the photoelectric conversion element in a planar view, and has an opening over which at least a part of the wire is superimposed in a planar view. | 2020-04-30 |
20200135787 | METHOD FOR FORMING LIGHT-SENSING DEVICE - A method for forming a light-sensing device is provided. The method includes forming a light-sensing region in a semiconductor substrate. The semiconductor substrate has a front surface and a light-receiving surface opposite to the front surface. The method also includes forming a first dielectric layer over the front surface and forming a second dielectric layer over the first dielectric layer. The second dielectric layer has a different refractive index than that of the first dielectric layer, and the first dielectric layer and the second dielectric layer together form a (or a part of a) light-reflective element. The method further includes partially removing the first dielectric layer and the second dielectric layer to form a contact opening. In addition, the method includes forming a conductive contact to partially (or completely) fill the contact opening. | 2020-04-30 |
20200135788 | WAFER-LEVEL OPTICAL STRUCTURE - A wafer-level optical structure includes at least two optical lens sets disposed on an optically transparent wafer, at least one trench disposed between two adjacent optical lens sets to divide the two adjacent optical lens sets, at least one spacer disposed between two adjacent optical lens sets to be correspondingly and partially disposed in the trench, and an adhesive disposed inside the trench. | 2020-04-30 |
20200135789 | IMAGE SENSOR HAVING STRESS RELEASING STRUCTURE AND METHOD OF FORMING SAME - A semiconductor structure includes a sensor wafer comprising a plurality of sensor chips on and within a substrate. Each of the plurality of sensor chips includes a pixel array region, a bonding pad region, and a periphery region. The periphery region is between adjacent to a scribe line, and the scribe line is between adjacent sensor chips of the plurality of sensor chips. Each of the plurality of sensor chips further includes a stress-releasing trench structure embedded in the substrate, wherein the stress-releasing trench structure is in the periphery region, and the stress-releasing trench structure fully surrounds a perimeter of the pixel array region and the bonding pad region of a corresponding sensor chip of the plurality of sensor chips. | 2020-04-30 |
20200135790 | IMAGE SENSOR PACKAGE - An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip. | 2020-04-30 |
20200135791 | IMAGE SENSOR AND IMAGE SENSING APPARTATUS - An image sensing apparatus includes a first substrate structure, a second substrate structure, and a memory chip. The first substrate structure includes a pixel region having a photoelectric conversion element. The second substrate structure includes a first surface connected to the first substrate structure and a second surface opposite the first surface, and also includes a circuit region to drive the pixel region. The memory chip is mounted on the second surface of the second substrate structure. The first substrate structure and the second substrate structure are electrically connected by first connection vias passing through the first substrate structure. The second substrate structure and the memory chip are electrically connected by second connection vias passing through a portion of the second substrate structure. The first connection vias and the second connection vias are at different positions on a plane. | 2020-04-30 |
20200135792 | HIGH PERFORMANCE IMAGE SENSOR - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a pixel region of a substrate. A plurality of conductive interconnect layers are disposed within a dielectric structure arranged along a first side of the substrate. A second side of the substrate includes a plurality of interior surfaces arranged directly over the image sensing element. The plurality of interior surfaces respectively include a substantially flat surface that extends along a plane. | 2020-04-30 |
20200135793 | PHOTOELECTRIC CONVERTING DEVICE AND APPARATUS - A photoelectric converting device including: a semiconductor layer with a front surface and a back surface, the semiconductor layer including a photoelectric conversion portion; a wire structure including an insulating film, the wire structure being disposed on the front surface of the semiconductor layer; a first insulator portion disposed in a trench provided in the semiconductor layer; and a second insulator portion disposed between the first insulator portion and the insulating film, wherein the first insulator portion has a maximum width larger than a maximum width of the second insulator portion. | 2020-04-30 |
20200135794 | VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire disposed within a dielectric structure on a substrate. A bond pad has a lower surface contacting the first interconnect wire. A via layer is vertically between the first interconnect wire and a second interconnect wire within the dielectric structure. The via layer includes a plurality of support vias having a first size and a plurality of additional vias having a second size that is smaller than the first size. The plurality of support vias extend from directly under the lower surface of the bond pad to laterally past outermost edges of the lower surface of the bond pad. | 2020-04-30 |
20200135795 | STACKED-DIE IMAGE SENSORS WITH SHIELDING - A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels. | 2020-04-30 |
20200135796 | DIGITAL X-RAY DETECTOR AND THIN-FILM TRANSISTOR ARRAY SUBSTRATE FOR THE SAME - The present disclosure relates to a digital X-ray detector and a thin-film transistor array substrate for the same. Disclosed is a thin-film transistor array substrate for a digital X-ray detector in which deterioration of electrical characteristics of a thin-film transistors made of an oxide semiconductor may be reduced or minimized and aging of a PIN diode caused by external moisture may be reduced or minimized. Further, disclosed is a digital X-ray detector including the array substrate. To this end, the array substrate includes a second protective layer having a variety of patterns so as to cover at least a portion of the PIN diode but not to cover the thin-film transistor. The second protective layer includes SiN | 2020-04-30 |
20200135797 | ACTIVE MATRIX SUBSTRATE, X-RAY IMAGING PANEL WITH THE SAME, AND METHOD OF MANUFACTURING THE SAME - An active matrix substrate includes a TFT. The TFT includes a gate electrode, a semiconductor layer overlapping the gate electrode with a gate insulating film interposed therebetween, and a source electrode and a drain electrode disposed on the semiconductor layer. The source electrode, the drain electrode, and the semiconductor layer are covered with a first insulating film. The gate insulating film includes a first stepped portion in a portion covering a peripheral portion of the gate electrode. The first insulating film includes a first opening at a position overlapping a portion of the first stepped portion that is not covered with the source electrode and the drain electrode in a plan view. | 2020-04-30 |
20200135798 | METHOD OF FORMING SELF ALIGNED GRIDS IN BSI IMAGE SENSOR - A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid. | 2020-04-30 |
20200135799 | DISPLAY DEVICE - A display device includes a substrate, a first light-emitting unit, a second light-emitting unit, a first buffer layer, a second buffer layer, a first light conversion unit, and a second light conversion unit. The first light-emitting unit is disposed on the substrate. The second light-emitting unit is disposed on the substrate and adjacent to the first light-emitting unit. The first buffer layer is disposed on the first light-emitting unit. The second buffer layer is disposed on the second light-emitting unit. The first light conversion unit is disposed on the first buffer layer. The second light conversion unit is disposed on the second buffer layer. At least one of the first buffer layer and the second buffer layer has a curved bottom surface. | 2020-04-30 |
20200135800 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a display device includes providing a display substrate with a plurality of pixels, mounting an encapsulation substrate on the display substrate, bonding the display substrate and the encapsulation substrate to form a display panel, and forming a module hole penetrating a hole region of the display panel in the display panel. The hole region encloses the module hole, and the display substrate and the encapsulation substrate may be bonded by irradiating the hole region with an ultra-high-frequency pulsed laser. The display substrate and the encapsulation substrate are bonded in the hole region as the ultra-high-frequency pulsed laser is irradiated onto the hole region. | 2020-04-30 |
20200135801 | TOP EMISSION MICROLED DISPLAY AND BOTTOM EMISSION MICROLED DISPLAY AND A METHOD OF FORMING THE SAME - A microLED display includes a first main substrate, microLEDs disposed above the first main substrate, a first light blocking layer disposed above the first main substrate to define emission areas, a light guiding layer disposed in the emission areas, and a plurality of connecting structures disposed in the emission areas respectively and electrically connected with the microLEDs. | 2020-04-30 |
20200135802 | LIDAR SYSTEM WITH FIBER TIP REIMAGING - A light detection and ranging (LIDAR) system is provided that includes an optical a scanning mirror to steer a laser beam emitted from the tip of an optical fiber to scan a scene, and collect light incident upon any objects in the scene that is returned to the fiber tip. The LIDAR system further includes a re-imaging lens located between the optical fiber and scanning mirror, and an optic located between the scanning mirror and the scene. The re-imaging lens focuses the laser beam emitted from the optical fiber on or close to the first scanning mirror's center of rotation and thereby re-image the fiber tip at or close to the center of rotation, from which the laser beam is reflected as a divergent laser beam. And the optic is configured to collimate or focus the divergent laser beam from the first scanning mirror that is launched toward the scene. | 2020-04-30 |
20200135803 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATION - A semiconductor device is provided. The semiconductor device has a semiconductor layer comprising a source/drain region, a first magnetic layer over the semiconductor layer, and a first dielectric layer over the source/drain region and adjacent the first magnetic layer. The semiconductor device has a metal structure extending through the first dielectric layer, a second magnetic layer over the metal structure, and a second dielectric layer over the first magnetic layer and adjacent the first dielectric layer. | 2020-04-30 |
20200135804 | MAGNETIC TUNNEL JUNCTION STRUCTURES AND RELATED METHODS - The disclosure is directed to spin-orbit torque MRAM structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers. | 2020-04-30 |
20200135805 | NOVEL HARD MASK FOR MTJ PATTERNING - In some embodiments, the present disclosure relates to a method to form an integrated chip. The method may be performed by forming magnetic tunnel junction (MTJ) layers over a bottom electrode layer, and forming a sacrificial dielectric layer over the MTJ layers. The sacrificial dielectric layer is patterned to define a cavity, and a top electrode material is formed within the cavity. The sacrificial dielectric layer is removed and the MTJ layers are patterned according to the top electrode material to define an MTJ stack, after removing the sacrificial dielectric layer. | 2020-04-30 |
20200135806 | Semiconductor Device With Magnetic Tunnel Junctions - A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer. | 2020-04-30 |
20200135807 | ATOMIC LAYER DEPOSITION AND PHYSICAL VAPOR DEPOSITION BILAYER FOR ADDITIVE PATTERNING - A method for manufacturing a semiconductor device includes forming a memory element in a dielectric layer. A first conductive layer is deposited on the dielectric layer and the memory element by atomic layer deposition, and a second conductive layer is deposited on the first conductive layer by physical vapor deposition. In the method, the first and second conductive layers are patterned into an electrode on the memory element. | 2020-04-30 |
20200135808 | DISPLAY SUBSTRATE, LIGHT FIELD DISPLAY APPARATUS AND METHOD FOR DRIVING THE SAME - The embodiments of the present application provide a display substrate, a light field display apparatus, and a method for driving the same. The display substrate includes: a base substrate; a light emitting block on the base substrate, wherein the light emitting block comprises a plurality of first light emitting units, and each of the first light emitting units comprises a plurality of first light emitting points which are located at a plurality of predetermined positions in the first light emitting unit respectively; and first driving leads each electrically connected to first light emitting points located at the same predetermined positions in the respective first light emitting units and configured to receive a first driving signal from a driving circuit. | 2020-04-30 |
20200135809 | METAL-INSULATOR-SEMICONDUCTOR-INSULATOR-METAL (MISIM) DEVICE, METHOD OF OPERATION, AND MEMORY DEVICE INCLUDING THE SAME - A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other. | 2020-04-30 |
20200135810 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display that includes a base layer having an emission area and a non-emission area adjacent to the emission area. A circuit element layer is disposed on the base layer. A display element layer is disposed on the circuit element layer. The display element layer includes an organic light emitting diode. An encapsulation layer is disposed on the display element layer and is configured to encapsulate the organic light emitting diode. A color filter layer is disposed in the encapsulation layer. The color filter layer includes a color shielding layer having a plurality of layers disposed in the non-emission area and a color filter disposed in the emission area. | 2020-04-30 |
20200135811 | OPTICAL FILTER SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME - A display device includes an optical filter substrate including: a substrate; a first color filter on the substrate; a second color filter on the substrate, the second color filter spaced apart from the first color filter; a first color conversion element on the first color filter, the first color conversion element converting incident light into light of a first color; a second color conversion element on the second color filter, the second color conversion element converting the incident light into light of a second color; and a black matrix located between the first color conversion element and the second color conversion element, and between the first color filter and the second color filter. | 2020-04-30 |
20200135812 | DISPLAY DEVICE - A display device includes a sealing film covering a display region where an image is displayed, a touch sensor layer configured to detect a touched position of the display region, the touch sensor layer including a first electrode layer that is arranged on the sealing film, a first insulating layer that is formed on the first electrode layer using a material including nitrogen, and a second electrode layer that is arranged over the first insulating layer, an overcoat covering the touch sensor layer, and a polarizing plate being arranged on the overcoat. The touch sensor layer further includes a second insulating layer configured to inhibit a reaction between nitrogen included in the first insulating layer and water included in the overcoat, the second insulating layer being formed between the first insulating layer and the overcoat using a material not including nitrogen. | 2020-04-30 |
20200135813 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING TOUCHSCREEN AND METHOD OF MANUFACTURING THE SAME - Disclosed is an organic light-emitting display device having a touchscreen in which the configuration of a pad unit and a circuit board connected to the pad unit is simplified, resulting in bonding stability and an improved form factor of the device, and a method of manufacturing the same. In the organic light-emitting display device having the touchscreen in which a touch electrode is directly provided on an encapsulation layer, a touch pad and a display pad are disposed parallel to each other on the same side so as to be connected to a flexible printed circuit board with a difference in height therebetween. Thereby, increased bonding reliability and an increased effective display area are achieved. | 2020-04-30 |
20200135814 | DISPLAY DEVICE - A display device includes a display panel including a first region and a second region, and a sensing module on a rear side of the display panel. The first region includes a first pixel area to display an image. The second region includes a second pixel area to display the image and a transmission area to transmit light output by the sensing module. The second region overlaps the sensing module. The second pixel area overlaps a first layer that blocks light output by the sensing module. The transmission area does not overlap the first layer. | 2020-04-30 |
20200135815 | ARRAY TEST APPARATUS AND METHOD - An array test apparatus includes a signal transmission unit which transmits a data signal to each of a plurality of data lines of a low-temperature polysilicon (“LTPS”) substrate, a signal measurement unit which measures the data signal of each of the data lines of the LTPS substrate, a timer which generates a horizontal period for setting a section in which the data signal is transmitted from the signal transmission unit to each of the data lines and a section in which the data signal output from each of the data lines is measured by the signal measurement unit, and a determination unit which determines whether each of the data lines of the LTPS substrate is normal based on the data signal measured by the signal measurement unit. | 2020-04-30 |
20200135816 | Display Substrate, Fabrication Method Thereof, and Display Panel - A display substrate and a fabrication method thereof, and a display panel are disclosed. The display substrate includes: a base substrate; a pixel defining layer, on the base substrate and configured to define a plurality of sub-pixel regions, each sub-pixel region including a first electrode layer and a second electrode layer; an auxiliary electrode layer, on at least a portion of the pixel defining layer, the auxiliary electrode layer having a hydrophobic surface, and the hydrophobic surface being configured to be in contact with and electrically connected with the second electrode layer. | 2020-04-30 |
20200135817 | DISPLAY PANEL, DISPLAY DEVICE AND DRIVING METHOD FOR DISPLAY DEVICE - The present disclosure provides a display panel, a display device, and a method for driving a display device. The display panel has a display region, a partial region of which is reused as a photographing photosensitive region. The display panel includes: a first substrate; a second substrate disposed opposite to the first substrate; a plurality of pixel units disposed in the display region, and a plurality of photosensitive elements disposed in the photographing photosensitive region. The first substrate is located on a side of the second substrate facing a light-emitting surface, the plurality of pixel units is formed on the second substrate, each of the plurality of pixel units includes a pixel circuit and a light-emitting element, and a planarization layer is arranged between the pixel circuit and the light-emitting element, and the plurality of photosensitive elements is located on a side of the planarization layer facing the first substrate. | 2020-04-30 |
20200135818 | ELECTROLUMINESCENT DISPLAY APPARATUS - An electroluminescent display apparatus includes: a substrate including a first subpixel and a second subpixel; a first electrode in each of the first subpixel and the second subpixel; a partition wall between the first electrode of the first subpixel and the first electrode of the second subpixel; a light emitting layer on the first electrode and the partition wall; a second electrode on the light emitting layer; a first trench between the first electrode of the first subpixel and the partition wall; and a second trench between the first electrode of the second subpixel and the partition wall. | 2020-04-30 |
20200135819 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes an insulating layer disposed on a substrate, a pixel electrode including a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked on the insulating layer, a pixel defining layer covering the pixel electrode and partially exposing the pixel electrode through an opening, an organic light emitting layer disposed in the opening of the pixel defining layer, and an opposing electrode disposed on the organic light emitting layer and overlapping the pixel electrode. A length of the first conductive layer is less than a length of the second conductive layer. | 2020-04-30 |
20200135820 | DISPLAY DEVICE, AND ELECTRONIC APPARATUS - In a display device, light emitting units each formed by stacking a first electrode, an organic layer, and a second electrode are formed and arranged in a two-dimensional matrix on a substrate, the first electrode is provided for each light emitting unit, partition walls are formed between adjacent ones of the first electrodes, the organic layer and the second electrode are stacked on the entire surface including a part over the first electrodes and a part over the partition walls, a filling layer filling recesses between the partition walls is formed on the second electrode, the partition walls include stacks each including at least two layers including a lower layer portion on the light emitting unit side and an upper layer portion located above the lower layer portion, and at least part of light entering from the light emitting units is totally reflected on surfaces of the upper layer portions of the partition walls. | 2020-04-30 |
20200135821 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE HAVING THE SAME - A semiconductor device includes: a semiconductor chip including a substrate having a first surface and a second surface, which are opposite to each other; a through hole penetrating the substrate; a first conductive pad on the first surface of the substrate; a first bump formed over and electrically connected to the first conductive pad; a second conductive pad on the second surface of the substrate; a second bump formed over and electrically connected to the second conductive pad; and a connection electrode buried in the through hole, the connection electrode electrically connecting the first bump and the second bump. | 2020-04-30 |
20200135822 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus having a display area and a pad area and a method of manufacturing the same, the display apparatus including a base substrate; a thin film transistor on the base substrate in the display area; an insulation layer on the base substrate and the thin film transistor; a conductive pattern layer on the insulation layer, the conductive pattern layer including a pad electrode in the pad area; and a via insulation layer on the insulation layer, exposing an upper surface of the pad electrode, and covering edges of the pad electrode, wherein, in the pad area, the insulation layer includes a groove having a depth, the pad electrode being in the groove. | 2020-04-30 |
20200135823 | ELECTROLUMINESCENT DISPLAY APPARATUS - An electroluminescent display apparatus includes: a substrate, a plurality of subpixels on the substrate, a first electrode respectively in each of the plurality of subpixels, the first electrode including: a first sub-electrode, and a second sub-electrode, a light-emitting layer on the first electrode, and a second electrode on the light-emitting layer, wherein a whole upper surface of each of the first sub-electrode and the second sub-electrode contacts a lower surface of the light-emitting layer. | 2020-04-30 |
20200135824 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a substrate, a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display device on the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region. | 2020-04-30 |
20200135825 | SCAN DRIVER AND DISPLAY DEVICE INCLUDING THE SAME - A scan driver includes a substrate, a first transistor on the substrate, the first transistor including a first active pattern and a first gate electrode, the first active pattern including first and second regions, and a first channel region between the first and second regions, a second transistor on the first transistor, the second transistor including a second active pattern and a second gate electrode, the second active pattern including third and fourth regions, and a second channel region between the third and fourth regions, first and second electrodes on the second transistor, the first electrode and the second electrode electrically connected to the first region and the second region, respectively, and third and fourth electrodes on the second transistor, the third electrode and the fourth electrode electrically connected to the third region and the fourth region, respectively, wherein the first and third electrodes are electrically connected. | 2020-04-30 |
20200135826 | DISPLAY APPARATUS AND ELECTRONIC DEVICE - A display apparatus including pixels is provided. Each pixels comprises a light-emitting element, a first transistor having a drain region connected to an anode of the light-emitting element, and a second transistor having a drain region connected to a gate electrode of the first transistor. The drain region of the first transistor includes a first region and a second region arranged between the first region and a channel region and having a higher resistivity than the first region. The drain region of the second transistor includes a third region and a fourth region arranged between the third region and a channel region and having a higher resistivity than the third region. A length of the second region in a direction in which a current flows is longer than that of the fourth region in a direction in which a current flows. | 2020-04-30 |
20200135827 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - Embodiments may disclose an organic light-emitting display device including a first substrate including a pixel area emitting light in a first direction, and a transmittance area that is adjacent to the pixel area and transmits external light; a second substrate facing the first substrate and encapsulating a pixel on the first substrate; an optical pattern array on the first substrate or the second substrate to correspond to the transmittance area, the optical pattern array being configured to transmit or block external light depending on the transmittance area according to a coded pattern; and a sensor array corresponding to the optical pattern array, the sensor array being arranged in a second direction that is opposite to the first direction in which the light is emitted, the second array receiving the external light passing through the optical pattern array. | 2020-04-30 |
20200135828 | FLEXIBLE SEMICONDUCTOR DEVICE AND FLEXIBLE DISPLAY DEVICE - A display device includes a substrate having flexibility, a transistor having a gate insulating film and further having a semiconductor layer and a gate electrode that sandwich the gate insulating film, the transistor formed in an area where the substrate is bent, and a gate wiring line so formed on the substrate as to be connected to the gate electrode, and the gate electrode has an area that is present in an area where the gate electrode overlaps with the semiconductor layer and is thinner than at least part of the gate wiring line. | 2020-04-30 |
20200135829 | ELECTROLUMINESCENT DISPLAY DEVICE - Discussed is an electroluminescent display device, wherein a first electrode of a first sub pixel includes a first lower electrode and a first upper electrode, a first electrode of a second sub pixel includes a second lower electrode and a second upper electrode, a first electrode of a third sub pixel includes a third lower electrode and a third upper electrode, a distance between the first lower electrode and the first upper electrode, a distance between the second lower electrode and the second upper electrode, and a distance between the third lower electrode and the third upper electrode are different from one another, the third upper electrode includes a third lower layer and a third upper layer, and the third lower layer is formed in the same pattern as that of the third lower electrode in an upper surface of the third lower electrode. | 2020-04-30 |
20200135830 | DISPLAY APPARATUS - A display apparatus includes a substrate, a first pixel positioned on the substrate, a first data line which applies a first data signal to the first pixel, a second pixel positioned on the substrate and being adjacent to the first pixel, a second data line which applies a second data signal to the second pixel, and a shielding layer between the first data line and the second data line. The first data line and the second data line are parallel to each other and are disposed at different heights, and the shielding layer includes a metallic layer. | 2020-04-30 |
20200135831 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a substrate, an overlap layer on the substrate, a semiconductor layer on the overlap layer, a first gate conductor on the semiconductor layer, a second gate conductor on the first gate conductor, a data conductor on the second gate conductor, a driving transistor on the overlap layer, and an organic light emitting diode connected with the driving transistor. The driving transistor includes, in the semiconductor layer, a first electrode, a second electrode, with a channel therebetween. A gate electrode of the first gate conductor overlaps the channel. The overlap layer overlaps the channel of the driving transistor and at least a portion of the first electrode. A storage line of the second gate conductor receives a driving voltage through a driving voltage line in the data conductor. The overlap layer receives a constant voltage. | 2020-04-30 |
20200135832 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel comprises a display area including a first display area and a second display area arranged in a row direction, and the first display area includes at least one notch; and a non-display area surrounding the display area. The non-display area includes a first non-display area and a second non-display area, and along the row direction, the first non-display area and the second non-display area are respectively disposed at two opposite sides of the display area. The first non-display area include a first driving circuit, which includes a plurality of cascaded first shift registers, and the second non-display area includes a second driving circuit, which includes a plurality of cascaded second shift registers. The display panel includes a first driving unit and a second driving unit. | 2020-04-30 |
20200135833 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel comprises a display area including data lines and an irregular-shaped edge extending in a column direction, and scanning lines and light-emitting controlling lines extending in a row direction; a non-display area including a first and a second non-display areas disposed at opposite sides of the display area along the row direction; and at least one notch formed by recessing the irregular-shaped edge towards an inside of the display area. The first non-display area includes first shift registers, the second non-display area includes second shift registers and light-emitting controllers, a first and second shift registers are connected to two ends of a scanning line, and a light-emitting controller is connected to a light-emitting controlling line. The first non-display area includes a first sub-non-display area disposed adjacent to the at least one notch and including electrostatic discharge circuits. | 2020-04-30 |
20200135834 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, DISPLAY PANEL, AND DISPLAY APPARATUS - A display substrate, a method of manufacturing the same, a display panel, and a display apparatus are provided. In one embodiment, a display substrate includes: a base substrate; a plurality of lead wires and a barrier on the base substrate, the plurality of lead wires being separated from one another to form a concave between every two adjacent ones of the plurality of lead wires; and a cover layer covering over the plurality of lead wires and the barrier; wherein the plurality of lead wires are insulated from the barrier, the plurality of lead wires are insulated from the cover layer, the plurality of lead wires are between the base substrate and the cover layer, the barrier is between the plurality of lead wires and the cover layer, and the barrier is formed at least at the concave between at least two of the plurality of lead wires to block the concave. | 2020-04-30 |
20200135835 | DISPLAY DEVICE - A display device includes a substrate having a display area and a non-display area. A light emitting element is disposed in the display area. An encapsulation layer is configured to cover the display area and encapsulate the light emitting element. A power line is disposed in the non-display area. A first edge of the encapsulation layer in the non-display area is disposed to coincide with an edge of the power line or is disposed closer to the display area than the edge of the power line. | 2020-04-30 |
20200135836 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - The present disclosure discloses a display panel, a manufacturing method thereof and a display device. By arranging positions of first transmission pads and second transmission pads, and setting areas of first film layers in the first transmission pads to be less than those of second film layers, when the first transmission pads and the second transmission pads are disposed oppositely, fully-opened openings are formed between the two pads, so that it is convenient to fill spaces between the first transmission pads and the second transmission pads with conductive components to allow the first transmission pads be electrically connected with the second transmission pads through the conductive components, guaranteeing an effective electrical connection between the first transmission pads and the second transmission pads and then ensuring signal transmission via first wires and second wires through the first transmission pads and the second transmission pads. | 2020-04-30 |
20200135837 | ORGANIC LIGHT-EMITTING DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND MASK - Provided are an organic light-emitting display panel and manufacturing method thereof, a display device and a mask. The organic light-emitting display panel includes: multiple organic light-emitting units, a photosensitive module setting area, a display area surrounding the photosensitive module, and a bezel area surrounding the display area. The display area includes a first display area and a second display area. Organic light-emitting units in the first display area share a first cathode. Organic light-emitting units in the same group in the second display area share a second cathode. Two adjacent second cathodes are separated by a first gap. The bezel area extends to the photosensitive module setting area by the first gap. | 2020-04-30 |
20200135838 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device comprises a substrate comprising a plurality of sub-pixels, each of the sub-pixels having an emission area and a non-emission area provided to surround the emission area; an auxiliary line disposed in the non-emission area; a first insulating film having a first hole configured to expose a portion of the auxiliary line; an auxiliary line connection pattern disposed on the first insulating film having a protruding portion protruding towards a center of the first hole and overlapping the auxiliary line; at least one bump disposed on the auxiliary line within the first hole and adjacent to the protruding portion of the auxiliary line connection pattern; and a bank having a second hole larger than the first hole to expose the protruding portion of the auxiliary line connection, thereby lowering resistance of a cathode covering a plurality of sub-pixels and preventing lateral current leakage between the sub-pixels through a change of the connection structure between the auxiliary line and the cathode. | 2020-04-30 |
20200135839 | SUBSTRATE COMPRISING RECESSED INTERCONNECTS AND A SURFACE MOUNTED PASSIVE COMPONENT - A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect. | 2020-04-30 |