18th week of 2020 patent applcation highlights part 68 |
Patent application number | Title | Published |
20200135440 | MASS SPECTROMETRY DATA ACQUISITION METHOD - A data acquisition method for a mass spectrometer includes providing at least one ion source for generating ions; not fragmenting or less fragmenting the ions when a collision cell is in a first working mode; recording a mass spectrum of the ions generated in the first working mode; selecting more than one ion from the ions, the more than one ion being distributed in a plurality of discontinuous mass-to-charge ratio channels; partially fragmenting the selected ions when the collision cell is in a second working mode; recording a mass spectrum of the ions generated in the second working mode; and, repetitively executing the above steps for several times. The ions distributed in the discontinuous mass-to-charge ratio channels is always selected during the subsequent repeated execution, until the ion intensity of the selected ions is less than a set value. | 2020-04-30 |
20200135441 | AN AMPLIFIER - The use of a capacitor ( | 2020-04-30 |
20200135442 | ION GUIDE - An ion guide is disclosed that comprises a plurality of electrodes arranged to form a multipole ion guide and one or more rigid support members. The plurality of electrodes comprises one or more groups of electrodes, and each group of electrodes comprises plural electrodes that are axially spaced apart from one another. The electrodes of one or more groups of electrodes are attached to one of the one or more rigid support members. One or more of the electrodes comprises a curved metal sheet, plate or strip. | 2020-04-30 |
20200135443 | AUTOMATED DETECTION OF NANOPARTICLES USING SINGLE-PARTICLE INDUCTIVELY COUPLED PLASMA MASS SPECTROMETRY (SP-ICP-MS) - Particles such as nanoparticles in a sample are analyzed by single-particle inductively coupled plasma-mass spectrometry (spICP-MS). The sample is processed in an ICP-MS system to acquire time scan data corresponding to ion signal intensity versus time. A signal distribution, corresponding to ion signal intensity and the frequency at which the ion signal intensity was measured, is determined from the time scan data. A particle detection threshold is determined as an intersection point of an ionic signal portion and a particle signal portion of the signal distribution. The particle signal portion corresponds to measurements of particles in the sample, and the ionic signal portion corresponds to measurements of components in the sample other than particles. The particle detection threshold separates the particle signal portion from the ionic signal portion, and may be utilized to determine data regarding the particles. | 2020-04-30 |
20200135444 | APPARATUS AND METHOD FOR RAPID CHEMICAL ANALYSIS USING DIFFERENTIAL DESORPTION - The present invention is directed to a method and device to generate a chemical signature for a mixture of analytes. The present invention involves using a SPME surface to one or both absorb and adsorb the mixture of analytes. In an embodiment of the invention, the surface is then exposed to different temperature ionizing species chosen with appropriate spatial resolution to desorb a chemical signature for the mixture of analytes. | 2020-04-30 |
20200135445 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device having favorable electrical characteristics is provided. | 2020-04-30 |
20200135446 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A field is applied to the intermediate layer, wherein the field source does not contact the semiconductor device. The polarity of the intermediate layer is changed by the field to form a desired dipole orientation in the intermediate layer. | 2020-04-30 |
20200135447 | GROUP III NITRIDE SEMICONDUCTOR AND METHOD FOR PRODUCING SAME - A Group III nitride semiconductor for growing a high-quality crystal having a low defect density and a method for producing the Group III nitride semiconductor. The Group III nitride semiconductor includes an RAMO | 2020-04-30 |
20200135448 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD - A semiconductor manufacturing apparatus includes a chuck stage, a stage rotation mechanism, a chemical liquid nozzle, a chemical liquid nozzle scan mechanism, a lower surface gas nozzle, a gas temperature controller configured to control a temperature of gas to be supplied to the lower surface gas nozzle, a gas bypass pipe configured to allow the gas to be supplied to the lower surface gas nozzle without causing the gas to pass through the gas temperature controller, and first and second on-off valves configured to open and shut to allow either of the gas whose temperature has been controlled by the gas temperature controller and the gas passing through the gas bypass pipe to be supplied to the lower surface gas nozzle. Actuation of the first and second on-off valves allows a temperature of the gas passing through the lower surface gas nozzle to be changed. | 2020-04-30 |
20200135449 | SOURCE AND DRAIN PROCESS FOR FINFET - A method includes forming a dielectric layer over a fin structure, forming a dummy gate crossing over the dielectric layer, forming a spacer on a sidewall of the dummy gate, etching the dielectric layer and the fin structure, such that the dielectric layer and the fin structure are recessed from an outer sidewall of the spacer, and etching the fin structure, such that the fin structure is recessed from an end surface of the dielectric layer. | 2020-04-30 |
20200135450 | SEMICONDUCTOR MANUFACTURING METHOD AND APPARATUS THEREOF - The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a photo-sensitive layer on a first surface of a semiconductor substrate. The photo-sensitive layer has a top surface. The method also includes obtaining a first profile of the first surface of the semiconductor substrate, and obtaining a second profile of the top surface of the photo-sensitive layer. The method also includes calculating a vertical displacement profile of the semiconductor substrate according to the first profile and the second profile. An apparatus for manufacturing a semiconductor structure is also disclosed. | 2020-04-30 |
20200135451 | PROTECTIVE COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN - A method includes forming protective layer over substrate edge and photoresist over substrate. Protective layer removed and photoresist exposed to radiation. Protective layer made of composition including acid generator and polymer having pendant acid-labile groups. Pendant acid-labile groups include polar functional groups; acid-labile groups including polar switch functional groups; acid-labile groups, wherein greater than 5% of pendant acid-labile groups have structure | 2020-04-30 |
20200135452 | METHOD FOR PERFORMING A PHOTOLITHOGRAPHY PROCESS - A method for performing a photolithography process is provided. The method includes forming a layer over a substrate, and exposing a portion of the layer to form an exposed region. The method also includes performing a baking process on the layer, so that voids are formed in the exposed region of the layer. The method further includes filling the void with a post treatment coating material, and the post treatment coating material is over the exposed region of the layer. | 2020-04-30 |
20200135453 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a substrate and a redistribution structure. The substrate has at least one contact. The redistribution structure is disposed on the substrate and electrically connected to the at least one contact, wherein the redistribution structure includes a plurality of redistribution layers. Each of the redistribution layers include a seed layer, a conductive material layer and a dielectric material layer. The conductive material layer is disposed on the seed layer. The dielectric material layer is surrounding the conductive material layer and the seed layer. At least one of the redistribution layers include an anti-reflective layer disposed in between the seed layer and the conductive material layer. | 2020-04-30 |
20200135454 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND A COATING MATERIAL - In a method of manufacturing a semiconductor device, an underlying structure is formed. A surface grafting layer is formed on the underlying structure. A photo resist layer is formed on the surface grafting layer. The surface grafting layer includes a coating material including a backbone polymer, a surface grafting unit coupled to the backbone polymer and an adhesion unit coupled to the backbone polymer. | 2020-04-30 |
20200135455 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes filling a concave portion formed on a surface of a substrate with a first film and a second film by performing: (a) forming the first film having a hollow portion using a first precursor so as to fill the concave portion formed on the surface of the substrate; (b) etching a portion of the first film which makes contact with the hollow portion, using an etching agent; and (c) forming the second film on the first film of which the portion is etched, using a second precursor, wherein (b) includes performing, a predetermined number of times: (b-1) modifying a portion of the first film using a modifying agent; and (b-2) selectively etching the modified portion of the first film using the etching agent. | 2020-04-30 |
20200135456 | LINERLESS CONTINUOUS AMORPHOUS METAL FILMS - Embodiments described herein generally relate to methods of depositing thin films and, more particularly, to depositing metal thin films. The methods herein provide a nucleation free conversion (NFC) approach which involves forming an amorphous silicon layer over the dielectric layer, and performing an NFC process which acts to convert the amorphous silicon layer into a thin metal film. In some embodiments, the NFC process is performed multiple times until the resulting thin metal film is continuous. A bulk metal is formed over the thin metal film. | 2020-04-30 |
20200135457 | STACK VIABAR STRUCTURES - Various methods and structures for fabricating a semiconductor structure. The semiconductor structure includes in a top layer of a semiconductor stack a semiconductor contact located according to a first horizontal pitch. A first metallization layer is disposed directly on the top layer and includes a metallization contact located according to a second horizontal pitch, the second horizontal pitch being different from the first horizontal pitch such that the location of the metallization contact is vertically mismatched from the location of the semiconductor contact. A second metallization layer is disposed directly on the first metallization layer. The second metallization layer includes a super viabar structure that forms an electrical interconnect, in the second metallization layer, between the semiconductor contact in the top layer of the semiconductor stack and the metallization contact in the first metallization layer. | 2020-04-30 |
20200135458 | DELAYED PULSING FOR PLASMA PROCESSING OF WAFERS - A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer. | 2020-04-30 |
20200135459 | METHODS FOR ETCHING A STRUCTURE FOR SEMICONDUCTOR APPLICATIONS - Embodiments of the present disclosure provide methods and apparatus for forming and patterning features in a film stack disposed on a substrate. In one embodiment, a method for patterning a conductive layer on a substrate includes supplying a gas mixture comprising a chlorine containing gas at a first flow rate to etch a first conductive layer disposed on the substrate, lowing the chlorine containing gas in the first gas mixture to a second flow rate lower than the first flow rate to continue etching the first conductive layer, and increasing the chlorine containing gas in the first gas mixture to a third flow rate greater than the second flow rate to remove the first conductive layer from the substrate. | 2020-04-30 |
20200135460 | SINGLE CRYSTAL SILICON PRODUCTION METHOD, EPITAXIAL SILICON WAFER PRODUCTION METHOD, SINGLE CRYSTAL SILICON, AND EPITAXIAL SILICON WAFER - A production method of a monocrystalline silicon includes adding red phosphorus in a silicon melt so that an electrical resistivity of the monocrystalline silicon falls in a range of 0.5 mΩ·cm or more and less than 0.7 mΩ·cm; and pulling up the monocrystalline silicon so that a time for a temperature of at least a part of a straight body of the monocrystalline silicon to be within a range of 570 degrees C. 70 degrees C. is in a range from 10 minutes to 50 minutes. | 2020-04-30 |
20200135461 | Single Crystal Substrate And Silicon Carbide Substrate - A single crystal substrate is provided and is characterized in that the single crystal substrate has a foundation substrate provided with a plurality of first grooves, which include a first crystal face and a second crystal face opposed to the first crystal face in an inner face thereof, and the extending direction of which is a <110> direction, and a plurality of second grooves, the extending direction of which intersects with the first grooves, and in which the first grooves are formed in a displaced manner in a depth direction, and a transverse cross-sectional shape of the second groove is a shape in which straight lines are open at an opening angle less than 180°. Further, it is preferred that an angle formed by the first crystal face and the second crystal face is more than 70.6°. | 2020-04-30 |
20200135462 | SEMICONDUCTOR DEVICE AND METHOD - A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material. | 2020-04-30 |
20200135463 | METHODS OF FORMING SEMICONDUCTOR DEVICES - Methods of forming semiconductor devices are provided. One of the methods includes following steps. A plurality of hard mask patterns is formed around a region of a substrate, wherein an imaginary connecting line is formed between corners of two of the plurality of hard mask patterns at the same side of the region, and the imaginary connecting line is substantially parallel to or perpendicular to a horizontal direction. A semiconductor layer is formed on the substrate by a selective epitaxial growth process. | 2020-04-30 |
20200135464 | METHODS AND APPARATUS FOR PATTERNING SUBSTRATES USING ASYMMETRIC PHYSICAL VAPOR DEPOSITION - Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method for processing a substrate includes: directing a stream of material from a PVD source toward a surface of a substrate at a non-perpendicular angle to the plane of the surface to selectively deposit the material on a top portion of one or more features on the substrate and form an overhang extending beyond a first sidewall of the one or more features; and etching a first layer of the substrate beneath the one or more features selective to the deposited material. | 2020-04-30 |
20200135465 | SELECTIVE DEPOSITION BY LASER HEATING - A method for forming a semiconductor structure is provided. The method includes forming a first material and a second material on a semiconductor substrate. The first material is different from the second material. The method also includes heating the first material to a first temperature and the second material to a second temperature with a laser beam. The first temperature is different from the second temperature. The method also includes depositing a third material on the first material. | 2020-04-30 |
20200135466 | HIGH DENSITY CARBON FILMS FOR PATTERNING APPLICATIONS - Embodiments of the present disclosure generally relate to deposition of high transparency, high-density carbon films for patterning applications. In one embodiment, a method of forming a carbon film on a substrate is provided. The method includes flowing a hydrocarbon-containing gas mixture into a process chamber having a substrate positioned on an electrostatic chuck, wherein the substrate is maintained at a temperature of about −10° C. to about 20° C. and a chamber pressure of about 0.5 mTorr to about 10 Torr, and generating a plasma by applying a first RF bias to the electrostatic chuck to deposit a diamond-like carbon film containing about 60% or greater hybridized sp | 2020-04-30 |
20200135467 | Semiconductor Device and Method - In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin. | 2020-04-30 |
20200135468 | Methods and Systems for Dopant Activation Using Microwave Radiation - A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction. | 2020-04-30 |
20200135469 | Reduce Well Dopant Loss in FinFETs Through Co-Implantation - A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the dee p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET. | 2020-04-30 |
20200135470 | ION IMPLANTATION APPARATUS AND METHOD - The present disclosure describes a system and a method for a ion implantation (IMP) process. The system includes an ion implanter configured to scan an ion beam over a target for a range of angles, a tilting mechanism configured to support and tilt the target, an ion-collecting device configured to collect a distribution and a number of ejected ions from the ion beam scan over the target, and a control unit configured to adjust a tilt angle based on a correction angle determined based on the distribution and number of ejected ions. | 2020-04-30 |
20200135471 | FORMATION AND IN-SITU ETCHING PROCESSES FOR METAL LAYERS - The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber. | 2020-04-30 |
20200135472 | Cut Metal Gate Processes - A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack. | 2020-04-30 |
20200135473 | INSULATING GATE SEPARATION STRUCTURE FOR TRANSISTOR DEVICES - One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface. | 2020-04-30 |
20200135474 | Semiconductor Device and Method of Forming - A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure. | 2020-04-30 |
20200135475 | Gate Structures Having Interfacial Layers - Examples of a method of forming an integrated circuit device with an interfacial layer disposed between a channel region and a gate dielectric are provided herein. In some examples, the method includes receiving a workpiece having a substrate and a fin having a channel region disposed on the substrate. An interfacial layer is formed on the channel region of the fin, and a gate dielectric layer is formed on the interfacial layer. A first capping layer is formed on the gate dielectric layer, and a second capping layer is formed on the first capping layer. An annealing process is performed on the workpiece configured to cause a first material to diffuse from the first capping layer into the gate dielectric layer. The forming of the first and second capping layers and the annealing process may be performed in the same chamber of a fabrication tool. | 2020-04-30 |
20200135476 | FinFET Device and Method of Forming - A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer. | 2020-04-30 |
20200135477 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor fin and a gate structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction substantially perpendicular to the first direction. The gate structure includes a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer. | 2020-04-30 |
20200135478 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURE - A semiconductor arrangement includes a semiconductor layer having a source/drain region and a first epitaxial layer over the semiconductor layer. The semiconductor arrangement includes a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer define a contact structure for the source/drain region. | 2020-04-30 |
20200135479 | SEMICONDUCTOR STRUCTURE ETCHING SOLUTION AND METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING THE SAME ETCHING SOLUTION - The present disclosure provides a semiconductor structure etching solution, including an etchant, an ionic strength enhancer having an ionic strength greater than 10 | 2020-04-30 |
20200135480 | WORKPIECE PROCESSING METHOD - An embodiment of the present disclosure provides a method of processing a workpiece in which a plurality of holes are formed on a surface of the workpiece. The method includes a first sequence including a first process of forming a film with respect to an inner surface of each of the holes and a second process of isotropically etching the film. The first process includes a film forming process using a plasma CVD method, and the film contains silicon. | 2020-04-30 |
20200135481 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A fin strip is formed over a substrate using a hardmask. The fin strip includes a first portion and a second portion laterally adjoining the first portion. A BARC layer is formed to cover the fin strip over the substrate. A first etching operation is performed to remove a first portion of the BARC layer, so as to expose a portion of the hardmask where the first portion of the fin strip underlies. A coating layer is deposited over the portion of the hardmask and the BARC layer. A second etching operation is performed to remove a portion of the coating layer, the portion of the hardmask and a second portion of the BARC layer. A third etching operation is performed to remove the first portion of the fin strip and a remaining BARC layer, such that the second portion of the fin strip forms a plurality of semiconductor fins. | 2020-04-30 |
20200135482 | CONTROLLED HARDMASK SHAPING TO CREATE TAPERED SLANTED FINS - Embodiments described herein relate to methods forming optical device structures. One embodiment of the method includes exposing a substrate to ions at an ion angle relative to a surface normal of a surface of the substrate to form an initial depth of a plurality of depths. A patterned mask is disposed over the substrate and includes two or more projections defining exposed portions of the substrate or a device layer disposed on the substrate. Each projection has a trailing edge at a bottom surface contacting the device layer, a leading edge at a top surface of each projection, and a height from the top surface to the device layer. Exposing the substrate to ions at the ion angle is repeated to form at least one subsequent depth of the plurality of depths. | 2020-04-30 |
20200135483 | ETCH SELECTIVITY IMPROVED BY LASER BEAM - A method for forming a semiconductor structure is provided. The method includes forming a first layer over a semiconductor substrate. The first layer is made of a first material. The method also includes forming a second layer over the first layer. The second layer is made of a second material that is different from the first material. The second layer has a first opening exposing a portion of a top surface of the first layer. The method also includes heating the first layer and the second layer with a laser beam, depositing a third layer over the second layer and covering a sidewall of the first opening, and etching the first layer through the first opening to form a second opening in the first layer. | 2020-04-30 |
20200135484 | FIN CUT PROFILE USING FIN BASE LINER - Methods for forming semiconductor fins include forming a protective layer around a base of a hardmask fin on an underlying semiconductor layer. A portion of the hardmask fin is etched away with an etch that is selective to the protective layer. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask. | 2020-04-30 |
20200135485 | BORON-DOPED AMORPHOUS CARBON HARD MASK AND RELATED METHODS - Described are boron-doped amorphous carbon hard masks, methods of preparing boron-doped amorphous carbon hard masks, methods of using the boron-doped amorphous carbon hard masks, and devices that include the boron-doped amorphous carbon hard masks. | 2020-04-30 |
20200135486 | SLURRY AND MANUFACTURING SEMICONDUCTOR USING THE SLURRY - The present disclosure provides a method for planarizing a metal-dielectric surface. The method includes: providing a slurry to a first metal-dielectric surface, wherein the first metal-dielectric surface comprises a silicon oxide portion and a metal portion, and wherein the slurry comprises a ceria compound; and performing a chemical mechanical polish (CMP) operation using the slurry to simultaneously remove the silicon oxide portion and the metal portion. The present disclosure also provides a method for planarizing a metal-dielectric surface and a method for manufacturing a semiconductor. | 2020-04-30 |
20200135487 | PATTERN FORMATION METHOD AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask. | 2020-04-30 |
20200135488 | METHOD FOR PREVENTING BOTTOM LAYER WRINKLING IN A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film. | 2020-04-30 |
20200135489 | METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE HAVING NITROGEN DIFFUSED THEREIN - A method for making a semiconductor device may include forming a superlattice layer and an adjacent semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include diffusing nitrogen into the superlattice layer. | 2020-04-30 |
20200135490 | METHOD OF FABRICATING INTEGRATED CIRCUITS - A method of fabricating an integrated circuit is disclosed. The method of removing excess metal of a metal interconnection layer during integrated circuit fabrication process comprises the steps of: plasma etching an excess metal portion of the metal interconnection layer using plasma comprising a noble gas, for an etch duration. The method further comprises stopping the etch process prior to the excess metal portion being completely removed and thus prior to a dielectric surface upon which the metal interconnection is formed, becoming completely exposed. The remaining excess metal portion comprising excess metal residues is subsequently removed using a second etch step. | 2020-04-30 |
20200135491 | SYSTEMS AND METHODS FOR ETCHING METALS AND METAL DERIVATIVES - Exemplary etching methods may include flowing a halogen-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include contacting a substrate housed in the substrate processing region with the halogen-containing precursor. The substrate may define an exposed region of a transition-metal-containing material. The methods may also include removing the transition-metal-containing material. The flowing and the contacting may be plasma-free operations. | 2020-04-30 |
20200135492 | METHODS OF PATTERNING NICKEL SILICIDE LAYERS ON A SEMICONDUCTOR DEVICE - Methods and apparatus for processing a substrate and etching a nickel silicide layer are provided herein. In some embodiments, a method of etching a nickel silicide film in a semiconductor device include: contacting a nickel silicide film disposed on a substrate in a process chamber with an etching gas sufficient to form one or more soluble or volatile products in order to reduce or eliminate re-deposition of products formed from the nickel silicide film upon the nickel silicide film. | 2020-04-30 |
20200135493 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an isolation insulating layer disposed over a substrate, a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer, a gate structure disposed over a part of the fin structure, the gate structure extending in a second direction crossing the first direction, and a source/drain structure formed on the upper portion of the fin structure, which is not covered by the gate structure and exposed from the isolation insulating layer. The source/drain structure includes a SiP layer, and an upper portion of the source/drain structure includes an alloy layer of Si, Ge and Ti. | 2020-04-30 |
20200135494 | SEMICONDUCTOR LAYER, OSCILLATION ELEMENT, AND SEMICONDUCTOR LAYER MANUFACTURING METHOD - A semiconductor layer of the present invention is a semiconductor layer including: a pn junction at which an n-type semiconductor (Al | 2020-04-30 |
20200135495 | Multi Integrated Circuit Chip Carrier Package - A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured. | 2020-04-30 |
20200135496 | METHOD FOR FORMING PATTERN AND MANUFACTURING METHOD OF PACKAGE - A method for forming a pattern includes at least the following steps. A first material and a second material abutting the first material are provided. The first material and the second material have different radiation absorption rates. A blocking layer is formed over the first material and the second material. The blocking layer is globally irradiated with an electromagnetic radiation to allow part of the blocking layer to turn into a crosslinked portion. The remaining blocking layer forms a non-crosslinked portion. The non-crosslinked portion covers the second material. The non-crosslinked portion of the blocking layer is removed to expose the second material. A third material is formed over the exposed second material. The crosslinked portion of the blocking layer is removed. | 2020-04-30 |
20200135497 | CONNECTION STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a connection structure is disclosed. A semiconductor structure having a first pad and a bump respectively on a bottom surface thereof is provided. A carrier having a second pad on a top surface thereof is provided. The second pad corresponds to the bump. An epoxy portion is disposed onto the second pad of the carrier. A diameter of the epoxy portion is less than or equal to a diameter of the bump. After depositing the epoxy portion, the bump is attached to the second pad via the epoxy portion. | 2020-04-30 |
20200135498 | CARRIER SUBSTRATE AND PACKAGING METHOD USING THE SAME - A carrier substrate and a packaging method, the carrier substrate including a first layer; a second layer; and a first glue layer between the first layer and the second layer, wherein the first glue layer is removably attached to the first layer. | 2020-04-30 |
20200135499 | SIDE STORAGE PODS, EQUIPMENT FRONT END MODULES, AND METHODS FOR OPERATING EQUIPMENT FRONT END MODULES - Electronic device processing assemblies including an EFEM with at least one side storage pod attached thereto. The side storage pod has a side storage pod container. A supply conduit extends between an upper plenum of the EFEM to the side storage pod container. A fan causes purge gas to simultaneously flow into the EFEM chamber and into the side storage pod container. The fan also causes recirculation of the purge gas from the EFEM chamber. Methods of operating EFEMs and EFEMs are also disclosed. | 2020-04-30 |
20200135500 | SEMICONDUCTOR WAFER STORAGE DEVICE - The present disclosure describes a device and a method for substrate storage. The device can include a first and a second groups of panels configured to form an enclosed volume, and fin structures disposed at inner surfaces of the second group of panels. Each of the fin structures can be configured to hold a substrate. Each fin structure can include a protrusion extending inwardly into the enclosed volume and a binding device disposed over the protrusion. The binding device can be configured to bind the substrate over the protrusion. | 2020-04-30 |
20200135501 | WAFER DRYING SYSTEM - The present disclosure is directed to a wafer drying method that detects molecular contaminants in a drying gas as a feedback parameter for a multiple wafer drying process. For example, the method includes dispensing, in a wafer drying module, a drying gas over a batch of wafers. Further, the method includes collecting the drying gas from an exhaust of the wafer drying module and determining the concentration of contaminants in the drying gas. The method also includes re-dispensing the drying gas over the batch of wafers if the concentration of contaminants is greater than a baseline value and transferring the batch of wafers out of the wafer drying module if the concentration is equal to or less than the baseline value. | 2020-04-30 |
20200135502 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD - A semiconductor manufacturing apparatus includes a chuck stage, a scrubber nozzle, a scrubber nozzle scan mechanism, a stage rotation mechanism, and a holding stage including a holding fluid nozzle and a top plate, the top plate having one main surface facing an opposite surface of a wafer, and the holding fluid nozzle being disposed adjacent to a center rather than a periphery portion of the top plate. A holding fluid discharged from the holding fluid nozzle is caused to flow through an area between the opposite surface of the wafer and the one main surface of the top plate to produce holding force, and the holding force causes the opposite surface to hold pressure applied to a processing surface of the wafer by a scrubbing fluid discharged from the scrubber nozzle. | 2020-04-30 |
20200135503 | SUBSTRATE TREATING METHOD, SUBSTRATE TREATING LIQUID AND SUBSTRATE TREATING APPARATUS - A substrate treating method, liquid and apparatus are provided which can reduce the amount of sublimable substance used for the drying of a substrate while reducing the collapse of pattern. The substrate treating method includes a step of supplying a liquid to the pattern-formed surface of the substrate, a step of solidifying the liquid on the pattern-formed surface to form a solidified body and a step of subliming the solidified body so as to remove it from the pattern-formed surface. The substrate treating liquid includes a molten sublimable substance and a solvent, the freezing point of the sublimable substance being higher than the freezing point of the solvent. When the sublimable substance and the solvent are separated, the sublimable substance is settled and in the solidification step, the settled sublimable substance is solidified to have a height equal to or higher than the height of a pattern. | 2020-04-30 |
20200135504 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes: a removing part configured to remove liquid droplets present in a recess; a drain hole located at the bottom of the recess of a nozzle head, and configured to discharge the liquid droplets as a target to be removed out of the recess; and a controller configured to control the discharge state of a gas discharge nozzle such that there is a period in which a gas is discharged from the gas discharge nozzle at a flow rate, at which the gas discharged does not reach a surface to be processed of the substrate, in a period from the end of the rinsing process using a treatment liquid to the start of the drying process using the gas. | 2020-04-30 |
20200135505 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes: a removing part configured to remove liquid droplets present in a recess; a drain hole located at the bottom of the recess of a nozzle head, and configured to discharge the liquid droplets as a target to be removed out of the recess; and a controller configured to control the discharge state of a gas discharge nozzle such that there is a period in which a gas is discharged from the gas discharge nozzle at a flow rate, at which the gas discharged does not reach a surface to be processed of the substrate, in a period from the end of the rinsing process using a treatment liquid to the start of the drying process using the gas. | 2020-04-30 |
20200135506 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device, and Non-Transitory Computer-readable Recording Medium - Described herein is a technique capable of improving the controllability of a thickness of a film formed on a large surface area substrate having a surface area greater than a surface area of a bare substrate and improving the thickness uniformity between films formed on a plurality of large surface area substrates accommodated in a substrate loading region by reducing the influence of the surface area of the large surface area substrate and the number of the large surface area substrates due to a loading effect even when the plurality of large surface area substrates are batch-processed using a batch type processing furnace. | 2020-04-30 |
20200135507 | MEDICAL INSTRUMENT FOR IN VIVO HEAT SOURCE - A biocompatible medical device can be at least partially implantable into a living human or animal subject to provide active treatment of biofilm that can occur use within the subject. The medical device can include a catheter, including an interior conduit capable of permitting fluid flow. A heating device can be located on a portion of the catheter to be located within the subject, the heating device including at least a pair of electrodes having a variable spacing therebetween, the variable spacing specified to allow heat to be generated using a time-varying electromagnetic input signal providing a variable frequency to control a variable location along the electrodes at which heat is generated, such as can provide a virtual matrix of local heat sources. | 2020-04-30 |
20200135508 | Processing Chamber With Annealing Mini-Environment - Apparatus and methods to process one or more wafers are described. The apparatus comprises a chamber defining an upper interior region and a lower interior region. A heater assembly is on the bottom of the chamber body in the lower interior region and defines a process region. A wafer cassette assembly is inside the heater assembly and a motor is configured to move the wafer cassette assembly from the lower process region inside the heater assembly to the upper interior region. | 2020-04-30 |
20200135509 | GAS CURTAIN FOR SEMICONDUCTOR MANUFACTURING SYSTEM - The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber, a slit valve configured to provide access to the chamber, a chuck disposed in the chamber and configured to hold a substrate, and a gas curtain device disposed between the chuck and the slit valve and configured to flow an inert gas to form a gas curtain. An example benefit of the gas curtain is to block an inflow of oxygen or moisture from entering the chamber to ensure a yield and reliability of the semiconductor manufacturing processes conducted in the chamber. | 2020-04-30 |
20200135510 | Integrated Circuit Fabrication System with Adjustable Gas Injector and Method Utilizing the Same - The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber; a substrate stage provided in the processing chamber and being configured to secure and rotate a semiconductor wafer; a gas injector configured to inject a chemical to the processing chamber; a window attached to the gas injector; and an adjustable fastening device coupled with the gas injector and the window. | 2020-04-30 |
20200135511 | WAFER TAPING APPARATUS AND METHOD - Wafer taping apparatuses and methods are provided for determining whether taping defects are present on a semiconductor wafer, based on image information acquired by an imaging device. In some embodiments, a method includes applying an adhesive tape on a surface of a semiconductor wafer. An imaging device acquires image information associated with the adhesive tape on the semiconductor wafer. The presence or absence of taping defects is determined by defect recognition circuitry based on the acquired image information. | 2020-04-30 |
20200135512 | SUBSTRATE PROCESSING APPARATUS FOR PROCESSING SUBSTRATES - The disclosure relates to substrate processing apparatus, with a first and second reactor, each reactor configured for processing a plurality of substrates; and, a substrate handling robot constructed and arranged to transfer substrates between a substrate cassette at a substrate transfer position and the first and second reactor. The apparatus is constructed and arranged with a maintenance area between the first and second reactors to allow maintenance of the reactors from the maintenance area to both the first and second reactor. | 2020-04-30 |
20200135513 | DIFFUSER AND SEMICONDUCTOR PROCESSING SYSTEM USING SAME - A diffuser for diffusing a gas includes a base portion and a head portion fluidly coupled to the base portion. The head portion includes a diffuser element configured to diffuse a first fraction of the gas through a circumference of the diffuser element and a second fraction of the gas through an end surface of the diffuser element. The head portion further includes a connecting structure having a first connecting portion configured to receive a portion of the diffuser element therein and a second connecting portion protruding outwardly from the first connecting portion and configured to couple to the base portion. | 2020-04-30 |
20200135514 | ELECTROMIGRATION EVALUATION METHODOLOGY WITH CONSIDERATION OF THERMAL AND SIGNAL EFFECTS - A method for evaluating a heat sensitive structure involving identifying a heat sensitive structure in an integrated circuit design layout, the heat sensitive structure characterized by a nominal temperature, identifying a heat generating structure within a thermal coupling range of the heat sensitive structure, calculating an operating temperature of the first heat generating structure; calculating a temperature increase or the heat sensitive structure induced by thermal coupling to the heat generating structure at the operating temperature; and performing an electromigration (EM) analysis of the heat sensitive structure at an evaluation temperature obtained by adjusting the nominal temperature by the temperature increase induced by the heat generating structure. | 2020-04-30 |
20200135515 | CONTROL DEVICE OF SUBSTRATE PROCESSING APPARATUS AND CONTROL METHOD OF SUBSTRATE PROCESSING APPARATUS - A control device of a substrate processing apparatus includes a reading unit, an estimation unit, a comparison unit, and a correction unit. The reading unit reads out a reference processing condition for processing a substrate. The estimation unit estimates an actual processing condition when the substrate is processed. The comparison unit compares the reference processing condition and the actual processing condition with each other. The correction unit corrects a processing condition for the substrate based on a comparison result in the comparison unit. | 2020-04-30 |
20200135516 | WAFER CLEANING SYSTEM AND METHOD - A wafer cleaning system and method are provided. A brush element is configured to clean a backside of the wafer. The backside has a clear area and an unclear area, and some contaminants are located in the unclear area. A control device performs a first cleaning process to the brush element when the brush element is located at the clear area, and the control device performs a second cleaning process when the brush element is located at the unclear area. The contaminants are cleaned by an enhanced cleaning process. Since the contaminants are cleaned, the backside of the wafer is flatter, and quality of the exposed photoresist on the wafer is improved. | 2020-04-30 |
20200135517 | TECHNIQUES FOR COMBINING CMP PROCESS TRACKING DATA WITH 3D PRINTED CMP CONSUMABLES - Chemical mechanical polishing (CMP) apparatus and methods for manufacturing CMP apparatus are provided herein. CMP apparatus may include polishing pads, polishing head retaining rings, and polishing head membranes, among others, and the CMP apparatus may be manufactured via additive manufacturing processes, such as three dimensional (3D) printing processes. The CMP apparatus may include wireless communication apparatus components integrated therein. Methods of manufacturing CMP apparatus include 3D printing wireless communication apparatus into a polishing pad and printing a polishing pad with a recess configured to receive a preformed wireless communication apparatus. | 2020-04-30 |
20200135518 | ANNEALING APPARATUS AND METHOD THEREOF - An annealing apparatus includes a heater plate and a cooler plate disposed in a chamber, a delivering robot, a sensor and circuitry. The delivering robot is configured to deliver a wafer between the heater plate and the cooler plate in the chamber. The sensor is located on the delivering robot and configured to output a first signal in response to a motion of the delivering robot. The circuitry is coupled to the sensor and configured to detect whether an abnormality of the delivering robot occurs according to the first signal. | 2020-04-30 |
20200135519 | Shape-Distortion Standards for Calibrating Measurement Tools for Nominally Flat Objects - A first nominally flat object is obtained that has a controlled warpage that has been measured in a manner traceable through a standard reference material to a fundamental unit of measurement. A measurement tool is calibrated using the first nominally flat object. After calibrating the measurement tool using the first nominally flat object, the warpage of a plurality of nominally flat objects is measured using the measurement tool, wherein the plurality of nominally flat objects is distinct from the first nominally flat object. | 2020-04-30 |
20200135520 | SIDE STORAGE PODS, EQUIPMENT FRONT END MODULES, AND METHODS FOR OPERATING THE SAME - Electronic device processing assemblies including an equipment front end module (EFEM) with at least one side storage pod attached thereto are described. The side storage pod has a side storage container. In some embodiments, an exhaust conduit extends between the chamber and a pod plenum that can contain a chemical filter proximate thereto. A supplemental fan may draw purge gas from the pod plenum through the chemical filter and route the gas through a return duct to an upper plenum of the EFEM. Methods and side storage pods in accordance with these and other embodiments are also disclosed. | 2020-04-30 |
20200135521 | HIGH FLOW VELOCITY, GAS-PURGED, SIDE STORAGE POD APPARATUS, ASSEMBLIES, AND METHODS - In some embodiments, a side storage pod apparatus of an equipment front end module (EFEM) includes a side storage enclosure having a surface configured to couple to a side wall of a body of the equipment front end module, and an opening configured to receive substrates from the equipment front end module. The EFEM further includes a side storage chamber within the side storage enclosure having a plurality of support members configured to support substrates thereon. The EFEM further includes a plenum chamber provided proximate the side storage chamber, the plenum chamber being a separate chamber from the side storage chamber and an exhaust port coupled to the plenum chamber. | 2020-04-30 |
20200135522 | SIDE STORAGE PODS, ELECTRONIC DEVICE PROCESSING SYSTEMS, AND METHODS FOR OPERATING THE SAME - Electronic device processing systems including an equipment front end module with at least one side storage pod are described. The side storage pod has a chamber including a top substrate holder and a bottom substrate holder. In some embodiments, an exhaust port is located at a midpoint between the top substrate holder and the bottom substrate holder. Methods and systems in accordance with these and other embodiments are also disclosed. | 2020-04-30 |
20200135523 | FRONT-DUCTED EQUIPMENT FRONT END MODULES, SIDE STORAGE PODS, AND METHODS OF OPERATING THE SAME - Equipment front end module (EFFM) includes front located return ducts. The EFFM may include a front wall, a rear wall, and two side walls, the front wall including a plurality of load ports, and the rear wall configured to couple to a load lock apparatus. An EFFM chamber is formed between the front wall, the rear wall, and the two side walls. An upper plenum is positioned at a top of the EFFM and includes an opening into the EFFM chamber. Return ducts provide a return gas flow path enabling recirculation of gas from the EFFM chamber to the upper plenum. At least some of the plurality of return ducts are located between the load ports. Electronic device manufacturing assemblies and methods of operating equipment front end modules are also disclosed. | 2020-04-30 |
20200135524 | TRANSFER METHOD AND TRANSFER APPARATUS - A transfer method including following steps is provided. A pick-up device having a plurality of caves is provided. A first magnetic force capable of attracting a plurality of micro-devices to move toward the caves of the pick-up device is provided. Given that the first magnetic force is provided, the pick-up device is in contact with the micro-devices, so that the micro-devices are snapped by the caves of the pick-up device. The micro-devices are transferred from the caves of the pick-up device to a receiving device. Besides, a transfer apparatus is also provided. | 2020-04-30 |
20200135525 | SIDE STORAGE PODS, EQUIPMENT FRONT END MODULES, AND METHODS FOR OPERATING EFEMS - Electronic device processing systems including an equipment front end module with at least one side storage pod are described. The side storage pod has a side storage container and a container plenum. A fan draws purge gas from the equipment front end module chamber into the container plenum where the purge gas is directed into the side storage container to pass over substrates stored therein and is then exhausted back into the equipment front end module chamber. Methods and systems are also disclosed. | 2020-04-30 |
20200135526 | WAFER SUPPORT TABLE - A wafer support table includes a ceramic base and a rod. The ceramic base has a wafer placement surface and includes an RF electrode and a heater electrode that are embedded therein in the mentioned order from the side closer to the wafer placement surface. A hole is formed in the ceramic base to extend from a rear surface toward the RF electrode. The rod is made of Ni or Kovar, is bonded to a tablet exposed at a bottom surface of the hole, and supplies radio-frequency electric power to the RF electrode therethrough. An Au thin film is coated over a region of an outer peripheral surface of the rod ranging from a base end of the rod to a predetermined position. | 2020-04-30 |
20200135527 | APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor processing apparatus includes a chamber housing, an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer, an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring, and a ring voltage supply configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform comprises a positive voltage applied during a first time period and a negative voltage applied during a second time period, and wherein the negative voltage has a magnitude that increases during the second time period. | 2020-04-30 |
20200135528 | ELECTROSTATIC CHUCK - According to one embodiment, an electrostatic chuck includes a ceramic dielectric substrate, a base plate, and a first porous part. The ceramic dielectric substrate has a first major surface and a second major surface. The base plate supports the ceramic dielectric substrate and includes a gas feed channel. | 2020-04-30 |
20200135529 | ELECTROSTATIC CHUCK - According to one embodiment, an electrostatic chuck includes a ceramic dielectric substrate, a base plate, and a first porous part. The ceramic dielectric substrate has a first major surface and a second major surface on opposite side from the first major surface. The base plate supports the ceramic dielectric substrate and includes a gas feed channel. The first porous part is provided at a position between the base plate and the first major surface of the ceramic dielectric substrate. The position is opposed to the gas feed channel. The first porous part includes a plurality of sparse portions each including a plurality of pores. The plurality of sparse portions are spaced from each other. Each of the plurality of sparse portions extends in a direction inclined by a prescribed angle with respect to a first direction from the base plate to the ceramic dielectric substrate. | 2020-04-30 |
20200135530 | GRADED DIMPLE HEIGHT PATTERN ON HEATER FOR LOWER BACKSIDE DAMAGE AND LOW CHUCKING VOLTAGE - Embodiments disclosed herein may include a heater pedestal. In an embodiment, the heater pedestal may comprise a heater pedestal body and a conductive mesh embedded in the heater pedestal. In an embodiment, the conductive mesh is electrically coupled to a voltage source In an embodiment, the heater pedestal may further comprise a support surface on the heater pedestal body. In an embodiment, the support surface comprises a plurality of pillars extending out from the heater pedestal body and arranged in concentric rings. In an embodiment pillars in an outermost concentric ring have a height that is greater than a height of pillars in an innermost concentric ring. | 2020-04-30 |
20200135531 | PROTECTIVE MEMBER FORMING METHOD - A protective member forming method includes forming a water film on a flat holding surface of a support base, placing a wafer on the water film formed on the holding surface and next freezing the water film in a condition where the wafer floats on an upper surface of the water film owing to the surface tension of the water film, thereby forming an ice layer and fixing the wafer on the ice layer, supplying a liquid resin curable by the application of ultraviolet light to the upper surface of the wafer, opposing a transparent sheet to the wafer with the liquid resin interposed therebetween, and applying ultraviolet light to the liquid resin, thereby curing the liquid resin to form a protective member on a whole of the upper surface of the wafer. | 2020-04-30 |
20200135532 | WAFER EXPANDING METHOD AND WAFER EXPANDING APPARATUS - A wafer expanding method increases spacing between adjacent devices formed on a wafer. The method includes preparing an annular jig having a first restricting portion, a second restricting portion, and a curved restricting portion connecting the first restricting portion and the second restricting portion, mounting a ring frame supporting the wafer through an adhesive tape on a cylindrical frame fixing member, next mounting the annular jig on the ring frame, and next fixing the ring frame and the annular jig to the cylindrical frame fixing member, and operating a cylindrical pushing member having an outer circumference corresponding to an outer circumference of the wafer to push up an annular exposed portion of the adhesive tape defined between the wafer and the ring frame and thereby lift the wafer away from the ring frame, thereby expanding the annular exposed portion and increasing the spacing between the adjacent devices. | 2020-04-30 |
20200135533 | WAFER EXPANDING METHOD AND WAFER EXPANDING APPARATUS - A wafer expanding method for expanding a wafer having a plurality of rectangular devices respectively formed in a plurality of separate regions defined by a plurality of division lines, thereby increasing spacing between any adjacent ones of the devices, each rectangular device having a pair of shorter sides and a pair of longer sides. The wafer expanding method includes a jig preparing step of preparing an annular jig having an elliptical opening, the elliptical opening having a shorter portion for restricting a width of the annular exposed portion in a first direction where the shorter sides of the devices extend to a first width and a longer portion for restricting the width of the annular exposed portion in a second direction where the longer sides of the devices extend to a second width larger than the first width. | 2020-04-30 |
20200135534 | Setting Up Ultra-Small or Ultra-Thin Discrete Components for Easy Assembly - Among other things a method including releasing a discrete component from an interim handle and depositing a discrete component on a handle substrate, attaching the handle substrate to the discrete component, and removing the handle substrate from the discrete component. | 2020-04-30 |
20200135535 | TESTING TOOL FOR FLEXIBLE DISPLAY - A testing tool for testing a flexible display includes a platform, a first mechanical component and a second mechanical component. The platform includes a plane. The first mechanical component is disposed on the plane to drive the flexible display to move, wherein the first mechanical component includes a first clamping unit connected to a first end of the flexible display. The second mechanical component is disposed on the plane opposite to the first mechanical component, wherein the second mechanical component includes a second clamping unit connected to a second end of the flexible display. | 2020-04-30 |
20200135536 | Gate Driver Circuitry for Power Transistors - The present invention relates in a first aspect to a regulated high side gate driver circuit for power transistors. The regulated high side gate driver circuit comprises a gate driver powered by a floating voltage regulator which comprises a linear regulating device. | 2020-04-30 |
20200135537 | METAL SPACER SELF ALIGNED DOUBLE PATTERNING WITH AIRGAP INTEGRATION - A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal. | 2020-04-30 |
20200135538 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THEREOF - In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed. | 2020-04-30 |
20200135539 | CROSSBAR REINFORCED SEMICONDUCTOR FINS HAVING REDUCED WIGGLING - A method for forming a silicon structure. A non-limiting example of the method includes forming at least two semiconductor fins on a substrate. A polymer brush material is formed over the fins and the substrate. A block copolymer (BCP) composed of a first polymer and a second polymer which are covalently bound together is applied over the polymer brush material, such that the first polymer and second polymer self-assemble into a plurality of interleaved first microdomains and second microdomains perpendicular to and within a trench between the fins. The first microdomains are composed of the first polymer and the second microdomains are composed of the second polymer. The second microdomains can be selectively removed. | 2020-04-30 |