18th week of 2020 patent applcation highlights part 66 |
Patent application number | Title | Published |
20200135240 | COATED SLIDER TO INHIBIT CONTAMINATION ACCUMULATION - A slider is provided with a conformal coating (e.g., an oxide) on the air-bearing surface (ABS) to provide a consistent surface energy to the ABS. The conformal coating may be formed by an atomic layer deposition (ALD) process. A consistent surface energy inhibits accumulation of contaminants on the slider ABS, such as at topographical transition areas. | 2020-04-30 |
20200135241 | MEMORY STRUCTURE WITH NON-STRAIGHT WORD LINE - A memory structure includes a first memory cell, a first word line and a second word line. The first word line includes a first portion, a second portion and a third portion. The first portion extends from an end of the second portion along a first direction, and the third portion extends from an another end of the second portion along a second direction. An angle between the first direction and the second direction is less than 180°. The second word line includes a forth portion, a fifth portion and a sixth portion. The forth portion extends from an end of the fifth portion along a third direction, and the sixth portion extends from an another end of the fifth portion along a forth direction. An angle between the third direction and the forth direction is less than 180°. | 2020-04-30 |
20200135242 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: first to fifth interconnects; a semiconductor layer having one end located between the fourth interconnect and the fifth interconnect and other end connected to the first interconnect; a memory cell; a conductive layer having one end connected to the second interconnect and other end connected to the semiconductor layer; a first insulating layer provided to extend between the third and fourth interconnects and the semiconductor layer, and between the fifth interconnect and the conductive layer; an oxide semiconductor layer provided to extend between the fourth and fifth interconnects and the first insulating layer; and a second insulating layer provided to extend between the fourth and fifth interconnects and the oxide semiconductor layer. | 2020-04-30 |
20200135243 | SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING SENSE AMPLIFIER AND LATCH - A semiconductor integrated circuit includes a sense amplifier circuit suitable for generating differential output signals by sensing and amplifying a level difference of differential input signals in response to a clock signal, and outputting the differential output signals to first and second nodes, respectively, a latch circuit suitable for feeding back and latching the differential output signals between the first and second nodes, and a control circuit suitable for controlling the feedback of the differential output signals between the first and second nodes in response to an initialization signal. | 2020-04-30 |
20200135244 | DRIVING CIRCUIT - The present disclosure relates to a driving circuit including a first circuit, a transistor switch, and a voltage level conversion circuit. The first circuit includes an operational amplifier and a feedback circuit, and is configured to output a first signal (e.g., an analog signal). The feedback circuit is configured to feed back the first signal to the operational amplifier. A source terminal and a drain terminal of the transistor switch are respectively electrically coupled to the operational amplifier and an output pin of the driving circuit. The voltage level conversion circuit is connected to the source terminal and a gate terminal of the transistor switch. When the voltage level conversion circuit is enabled, a voltage difference between the gate terminal and the source terminal of the transistor switch is controlled to a set value, so that the first signal is output to the output pin through the transistor switch. | 2020-04-30 |
20200135245 | MEMORY DEVICE WITH SELECTIVE PRECHARGING - A memory device includes memory cells operably connected to column signal lines and to word signal lines. The column signal lines associated with one or more memory cells to be accessed (e.g., read) are precharged to a first voltage level. The column signal lines not associated with the one or more memory cells to be accessed are precharged to a second voltage level, where the second voltage level is less than the first voltage level. | 2020-04-30 |
20200135246 | PROCESSING DEVICE WITH NONVOLATILE LOGIC ARRAY BACKUP - A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements. | 2020-04-30 |
20200135247 | METHOD OF CONTROLLING ON-DIE TERMINATION AND SYSTEM PERFORMING THE SAME - A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation. | 2020-04-30 |
20200135248 | SEMICONDUCTOR DEVICES - A semiconductor device includes a control circuit and an address generation circuit. The control circuit generates a write column address signal, a write bank selection signal and an internal write bank selection signal from a command/address signal during a write operation. The control circuit also generates a read column address signal, a read bank selection signal and an internal read bank selection signal from the command/address signal during a read operation. The address generation circuit outputs the write column address signal as a bank group address signal in synchronization with the write bank selection signal and the internal write bank selection signal or outputs the read column address signal as the bank group address signal in synchronization with the read bank selection signal and the internal read bank selection signal. | 2020-04-30 |
20200135249 | APPARATUSES AND METHOD FOR REDUCING ROW ADDRESS TO COLUMN ADDRESS DELAY - Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a memory cell coupled to a first digit line in response to a wordline being set to an active state and a sense amplifier coupled to the first digit line and to a second digit line. The sense amplifier is configured to perform a threshold voltage compensation operation to bias the first digit line and the second digit line based on a threshold voltage difference between at least two circuit components of the sense amplifier. The apparatus further comprising a decoder circuit coupled to the wordline and to the sense amplifier. In response to an activate command, the decoder circuit is configured to initiate the threshold voltage compensation operation and, during the threshold voltage compensation operation, to the set the wordline to the active state. | 2020-04-30 |
20200135250 | Magnetic Memory and Method for Using the Same - The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element. | 2020-04-30 |
20200135251 | RANDOM ACCESS MEMORY - A memory cell includes a memory cell stack, a first word line, a second word line, a bit line coupled to one end of the memory cell stack, a first unidirectional selector having one end coupled to another end of the memory cell stack and another end coupled to the first word line, and a second unidirectional selector having one end coupled to the another end of the memory cell stack and another end coupled to the second word line. Current flow directions of the first unidirectional selector and the second unidirectional selector are opposite to each other. | 2020-04-30 |
20200135252 | READ CIRCUIT FOR MAGNETIC TUNNEL JUNCTION (MTJ) MEMORY - In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage. | 2020-04-30 |
20200135253 | CURRENT STEERING IN READING MAGNETIC TUNNEL JUNCTION - The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value. | 2020-04-30 |
20200135254 | KEY-BASED MULTI-QUBIT MEMORY - A memory is capable of storing coupled qubits. The memory includes a plurality of memory cells, wherein each of the memory cells is for storing values of one of the qubits. The memory also includes an electronic controller electrically connected to operate said memory cells. The controller is able to selectively store a qubit value to any of the memory cells in either a first state or a second state. The controller is configured to read any one of the memory cells in a manner dependent on whether the first state or the second state was previously used to store a qubit value in the same one of the memory cells. | 2020-04-30 |
20200135255 | MEMORY DEVICE AND REFRESH INFORMATION COHERENCE METHOD THEREOF - A memory device includes a memory with a plurality of memory blocks and a first storage circuit to store a first data table and a first refresh value, and a memory controller with a second storage circuit to store a second data table and a second refresh value. When the memory controller meets a refresh request, the memory controller reads the second refresh value and compares the corresponding access address to the corresponding bit in the second data table to determine whether valid data are stored in a specific memory block of the memory. The memory controller sends a valid-data refresh command to the memory when valid data are stored in the specific memory block, but sends an invalid-data refresh command to the memory when invalid data are stored in the specific memory block. | 2020-04-30 |
20200135256 | Signal Processing Circuit, Distributed Memory, ROM, and DAC which Signal Processing Circuit is Embedded - A signal processing circuit is provided that generates output signals to be output from spatially different output ports based on bit combinations of an input word consisting of a plurality of bit signals. A distributed memory, a ROM and a DAC in which the signal processing circuit is used are also provided. A recognition circuit includes a serial port to which a bit signal is input and 2 | 2020-04-30 |
20200135257 | SELECTIVELY CONTROLLING CLOCK TRANSMISSION TO A DATA (DQ) SYSTEM - An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal. | 2020-04-30 |
20200135258 | SENSING CHARGE RECYCLING CIRCUITRY - A memory device include one or more sections of memory banks. Each of the one or more sections may include multiple sensing amplifiers and a digit line to supply voltages to the sensing amplifiers during a refresh of the respective section. The memory device may also include transmission circuitry configured to transmit excess charge remaining on a first digit line of a first section to a second digit line of a second section after a refresh of the first section and before a refresh of the second section. | 2020-04-30 |
20200135259 | HIGH BANDWIDTH DRAM MEMORY WITH WIDE PREFETCH - An embodiment of an electronic apparatus may include a silicon substrate and a memory circuit coupled to the silicon substrate, the memory circuit including an array block of memory tiles coupled to the silicon substrate, a first set of global amplifiers coupled to the silicon substrate and the memory tiles and arranged along a first side of the array block, a first set of write drivers coupled to the silicon substrate and coupled to the memory tiles and arranged along the first side of the array block, a second set of global amplifiers coupled to the silicon substrate and coupled to the memory tiles and arranged along a second side of the array block opposite to the first side of the array block, and a second set of write drivers coupled to the silicon substrate and coupled to the memory tiles and arranged along the second side of the array block. Other embodiments are disclosed and claimed. | 2020-04-30 |
20200135260 | MEMORY DEVICE WRITE CIRCUITRY - Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers. | 2020-04-30 |
20200135261 | CONTROL DEVICE, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD FOR A SEMICONDUCTOR MEMORY DEVICE - According to a control device of a first aspect of the invention, for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the control device comprises a plurality of banks, a read/write control circuit, and a transfer control circuit. The banks are connected to one another by an internal data bus, and each bank, separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, comprises a plurality of subarrays. Each subarray comprises a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines. The read/write control circuit controls reading of data from the semiconductor memory device and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface. | 2020-04-30 |
20200135262 | STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies. | 2020-04-30 |
20200135263 | APPARATUSES AND METHODS FOR ACCESS BASED REFRESH TIMING - Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed. | 2020-04-30 |
20200135264 | PERFORMING AN ON DEMAND REFRESH OPERATION OF A MEMORY SUB-SYSTEM - A temporal attribute of user data stored in a memory component is identified. It is determined that the identified temporal attribute satisfies a time condition. An indication is provided whether a refresh operation of the user data improves performance of the memory component. A user input is received indicating to perform the refresh operation of the memory component. The refresh operation of the memory component is performed. | 2020-04-30 |
20200135265 | Method for Operating the Semiconductor Device - A method for performing a refresh operation on a memory cell efficiently is provided. A semiconductor device including a normal memory cell and a trigger memory cell that determines whether the refresh operation is performed or not is used. Specific data is written to the trigger memory cell, and the data is read from the trigger memory cell at predetermined timing. When the read data agrees with the written specific data, no special operation is performed. When the read data does not agree with the written specific data, a refresh operation is performed automatically. | 2020-04-30 |
20200135266 | RANDOM-ACCESS MEMORY WITH LOADED CAPACITANCE - A loaded capacitance static random-access memory (C-SRAM) is provided. The C-SRAM is configured to prevent full bit line discharge during a functional reads even where the number of bit cells on the bit lines is small. The C-SRAM includes one or more loaded capacitance structures that may take any of a variety of physical configurations designed to provide additional capacitance to the bit lines. For instance, the loaded capacitance structures may take the form of a MIM capacitor in which a ferroelectric layer is formed from one or more high K materials. In addition, the loaded capacitance structures may be positioned in a variety of locations within the C-SRAM, including the back end of line. | 2020-04-30 |
20200135267 | ORTHOGONAL DUAL PORT RAM (ORAM) - An Orthogonal Dual Port Ram (ORAM) memory cell may be provided. The ORAM memory cell may comprise a data storage element, a first port bit line, and a second port bit line that may be substantially perpendicular to first port bit line. The ORAM memory cell may further comprise a first word line that may be substantially perpendicular to first port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the first port bit line when the first word line is enabled. The ORAM memory cell may further comprise a second word line being substantially perpendicular to the second port bit line wherein the ORAM memory cell may be configured to read data from the data storage element to the second port bit line when the second word line is enabled. | 2020-04-30 |
20200135268 | METHOD AND SYSTEM TO BALANCE GROUND BOUNCE - A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port. | 2020-04-30 |
20200135269 | BOOST SCHEMES FOR WRITE ASSIST - A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal. | 2020-04-30 |
20200135270 | STORAGE DEVICE AND METHOD OF OPERATING THE SAME - A storage device includes a memory device including a memory cell array and a page buffer group coupled to the memory cell array, and a memory controller configured to store a plurality of cache data chunks to be sequentially programmed, and configured to input a next cache data chunk corresponding to a next program sequence to the page buffer group, when programming of Least Significant Bit (LSB) data of a cache data chunk among the plurality of cache data chunks is completed. | 2020-04-30 |
20200135271 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation being read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage higher than the first voltage to the bit line and also apply a third voltage lower than the first voltage to the source line, in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period. | 2020-04-30 |
20200135272 | MEMORY DEVICE AND METHOD THEREOF - A method is disclosed including following operations. A first signal is applied to memory cells in a memory device, to adjust resistance values of the memory cells. After the first signal is applied, a second signal is applied to the memory cells other than the first memory cell, to further adjust the resistance values of the plurality of memory cells other than the first memory cell. After the second signal is applied, data corresponding to the first predetermined resistance value and the second predetermined resistance value is stored in the first memory cell and the second memory cell, respectively. The first signal is configured for controlling a first memory cell in the memory cells to have a first predetermined resistance value. The second signal is configured for controlling a second memory cell in the memory cells to have a second predetermined resistance value. | 2020-04-30 |
20200135273 | SINGLE-ENDED PHASE-CHANGE MEMORY DEVICE AND READING METHOD - A phase-change memory device, comprising: a memory array of PCM cells, a variable current generator, and a sense amplifier. The current generator comprises a reference array of PCM cells programmed in SET resistance state. The phase-change memory device further comprises a decoder for addressing each cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; and a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current to be lower than said mean value. | 2020-04-30 |
20200135274 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same. | 2020-04-30 |
20200135275 | MEMORY ARRAYS AND METHODS OF FORMING THE SAME - A device having at least one memory cell over a substrate is provided. The at least one memory cell includes a source region and a drain region in the substrate, and a first gate and a second gate over the substrate. The first and second gates are arranged between the source region and the drain region. The first and second gate are separated by an intergate dielectric. The first gate is configured as a select gate and erase gate of the at least one memory cell, and the second gate is configured as a storage gate of the at least one memory cell. The second gate comprises a floating gate and a control gate over the floating gate. The device further includes source/drain (S/D) contacts extending from the source region and the drain region. The source region and the drain region are coupled to either one of a source line (SL) or a bit line (BL) through the S/D contacts. | 2020-04-30 |
20200135276 | EVENT COUNTERS FOR MEMORY OPERATIONS - A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage. | 2020-04-30 |
20200135277 | SECURE ERASE FOR DATA CORRUPTION - Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases. | 2020-04-30 |
20200135278 | DYNAMIC DELAY OF NAND READ COMMANDS - Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which increase read throughput by introducing a delay prior to issuing a command to increase the chances that read commands can be executed in parallel. Upon receipt of a read command, if there are no other read commands in the command queue for a given portion (e.g., plane or plane group) of the die, the controller can delay issuing the read command for a delay period using a timer. If, during the delay period, an eligible read command is received, the delayed command and the newly received command are both issued in parallel using a multi-plane read. If no eligible read command is received during the delay period, the read command is issued after the delay period expires. | 2020-04-30 |
20200135279 | IMPLEMENTING STICKY READ USING ERROR CONTROL SUCCESS RATE ASSOCIATED WITH A MEMORY SUB-SYSTEM - A memory sub-system can be determined to be operating within a target operating characteristic based on a threshold success rate associated with error control operations using a particular parameter. Upon determining that the memory sub-system is operating within the target operating characteristic, a sticky read mode is entered by performing subsequent read operations using the particular parameter. It is determined that additional error control operations are triggered for at least a first threshold number of read operations using the particular parameter during the sticky read mode. Upon determining that the additional error control operations are triggered for at least the first threshold number of read operations using the particular parameter during the sticky read mode, the sticky read mode is exited by performing further read operations using a default parameter associated with the memory sub-system. | 2020-04-30 |
20200135280 | READ RETRY METHOD FOR SOLID STATE STORAGE DEVICE - A read retry method for a solid state storage device is provided. The solid state storage device is in communication with a host. The solid state storage device includes a non-volatile memory. The read retry method includes the following steps. Firstly, the solid state storage device judges whether a specified read block of the non-volatile memory is in a specified failure mode. If the specified read block of the non-volatile memory is in the specified failure mode, a failure mode read retry process corresponding to the specified failure mode is performed. If an accurate read data is acquired in the failure mode read retry process, the accurate read data is transmitted to the host. If the accurate read data is not acquired in the failure mode read retry process, a read fail message is sent to the host. | 2020-04-30 |
20200135281 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE, AND METHOD OF CONTROLLING NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory cell array includes memory cells, a row decoder, a page buffer circuit and a control logic circuit. The row decoder is connected to the memory cells through word lines and includes switches configured to select the word lines, respectively. The page buffer circuit is connected to the memory cell array through bit lines. The control logic circuit is configured to perform operational functions when the row decoder turns on a switch corresponding to a particular word line among the word lines. The operational functions include supplying a charging voltage to the particular word line through the switch, stopping the supply of the charging voltage after the charging voltage is supplied to the particular word line, leaking a fixed current from the particular word line through the switch after stopping the supply of the charging voltage, and outputting, to an external device, time information about a time from when the fixed current is initially leaked to a time when a voltage of the particular word line becomes lower than a reference voltage. | 2020-04-30 |
20200135282 | MEMORY DEVICE AND READ OPERATION METHOD THEREOF - A memory device includes a memory cell array including a plurality of memory cells, a plurality of first even page buffers suitable for reading data from first even-numbered memory cells among the plurality of memory cells, and storing the read data, a plurality of first odd page buffers suitable for reading data from first odd-numbered memory cells among the plurality of memory cells, and storing the read data, and a plurality of first cache buffers corresponding to the first even page buffers, suitable for storing data received through a first common node from the first even page buffers, and a plurality of second cache buffers corresponding to the first odd page buffers, and suitable for storing data received through the first common node from the first odd page buffers. | 2020-04-30 |
20200135283 | MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME - Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory controller configured to control a memory device including a plurality of memory blocks, each including a plurality of memory cells. The memory controller may include a memory device interface configured to perform data communication with the memory device, and a soft program controller communicatively coupled to the memory device interface and configured to count a number of times that an erase operation on an erase target memory block, among the plurality of memory blocks, has been suspended until the erase operation is completed, and to perform a soft program operation on the erase target memory block after the erase operation has been completed, based on the number of iterations that the erase operation on the erase target memory block has been suspended. | 2020-04-30 |
20200135284 | SOLID STATE DRIVE (SSD) WITH IN-FLIGHT ERASURE ITERATION SUSPENSION - An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform. | 2020-04-30 |
20200135285 | SEMICONDUCTOR DEVICE - An object of the present invention is to increase a writing speed to a flash memory while suppressing an increase in noise. In the high-speed write mode, the memory controller simultaneously performs a first write operation with a second write current having a current value smaller than the first write current with respect to a second number of memory cells having a larger number than the first write current. At the completion of the first write operation, the memory controller simultaneously performs the second write operation by the third write current having a larger current value than the second write current with respect to the memory cell determined by the sense amplifier to have not completed the write operation in the determination process. | 2020-04-30 |
20200135286 | Shift Register Unit and Driving Method, Gate Drive Circuit and Display Device - A shift register unit, a gate drive circuit, a display device and a driving method are disclosed. The shift register unit includes a first input circuit, a second input circuit, an output circuit and an anti-crosstalk circuit. The first input circuit is configured to input a first input signal to a first node; the second input circuit is configured to input a second input signal to the first node in a situation where the second node is at a first level and to stop inputting the second input signal to the first node in a situation where the second node is at a second level; the output circuit is configured to output or not output an output signal; the anti-crosstalk circuit is configured to prevent a level of the second node from becoming the first level in a situation where the second node is at the second level. | 2020-04-30 |
20200135287 | SHIFT REGISTER UNIT AND METHOD FOR DRIVING THE SAME, GATE DRIVING CIRCUIT, AND DISPLAY APPARATUS - The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit includes: a first input sub-circuit configured to transmit a signal at a first signal input terminal to a pull-up node under control of the first signal input terminal; a second input sub-circuit configured to transmit the signal at the first signal input terminal to the pull-up node under control of a second signal input terminal; a first output sub-circuit configured to transmit a signal at a first clock signal terminal to a first signal output terminal under control of the pull-up node; and a second output sub-circuit configured to transmit a signal at a second clock signal terminal to a second signal output terminal under control of the pull-up node. | 2020-04-30 |
20200135288 | MEMORY DEVICE - A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory. | 2020-04-30 |
20200135289 | Quick Configurable Universal Register for a Configurable Integrated Circuit Die - An FPGA includes a number of logic elements in a core fabric. Each logic element includes a number of registers and each register includes a registered circuit path and a combinatorial circuit path. The registered and combinatorial circuit paths are in parallel. Each register includes a DFT circuit path that comprises an input in the registered circuit path and an output in the registered circuit path. The DFT circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. Each register includes a CE time-borrowing circuit path. Each the CE time-borrowing circuit path includes an input in the registered circuit path and an output that is coupled to the input of the registered circuit path. The CE time-borrowing circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. | 2020-04-30 |
20200135290 | TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER - A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM. | 2020-04-30 |
20200135291 | SHARED ERROR CHECK AND CORRECT LOGIC FOR MULTIPLE DATA BANKS - Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data. | 2020-04-30 |
20200135292 | MEMORY MODULES AND METHODS OF OPERATING MEMORY SYSTEMS INCLUDING THE SAME - A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories. | 2020-04-30 |
20200135293 | DATA RETENTION IN STORAGE DRIVES - A method and a system for monitoring conditions of offline storage devices is disclosed. Predetermined environmental conditions are monitored to determine whether a storage device should be brought online to perform a data integrity check process. The process receives a triggering event that corresponds with the storage device, powers on the storage devices, selects a page from the storage device, and determines a bit error rate. Once the bit error rate is determined, error-correcting code runs to correct the errors. Any uncorrectable errors are reported, and the storage device is brought back offline. | 2020-04-30 |
20200135294 | HAMMING-DISTANCE ANALYZER AND METHOD FOR ANALYZING HAMMING-DISTANCE - A device is disclosed for testing a memory, in which the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response in responses of the first memory circuit, and the first memory circuit is configured to store a second response of responses of the second memory circuit. The device includes a comparing circuit and a maximum hamming distance generating circuit. The comparing circuit is configured to compare the first response with the responses of the first memory circuit, and configured to compare the second response with the responses of the second memory circuit, to generate comparing results. The maximum hamming distance generating circuit is configured to generate a maximum hamming distance according to the comparing results. | 2020-04-30 |
20200135295 | DEVICE AND METHOD FOR SEARCHING COMPOUND - A device including: a defining unit to define lattice space that is collection of lattices where compound groups are sequentially arranged; a limiting unit; an assigning unit; an arithmetic unit; a judging unit; and a controlling unit to cause the limiting unit to execute expansion of the limited lattice space, the assigning unit to execute assignment of the bits to the lattice points included in the limited lattice space after the expansion, and the arithmetic unit to execute calculation of the minimum energy, in case where the judging unit judges any of the compound groups assigned to the lattice points is arranged on the outermost edge, wherein the device is device for searching the compound, in which the compound groups are linked with one another. | 2020-04-30 |
20200135296 | ESTIMATION OF PHENOTYPES USING DNA, PEDIGREE, AND HISTORICAL DATA - Disclosed are techniques for predicting a trait of an individual and identifying a set of enriched record collections of a genetic community. To predict a trait of an individual, DNA features and non-DNA features of the individual are accessed to generate a feature vector that is inputted into a machine learning model. The machine learning model generates a prediction of the trait. The prediction may be based on an inheritance prediction and/or a community prediction. To identify a set of enriched record collections, individuals belonging to a genetic community are identified and a set of candidate record collections are accessed. A community count and a background count is determined for each candidate record collection. The set of enriched record collections are identified based on a comparison of the community count and the background count. The genetic community may be annotated using the set of enriched record collections. | 2020-04-30 |
20200135297 | Computer Files and Methods Supporting Forensic Analysis of Nucleotide Sequence Data - In one illustrative embodiment, an allelotyping method may comprise using a massively parallel sequencing (MPS) instrument to read nucleotide sequences in a sample and to generate nucleotide sequence data quantifying each read of a nucleotide sequence in the sample, determining, for each read by the MPS instrument, whether a portion of the generated nucleotide sequence data represents a short tandem repeat (STR) associated with a corresponding locus, adding each portion of the nucleotide sequence data determined to represent an STR to a locus-specific list for the corresponding locus, determining, for each locus-specific list, a number of occurrences within that locus-specific list of identical nucleotide sequence data representing a unique STR, and identifying each unique STR for which the number of occurrences of identical nucleotide sequence data within the locus-specific list exceeds an abundance threshold as an allele of the corresponding locus for the sample. | 2020-04-30 |
20200135298 | SYSTEMS AND METHODS FOR GROUPING AND COLLAPSING SEQUENCING READS - Disclosed herein are systems and methods for collapsing sequencing reads and identifying similar sequencing reads. In one example, a method includes generating a plurality of first identifier subsequences from a first identifier sequence of each nucleotide sequencing read and generating a first signature for the nucleotide sequencing read by applying hashing to the plurality of first identifier subsequences. The method may include assigning the nucleotide sequencing read to a first particular bin of a first data structure based on the first signature and determining a nucleotide sequence for each first particular bin of the first data structure with one or more nucleotide sequencing reads assigned. | 2020-04-30 |
20200135299 | PEPTIDE LIBRARY CONSTRUCTING METHOD - An improved peptide library preparation method is described for constructing complete virtual peptide libraries such as a complete virtual tripeptide library, tetrapeptide library, pentapeptide library, hexapeptide library, heptapeptide library, or a complete octapeptide library, etc. The method includes constructing an expression vector for the expression of cyclic peptides. Each cyclic peptide displays an array of peptides of different sizes and sequences, and the number of cyclic peptides needed for constructing a complete virtual peptide library can be dramatically reduced compared with conventional chemical peptide synthesis. Furthermore, the cyclic peptide libraries can be readily reproduced by the expression and purification of the cyclic peptides using the constructed gene libraries. The improved peptide library preparation method can particularly be used, for example, to construct a complete virtual tetrapeptide library, a complete virtual pentapeptide library, a complete virtual hexapeptide library, a complete virtual heptapeptide library, and so on. The improved peptide library preparation method can also be used, for example, to construct a partial pentapeptide library, a partial hexapeptide library, a partial heptapeptide library, and so on. Other related methods and the related expression vectors are also described. | 2020-04-30 |
20200135300 | APPLYING LOW COVERAGE WHOLE GENOME SEQUENCING FOR INTELLIGENT GENOMIC ROUTING - Techniques for next generation sequencing (NGS), and more particularly, to techniques for applying low coverage whole genome sequencing (lcWGS) in genome wide association studies (GWAS). One aspect includes performing a lcWGS of a biological sample from a subject to obtain a set of reads, determining an inference of a phenotype from the set of reads, obtaining self-reported data from the subject, executing a first query on eligibility criteria for a plurality of genomic routes to obtain a set of genomic routes that satisfy the first query, executing a second query on routing criteria for the set of genomic routes to obtain a subset of ranked genomic routes that satisfy the second query, and selecting one or more genomic routes from the subset of ranked genomic routes based on the ranking of each of the one or more genomic routes. | 2020-04-30 |
20200135301 | SYSTEMS AND METHODS FOR ALIGNING SEQUENCES TO GRAPH REFERENCES - Various embodiments of the disclosure relate to systems and methods for aligning a sequence read to a graph reference. In one embodiment, the method comprises selecting a first node from a graph reference, the graph reference comprising a plurality of nodes connected by a plurality of directed edges, at least one node of the plurality of nodes having a nucleotide sequence. The method further comprises traversing the graph reference according to a depth-first search, and comparing a sequence read to nucleotide sequences generated from the traversal of the graph reference. The traversal of the graph is then modified in response to a determination that each and every node associated with a given nucleotide sequence was previously evaluated. | 2020-04-30 |
20200135302 | SYSTEMS AND METHODS FOR IDENTIFYING CANCER TREATMENTS FROM NORMALIZED BIOMARKER SCORES - Techniques for determining therapy scores for at least two of an anti-PD1 therapy, an anti-CTLA4 therapy, an IL-2 therapy, an IFN alpha therapy, an anti-cancer vaccine therapy, an anti-angiogenic therapy, and an anti-CD20 therapy. The techniques include determining, using sequencing data for the subject and information indicating distribution of biomarker values across one or more reference populations, a first set of normalized biomarker scores for a first set of biomarkers associated with a first therapy; and a second set of normalized biomarker scores for a second set of biomarkers associated with a second therapy; providing the first set of normalized biomarker scores as input to a statistical model to obtain a first therapy score for the first therapy; and providing the second set of normalized biomarker scores as input to the statistical model to obtain a second therapy score for the second therapy. | 2020-04-30 |
20200135303 | USER INTERFACE, SYSTEM, AND METHOD FOR COHORT ANALYSIS - A system and method that receive a distance matrix for multiple patients and a patient of interest, assign a radial distance value between the patient of interest and the other patients based on the distance matrix value for each of the multiple patients, generate an angular distance value between the multiple patients based at least in part on a measure of similarity between each patient, and minimize a cost function based at least in part on the angular distance value between each patient and each other patient. Minimizing the cost function may include calculating a patient contribution to the cost function for a plurality of angular distance values and selecting the angular distance value with the smallest patient contribution. The processor also may be configured to generate and display a radar plot based on the assigned radial distance value and generated angular distance value of each patient. | 2020-04-30 |
20200135304 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM - There is provided an information processing device that can improve motivation of providers of biological information for healthcare, the information processing device including: a data acquisition unit configured to acquire information related to biological information, the biological information being provided by a provider; and a determination unit configured to determine a reward value provided to the provider as feedback for provision of the biological information, based on the information related to biological information. | 2020-04-30 |
20200135305 | PROCEDURE FOR UNIFIED GLOBAL REGISTRY AND UNIVERSAL IDENTIFICATION OF PRODUCTS OF BIOLOGICAL ORIGIN FOR MEDICINAL PURPOSES - A procedure for the unified global registry and universal identification of products of biological origin for medicinal purposes comprises:
| 2020-04-30 |
20200135306 | Pseudonymous crypto-based systems and methods for patient data - Systems and methods of a cipher-based system for tracking a patient within a clinical pharmacy workflow, the system includes providing a meshed network having patient devices that communicate patient data with aggregators. The patient devices and aggregators located within the space form a meshed network, the aggregators communicate data to a computer in communication with a cloud-based network. A patient device with a mobile application wirelessly communicates with an internet system in communication with the cloud-based network. Receiving by the computer, information about the user patient device entering the meshed network by wireless tags positioned within the space. Information is obtained by the patient devices during a recognition process by wirelessly transmitting messages between the wireless tags to aggregators, and then wirelessly transmitting information from the aggregators to the computer, the computer communicates with the cloud-based network, the cloud-based network communicates with healthcare administrator systems via jointly defined API interface. | 2020-04-30 |
20200135307 | METHOD AND APPARATUS FOR A TREATMENT TIMELINE USER INTERFACE - A system and method for generating and displaying a treatment timeline user interface includes maintaining a database of patient information. The patient information includes patient identification information and exam data associated with patients. In response to a request for information pertaining to a particular patient, a treatment timeline user interface is generated and displayed based on information associated with the particular patient stored in the database. Input is received requesting modification of the displayed treatment timeline and, in response, the treatment timeline is updated and displayed. | 2020-04-30 |
20200135308 | EXPRESSION OF CLINICAL LOGIC WITH POSITIVE AND NEGATIVE EXPLAINABILITY - Methods, systems, and computer-storage media are provided for facilitating the management of population health. A parallel processing architecture receives patient population health data from healthcare facilities along with any updated data. A high-level clinical logic is executed against the data to identify, among other things, patients in the population who qualify for health intervention programs. Using this information, healthcare facilities can implement management programs to help care for these patients | 2020-04-30 |
20200135309 | CLINICAL DASHBOARD FOR MEDICAL DEVICE - A clinical dashboard device, system, method for providing clinical data for clinical dashboard display on a device is disclosed. The system includes a server for providing clinical dashboard data, which may include data from one or more defibrillators, and further includes a clinical dashboard device. The clinical dashboard device includes a processor, a communication module configured for enabling communication between the processor and the server for receiving the clinical dashboard data from the server, and a clinical dashboard client. The clinical dashboard client includes a clinical dashboard data manager module including an instance of a clinical dashboard data manager service that provides managed clinical dashboard data between one or more clinical dashboard applications and the server. The instance of the clinical dashboard data manager service further provides managed display of managed clinical dashboard data on the display of the clinical dashboard device. The processor is configured to execute the instance. | 2020-04-30 |
20200135310 | SYSTEM AND METHOD FOR MANUFACTURING CUSTOM NAILS - A system and method for manufacturing custom fit artificial nails includes a 3D surface scanning module and a 3D printing module and use thereof. A central processing module is connected to the 3D surface scanning module and the 3D printing module and performs: operating the 3D surface scanning module to obtain an image of a user's hands/feet; processing the image to create an input 3D model of nails of the user; generating an output 3D model corresponding to artificial nails matching dimensions of the user's nails according to the 3D input model; operating the 3D printing module to manufacture artificial nails according to the output 3D model; and generating medical data by correlating the identified features of the user's nails with known medical conditions, in order to diagnose a medical condition of the user which is known to exhibit the identified features as a symptom. Alternatively, or additionally, medicinal ingredient may be included in the artificial nail to treat the medical condition of the user. Embedded devices, sensors or an RFID chip may be integrated into the artificial nail. | 2020-04-30 |
20200135311 | MEDICAL DEVICES AND RELATED EVENT PATTERN PRESENTATION METHODS - Medical devices and related patient management systems and methods are provided. A method of presenting information pertaining to operation of a medical device involves obtaining historical glucose measurement data for a patient from a database, identifying, based on the historical glucose measurement data, a first plurality of event patterns within respective ones of a plurality of monitoring periods, determining a respective value for a confidence metric for each respective event pattern of the first plurality of event patterns based at least in part on a detection criterion associated with the respective event pattern, a respective subset of the historical glucose measurement data corresponding to the respective monitoring period of the plurality of monitoring periods associated with the respective event pattern, and an interval estimation metric associated with the historical glucose measurement data, and providing one or more graphical indicia influenced by the confidence metric. | 2020-04-30 |
20200135312 | METHODS FOR OPTIMIZING MANAGED HEALTHCARE ADMINISTRATION AND ACHIEVING OBJECTIVE QUALITY STANDARDS - Healthcare is administered to members/enrollees of a healthcare plan according to objective quality standards. A patient population of eligible members/enrollees is identified and for each member/enrollee, medical information is aggregated via a web-based compilation of medical data from multiple sources that is continuously updated so as to provide an accurate, up-to-date and readily accessible compilation of a member/enrollee past diagnoses, healthcare history, medical procedures, medications and the like. Such member/enrollees are continuously tracked, on an individual basis, and monitored to ensure healthcare is delivered for a variety of specific medical conditions pursuant to objective health program quality criteria. | 2020-04-30 |
20200135313 | TREATMENT ANALYSIS SYSTEMS AND METHODS - A dental treatment planning system includes an input form to receive one or more dental patient inputs; and an engine adapted to receive the dental patient data from the input form and validating the dental patient data in a predetermined sequence | 2020-04-30 |
20200135314 | PERSONALIZED MEDICATION MANAGEMENT AND ALERT SYSTEM AND METHOD - A personalized medication management and alert method and system is provided. The method includes, creating a user profile based at least upon received user genetic information, storing the user profile in memory on a computer, updating the user profile based on received user personal information, the received personal information including any medications currently used by the user, comparing, by a processor, information in the updated user profile to information in a medication-interaction database, and based on the comparing, determining whether there exists at least one interaction between the information in the updated user profile and the information in the medication-interaction database. | 2020-04-30 |
20200135315 | Unsaleable Pharmaceutical Item Handling and Disposal Systems, Methods, and Devices - In some embodiments, a device may include at least one camera, a display device, and a processor coupled to the camera and the display device. The camera may be configured to capture first optical data of a unsaleable pharmaceutical item and second optical data of an operator. The processor may be configured to provide a graphical interface to the display device. The graphical interface may include information to guide the operator through a process of sorting unsaleable pharmaceutical items for disposal, the graphical interface including the first optical data and the second optical data. | 2020-04-30 |
20200135316 | ENHANCED PRESCRIPTION MANAGEMENT SYSTEM - A system for providing to a patient a user experience for securely submitting a prescription to a pharmacy is provided. The system receives a notification of a prescription prescribed by a prescriber for the patient. The system displays to the patient information on drug options relating to the prescribed drug. The system then receives from the patient a selection of a drug option. The system displays to the patient pharmacy options relating to the selected drug option. Each pharmacy option identifies a pharmacy. The system receives from the patient a selection of a pharmacy option. The system then directs that an indication of the prescription be sent to the pharmacy identified by the selected pharmacy option so that that pharmacy can dispense the prescription. | 2020-04-30 |
20200135317 | METHODS AND SYSTEMS FOR PATIENT CONTROL OF AN ELECTRONIC PRESCRIPTION - Methods and systems are provided for an online system for patient control of a medical prescription. In one example, a method is provided for transmitting a prescription to a first pharmacy in response to a patient selecting the first pharmacy for a first fill of the prescription. The method may further include transmitting the prescription to a second pharmacy in response to the patient selecting the second pharmacy, different than the first pharmacy, for a second fill of the prescription. | 2020-04-30 |
20200135318 | METHODS OF REGULATING ACCESS TO QSYMIA TO MITIGATE POTENTIAL DRUG-ASSOCIATED RISKS - The present invention provides methods for dispensing or distributing a drug, particularly a potentially teratogenic drug, to a patient while minimizing the occurrence of an adverse side effect. In particular, the present invention provides methods for dispensing or distributing a drug containing topiramate to a patient in need of weight loss to minimize the occurrence of potential birth defects associated with the drug. Methods for providing training to prescribers on the potential risks associated with particular drugs are also disclosed. | 2020-04-30 |
20200135319 | AUTOMATED DETECTION OF A PHYSICAL BEHAVIOR EVENT AND CORRESPONDING ADJUSTMENT OF A MEDICATION DISPENSING SYSTEM - An automated medication dispensing system provides for triggering a medication administration message when an inferred event is detected for which a medication administration message is to be sent. The event might be the start, the beginning, or an anticipation of a start, of an eating event, detected by an event detection module from gestures of a user from a set of sensor readings. The message can be a signal to medication dispensing apparatus, and/or a reminder message to the user, an ancillary message to a caregiver, health professional, or others. The medication administration message might comprise a signal to an input of an insulin management system or an input of a meal-aware artificial pancreas. The events might also include a drinking event, a smoking event, a personal hygiene event, and/or a medication related event. | 2020-04-30 |
20200135320 | AUTOMATED DETECTION OF A PHYSICAL BEHAVIOR EVENT AND CORRESPONDING ADJUSTMENT OF A MEDICATION DISPENSING SYSTEM BASED ON HISTORICAL EVENTS - An automated medication dispensing system provides for triggering a medication administration message when an inferred event is detected for which a medication administration message is to be sent. The event might be the start, the beginning, or an anticipation of a start, of an eating event, detected by an event detection module from gestures of a user from a set of sensor readings. The message can be a signal to medication dispensing apparatus, and/or a reminder message to the user, an ancillary message to a caregiver, health professional, or others. The medication administration message might comprise a signal to an input of an insulin management system or an input of a meal-aware artificial pancreas. The events might also include a drinking event, a smoking event, a personal hygiene event, and/or a medication related event. | 2020-04-30 |
20200135321 | SYSTEM, METHODS, & DEVICE FOR MANAGING A PRODUCT - A dose management system receives a product characteristic for a product. The dose management system then associates the product with user, along with a smart monitor device that includes an embedded token. When the user thereafter installs a dose management application on a user device of the user, the dose management system receives the token, thereby authenticating the user device. The dose management system can additionally authenticate the user based on user access credentials of the user. Once the user device is authenticated, the user device, smart monitor device, and the dose management system remain in contact with each other, thereby permitting management of the product. For example, the dose management system can initiate a product refill, automatically or based on a user's request. The dose management system can also discern whether the user likely missed a dose (or not) and provide intelligent reminders to the user regarding the product. | 2020-04-30 |
20200135322 | AUTOMATIC PICKING MACHINE FOR FILLING A TRANSPORT CONTAINER - An automatic picking machine for pharmaceutical drug packages includes at least one storage rack, at least one storage and retrieval machine, a control apparatus for controlling the storage and retrieval machine, and a filling apparatus for successively filling each of a plurality of transport containers with a group of pharmaceutical drug packages corresponding to one order, wherein the filling apparatus includes a plurality of collection containers, first transport apparatuses, each having a transport channel for conveying the pharmaceutical drug packages towards the respective collection container, and a receiving apparatus for receiving a transport container to be filled at a filling location of the filing apparatus. | 2020-04-30 |
20200135323 | INFUSION SYSTEM CONSUMABLES AND RELATED CALIBRATION METHODS - Infusion systems including infusion devices and consumables and related operating methods are provided. An exemplary consumable component includes a housing, a reservoir contained within the housing, a pumping mechanism for dispensing a fluid from the reservoir, and a readable element associated with the housing. The readable element maintains calibration data characterizing a relationship between delivery of the fluid and actuation of the pumping mechanism. | 2020-04-30 |
20200135324 | METHOD AND SYSTEM FOR INTERPRETING NEURAL INTERPLAY INVOLVING PROPRIOCEPTIVE ADAPTATION DURING A DUAL TASK PARADIGM - Collision avoidance and postural stability adjustment may provide an effective dual task paradigm to interpret the effect of proprioceptive adaptation on balance control. However, conventionally tasks are physical tasks performed under supervision in specific set up environments. Implementations of the present disclosure provide methods and systems for interpreting neural interplay involving proprioceptive adaptation in a lower limb during a dual task paradigm. The disclosed method provides a better interpreting of the neuronal mechanisms underlying adaptation and learning of skilled motor movement and to determine the relationship of lower limb proprioceptive sense and postural stability by simulating integration of a Single Limb Stance (SLS) functionality test for postural stability and a single limb collision avoidance task, in an adaptive Virtual Reality (VR) environment provided to a subject. | 2020-04-30 |
20200135325 | ANALYZING EFFECT OF A SECONDARY COGNITIVE LOAD TASK ON A PRIMARY EXECUTIVE TASK - This disclosure relates to analyzing effect of a secondary cognitive load task on a primary executive task. Human random sequence generation is a marker to study cognitive functions and inability to generate random sequences (RS) can reveal underlying impairments. Traditionally, ‘call out’ or ‘write down’ procedures are used to obtain human generated numbers, wherein short term memory and number of previously generated entities visible to a subject plays a major role. Also precise trial-wise or response-wise analysis may not be possible. In the present disclosure, the human generated random numbers are digitized into RS and a cognitive load (CL) inducing task is imposed on the executive task. The CL demanding task disrupts randomization performance. Deviation from randomness, load index based on gaze data and deviation from pupillometry data of healthy subjects are provided as indicators of an interference effect imposed by the CL and thereby indicative of underlying impairments. | 2020-04-30 |
20200135326 | METHOD OF FACILITATING IMAGING STUDY INTERPRETATIONS BETWEEN HEALTHCARE FACILITIES AND PHYSICIANS - A method for facilitating selection, by a healthcare facility, of a physician from a plurality of physicians to provide interpretation of an imaging study, is provided. The method includes receiving physician credentials from at least one physician, receiving, from the healthcare facility, an imaging study and a request for interpretation of the imaging study, the request including physician selection criteria, providing access to the imaging study and the request for interpretation to qualified physicians whose credentials match the physician selection criteria, receiving an interpretation of the imaging study from those qualified physicians that have accepted the request for interpretation, comparing the physician credentials to the physician selection criteria, and selecting an imaging study interpretation from the received imaging study interpretations based on the comparing of the physician credentials to the physician selection criteria. | 2020-04-30 |
20200135327 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM - An information processing apparatus includes an acquisition unit, a search unit, and a display control unit. The acquisition unit acquires a comparison image generated using a first examination image and a second examination image which are acquired by imaging a subject at different times/dates from each other. The search unit searches for clinical practice infonnation about a clinical practice perfonned on the subject during a period defined by a first examination date, at which the first examination image is acquired, and a second examination date, at which the second examination image is acquired. The display control unit displays the comparison image and the searched clinical practice information on a display unit. | 2020-04-30 |
20200135328 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - Provided are an information processing apparatus, an information processing method, and a program capable of accumulating appropriate relearning data. An information processing apparatus includes an input unit that inputs input data to a learned model acquired in advance through machine learning using learning data, an acquisition unit that acquires output data output from the learned model through the input using the input unit, a reception unit that receives correction performed by a user for the output data acquired by the acquisition unit, and a storage controller that performs control for storing, as relearning data of the learned model, the input data and the output data that reflects the correction received by the reception unit in a storage unit in a case where a value indicating a correction amount acquired by performing the correction for the output data is equal to or greater than a threshold value. | 2020-04-30 |
20200135329 | METHOD AND SYSTEM FOR TISSUE DENSITY ANALYSIS - The present disclosure provides a tissue density analysis system. The system includes an acquisition module configured to obtain image data and tissue density distribution data; a display module configured to display the obtained tissue density distribution data in one or more charts; a processing module configured to adjust the tissue density distribution data displayed in the one or more charts; and a storage module configured to store the image data, the tissue density distribution data and an instruction. | 2020-04-30 |
20200135330 | MEDICAL IMAGE PROCESSING APPARATUS, MEDICAL IMAGE PROCESSING METHOD, AND COMPUTING DEVICE - A medical image processing apparatus for allocating at least two medical imaging processes to a plurality of assignable processing resources is provided. The plurality of assignable processing resources is allocated by the medical image processing apparatus based on resource information of the plurality of assignable processing resources. The medical image processing apparatus includes circuitry configured to acquire medical image processing content, from medical equipment, to be processed according to the at least two medical imaging processes prior to display on a display device connected to a surgical operating room network. The circuitry is configured to acquire the resource information of the plurality of assignable processing resources, and allocate each of the at least two medical imaging processes to a different one of the plurality of assignable processing resources based on the resource information of the plurality processing resources and the medical image processing content. | 2020-04-30 |
20200135331 | MEDICATION MONITORING AND IDENTIFICATION - A medical monitoring system extracts characteristic information for one or more medications from an image of the one or more medications on an uncontrolled background, the image being taken by a client device associated with a user of the medical monitoring system. The medical monitoring system determines prescription information associated with a medication, of the one or more medications, using the extracted characteristic information and a medication database, the medication database containing mappings between prescription information and characteristic information for a plurality of medications. The medical monitoring system provides a portion of the prescription information to the client device. | 2020-04-30 |
20200135332 | SYSTEM AND METHOD OF UTILIZING DATA OF MEDICAL SYSTEMS - The present disclosure provides a system that may receive first sensor data associated with first multiple measurements of multiple components of multiple medical systems; may receive filter information from first user input; may search, based at least on the filter information, the first sensor data to determine report data; may provide, via a graphical user interface, the report data to a user; may receive second user input that indicates one or more issues associated with at least one of the multiple medical systems; may determine one or more thresholds based at least on the second user input; may receive second sensor data associated with second multiple measurements of the multiple components of the multiple medical systems; and may determine, based at least on the one or more thresholds, at least one of the one or more issues associated with at least one of the multiple medical systems. | 2020-04-30 |
20200135333 | System For Communication Of Data - A system for communication of data is provided. The system includes a medical device. A data consuming device is positioned at a first network layer. An edge communication device is positioned at a second network layer. The edge communication device is in communication with the medical device to receive data from the medical device. The edge communication device has a profile. The profile defines a data format for the data and a communication path for transmitting the data between the network layers. A gateway device is configured to route the data from the edge communication device to the data consuming device via the communication path. The edge communication device is also configured to modify the data format to correspond to the data consuming device and to format the data according to the data format. | 2020-04-30 |
20200135334 | DEVICES AND METHODS FOR REMOTELY MANAGING CHRONIC MEDICAL CONDITIONS - A method for managing or remotely monitoring chronic medical conditions (e.g., chronic respiratory conditions) of a plurality of patients includes, at one or more processors, receiving a plurality of bodily metrics associated with each of the plurality of patients over one or more remote communication links (e.g., an automated phone system), characterizing the severity of the medical condition for each patient based on the plurality of bodily metrics associated with the patient, and transmitting a programmed alert to a medical care provider for at last one patient having a medical condition characterized as having a threshold level of severity. | 2020-04-30 |
20200135335 | SYSTEMS AND METHODS FOR INTEGRATING A GLOBALLY SECURE COMMUNICATIONS NETWORK WITH STORED MEDICAL DIAGNOSTICS - The present disclosure relates to systems and methods for integrating a globally secure communications network with stored medical diagnostics. In one example, the system may include at least one memory storing instructions and at least one processor configured to execute the instructions. The instructions may include instructions to receive a request for a medical diagnostic; verify that the request originates from a location within an approved area; verify credentials of a user that originated the request; send the medical diagnostic to the user; receive, from the user, an identification of a recipient separate from the user; verify that the recipient originates from a location within an approved area; verify credentials of a user that originated the request; and in response to receiving the identification, send the medical diagnostic to the recipient. | 2020-04-30 |
20200135336 | METHOD AND APPARATUS FOR DETERMINING AND PRESENTING INFORMATION REGARDING MEDICAL CONDITION LIKELIHOOD - A method and system for determining a composite post-test likelihood that a patient has a medical condition using an iterative Bayesian analysis of test information and test results for multiple tests. Multiple medical conditions can be assessed and results viewed simultaneously, including assessments performed based on hypothetical tests and test results. Such assessment may help guide a clinician to selecting tests and/or treatment that are particularly relevant to a patient's medical condition diagnosis. | 2020-04-30 |
20200135337 | INDIVIDUAL AND COHORT PHARMACOLOGICAL PHENOTYPE PREDICTION PLATFORM - For patients who exhibit or may exhibit primary or comorbid disease, pharmacological phenotypes may be predicted through the collection of panomic data over a period of time. A machine learning engine may generate a statistical model based on training data from training patients to predict pharmacological phenotypes, including drug response and dosing, drug adverse events, disease and comorbid disease risk, drug-gene, drug-drug, and polypharmacy interactions. Then the model may be applied to data for new patients to predict their pharmacological phenotypes, and enable decision making in clinical and research contexts, including drug selection and dosage, changes in drug regimens, polypharmacy optimization, monitoring, etc., to benefit from additional predictive power, resulting in adverse event and substance abuse avoidance, improved drug response, better patient outcomes, lower treatment costs, public health benefits, and increases in the effectiveness of research in pharmacology and other biomedical fields. | 2020-04-30 |
20200135338 | SYSTEMS AND METHODS FOR EMBOLISM PREDICTION USING EMBOLUS SOURCE AND DESTINATION PROBABILITIES - Systems and methods are disclosed for determining a patient risk assessment or treatment plan based on emboli dislodgement and destination. One method includes receiving a patient-specific anatomic model generated from patient-specific imaging of at least a portion of a patient's vasculature; determining or receiving a location of interest in the patient-specific anatomic model of the patient's vasculature; using a computing processor for calculating blood flow through the patient-specific anatomic model to determine blood flow characteristics through at least the portion of the patient's vasculature of the patient-specific anatomic model downstream from the location of interest; and using a computing processor for particle tracking through the simulated blood flow to determine a destination probability of an embolus originating from the location of interest in the patient-specific anatomic model, based on the determined blood flow characteristics. | 2020-04-30 |
20200135339 | SYSTEMS AND METHODS FOR EXECUTING PATHWAYS FOR HEALTHCARE - The present application is directed to systems and methods providing a pathway configurable and executable via a pathway engine on a device. A device may establish a pathway configured via a pathway engine to execute on the device to monitor data points of a user and to generate actions based on monitoring of the data points. A monitor of the pathway engine may monitor data points of the user received by the device. The monitor may compare each value of the data points to the expected value and the predetermined threshold specified for the trigger condition. The pathway, based on the comparison, may determine that the trigger condition has been triggered. The pathway, responsive to the triggering of the trigger condition, may initiate an alert to identify the trigger condition and execution of the action specified by the pathway. | 2020-04-30 |