17th week of 2010 patent applcation highlights part 60 |
Patent application number | Title | Published |
20100106905 | DISK ARRAY CONTROL DEVICE AND STORAGE DEVICE - According to one embodiment, a disk array control device manages a plurality of drives as a single logical drive. The disk array control device includes a first register configured to store a to-he-accessed drive number which is designated by a host, and a control module. The control module is configured to receive a command from the host, determine whether the received command is a predetermined command which is used for maintenance of each of the drives, and execute, in a case where the received command is the predetermined command, a pass-through process of sending the received command to the drive which is designated by the to-be-accessed drive number in the first register. | 2010-04-29 |
20100106906 | METHOD AND SYSTEM FOR PROTECTING AGAINST MULTIPLE FAILURES IN A RAID SYSTEM - Embodiments of methods of protecting RAID systems from multiple failures and such protected RAID systems are disclosed. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks. Furthermore, one or more levels of RAID may be implemented within one or more of the data banks comprising the distributed RAID system. | 2010-04-29 |
20100106907 | Computer-readable medium storing data management program, computer-readable medium storing storage diagnosis program, and multinode storage system - A computer-readable medium storing a data management program makes a computer manage data redundantly stored in storage devices having storage areas split into slices for data management. The data management program realizes the following functions in the computer. A first function receives irregularity information indicating that each of one or more of the storage devices may be possibly faulty, and stores the irregularity information in a storage; and a second function determines, by reference to the irregularity information, whether or not a first storage device containing a slice to be accessed is possibly faulty, on receipt of access information indicating occurrence of a request to access the slice. When yes is determined, the second function instructs an external device to recover data stored in the slice, where the external device controls a second storage device storing redundant data identical to the data stored in the slice. | 2010-04-29 |
20100106908 | COMPUTER SYSTEM, STORAGE AREA ALLOCATION METHOD, AND MANAGEMENT COMPUTER - Disclosed is a system and method for preventing deterioration in I/O performance of a computer resulted from a use of the same physical disk among different logical volumes. A volume management server | 2010-04-29 |
20100106909 | SYSTEMS AND METHODS OF MEDIA MANAGEMENT, SUCH AS MANAGEMENT OF MEDIA TO AND FROM A MEDIA STORAGE LIBRARY, INCLUDING REMOVABLE MEDIA - A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed. | 2010-04-29 |
20100106910 | CACHE MEMORY AND METHOD OF CONTROLLING THE SAME - It is an object of the present invention to reduce output of a WAIT signal to maintain data consistency to effectively process subsequent memory access when there is no subsequent memory access in case of miss hit in a cache memory having a multi-stage pipeline structure. A cache memory according to the present invention performs update processing of a tag memory and a data memory and decides whether or not there is a subsequent memory access upon decision by a hit decision unit that an input address is a miss hit. Upon decision that there is a subsequent memory access, a controller outputs a WAIT signal to generate a pipeline stall for the pipeline processing of the processor to the processor, while the controller does not output a WAIT signal upon decision that there is no subsequent memory access. | 2010-04-29 |
20100106911 | METHODS AND SYSTEMS FOR COMMUNICATION BETWEEN STORAGE CONTROLLERS - Methods and systems for communication between two storage controllers. A first storage controller specifies a special frame indicator in a frame of a protocol that is also used by a first storage controller to send a storage command to a storage device. The first storage controller transmits the frame to a second storage controller such that the frame comprises data in a payload field of the frame. | 2010-04-29 |
20100106912 | COHERENCE PROTOCOL WITH DYNAMIC PRIVATIZATION - Embodiments of the present invention provide a system that maintains coherence between cache lines in a computer system by using dynamic privatization. During operation, the system starts by receiving a request for a read-only copy of a cache line from a processor. The system then determines if the processor has privately requested the cache line a predetermined number of times. If so, the system provides a copy of the cache line to the processor in an exclusive state. Otherwise, the system provides a copy of the cache line to the processor in a shared state. | 2010-04-29 |
20100106913 | Cache memory control apparatus and cache memory control method - According to an aspect of the embodiment, an FP includes a plurality of entries which holds requests to be processed, and each of the plurality of entries includes a requested flag indicating that data transfer is once requested. An FP-TOQ holds information indicating an entry holding the oldest request. A data transfer request prevention determination circuit checks the requested flag of a request to be processed and the FP-TOQ, and when a transfer request of data as a target of the request to be processed has already been issued and the entry holding the request to be processed is not the entry indicated by the FP-TOQ, transmits a signal which prevents the transfer request of the data to a data transfer request control circuit. Even when a cache miss occurs in a primary cache RAM, the data transfer request control circuit does not issue a data transfer request when the signal which prevents the transfer request is received. | 2010-04-29 |
20100106914 | CONSISTENCY MODELS IN A DISTRIBUTED STORE - Systems and methods that designate read/write consistency models based on requirements of a distributed store to increase performance or scale. Such sever loads can be determined via a plurality of mechanisms, including delays in responses by the primary node; setting predetermined threshold limits that if exceeded results in contacting secondary nodes; polling services of the distributed cache periodically and maintaining track of loads on the servers, and the like. The weak or scalable read can occur when read requests are directed to a secondary node, and upon over loading of the primary node. | 2010-04-29 |
20100106915 | POLL BASED CACHE EVENT NOTIFICATIONS IN A DISTRIBUTED CACHE - Systems and methods that supply poll based notification system in a distributed cache, for tracking changes to cache items. Local caches on the client can employ the notification system to keep the local objects in sync with the backend cache service; and can further dynamically adjust the “scope” of notifications required based on the number and distribution of keys in the local cache. The server can maintain the changes in an efficient fashion (in blocks) and returns the changes to clients that perform the appropriate filtering. Notifications can be associated with a session and/or an application. | 2010-04-29 |
20100106916 | Data Cache Block Zero Implementation - In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents. | 2010-04-29 |
20100106917 | METHOD AND SYSTEM FOR IMPROVING SERIAL PORT MEMORY COMMUNICATION LATENCY AND RELIABILITY - A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval. | 2010-04-29 |
20100106918 | VARIABLE-LENGTH CODING DATA TRANSFER INTERFACE - A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination. | 2010-04-29 |
20100106919 | LOGICAL UNIT OPERATION - The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address. | 2010-04-29 |
20100106920 | DATA LOCATION OBFUSCATION - Programs running on an open architecture, such as a personal computer, are vulnerable to inspection and modification. This is a concern as the program may include or provide access to valuable information. As a defense, the actual location of data can be hidden throughout execution of the program by way of periodic location reordering and pointer scrambling, among other things. These techniques serve to complicate static data flow analysis and dynamic data tracking thereby at least deterring program tampering. | 2010-04-29 |
20100106921 | SYSTEM AND METHOD FOR CONCURRENTLY MANAGING MEMORY ACCESS REQUESTS - A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss. | 2010-04-29 |
20100106922 | Interleaver Memory Allocation Method and Apparatus - A first communication device estimates upstream channel conditions for an upstream channel and determines an upstream memory requirement for a first buffer at a second communication device and a first buffer at the first communication device based on the upstream channel conditions. A downstream memory requirement is received from the second communication device for a second buffer at the first communication device and a second buffer at the second communication device based on downstream channel conditions estimated at the second communication device for a downstream channel. The first communication device determines whether the sum of the upstream and downstream memory requirements exceeds an available amount of memory for implementing the first and second buffers at the first communication device and revises at least one of the memory requirements if the sum of the upstream and downstream memory requirements is different than the available amount of memory. | 2010-04-29 |
20100106923 | SYSTEM AND METHOD FOR POLICY-BASED DATA ARCHIVING TRIGGERED BY USER ACTIVITY - A system and method for providing cost-effective policy-based data archiving triggered by end-user activity. When an end-user makes a request to store data, the storage device communicates with a storage policy rules software engine. The storage policy rules software engine compares the user activity to a set of previously established rules and then invokes a translation software engine to translate the intended actions into instructions specific for a particular data archiving product in order for that application to archive data as intended. | 2010-04-29 |
20100106924 | COMPUTER SYSTEM FOR PERFORMING REMOTE COPY USING JOURNAL - An object of the invention is to maintain conformability of data stored in a secondary storage system although a time stamp is not granted to write data received by a primary storage system. At least one of one or more computers includes a storage managing unit. The storage managing unit issues an ID next to an immediately previously issued ID to one or more primary storage systems (PDKCs) at regular or irregular intervals. Upon receiving a write command from one of the one or more computers, each PDKC prepares a journal (JNL) including a replica (journal data) of write data and the newest ID from the storage managing unit, and transmits the journal to a secondary storage system (SDKC). The SDKC stores a received JNL and reflects up to a particular JNL of non-reflected JNLs in a secondary volume. The particular JNL has an ID older by one than the oldest ID of the newest arrival completion IDs in one or more SDKCs. | 2010-04-29 |
20100106925 | PROGRAMMING AND CONFIGURATION IN A HEATING, VENTILATION AND AIR CONDITIONING NETWORK - The disclosure provides an a system and method of backing up operating control data about a device connected to a controller in a network. In an embodiment, the network includes a storage system for the data about the device is in the controller; a first subsystem for determining that the data should be transferred to the device; and a second subsystem for transferring the data to the device for use. | 2010-04-29 |
20100106926 | SECOND FAILURE DATA CAPTURE PROBLEM DETERMINATION USING USER SELECTIVE MEMORY PROTECTION TO TRACE APPLICATION FAILURES - The present invention discloses a solution for second failure data capture problem determination using user selective memory protection to trace application failures. In the solution, one or more data structures can be selected by a user to be allocated a unique address space from a debug heap. The address space called a region can be assigned permissions for which executable code can access the contents. Permissions can include full access (e.g., read/write), read, and no access which can “lock” the region against specific types of access. The user can permit known trusted executable code to access allocated regions. Untrusted executable code attempting to access “locked” regions will result in an application failure event (e.g., segmentation fault). The failure can be used to determine the point of memory corruption through inspection of the stack trace. | 2010-04-29 |
20100106927 | SID MANAGEMENT FOR ACCESS TO ENCRYPTED DRIVES - A method and a system for unlocking a storage device that has become locked or cannot be unlocked are disclosed. A hint is generated from a key by removing bits and adding bits. A position of removed bits, a position of added bits, the number of removed bits and the number of added bits are stored and known securely. When the key cannot unlock a storage device corresponding to the key, the position of removed bits, the position of added bits, the number of removed bits (N) and the number of added bits are retrieved. Then, the added bits are removed in the hint. Each possible N bits are placed in the hint at the position of removed bits to generate 2 | 2010-04-29 |
20100106928 | STORAGE DEVICE, STORAGE SYSTEM, AND UNLOCK PROCESSING METHOD - According to one embodiment, a storage device manages a user data area by dividing the area into a plurality of division data areas. The storage device includes a storage module, an access authority setting module, a lock processor, a command receiver, and an unlock processor. The storage module includes the division data areas. The access authority setting module sets access authority with respect to each division data area for each user. The lock processor disables access to the storage module from a host device that reads data from and writes data to the storage module. The command receiver receives from the host device an unlock command including a basic area storing basic unlock information and an expansion area storing additional unlock information. The unlock processor unlocks each division data area, to which access is restricted for each user, based on the basic unlock information and the additional unlock information. | 2010-04-29 |
20100106929 | Method and Apparatus for Providing Secure Register Access - The method and accompanying apparatus provides secure register access. In one example, as part of a secure boot process, data is written into a managed secure register (MSR) register and access policy data is written into programmable MSR policy registers. During run-time, the MSR register securely stores data in compliance with the programmable register access policy data. Access policy is enforced during run-time based on the programmable register access policy data. | 2010-04-29 |
20100106930 | OPPORTUNISTIC PAGE LARGIFICATION - Page tables in the last level of a hierarchical page table system are scanned for candidate page tables. Candidate page tables are converted to large pages, having a page table entry in a level before the last level of the hierarchical page table system adjusted to be associated with the newly created large page. Upon receiving a notification that a large page is to be converted into a page table, a new page table is created. Each entry in the new page table is associated with a small segment of memory in the large page and an entry in a page table one level before the last level in a hierarchical page table system is adjusted to be associated with the new page table. | 2010-04-29 |
20100106931 | AVOIDING INFORMATION DISCLOSURE WHEN DIRECT MAPPING NON-PAGE ALIGNED BUFFERS - A method and a processing device are provided for mapping a non-page aligned memory buffer to an address space of a process. A beginning portion of a non-page aligned memory buffer and an ending portion of the non-page aligned memory buffer may be copied from respective original memory pages to new memory pages. Unused portions of the new memory pages may be initialized to zeros, ones, or other values. A safe buffer may be created, which resides in the new memory pages and all original memory pages of the non-page aligned memory buffer, except for the original memory pages including either the beginning portion or the ending portion of the non-page aligned buffer. The safe buffer may then be mapped to an address space of a process while avoiding unintended information disclosure. | 2010-04-29 |
20100106932 | CONTROL APPARATUS - A control apparatus, control method and computer readable article of manufacture for controlling data. The control apparatus includes a data storage unit; a plurality of entry storage units, and a plurality of registration units. The data storage unit stores data. Each of the entry storage units stores an entry for registering a pointer to data. If each of the registration units receives an instruction for registering data, then each registration unit (i) searches the entry storage units for an entry storage unit having an empty entry, (ii) registers a pointer to the data to be registered in the retrieved entry storage unit and (iii) stores the data to be registered and identification information of the retrieved entry storage unit in the data storage unit in such a manner that the data to be registered and the identification information is associated with each other. | 2010-04-29 |
20100106933 | METHOD AND SYSTEM FOR MANAGING STORAGE CAPACITY IN A STORAGE NETWORK - A system for managing configuration of a storage network having multiple storage resources is disclosed. The system uses a storage management policy to set parameters for detecting storage resource problems in the storage network. The system monitors the storage resources in the storage network based on the storage management policy. Based on the monitoring, the system detects limited storage resource conditions, and identifies one or more potential solutions to the condition. After identifying potential solutions, the system simulates effects on the storage resources of implementing individual solutions. Based on the simulations, the system then implements one or more selected solutions. These solutions may be selected automatically or by a user. | 2010-04-29 |
20100106934 | PARTITION MANAGEMENT IN A PARTITIONED, SCALABLE, AND AVAILABLE STRUCTURED STORAGE - Partition management for a scalable, structured storage system is provided. The storage system provides storage represented by one or more tables, each of which includes rows that represent data entities. A table is partitioned into a number of partitions, each partition including a contiguous range of rows. The partitions are served by table servers and managed by a table master. Load distribution information for the table servers and partitions is tracked, and the table master determines to split and/or merge partitions based on the load distribution information. | 2010-04-29 |
20100106935 | Pretranslating Input/Output Buffers In Environments With Multiple Page Sizes - Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports more than one memory page size, identifying pretranslation page frame numbers for the buffer in dependence upon the pretranslation page size, pretranslating the pretranslation page frame numbers to physical page numbers, and storing the physical page numbers in association with the pretranslation page size. Typical embodiments also include accessing the buffer, including translating a virtual memory address in the buffer to a physical memory address in dependence upon the physical page numbers and the pretranslation page size and accessing the physical memory of the buffer at the physical memory address. | 2010-04-29 |
20100106936 | Calculator and TLB control method - A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. In the micro TLB, a TLB virtual address [63:13] and a TLB absolute address [46:13] are registered in a correlated manner. With such configuration, when registering an address translation pair in the micro TLB, the calculator chops the address translation pair to a page size of a first size or a fourth size to register it in the micro TLB. Upon receiving an address translation request, the calculator searches for an address corresponding to the page size of the first size or the fourth size registered in the micro TLB, so that address comparison conditions can be reduced, enabling to improve a processing performance. | 2010-04-29 |
20100106937 | INDEXING A TRANSLATION LOOKASIDE BUFFER (TLB) - A processor is to comprise a central processing unit (CPU), an address generation unit (AGU), an index generation unit and a translation look-aside buffer (TLB). The CPU of the processor is to generate signal to retrieve instructions from a memory. The AGU is to generate a final linear address and an initial linear address after receiving at least three input source values. An index generation unit coupled to the AGU is to generate a set-index value using the bits of at least the three input source values or the bits of the initial linear address even before the bits of the initial linear address are adjusted for carry. A TLB is to generate a physical address using the final linear address and an entry indexed by the set-index value. | 2010-04-29 |
20100106938 | Arithmetic processing unit and entry control method - An arithmetic processing apparatus includes: a plurality of TLBs holding as entries a portion of a conversion table for conversion of virtual addresses into physical addresses that has been placed in a main memory unit; an entry registration determining unit that, while registering an entry output from the main memory unit in any one of a plurality of TLBs, determines whether an entry has already been registered in an area of a TLB as registration destination; and a relocation control unit that, when the entry registration determining unit determines that an entry has already been registered in the area of the TLB as registration destination, evicts the entry that has already been registered and registers evicted entry in other TLB. | 2010-04-29 |
20100106939 | TRANSFERRING DATA FROM INTEGER TO VECTOR REGISTERS - A method for transferring data from a general purpose register to a vector register, the method including splatting a byte of data directly from a general purpose register (GPR) to a vector register (VR) by means of vector permute instructions, and splatting another byte of data from the GPR to the VR and vectorially combining the data in the VR. | 2010-04-29 |
20100106940 | Processing Unit With Operand Vector Multiplexer Sequence Control - Operand vector multiplexer sequence control is used in a vector-based execution unit to control the shuffling of data elements in operand vectors used by a sequence of vector instructions processed by the vector-based execution unit. A swizzle sequence instruction is defined in an instruction set for the vector-based execution unit and is used to selectively apply a sequence of vector data element shuffle orders to one or more operand vectors to be used by the associated sequence of vector instructions. As a result, when a common sequence of data element shuffle orders is used frequently for a sequence of vector instructions, a single swizzle sequence instruction may be used to select the desired sequence of custom data element ordering for each of the vector instructions in the sequence. | 2010-04-29 |
20100106941 | MULTI-CORE STREAM PROCESSING SYSTEM, AND SCHEDULING METHOD FOR THE SAME - In a multi-core stream processing system and scheduling method of the same, a scheduler is coupled to a number (N) of stream processing units and a number (N+1) of stream fetching units, where N≧2. When the scheduler receives a stream element from a P | 2010-04-29 |
20100106942 | RISC Microprocessor Architecture Implementing Multiple Typed Register Sets - Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types. The register file is responsive to the one or more fields in at least one of the instructions to retrieve an operand of the at least one of the instructions from, or to store a result of the at least one of the instructions into, one of the registers of the first register set or the second register set as defined by the one or more fields of the at least one of the instructions. | 2010-04-29 |
20100106943 | Processing device - It is possible to realize fetch of instructs constituting a loop by using a simple configuration without fixing a loop start point. Provided is a processing method performed by a processing device including: a instruction buffer; a instruction decoder; a pointer arranged to correspond to the instruction buffer and indicating a connection relationship between one instruction buffer from which a instruction stream is read out and other instruction buffer containing the next instruction stream to be read out, according to an identifier of other instruction buffer; a start point storage unit containing an identifier of the instruction buffer containing a instruction stream serving as a start point of repetition when performing a instruction fetch of such a predetermined instruction that processing of a instruction stream is repeated in a loop. When a instruction stream is read out from the instruction buffer and the predetermined instruction is detected from the instruction stream, the identifier stored in the start point storage unit is set as a pointer of the identifier of the next instruction buffer from which a instruction is to be read out. | 2010-04-29 |
20100106944 | Data processing apparatus and method for performing rearrangement operations - A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques. | 2010-04-29 |
20100106945 | Instruction processing apparatus - The present invention includes a decode section for simultaneously holding a plurality of instructions in one thread at a time and for decoding the held instructions; an execution pipeline capable of simultaneously executing each processing represented by the respective instructions belonging to different threads and decoded by the decode section; a reservation station for receiving the instructions decoded by the decode section and holding the instructions, if the decoded instructions are of sync attribute, until executable conditions are ready and thereafter dispatching the decoded instructions to the execution pipeline; a pre-decode section for confirming by a simple decoding, prior to decoding by the decode section, whether or not the instructions are of sync attribute; and an instruction buffer for suspending issuance to the decode section and holding the instructions subsequent to an instruction of sync attribute. | 2010-04-29 |
20100106946 | METHOD FOR PROCESSING STREAM DATA AND SYSTEM THEREOF - The present invention provides a method for processing stream data and a system thereof capable of implementing general data processing including recursive processing with low latency. In the system for processing stream data, a single operator graph is prepared from operator trees of a plurality of queries, an execution order of the operators is determined so that execution of a streaming operator is progressed in one way from an input to an output, the ignition time of an external ignition operator that inputs data from the outside of the system and an internal ignition operator that time-limitedly generates data is monitored, and an operator execution control unit repeats processing that completes the processing in the operator graph at the time according to the determined operator execution order, assuming the operator of the earliest ignition time as a start point. | 2010-04-29 |
20100106947 | PROCESSOR EXPLOITING TRIVIAL ARITHMETIC OPERATIONS - The present application relates to the field of processors and in particular to the carrying out of arithmetic operations. Many of the computations performed by processors consist of a large number of simple operations. As a result, a multiplication operation may take a significant number of clock cycles to complete. The present application provides a processor having a trivial operand register, which is used in the carrying out of arithmetic or storage operations for data values stored in a data store. | 2010-04-29 |
20100106948 | MANAGING AN OUT-OF-ORDER ASYNCHRONOUS HETEROGENEOUS REMOTE DIRECT MEMORY ACCESS (RDMA) MESSAGE QUEUE - A system and method operable to manage a message queue is provided. This management may involve out-of-order asynchronous heterogeneous remote direct memory access (RDMA) to the message queue. This system includes a pair of processing devices, a primary processing device and an additional processing device, a memory in storage location and a data bus coupled to the processing devices. The processing devices cooperate to process queue data within a shared message queue wherein when an individual processing device successfully accesses queue data the queue data is locked for the exclusive use of the processing device. When the processing device acquires the queue data, the queue data is locked and the queue data acquired by the acquiring processing device includes the queue data for both the primary processing device and additional processing device such that the processing device has all queue data necessary to process the data and return processed queue data. | 2010-04-29 |
20100106949 | SOURCE CODE PROCESSING METHOD, SYSTEM AND PROGRAM - A method, system, and computer readable article of manufacture to enable parallel execution of a divided source code in a multiprocessor system. The method includes the steps of: inputting an original source code by an input device into the computing apparatus; finding a critical path in the original source code by a critical path cut module; cutting the critical path in the original source code into a plurality of process block groups by the critical path cut module; and dividing the plurality of process block groups among a plurality of processors in the multiprocessor system by a CPU assignment code generation module to produce the divided source code. The system includes an input device; a critical path cut module; and a CPU assignment code generation unit to produce the divided source code. The computer readable article of manufacture includes instructions to implement the method. | 2010-04-29 |
20100106950 | METHOD AND SYSTEM FOR LOADING STATUS CONTROL OF DLL - Apparatus and methods are provided for controlling the loading status of DLLs. Specifically, a streaming program compiler is provided. The compiler includes operation modules for calling DLLs during streaming program execution; association table generating units for generating association tables according to user-defined rules, where the association table includes entries indicating (i) stream branches of the streaming program and (ii) an operation module corresponding to the stream branches; and a trigger generating unit for generating a trigger based on user-defined rules, where the trigger generating unit (i) determines which conditions for loading and unloading DLLs fit the streaming program, (ii) matches these conditions to a particular stream branch to identify a matched stream branch, and (iii) sends out triggering signals indicating the matched stream branch. This invention also provides a corresponding method and controller. | 2010-04-29 |
20100106951 | COMPUTER SYSTEM AND METHOD FOR TRANSMITTING SYSTEM INFORMATION OF CONFIGURATION MANAGEMENT PROGRAM THEREOF - A computer system and a method for a configuration management program transmitting a system information are provided. The method includes the following steps. A first memory is provided, wherein the first memory records at least one system information. An interrupt is enabled from the configuration management program when the configuration management program needs a system information of the computer system, wherein the interrupt has a corresponding command information. An interrupt processing program processes the interrupt so as to perform a corresponding configuration setting operation according to the command information or to return the corresponding system information in the first memory to the configuration management program. | 2010-04-29 |
20100106952 | APPARATUS, METHOD AND PROGRAM PRODUCT FOR INITIATING COMPUTER SYSTEM OPERATION - A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS. | 2010-04-29 |
20100106953 | METHOD FOR PATCHING ROM BOOT CODE - The present invention relates to a method for patching a boot code stored on ROM comprising the steps of (a) storing at least one patching command for said boot code in a PROM; (b) loading said boot code from said ROM to a memory; (c) reading said at least one patching command from said PROM; (d) patching at least one command of said boot code residing in said memory with said at least one patching command from said PROM; and (e) executing the patched boot code. | 2010-04-29 |
20100106954 | Multi-Layer Content Protecting Microcontroller - The present invention relates to a microcontroller designed for protection of intellectual digital content. The microcontroller includes a secure CPU, a real-time cipher, and a user programmable multi-layer access control system for internal memory realized by programmable nonvolatile memory. Programmable nonvolatile memory allows in-system and in-application programming for the end user. The programmable nonvolatile memory is mainly used for program code and operating parameter storage. The multiple-layer access control is an integral part of the CPU, providing confidentiality protection to embedded digital content by controlling reading, writing, and/or execution of a code segment according to a set of user-programmed parameters. The cipher incorporates a set of cryptographic rules for data encryption and decryption with row and column manipulation for data storage. All cryptographic operations are executed in parallel with CPU run time without incurring additional latency and delay for system operation. | 2010-04-29 |
20100106955 | METHODS AND SYSTEMS FOR RECOVERING A COMPUTER SYSTEM USING A STORAGE AREA NETWORK - Methods and systems for recovering and booting a computer system using a SAN. The computer system comprises a local storage device. A request for writing data to a boot volume on the local storage device is received. The data is written to the local storage device, as well as to the SAN at substantially the same time as receiving the request. The computer system can then be booted using the data written to the SAN. | 2010-04-29 |
20100106956 | BIOS SWITCHING SYSTEM AND A METHOD THEREOF - A BIOS switching system applicable to a computer system is provided. The BIOS switching system includes an input module and a memory module, and the memory module further includes a plurality of BIOS's, an option recording block, and a boot-up management block. The input module produces a switching signal according to a user input. The boot-up management block determines whether replacing an execution option block's data in the option recording block is necessary or not based on the switching signal. The data of the execution option block is identification data of one of the BIOS's. The boot-up management block executes the BIOS indicated by the data of the execution option block while the computer system boots up. | 2010-04-29 |
20100106957 | PROGRAMMING AND CONFIGURATION IN A HEATING, VENTILATION AND AIR CONDITIONING NETWORK - Various embodiments of systems and methods of creating a memory of an HVAC device. A bootloader code is stored into a first protected memory of the HVAC device. A device designator is stored into a second protected memory of the HVAC device. A control serial number is stored into a third protected memory of the HVAC device. A control part number is stored into a fourth protected memory of the HVAC device. An application data is stored into a separate application memory of the HVAC device. | 2010-04-29 |
20100106958 | SECURITY AUDIT SYSTEM AND METHOD - Methods, apparatuses and a system are provided for performing a security audit of, for example, a multi-function device. | 2010-04-29 |
20100106959 | Triple and quadruple churning security for 1G and 10G PON - A data encryption-decryption method for enhancing the confidentiality of data transmitted between two, first and second communication network entities including the steps of: at the first network entity, performing a quadruple-churning operation on a byte N to obtain an encrypted byte N, the quadruple-churning operation including: performing a first churning operation to obtain a first churned output; bit-wise XORing the first churned output with two values to obtain a first XOR result; bit-swapping the first XOR result; performing a second churning and XORing stages to obtain a second XOR result; performing a third churning and XORing stages to obtain a third XOR result; bit swapping the third XOR result; and performing a fourth churning operation on the third bit-swapped XOR result to obtain encrypted byte N; and transmitting the encrypted byte N to the second network entity. | 2010-04-29 |
20100106960 | CONTENT TRANSMITTING DEVICE, CONTENT RECEIVING DEVICE AND CONTENT TRANSMITTING METHOD - Before content transmission, the content transmitting device and the content receiving device mutually authenticate each other to verify that the other device respects copyright and rightfully handles content, and then content is encrypted by shared key data and transmitted. It is arranged that in an authentication process, a time from transmission of an authentication request or a time from transmission of an authentication response until arrival of receipt acknowledgement data is measured and only when a measured time is less than a fixed upper-limit value, content is transmitted. | 2010-04-29 |
20100106961 | METHODS AND APPARATUS FOR ENABLING UNIFIED (INTERNET PROTOCOL VERSION) IPV6/IPV4 ROUTING SERVICES OVER IPv4-ONLY INTERFACES - Some embodiments of the present invention provide an apparatus that provides routing services between a red network and a black network. The apparatus includes a red router within the red network, a black router within the black network, and an IP encryptor having a red side IPv4-only interface and a black side interface, with the red side interface operatively coupled to the red router and the black side interface operatively coupled to the black network. The apparatus is configured to provide unified IPv6/IPv4 OSPFv3 routing over IPv4-only interfaces using cross-layer extensions. | 2010-04-29 |
20100106962 | METHOD, APPARATUS, AND SYSTEM FOR MANAGING MULTIMEDIA SERVICES - A method for managing multimedia services includes the following steps: A session receiver sends Real-time Transport Control Protocol (RTCP) packets to a distribution aggregation point, and each distribution aggregation point is connected to at least one session receiver and aggregates the received RTCP packets into the first aggregated packet whose format is different from the format of the RTCP packets; the distribution aggregation point sends the first aggregated packet to a distribution source over a transmission network, and the distribution source aggregates the aggregated packet into a second aggregated packet, and then processes the second aggregated packet and transmits it to a session sender, or transmits the second aggregated packet to the session sender directly. The present invention implements feedback of mass packets from the session receiver to the sender in large-scale multicast applications, and avoids the unicast bottleneck. | 2010-04-29 |
20100106963 | System and method for secure remote computer task automation - A system includes a third party authority in communication with a client computer and a target computer. The third party authority is configured to receive a request including authentication information and an access request from the client computer. The third party authority is configured to authenticate the client computer based on the authentication information and to process the access request to grant the client computer access to the target computer to perform a task on the target computer, the access request including the task. The third party authority is further configured to send an access token to the client computer to access the target computer to perform the task, to receive the access token from the target computer for validation, to validate the received access token based on the request for the target computer to process the task, and to grant the target computer permission to process the task upon validation. | 2010-04-29 |
20100106964 | AUTHENTICATION TERMINAL, AUTHENTICATION SERVER, AND AUTHENTICATION SYSTEM - In registration, a feature array x[i] obtained by client is basis-transformed into array X[i], transformed with a transformation filter array K[i] into a template array T[i] to be registered in the client. In authentication, the feature array y[i] is basis-transformed into an array Y[i] after inversely sorting and applied to filter K by computation V[i]=Y[i]K[i]. The server obtains array e[i]=Enc (T[i]), and the client obtains e′[i]=Enc (Σ | 2010-04-29 |
20100106965 | DELIVERY OF MULTIPLE THIRD-PARTY SERVICES TO NETWORKED DEVICES - Systems and methods for authenticating a media device or other information handling system so as to be able to receive content from one or more media content providers. Authenticating the device includes determining what authentication information the media content providers require for access and then to generating and providing to the media device an authentication token that includes the required information. In some embodiments this may be accomplished by a service center, which removes the need for additional authentication steps to be performed by the media device or the media content providers. In addition, the service center may also determine when changes are made to the authentication information and may then ensure that the authentication token is changed or updated to reflect these changes. This ensures that the media device is at least partially immune to changes to authentication. | 2010-04-29 |
20100106966 | Method and System for Registering and Verifying the Identity of Wireless Networks and Devices - The present invention discloses a method for registering a wireless network's identity using a central server. The central server receives a request for registration of an identifier of a wireless network. If the identifier has not been previously registered, the central server creates an association between the identifier and the wireless network, which is stored in a database maintained by the central server. The present invention also discloses a method for verifying a wireless network's identity by a wireless device. A central server comprising a database is provided, which registers an identifier of the wireless network. The central server receives from a wireless device an authentication request of the identifier. The authentication request arrives through a gateway of the wireless network. The central server then authenticates the identifier. | 2010-04-29 |
20100106967 | METHOD AND ARRANGEMENT FOR PROVISIONING AND MANAGING A DEVICE - A system, method, and owner node for securely changing a mobile device from an old owner to a new owner, or from an old operator network to a new operator network. The old owner initiates the change of owner or operator. The old owner or operator then commands the mobile device to change a currently active first key to a second key. The second key is then transferred to the new owner or operator. The new owner or operator then commands the mobile device to change the second key to a third key for use between the mobile device and the new owner or operator. Upon completion of the change, the new owner or operator does not know the first key in use before the change, and the old owner does not know the third key in use after the change. | 2010-04-29 |
20100106968 | CONTENT DISTRIBUTION STORAGE SYSTEM, METHOD FOR OBTAINING CONTENT, NODE DEVICE, AND COMPUTER READABLE MEDIUM - A content distribution storage system includes: a first transmission unit configured to transmit a special content including certificate revocation list information indicating a list of at least an invalid electronic certificate to a first node group; a second transmission unit configured to transmit identification information for identifying the special content to a second node group; and a first node device. The first node device includes: a certificate obtaining unit configured to obtain the electronic certificate; an identification information obtaining unit configured, based on the obtained electronic certificate, to obtain the identification information of the special content comprising the certificate revocation list information corresponding to the obtained electronic certificate obtained; and a special content obtaining unit configured to obtain the special content from at least one node device of the first node group which stores the special content associated with the obtained identification information. | 2010-04-29 |
20100106969 | DYNAMIC FOREIGN AGENT-HOME SECURITY ASSOCIATION ALLOCATION FOR IP MOBILITY SYSTEMS - The present invention utilizes the AAA infrastructure to dynamically allocate the various parameters needed to establish the security association between the Foreign Agent and the Home Agent. The present invention uses the AAA server as a central entity to dynamically generate and distribute the chosen security association parameters needed to support the Foreign Agent and Home Agent security association based on a request from the Foreign Agent. The AAA server can also dynamically assigns a unique SPI value to the Foreign Agent and Home Agent pairs. The various parameters that can be allocated in the present invention include a FA-HA shared secret key or a public/private key pair, an authentication algorithm and mode, a FA-HA secret key lifetime, and security parameter index or security index values. The present invention also can assist in making sure that the Foreign Agent and the Home Agent stay synchronized with respect to their security association. | 2010-04-29 |
20100106970 | DEVICE AUTHENTICATION - Authentication of two devices in communication with a third device is achieved where the first and second devices each possess a shared secret value. The authentication includes communication of authentication values from the first device to the second device using the third device. Similarly, there is communication of values from the second device to the first device using the third device. The third device retains the communicated values. The values are calculated to permit the third device to authenticate the first and second devices without the third device receiving the shared secret value. The authentication may be used to establish a communications channel between the first and the second devices. | 2010-04-29 |
20100106971 | METHOD AND COMMUNICATION SYSTEM FOR PROTECTING AN AUTHENTICATION CONNECTION - A method for protecting an authentication connection is described, comprising generating a first keying material by generating a first authentication connection, deriving from the generated first keying material a second keying material and utilizing the second keying material for protecting a second authentication connection. | 2010-04-29 |
20100106972 | SIGNALLING DELEGATION IN A MOVING NETWORK - In order to delegate location update signaling responsibility from a Mobile Node to a Mobile Router, the Mobile Router is provided with a second symmetric key generated by a Mobile Node using a first symmetric key shared between the Mobile Node and a Peer Node. The Mobile Router is additionally provided with a “certificate” authenticating the second symmetric key using the first symmetric key. In this way, the mobile router can sign location update related messages sent to the Peer Node with the second symmetric key, and can provide the Peer Node with the certificate in order to allow the Peer Node to authenticate the right of the Mobile Router to act on behalf of the Mobile Node. | 2010-04-29 |
20100106973 | Method and Device for Safeguarding of a Document with Inserted Signature image and Biometric Data in a Computer System - A method for safeguarding an electronic document includes inserting at least one digital signature image into the electronic document and generating a first check sum for the electronic document, with or without optionally-inserted biometric signature data, using a first hash function. A second check sum is then generated using a second hash function. The first check sum and the biometric data, if provided, are then symmetrically encrypted using a key that is the sum of the second check sum and a generated random value. The symmetrically-encrypted first check sum is attached to the document. The random value is then asymmetrically encrypted using a first public key of a first key pair and the asymmetrically-encrypted random value is added to the document. | 2010-04-29 |
20100106974 | System For And Method Of Writing And Reading Redundant Data - In accordance with an embodiment of the invention, a method of writing and reading redundant data is provided. Data is written by storing a copy of the data along with a timestamp and a signature at each of a set of storage devices. The data is read by retrieving the copy of the data, the timestamp and the signature from each of a plurality of the set of data storage devices. One of the copies of the data is selected to be provided to a requestor of the data. Each of the storage devices of the set is requested to certify the selected copy of the data. Provided that a proof of certification of the selected copy of the data is valid, the storage devices of the set are instructed to store the selected copy of the data along with a new timestamp. | 2010-04-29 |
20100106975 | SYSTEM AND METHOD FOR USER AUTHENTIFICATION USING NON-LANGUAGE WORDS - A system and method for user authentication include a user instructing component and a voice authentication component. The user instructing component generates an instruction for authenticating a voice of a user. The instruction includes a first instruction to recite one or more non-language words. The voice authentication component analyzes a sound signal which includes a response to the instruction. The voice authentication component can authenticate the voice of the user using the response to the instruction including a response to the first instruction to recite the one or more non-language words. | 2010-04-29 |
20100106976 | REPRESENTATION AND VERIFICATION OF DATA FOR SAFE COMPUTING ENVIRONMENTS AND SYSTEMS - Techniques for representation and verification of data are disclosed. The techniques are especially useful for representation and verification of the integrity of data (integrity verification) in safe computing environments and/or systems (e.g., Trusted Computing (TC) systems and/or environments). Multiple independent representative values can be determined independently and possibly in parallel for respective portions of the data. The independent representative values can, for example, be hash values determined at the same time for respective distinct portions of the data. The integrity of the data can be determined based on the multiple hash values by, for example, processing them to determine a single hash value that can serve as an integrity value. By effectively dividing the data into multiple portions in multiple processing streams and processing them in parallel to determine multiple hash values simultaneously, the time required for hashing the data can be reduced in comparison to conventional techniques that operate to determine a hash value for the data as a whole and in a single processing stream. As a result, the time required for integrity verification can be reduced, thereby allowing safe features to be extended to devices that may operate with relatively limited resources (e.g., mobile and/or embedded devices) as well as improving the general efficiency of device that are or will be using safety features (e.g., Trusted Computing (TC) device). | 2010-04-29 |
20100106977 | Method and Apparatus for Secure Software Platform Access - In an advantageous approach to securing type safety in software platform accesses made by software applications, this disclosure teaches the inclusion of cryptographically signed type information in software applications, for authentication and registration by a software platform. With this approach, a given software application is permitted to make platform accesses (e.g., data type instantiations, memory accesses, method invocations, etc.) only in conformance with the registered type information. | 2010-04-29 |
20100106978 | DISPLAY DEVICE AND DISPLAY CONTENT SHARING METHOD - This present disclosure provides a display device and a display content sharing method by employing the display device, the display device includes a storage unit and a display unit, the display content sharing method includes: obtaining an identity code of a wireless communication device; obtaining encrypted digital content of the identity code in the storage unit; decrypting the encrypted digital content of the identity code; displaying the decrypted content on the display unit. | 2010-04-29 |
20100106979 | Method, Apparatus, and Device for Providing Security Among a Calling Function and a Target Function - The device and accompanying apparatus and method provides security among a calling function, such as an any executable code, and at least one target function, such as any executable code that the calling function wishes to have execute. In one example, the device includes an engine operative to perform run-time verification of the signatures of secure interrupt handler code and at least one target function before allowing execution of the at least one target function. If both the secure interrupt handler code's signature and the at least one target function's signature are successfully verified, the at least one target function is allowed to execute. | 2010-04-29 |
20100106980 | SEARCHABLE ENCRYPTION FOR OUTSOURCING DATA ANALYTICS - A method for performing data analytics on outsourced data may include receiving, at a data analyst, cipher text representing data from a data owner such that the data remains hidden from the data analyst, generating a query token using a constant provided by the data analyst such that the constant remains hidden from the data owner, and analyzing the cipher text using the query token. | 2010-04-29 |
20100106981 | METHODS OF INVOKING VARIOUS FUNCTIONS OF A DIGITAL MEDIA PLAYER USING A SINGLE SWITCH OF THE DIGITAL MEDIA PLAYER - There is provided a method for charging a power source of a digital media player ( | 2010-04-29 |
20100106982 | ADAPTIVE COMPUTING RESPONSIVE TO ENVIRONMENTAL CONDITIONS - Methods, including service methods, articles of manufacture, systems, articles and programmable devices are provided for adapting the power consumption of a computational device in response to environmental conditions. Operating environmental condition data relevant to the generation of electric power is acquired from an operating environment feed and analyzed to determine a high electric power demand indication. If the analyzing determines a high electric power demand indication, then a computational device automatically reduces an amount of electric power consumption. | 2010-04-29 |
20100106983 | System and Method for Adjusting Information Handling System Over Current Protection - An AC-to-DC adapter provides power to information handling systems at different power levels based on the power rating of the information handling system. An adapter manager sets a first lower level at an over current protection circuit unless the information handling system sends identification information that indicates the information handling system is rated to accept a second higher power level, such as by sending a low signal pulse through a serial communication line. While the identification information is present and external power is applied to the adapter, the adapter manager sets a second higher level at an over current protection circuit to allow output of a second higher power level. | 2010-04-29 |
20100106984 | Shared interface device for power supply over ethernet (POE) and wireless network mdoule - The present invention relates to a shared interface device for Power Over Ethernet (POE) and a wireless network module, comprises a motherboard and an interface device used for inserting a POE card or a wireless interface card. The motherboard includes an Ethernet connection interface, a signal processing unit, a logical conversion unit and an external power supply interface. When signals and power from an external network are transmitted via the Ethernet connection interface to the interface device, these signals and power will be further transmitted into the POE card for filtering to capture the power. Then, the captured power will be fed back to the interface device and transmitted via the logical conversion unit to the motherboard for use; when the logical conversion unit receives the power from the external power supply interface, the power is provided for the wireless interface card and the motherboard for use. Such shared design will effectively reduce complexity of circuit layout in the motherboard and lower costs for enterprises in developing a set of independent modules separately. | 2010-04-29 |
20100106985 | SYSTEM AND METHOD FOR GLOBAL POWER MANAGEMENT IN A POWER OVER ETHERNET CHASSIS - A system and method for global power management in a power over Ethernet (PoE) chassis. Power supply status signals indicative of an operating condition of a plurality of power supplies are provided to a plurality of power sourcing equipment (PSE) controller chips in a plurality of blades of a chassis system. Pre-configured combination logic within each of the PSE controller chips converts an indicated operational state of the plurality of power supplies into a powering decision for each of the ports served by the PSE controller chip. Global power management is also effected through the use of scaling factors for the various blades to ensure that the lowest priority powered port (LPPP) in a first blade does not have a lower priority than the highest priority non-powered port (HPNPP) in a second blade. | 2010-04-29 |
20100106986 | DEVICE STATE CONTROL METHOD AND INFORMATION PROCESSING APPARATUS - A device state control method for use in an information processing apparatus that has a body, a device connectable to the body, a storage portion which stores information of a state of power supply to the device, the device state control method including: determining whether the information of state of power supply stored in the storage portion is information of power-supply OFF state or not, after instructing to shift the state of the power supply to the device from the power-supply OFF state into a power-supply. ON state; and starting the power supply to the device, when the information of power-supply OFF state is stored in the storage portion. | 2010-04-29 |
20100106987 | Method for pre-chassis power multi-slot blade identification and inventory - Systems and methods for a blade server to obtain the blade type and configuration of the chassis without requiring the blades to be fully powered. Using this method the user has the ability to acquire correct inventory and slot status of the chassis through the use of a low power auxiliary power state. The user is then able to apply the proper power budgeting and thermal algorithm requirements utilizing this information while minimizing the power consumption necessary to acquire such information. In addition, an intelligent search algorithm may be utilized to scan the blades for blade information thus further minimizing power consumption and decreasing the time needed to inventory the blades. | 2010-04-29 |
20100106988 | CONTROL METHOD WITH MANAGEMENT SERVER APPARATUS FOR STORAGE DEVICE AND AIR CONDITIONER AND STORAGE SYSTEM - To provide a system that can reduce the power consumption of an air conditioner and the power consumption of a storage device. A control method with a management server apparatus for a plurality of storage devices and an air conditioner includes calculating plural combinations of allocating the work amount to the plurality of storage devices, calculating the heating value of each storage device included in the plurality of storage devices for each of the plural combinations, calculating the quantity of heat conducted to the air conditioner, based on the heating value and positional information of the plurality of storage devices and the air conditioner, calculating the power consumption to cool the quantity of heat conducted to the air conditioner, selecting a combination included in the plural combinations based on the power consumption of the air conditioner, and issuing a move instruction of moving the data stored in a first storage device to a second storage device to the plurality of storage devices, based on the selected combination. | 2010-04-29 |
20100106989 | EMBEDDED SYSTEM WITH POWER-SAVING FUNCTIONS AND POWER-SAVING METHOD THEREOF - An embedded system with power-saving functions includes a central processing unit, a detecting and controlling unit, and a clock generating unit. The central processing unit is used for controlling operations of the embedded system. The detecting and controlling unit is used for detecting a designated operating status of the central processing unit to generate a control signal. The clock generating unit is coupled to the detecting and controlling unit and the central processing unit for setting a clock signal to the central processing unit according to the control signal. The designated operating status includes a usage or a loading status of the central processing unit. | 2010-04-29 |
20100106990 | POWER SAVINGS USING DYNAMIC STORAGE CLUSTER MEMBERSHIP - A system for controlling power usage in a storage cluster by dynamically controlling membership in the storage cluster is disclosed. The storage cluster includes multiple storage servers that provide access to one or more storage subsystems. The power management system uses a power management policy to set parameters for controlling membership in the storage cluster and monitors the storage cluster based on the policy. Based on the monitoring, the system detects when the number of storage servers in the storage cluster should be reduced or increased. To reduce the number, the system selects a storage server to deactivate and directs the selected storage server to migrate storage resources (e.g. data, metadata) associated with the server to a different storage server. The system then deactivates the selected storage server by directing it to transition to a low power mode. The system may increase the number of servers in the storage cluster by reversing these steps. | 2010-04-29 |
20100106991 | SLAVE CIRCUIT OF A LIN BUS AND METHOD FOR OPERATION - A slave circuit of a LIN bus and method for operating a slave circuit is provided. The slave circuit includes a receiver circuit that is connected to the bus in order to output bit sequences as a function of a bus voltage, an interface circuit for controlling a sleep mode and a normal mode, a detector circuit for evaluating the bus voltage which is connected to the bus, a timer device that is connected to an output of the detector circuit and to the interface circuit. Whereby, the detector circuit, the timer device, and the interface circuit are designed to detect an exceedance of a time threshold by a waveform of the bus voltage of the bus, and to continue a sleep mode in the event of an exceedance, wherein the time threshold is greater than the duration of a wake-up command. | 2010-04-29 |
20100106992 | METHOD AND APPARATUS FOR DETECTING AN IDLE MODE OF PROCESSING EQUIPMENT - Methods and apparatus for detecting an idle mode of processing equipment are provided herein. In some embodiments, an apparatus for monitoring a processing system may include a first system adapter for monitoring a first process chamber and determining a state thereof; and a first support adapter for communicating with the first system adapter and a first support system coupled to the first process chamber, the support adapter configured to communicate a readiness to operate the first support system at a low power mode to a controller of the support system in response to the state of the first process chamber being in an idle mode. | 2010-04-29 |
20100106993 | IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus and a control method thereof includes an image forming unit to form images, a main control unit to control operations of the image forming unit; a switching unit to selectively supply an operating voltage to the main control unit according to a level of the voltage control, a power mode selecting unit to convert an on state or an off state according to a user's operation, a first voltage determining unit to determine a level of the control voltage according to the state of the power mode selecting unit, and a second voltage determining unit to determine the level of the control voltage in parallel with the first voltage determining unit, according to the control signal output from the main control unit. | 2010-04-29 |
20100106994 | METHOD, APPARATUS, AND SYSTEM FOR ADAPTING POWER CONSUMPTION - A method, apparatus, and system are disclosed for adapting power consumption. A recording module records a usage record for each component within a computer at scheduled audit times. The usage record comprises a usage level, an application list, a time stamp, a network access point, a computation category, a time category, and a location category. A scenario module creates a plurality of usage scenarios. Each usage scenario comprises a unique combination of a specified computation category, a specified time category, and a specified location category. A profile module creates a power setting profile for each usage scenario. Each power setting profile specifies a target power status for each component of the computer. A scenario detection module detects a first usage scenario. An adjustment module sets a power status of each component to the first usage scenario target power status for the component. | 2010-04-29 |
20100106995 | MODE PROCESSING APPARATUS - A mode processing apparatus includes an MCU. The MCU executes a processing operation according to one of an audio reproducing mode and an audio recording mode, by using a battery as a power supply. Also, the MCU cyclically determines, in parallel with the processing operation according to an operating mode at a current time point, whether or not a terminal voltage Vbat of the battery is equal to or less than a threshold value. When a determination result indicating the terminal voltage Vbat≦the threshold value is continued, the MCU requests to stop the processing operation according to the operating mode at a current time point. Moreover, the MCU adjusts a length of a cycle in which the above-described determining process is performed to a length different depending on each operating mode. | 2010-04-29 |
20100106996 | SerDes double rate bitline with interlock to block precharge capture - An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened | 2010-04-29 |
20100106997 | METHOD AND APPARATUS FOR GENERATING EXPECT DATA FROM A CAPTURED BIT PATTERN, AND MEMORY DEVICE USING SAME - Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAMs. | 2010-04-29 |
20100106998 | Robust Generative Features - Disclosed are systems and methods for developing robust features for representing data. In embodiments, a linear generative model is computed using data. In embodiments, based upon a robustness measure, a set of features is selected. In embodiments, the set of features may be evaluated to gauge the capacity of the set of features to represent the data. Responsive to the set of features not satisfying an evaluation criterion or criteria, the set of features may be refined until the selected set of features complies with the evaluation criterion or criteria. | 2010-04-29 |
20100106999 | TECHNIQUES FOR DETERMINING LOCAL REPAIR PATHS USING CSPF - Techniques for computing a path for a local repair connection to be used to protect a connection traversing an original path from an ingress node to an egress node. The computed path originates at a node (start node) in the original path and terminates at another node (end node) in the original path that is downstream from the start node. A Constraint Shortest Path First (CSPF) algorithm may be used to compute the path. The computed path is such that it satisfies one or more constraints and does not traverse a path from a first node in the original path to a second node in the original path, wherein the first and second nodes are upstream from the start node in the original path and the second node is downstream from the first node in the original path. A local repair connection may then be signaled using the computed path. | 2010-04-29 |
20100107000 | Active Link Verification For Failover Operations In A Storage Network - Systems and methods for active link verification for failover operations in a storage network are disclosed. An exemplary method includes issuing a command from a first port of a storage device to a local network device in the storage network. The method also includes receiving a response to the command at the first port of the storage device from the local network device in the storage network. The storage device fails over to a second port of the storage device if no response is received at the first port of the storage device. | 2010-04-29 |
20100107001 | Activating Correct Ad-Splicer Profile In Ad-Splicer Redundancy Framework - In particular embodiments, method and system for detecting a failure of a primary ad-splicer, conveying a failure information for the failed primary ad-splicer to a redundant ad-splicer, dynamically forwarding one or more pre-spliced packets intended for the failed primary ad-splicer to the redundant ad-splicer, receiving one or more post-spliced packets from the redundant ad-splicer, and transmitting the post-spliced packets towards one or more target receivers are provided. | 2010-04-29 |
20100107002 | FAILURE NOTIFICATION IN RENDEZVOUS FEDERATION - Systems and methods that supply a global knowledge on what nodes are available in the system, via employing routing tokens that are analyzed by a centralized management component to infer status for the nodes. When nodes fail, the routing tokens associated therewith are acquired by neighboring nodes, and the global knowledge updated. Moreover, upon inferring a failed or down status for a node, a challenge can be sent to a node reporting such failure to verify actual failure(s). | 2010-04-29 |
20100107003 | Fast Data Recovery From HDD Failure - A storage system comprises a first storage device having a first plurality of hard disk drives and a first controller. The first controller stores data in the first plurality of hard disk drives by stripes. Each stripe includes M data and N parity data allocated to M+N hard disk drives of the first plurality of hard disk drives. A first hard disk drive includes data or parity data of both a first stripe of the stripes and a second stripe of the stripes, while a second hard disk drive includes data or parity data of only one of the first stripe or the second stripe. During data recovery involving failure of one of the first plurality of hard disk drives, the data in the failed hard disk drive is recovered for each stripe by calculation using data and parity data in other hard disk drives for each stripe. | 2010-04-29 |
20100107004 | METHOD FOR SELECTIVELY RETRIEVING COLUMN REDUNDANCY DATA IN MEMORY DEVICE - Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials. | 2010-04-29 |