17th week of 2022 patent applcation highlights part 59 |
Patent application number | Title | Published |
20220130771 | SUBSTRATE PROCESSING AND PACKAGING - An example ceramic panel has a first surface and a second surface. The ceramic panel has a bond finger well on the first surface of the ceramic panel a scribe line well on the second surface of the ceramic panel. The ceramic panel also has a scribe line along the scribe line well. | 2022-04-28 |
20220130772 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER - A semiconductor device, including: a semiconductor substrate formed of silicon carbide, components being formed at one surface of the semiconductor substrate; a periphery portion disposed at a pre-specified region of a periphery of the semiconductor substrate, the components not being formed at the periphery portion; and a plurality of trenches or portions of trenches formed at the periphery portion, an interior of each of the trenches being filled with a material with a different coefficient of thermal expansion from the silicon carbide. | 2022-04-28 |
20220130773 | ELECTRONIC DEVICE PACKAGES WITH INTERNAL MOISTURE BARRIERS - A method of packaging an RF transistor device includes attaching one or more electronic devices to a carrier substrate, applying an encapsulant over at least one of the one or more electronic devices, and providing a protective structure on the carrier substrate over the one or more electronic devices. A packaged RF transistor device includes a carrier substrate, one or more electronic devices attached to the carrier substrate, an encapsulant material over at least one of the one or more electronic devices and extending onto the carrier substrate, and a protective structure on the carrier substrate over the one or more electronic devices and the encapsulant material. | 2022-04-28 |
20220130774 | SECURE INTEGRATED-CIRCUIT SYSTEMS - A method of making a secure integrated-circuit system comprises providing a first integrated circuit in a first die having a first die size and providing a second integrated circuit in a second die. The second die size is smaller than the first die size. The second die is transfer printed onto the first die and connected to the first integrated circuit, forming a compound die. The compound die is packaged. The second integrated circuit is operable to monitor the operation of the first integrated circuit and provides a monitor signal responsive to the operation of the first integrated circuit. The first integrated circuit can be constructed in an insecure facility and the second integrated circuit can be constructed in a secure facility. | 2022-04-28 |
20220130775 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate; an integrated circuit region formed in the semiconductor substrate; and a seal ring arranged in the semiconductor substrate and around the integrated circuit region and configured to protect the integrated circuit region, wherein the seal ring has a wavy structure. | 2022-04-28 |
20220130776 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes an electronic component and a substrate. The electronic component has a first surface and a second surface. The substrate is connected to the first surface of the electronic component through an adhesive layer. The substrate includes a first antenna disposed over the second surface of the electronic components through the adhesive layer. | 2022-04-28 |
20220130777 | HIGH-FREQUENCY DEVICE - A high-frequency device includes a second substrate disposed opposite to a first substrate, a first electrode disposed on a side surface of the first substrate adjacent to the second substrate, a second electrode disposed on a side surface of the second substrate adjacent to the first substrate, a sealant disposed between the first substrate and the second substrate, and a dielectric layer sandwiched between the first substrate and the second substrate by the sealant. The dielectric layer includes a gas or vacuum. | 2022-04-28 |
20220130778 | COUPLING OF INTEGRATED CIRCUITS (ICS) THROUGH A PASSIVATION-DEFINED CONTACT PAD - Components may be placed on an active side of a wafer as part of wafer-level chip scale packaging (WLCSP) for use in electronic devices. Pad layouts for the components on an active side of a wafer may be passivation-defined by forming a conductive terminal over a first dielectric layer and a forming a passivating, second dielectric layer over the conductive terminal. Openings formed in the second dielectric layer define component contacts to the conductive terminal and circuitry on the wafer coupled to the conductive terminal. Trenches may be used between pairs of contact pads to further reduce issues resulting from short circuits and/or underfills. A conductive pad may further be deposited in the opening to form underbump metallization (UBM) for coupling the component to the wafer. | 2022-04-28 |
20220130779 | SEMICONDUCTOR DEVICE WITH SPACER OVER BONDING PAD - The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner. | 2022-04-28 |
20220130780 | METHODS FOR FORMING SUBSTRATE TERMINAL PADS, RELATED TERMINAL PADS AND SUBSTRATES AND ASSEMBLIES INCORPORATING SUCH TERMINAL PADS - An apparatus comprising a substrate having conductive traces and associated integral terminal pads on a surface thereof, the terminal pads having an irregular surface topography formed in a thickness of a single material of the conductive traces and integral terminal pads. Solder balls may be bonded to the terminal pads, and one or more microelectronic components operably coupled to conductive traces of the substrate on a side thereof opposite the terminal pads. Methods of fabricating terminal pads on a substrate, and electronic systems including substrates having such terminal pads are also disclosed. | 2022-04-28 |
20220130781 | CIRCUIT SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits. | 2022-04-28 |
20220130782 | SEMICONDUCTOR MEMORY DEVICE, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure. | 2022-04-28 |
20220130783 | SELECTIVE MICRO DEVICE TRANSFER TO RECEIVER SUBSTRATE - A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques. | 2022-04-28 |
20220130784 | METHOD FOR PREPARING INDIUM PILLAR SOLDER, CHIP SUBSTRATE AND CHIP - This disclosure discloses a method for preparing an indium pillar, a chip substrate and a chip. The method includes: applying a first photoresist layer on a substrate; applying a second photoresist layer on the first photoresist layer; covering a part of a surface of the second photoresist layer; underexposing the part of the second photoresist layer to obtain a processed second photoresist layer; developing and fixing the processed second photoresist layer to form an undercut structure; etching the first photoresist layer through the undercut structure to form an expose area; and depositing an indium material on the exposed area to form an indium pillar solder. | 2022-04-28 |
20220130785 | HYBRID DEVICE ASSEMBLIES AND METHOD OF FABRICATION - A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology. | 2022-04-28 |
20220130786 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern. | 2022-04-28 |
20220130787 | METHOD AND STRUCTURES FOR LOW TEMPERATURE DEVICE BONDING - Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials. | 2022-04-28 |
20220130788 | Multi-Chip Integrated Fan-Out Package - A method includes surrounding a die and a conductive pillar proximate the die with a molding material, where the die and the conductive pillar are disposed over a first side of a first redistribution structure, where a second side of the first redistribution structure opposing the first side is attached to a first carrier; bonding conductive pads disposed on a first surface of a pre-made second redistribution structure to the die and to the conductive pillar, where a second surface of the pre-made second redistribution structure opposing the first surface is attached to a second carrier; after bonding the conductive pads, removing the second carrier to expose conductive features of the pre-made second redistribution structure proximate the second surface; and forming conductive bumps over and electrically coupled to the conductive features of the pre-made second redistribution structure. | 2022-04-28 |
20220130789 | HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE - Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads. | 2022-04-28 |
20220130790 | THERMOSETTING SHEET, DICING DIE BONDING FILM, AND SEMICONDUCTOR APPARATUS - Provided in the present invention is a thermosetting sheet including a thermosetting resin, a thermoplastic resin, a volatile component, and conductive particles. The thermosetting sheet has an arithmetic average roughness Ra of 0.1 μm or more and 1.2 μm or less that is measured in a state before being cured. | 2022-04-28 |
20220130791 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating layer, wire contacts spaced apart from each other by the first insulating layer, and a bonding wire connected to the wire contacts. Each of the wire contacts includes a base part in the first insulating layer and a protrusion part protruding from inside to outside the first insulating layer. The protrusion parts of the wire contacts are in contact with the bonding wire. | 2022-04-28 |
20220130792 | SEMICONDUCTOR DEVICE - A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween. | 2022-04-28 |
20220130793 | SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIPS - A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip. | 2022-04-28 |
20220130794 | Aligning Bumps in Fan-Out Packaging Process - A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars. | 2022-04-28 |
20220130795 | REFLOW METHOD AND SYSTEM - A system for reflowing a semiconductor workpiece including a stage, a first vacuum module and a second vacuum module, and an energy source is provided. The stage includes a base and a protrusion connected to the base, the stage is movable along a height direction of the stage relative to the semiconductor workpiece, the protrusion operably holds and heats the semiconductor workpiece, and the protrusion includes a first portion and a second portion surrounded by and spatially separated from the first portion. The first vacuum module and the second vacuum module respectively coupled to the first portion and the second portion of the protrusion, and the first vacuum module and the second vacuum module are operable to respectively apply a pressure to the first portion and the second portion. The energy source is disposed over the stage to heat the semiconductor workpiece held by the protrusion of the stage. | 2022-04-28 |
20220130796 | MOUNTING APPARATUS - A mounting apparatus for mounting a semiconductor chip on a mounting body includes a stage on which the mounting body is placed, a mounting head provided to be movable up and down above the stage and pressing the semiconductor chip against the mounting body, and a film disposition mechanism which interposes a belt-like cover film between the mounting head and the stage, and the film disposition mechanism includes a film feeding part having a feeding reel around which at least the cover film has been wound, a film recovery part having a recovery reel also winding up at least the fed cover film, and one or more relay shafts provided in the course of a path of the cover film from the feeding reel to the recovery reel and by which the cover film is folded back in order to bend a moving direction of the cover film. | 2022-04-28 |
20220130797 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first lower stack on a substrate and including first lower semiconductor chips, a redistribution substrate on the first lower stack, a redistribution connector electrically connecting the substrate to the redistribution substrate, a first upper stack on the redistribution substrate and including first upper semiconductor chips, a first upper connector electrically connecting the redistribution substrate to the first upper stack, a second upper stack horizontally spaced apart from the first upper stack and including second upper semiconductor chips, and a second upper connector electrically connecting the redistribution substrate to the second upper stack may be provided. The redistribution connector may be on one side of the redistribution substrate. The first upper connector may be on one side of the first upper stack. The second upper connector may be on one side of the second upper stack. | 2022-04-28 |
20220130798 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided. | 2022-04-28 |
20220130799 | SEMICONDUCTOR PACKAGE - A semiconductor package comprising a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor body, an upper pad structure, and a first through-electrode penetrating the first semiconductor body and electrically connected to the upper pad structure, and the second semiconductor chip includes a second semiconductor body, a lower bonding pad, and an internal circuit structure including a circuit element, internal circuit wirings, and a connection pad pattern disposed on the same level as the lower bonding pad, the upper pad structure includes upper bonding pads and connection wirings, the upper bonding pads are disposed at positions corresponding to the lower bonding pad and the connection pad pattern, and the internal circuit structure is electrically connected to the first through-electrode through at least one of the upper bonding pads and the connection wirings. | 2022-04-28 |
20220130800 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a first substrate, a first semiconductor die, a second semiconductor die, and a multi-terminal multi-capacitor structure. The first substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are disposed on the first substrate. The multi-terminal multi-capacitor structure is disposed on the first substrate and includes a second substrate, an insulating layer, a first multi-terminal capacitor, and a second multi-terminal capacitor. The insulating layer is disposed over the second substrate. The first multi-terminal capacitor is disposed over the insulating layer and electrically coupled to the first semiconductor die through the wiring structure. The second multi-terminal capacitor is disposed over the insulating layer and electrically coupled to the second semiconductor die through the wiring structure, wherein the first multi-terminal capacitor and the second multi-terminal capacitor are electrically isolated from the second substrate. | 2022-04-28 |
20220130801 | SEMICONDUCTOR PACKAGE HAVING STACKED SEMICONDUCTOR CHIPS - Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads. | 2022-04-28 |
20220130802 | SEMICONDUCTOR PACKAGES - A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad. | 2022-04-28 |
20220130803 | FABRICATION AND USE OF THROUGH SILICON VIAS ON DOUBLE SIDED INTERCONNECT DEVICE - An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via. | 2022-04-28 |
20220130804 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus and a method of manufacturing the same, including a circuit board; and a plurality of pixels formed on the circuit board. At least one of a blue light emitting diode chip, a red light emitting diode part, and a green light emitting diode chip is disposed in each of the pixels, and the blue light emitting diode chip, the red light emitting diode part and the green light emitting diode chip are covered by a coupling structure. | 2022-04-28 |
20220130805 | LIGHT EMITTING MODULE HAVING A PLURALITY OF LIGHT EMITTING DIODE CHIPS CONNECTED IN SERIES-PARALLEL - A light emitting module includes a circuit board, and light emitting diode chips arranged in a plurality of regions on the circuit board. The light emitting diode chips are divided into a plurality of light emitting diode groups connected in series. The plurality of light emitting diode groups is connected in parallel to one another, and at least one of the light emitting diode chips in at least one of the plurality of light emitting diode groups is disposed in a region different from that of at least one other light emitting diode chip. | 2022-04-28 |
20220130806 | ELECTRONIC DEVICE - An electronic device including a driving circuit substrate, a plurality of light emitting units, and a first passivation layer is provided. The driving circuit substrate includes a plurality of active elements, the light emitting units are disposed on the driving circuit substrate, wherein each of the light emitting units is electrically connected to the corresponding active element. The first passivation layer covers the light emitting units. One of the active elements provides a first current to the corresponding light emitting element, such that the lighting efficiency of the light emitting units is ranged from 70% to 100%. | 2022-04-28 |
20220130807 | DISCONTINUOUS PATTERNED BONDS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS - Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein. | 2022-04-28 |
20220130808 | Electronic Power Module - Electronic power modules are disclosed. In one example, an electronic power module includes a first aluminum substrate, a second aluminum substrate, and a third aluminum substrate arranged in a common plane. The electronic power module includes first gap separating the first aluminum substrate from the second aluminum substrate. The electronic power module includes a second gap separating the second aluminum substrate from the third aluminum substrate. The electronic power module includes a first semiconductor switching component electrically coupled to the first aluminum substrate and the second aluminum substrate. The electronic power module includes a second semiconductor switching component electrically coupled to the second aluminum substrate and the third aluminum substrate. | 2022-04-28 |
20220130809 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - The semiconductor structure includes a die, a dielectric layer surrounding the die, a photoelectric device disposed adjacent to the die and surrounded by the dielectric layer, a first opening extending through the redistribution layer and configured to receive a light-conducting member, and a dielectric liner extending at least partially through the redistribution layer and surrounding the first opening. A method for forming a semiconductor structure includes forming a dielectric layer to surround a die; and disposing a photoelectric device surrounded by the dielectric layer; forming a redistribution layer over the die, the dielectric layer and the photoelectric device; forming a recess over the photoelectric device; disposing a dielectric material into the recess; removing a portion of the dielectric material to form a dielectric liner and a first opening over the photoelectric device. The dielectric liner extends at least partially through the redistribution layer and surrounding the first opening. | 2022-04-28 |
20220130810 | DISPLAY DEVICE - A display device according to an embodiment of the present disclosure includes a first pixel including a first sub-emission area and a second sub-emission area that are spaced from each other, and first light-emitting elements in the first and second sub-emission areas, the first light-emitting elements being configured to emit light having a first color; a light blocking pattern on the first pixel to cover an area between the first sub-emission area and the second sub-emission area and including a plurality of openings respectively corresponding to the first and second sub-emission areas; and a first color filter including a plurality of first color filter patterns disposed on the first and second sub-emission areas. | 2022-04-28 |
20220130811 | STACKED-CHIP PACKAGES - A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals. | 2022-04-28 |
20220130812 | IMAGE SENSOR PACKAGE AND MANUFACTURING METHOD THEREOF - An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip. | 2022-04-28 |
20220130813 | PACKAGE METHOD OF A MODULAR STACKED SEMICONDUCTOR PACKAGE - A package method of modular stacked semiconductor package is disclosed. A carrier and a plurality of the chip modules are provided. A plurality of redistribution layers are respectively formed in device areas of the carrier. The chip modules are stacked on the corresponding device areas of the carrier and are electrically connected to each other. A molding compound is formed on the redistribution layers on the carrier to encapsulate the chip modules. The carrier is removed to expose the redistribution layers. A plurality of solder balls are formed on the exposed redistribution layers. The molding compound is cut along adjacent edges of the device areas to form a plurality of modular stacked semiconductor packages. Since the chip modules are previously fabricated, connecting quality among the stacked chip modules is enhanced and is not affected by positioning error. | 2022-04-28 |
20220130814 | LAND-SIDE SILICON CAPACITOR DESIGN AND SEMICONDUCTOR PACKAGE USING THE SAME - A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region. | 2022-04-28 |
20220130815 | METHOD OF MANUFACTURING PACKAGE STRUCTURE - A method of manufacturing a package structure includes: forming a backside RDL structure on a carrier; forming TIVs on the backside RDL structure; mounting at least one passive device on the backside RDL structure, so that the at least one passive device is disposed between the TIVs; placing a die on the at least one passive device, so that the at least one passive device is vertically sandwiched between the die and the backside RDL structure; forming an encapsulant laterally encapsulating the die, the TIVs, and the at least one passive device; forming a front side RDL structure on a front side of the die, the TIVs, and the encapsulant; releasing the backside RDL structure from the carrier; and mounting a package on the backside RDL structure, wherein the package is electrically connected to the at least one passive device by conductive connectors and solders. | 2022-04-28 |
20220130816 | TSV Coupled Integrated Circuits and Methods - According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit. | 2022-04-28 |
20220130817 | POWER DISTRIBUTION NETWORK - An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias. | 2022-04-28 |
20220130818 | LAYOUT DESIGN METHODOLOGY FOR STACKED DEVICES - A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout. | 2022-04-28 |
20220130819 | SEMICONDUCTOR CHIP WITH GATE OXIDE PROTECTION OF METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND/OR OXIDE PROTECTION OF METAL-OXIDE-METAL CAPACITOR - A semiconductor chip includes a metal-oxide-semiconductor (MOS) transistor, a first oxide protection circuit, and a second oxide protection circuit. The first oxide protection circuit has a first terminal coupled to a gate terminal of the MOS transistor, and further has a second terminal arranged to receive a first ground voltage, wherein a noise level of the first ground voltage is lower than a noise level of a second ground voltage defined in the semiconductor chip. The second oxide protection circuit has a first terminal coupled to the gate terminal of the MOS transistor, and further has a second terminal arranged to receive a first supply voltage, wherein a noise level of the first supply voltage is lower than a noise level of a second supply voltage defined in the semiconductor chip. | 2022-04-28 |
20220130820 | BACKEND ELECTROSTATIC DISCHARGE DIODE APPARATUS AND METHOD OF FABRICATING THE SAME - A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises the first material, wherein the second structure is between the first and third structures. | 2022-04-28 |
20220130821 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature. | 2022-04-28 |
20220130822 | SEMICONDUCTOR STRUCTURE WITH NANOSHEETS - Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another. | 2022-04-28 |
20220130823 | BACKSIDE POWER RAIL AND METHODS OF FORMING THE SAME - A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction. | 2022-04-28 |
20220130824 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS SHARING GATES WITH STRUCTURES HAVING REDUCED PARASITIC CIRCUIT - A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact. | 2022-04-28 |
20220130825 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS SHARING GATES WITH STRUCTURES HAVING REDUCED PARASITIC CIRCUIT - A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors. | 2022-04-28 |
20220130826 | Semiconductor Device and Manufacturing Method Thereof for Selectively Etching Dummy Fins - A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height. | 2022-04-28 |
20220130827 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including NMOS and PMOS regions; first and second active patterns on the NMOS region; third and fourth active patterns on the PMOS region, the third active pattern being spaced apart from the first active pattern; a first dummy gate structure on the first and third active patterns; a second dummy gate structure on the second and fourth active patterns; a normal gate structure on the third active pattern; a first source/drain pattern on the third active pattern and between the normal gate structure and the first dummy gate structure; and a first element separation structure between the first and second dummy gate structures and separating the third and fourth active patterns, wherein the first dummy gate structure includes a first dummy insulation gate intersecting the third active pattern. | 2022-04-28 |
20220130828 | Pattern layout and the forming method thereof - The invention discloses a pattern layout of an active region and a forming method thereof. The feature of the present invention is that in the sub-pattern unit, an appropriate active area pattern is designed according to the bit line pitch (BLP) and the word line pitch (WLP), the active area pattern is a stepped pattern formed by connecting a plurality of rectangular patterns in series, and the active area pattern is arranged along a first direction, the angle between the first direction and the horizontal direction is A. In addition, according to the angle A, the shortest distance (P) between adjacent stepped patterns, the length and width of sub-pattern units, etc., The positions of some stepped active area patterns are adjusted, so that the distance between multiple active area patterns can be consistent when being repeatedly arranged, thereby improving the uniformity of overall pattern distribution. | 2022-04-28 |
20220130829 | SEMICONDUCTOR STORAGE DEVICE COMPRISING STAIRCASE PORTION AND METHOD FOR MANUFACTURING THE SAME - A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. A first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction. | 2022-04-28 |
20220130830 | WIDENED CONDUCTIVE LINE STRUCTURES AND STAIRCASE STRUCTURES FOR SEMICONDUCTOR DEVICES - Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line. | 2022-04-28 |
20220130831 | VERTICAL DIGIT LINE FOR SEMICONDUCTOR DEVICES - Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region of the horizontally oriented access devices. The vertically oriented digit lines are formed in direct electrical contact with the first source/drain regions of the horizontally oriented access devices. A vertically oriented body contact line is integrated to form the body contact to the body region of the horizontally oriented access device and separate from the first source/drain region and the vertically oriented digit lines by a dielectric. | 2022-04-28 |
20220130832 | SEMICONDUCTOR STRUCTURE WITH VERTICAL GATE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate, a cell capacitor, a channel structure, a lining material, a word line and a bit line. The cell capacitor is disposed over the substrate. The channel structure is disposed over the cell capacitor, wherein the channel structure comprises a horizontal member and at least two vertical members extending from the horizontal member and separated by a ditch on the horizontal member. The lining material surrounds each of the at least two vertical members. The word line encloses the at least two vertical members and partially fills the ditch. The bit line is disposed over the channel structure. | 2022-04-28 |
20220130833 | SEMICONDUCTOR STRUCTURE FORMATION METHOD AND SEMICONDUCTOR STRUCTURE - Embodiments of the present application provide a semiconductor structure formation method and a semiconductor structure. The method includes: the substrate including contact region and dummy region, a first bitline structure and a first dielectric layer being formed on the substrate, the first bitline structure and the first dielectric layer defining discrete capacitor contact openings; forming a first sacrificial layer filling the capacitor contact opening; removing, in the dummy region, part of height of the first bitline structure, part of height of the first dielectric layer and part of height of the first sacrificial layer to form a first opening located at top of a second bitline structure, a second dielectric layer and a second sacrificial layer; forming an insulation layer filling the first opening; removing, in the contact region, the first sacrificial layer to form a second opening; and forming a capacitor contact structure located in the second opening. | 2022-04-28 |
20220130834 | VERTICAL DIGIT LINES FOR SEMICONDUCTOR DEVICES - Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric. | 2022-04-28 |
20220130835 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THEREOF - Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion. | 2022-04-28 |
20220130836 | SEMICONDUCTOR STRUCTURE FORMATION METHOD AND SEMICONDUCTOR STRUCTURE - Embodiments of the present application provide a semiconductor structure formation method and a semiconductor structure. The semiconductor structure formation method includes: providing a substrate, the substrate including a contact region and a virtual region arranged adjacent to each other, a bitline structure and a dielectric layer arranged discretely being formed on the substrate, an extension direction of the dielectric layer intersecting with that of the bitline structure, and the bitline structure and the dielectric layer defining discrete capacitor contact openings; forming a sacrificial layer filling the capacitor contact opening; removing, in the contact region, the sacrificial layer to form a second opening; forming a bottom conductive layer filling the second opening; removing, in the virtual region, some height of the sacrificial layer to form a first opening; forming an insulation layer filling the first opening; and forming a capacitor contact structure located in the second opening. | 2022-04-28 |
20220130837 | GROWTH OF THIN OXIDE LAYER WITH AMORPHOUS SILICON AND OXIDATION - A method for forming an oxide layer includes forming an interfacial layer on a substrate, forming an amorphous silicon layer on the interfacial layer, performing a direct oxidation process to selectively oxidize the formed amorphous silicon layer, and performing a thermal oxidation process to oxidize the formed amorphous silicon layer. | 2022-04-28 |
20220130838 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An embodiment of the present application provides a manufacturing method of a semiconductor structure, including: providing a base; forming a first mask layer with a first mask pattern on the base, and etching the base with the first mask layer as a mask to form an active region; forming a plurality of discrete bitlines on the active region; sequentially stacking a first spacer layer and a second spacer layer on a side wall of the bitline; forming a sacrificial layer between the adjacent second spacer layers; forming a second mask layer with a second mask pattern on the sacrificial layer, the first mask pattern being complementary to the second mask pattern; etching the sacrificial layer with the second mask layer and the bitline as masks to form multiple contact hole structures; and etching the first spacer layer to form a gap between the second spacer layer and the bitline. | 2022-04-28 |
20220130839 | BURIED WORD LINE OF A DYNAMIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME - A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench. | 2022-04-28 |
20220130840 | SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD - The present disclosure relates to the field of semiconductor technologies, and provides a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure includes a substrate, a bitline, a bitline isolator, a peripheral gate and a gate isolator. A plurality of active regions are formed in the substrate. The bitline is located on the substrate and connected to the active region. The bitline isolator is located on the substrate and covers a sidewall of the bitline. The bitline isolator includes a first air gap. The peripheral gate is located on the substrate. The gate isolator is located on the substrate and covers a sidewall of the peripheral gate. The gate isolator includes a second air gap. | 2022-04-28 |
20220130841 | SEMICONDUCTOR DEVICE USING DIFFERENT TYPES OF THROUGH-SILICON-VIAS - A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV. | 2022-04-28 |
20220130842 | PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In formation of an SRAM cell, a band-shaped contact hole C | 2022-04-28 |
20220130843 | Two-Port SRAM Structure - An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device, and a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. The integrated circuit structure further includes a first metal layer, with a bit-line, a CVdd line, and a first CVss line in the first metal layer, a second metal layer over the first metal layer, and a third metal layer over the second metal layer. A write word-line is in the second metal layer. A read word-line is in the third metal layer. | 2022-04-28 |
20220130844 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell formed on the surface of a p-well of a semiconductor substrate includes a drain region and a source region that are formed with a channel region therebetween; an insulating film that is formed to cover the channel region; a gate that is formed on the insulating film; sidewall spacers that are formed to be positioned at side surfaces of the gate and directly above the channel region; a salicide block film that is formed to cover a portion of the drain region, a portion of the source regio, the gat, and the sidewall spacers; a drain salicide layer and a source salicide layer that are formed at the salicide block film and on the drain region and the source region exposed from the salicide block film; and a nitride film that is formed to cover the salicide block film, the drain salicide layer, and the source salicide layer. | 2022-04-28 |
20220130845 | Array Of Capacitors, Array Of Memory Cells, Methods Of Forming An Array Of Capacitors, And Methods Of Forming An Array Of Memory Cells - A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another. A horizontally-elongated conductive line is formed atop and is directly electrically coupled to the upper capacitor electrode material in individual of the groups. Other methods, including structure independent of method of manufacture, are disclosed. | 2022-04-28 |
20220130846 | SEMICONDUCTOR DEVICE HAVING PERIPHERAL CIRCUIT AREAS AT BOTH SIDES OF SUBSTRATE AND DATA STORAGE SYSTEM INCLUDING THE SAME - A semiconductor device including a cell area including a first substrate, gate electrodes on the first substrate, a channel structure extending through the gate electrodes, cell contact plugs, a through contact plug, and first bonding pads, the first peripheral circuit area including second bonding pads on the first bonding pads; a second peripheral circuit area connected to the first peripheral circuit area; and a second substrate between the first peripheral circuit area and the second peripheral circuit area, the second substrate including a first surface in the first peripheral circuit area and a second surface in the second peripheral circuit area, wherein the second peripheral circuit area includes a device on the second surface, and a through electrode extending vertically through the second substrate and connected to the first peripheral circuit area. | 2022-04-28 |
20220130847 | 3D MEMORY DEVICES AND STRUCTURES WITH THINNED SINGLE CRYSTAL SUBSTRATES - A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding. | 2022-04-28 |
20220130848 | NON-VOLATILE MEMORY AND FORMING METHOD THEREOF - A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile. | 2022-04-28 |
20220130849 | MEMORY DEVICE - A memory device includes a cell region in which memory blocks, respectively including gate electrodes and insulating layers, alternately stacked on a substrate, and channel structures, extending in a first direction, perpendicular to an upper surface of the substrate, passing through the gate electrodes and the insulating layers, and connected to the substrate, are arranged. A peripheral circuit region includes a row decoder connected to the gate electrodes and a page buffer connected to the channel structures. The memory blocks include main blocks and at least one spare block, wherein a length of the spare block is shorter than a length of each of the main blocks, in a second direction, parallel to the upper surface of the substrate. | 2022-04-28 |
20220130850 | METHODS OF FORMING A MICROELECTRONIC DEVICE INCLUDING STAIR STEP STRUCTURES - A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed. | 2022-04-28 |
20220130851 | VERTICAL MEMORY DEVICE - A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures. | 2022-04-28 |
20220130852 | MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICE WITH NESTED CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME - A semiconductor structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces and located over a substrate, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces, and memory opening fill structures extending through the alternating stacks. A contact via assembly is provided, which includes a first conductive via structure vertically extending from a top surface of one of the first electrically conductive layers through a subset of layers within the second alternating stack and through the second retro-stepped dielectric material portion, an insulating spacer located within an opening through the subset of layers, and a second conductive via structure laterally surrounding the insulating spacer and contacting a second electrically conductive layer. | 2022-04-28 |
20220130853 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING METAL SILICIDE SOURCE REGIONS AND METHODS FOR FORMING THE SAME - A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second end of the vertical semiconductor channel, and a source contact layer contacting the source region. | 2022-04-28 |
20220130854 | THREE-DIMENSIONAL MEMORY DEVICES WITH SUPPORTING STRUCTURE FOR STAIRCASE REGION AND SPACER STRUCTURE FOR CONTACT STRUCTURE AND METHODS FOR FORMING THE SAME - Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure. | 2022-04-28 |
20220130855 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating layer, a first bonding pad in the first insulating layer, a second insulating layer in contact with the first insulating layer, and a second bonding pad in the second insulating layer. The first bonding pad includes a first conductive layer and a first barrier layer surrounding the first conductive layer, and the second bonding pad includes a second conductive layer and a second barrier layer surrounding the second conductive layer. The second barrier layer is in contact with the first conductive layer. The second conductive layer is spaced apart from the first conductive layer. The first conductive layer includes a metal material which is different from a metal material included in the second conductive layer. The first and second barrier layers each include at least one of titanium and tantalum. | 2022-04-28 |
20220130856 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes. | 2022-04-28 |
20220130857 | Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed. | 2022-04-28 |
20220130858 | Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material-string structures of memory cells extend through the insulative tiers and the conductive tiers. The channel-material-string structures individually comprise an upper portion above and joined. with a lower portion. Individual of the channel-material-string structures comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method are disclosed, | 2022-04-28 |
20220130859 | Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises sacrificial material of different composition from the first-tier material there-above and from the second-tier material tier there-above. The sacrificial material is of different composition from that of an uppermost portion of the conductor material of the conductor tier. The sacrificial material is isotropically etched selectively relative to the uppermost portion of the conductor material of the conductor tier, selectively relative to the first-tier material there-above, and selectively relative to the second-tier material there-above. After the isotropic etching, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other methods and structure independent of method are disclosed. | 2022-04-28 |
20220130860 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure. | 2022-04-28 |
20220130861 | INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME - An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines. | 2022-04-28 |
20220130862 | FLASH MEMORY AND METHOD OF FABRICATING THE SAME - Provided is a flash memory includes a gate stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, and a gate dielectric layer. The gate stack structure includes a plurality of gate layers electrically insulated from each other. Each gate layer includes a ferroelectric portion disposed between a sidewall of a first portion and a sidewall of a second gate portion. A thickness of the second gate portion is smaller than a thickness of the first gate portion. A channel pillar penetrates the gate stack structure. The first and second conductive pillars are disposed in the channel pillar. The first and second conductive pillars are separated from each other, and are each connected to the channel pillar. The gate dielectric layer is disposed between another sidewall of the first gate portion and the channel pillar. | 2022-04-28 |
20220130863 | FERROELECTRIC MATERIAL-BASED THREE-DIMENSIONAL FLASH MEMORY, AND MANUFACTURE THEREOF - Disclosed are: a three-dimensional flash memory in which the degree of integration in a horizontal direction is improved so as to promote integration; and a manufacturing method therefor. A three-dimensional flash memory according to one embodiment comprises: at least one channel layer extending in one direction; at least one ferroelectric film used as a data storage place while being extended in the one direction so as to encompass the at least one channel layer; and a plurality of electrode layers stacked so as to be vertically connected to the at least one ferroelectric film. | 2022-04-28 |
20220130864 | COAXIAL CONTACTS FOR 3D LOGIC AND MEMORY - In method for forming a semiconductor device, a first opening is formed in a dielectric stack that has a cylinder shape with a first sidewall. A first conductive layer is deposited along the first sidewall of the first opening and a first insulating layer is deposited along an inner sidewall of the first conductive layer. The dielectric stack is then etched along an inner sidewall of the first insulating layer so as to form a second opening that extends into the dielectric stack with a second sidewall. A second conductive layer is further formed along the second sidewall of the second opening and a second insulating layer is formed along an inner sidewall of the second conductive layer. A bottom of the second conductive layer is positioned below a bottom of the first conductive layer to form a staggered configuration. | 2022-04-28 |
20220130865 | SEMICONDUCTOR DEVICE - A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOT substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer. | 2022-04-28 |
20220130866 | Silicon-On-Oxide-On-Silicon - Some embodiments of the present technology simplify the process of producing SOI wafers significantly compared to traditional methods. Furthermore, various embodiments provide a route for the integration of perovskite transition metal oxide thin films with different properties into SOI wafers. As such films display a wide array of novel electronic, magnetic, and optical phenomena, their integration into technologically-relevant SOI wafers will likely allow for the construction of a wide array of novel devices. | 2022-04-28 |
20220130867 | ARRAY SUBSTRATE AND DISPLAY PANEL - An array substrate and a display panel are provided. The present disclosure can form a capacitor by having a first metal layer which forms a start pulse signal line to be a first plate, and having a second metal layer which is connected to a peripheral common electrode line to be a second plate, thereby achieving electrostatic protection. In addition, by designing the start pulse signal line from an original wire-wound type to a grid shape, accumulated electric charges accumulated in the start pulse signal line can be effectively eliminated, thereby reducing probability of electrostatic discharge in the start pulse signal line. | 2022-04-28 |
20220130868 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device and a method of manufacturing a display device are provided. An embodiment of a display device includes a substrate; a first conductive layer disposed on the substrate; a first insulating layer disposed on the first conductive layer; a second conductive layer connected to the first conductive layer through a first contact hole in the first insulating layer; a second insulating layer filling an inside of the first contact hole; and a third insulating layer disposed on the second conductive layer and the second insulating layer. The first insulating layer includes a first region that overlaps the second conductive layer and a second region that does not overlap the second conductive layer, and a top surface of the first region of the first insulating layer is positioned higher than a top surface of the second region of the first insulating layer. | 2022-04-28 |
20220130869 | DISPLAY SUBSTRATE AND DISPLAY DEVICE - A display substrate includes a base substrate; a gate metal pattern including a gate electrode of a thin film transistor and gate lines; a source-drain metal pattern including a source electrode and a drain electrode of the thin film transistor, and data lines, where the gate line cross the data line, to define a plurality of pixel regions arranged in an array form; and a first transparent metal pattern including a common electrode pattern. A minimum distance between each gate line and common electrode patterns in a row of pixel regions located in a same row as the gate line in a first direction is a first spacing, a minimum distance between the gate line and common electrode patterns in the other row of pixel regions adjacent to the gate line in the first direction is a second spacing, and the first spacing is greater than the second spacing. | 2022-04-28 |
20220130870 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, MASK AND DISPLAY PANEL - An array substrate of this disclosure includes: a substrate and a first conductive layer and a second conductive layer sequentially stacked on the substrate; orthographic projections of the first and second conductive layers on the substrate have an overlapping region; portions of the first and second conductive layers in the overlapping region constitute a first conductive pattern; a portion of the first conductive layer outside the overlapping region includes a second conductive pattern and a third conductive pattern; the second and third conductive patterns have an interval therebetween. A first distance between first regions of the second and third conductive patterns proximal to the first conductive pattern is larger than a second distance between second regions of the second and third conductive patterns distal to the first conductive pattern. | 2022-04-28 |