17th week of 2016 patent applcation highlights part 54 |
Patent application number | Title | Published |
20160118493 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device structure can include: (i) a first semiconductor layer having dopants of a first type; (ii) a second semiconductor layer having the dopants of the first type on the first semiconductor layer, where the second semiconductor layer is lightly-doped relative to the first semiconductor layer; (iii) first and second column regions spaced from each other in the second semiconductor layer, where the second column region is arranged between two of the first column regions; and (iv) first and second first sub-column regions laterally arranged in the second column region, where a doping concentration of the first sub-column region decreases in a direction from the first column region to the second sub-column region, and where a doping concentration of the second sub-column region decreases in a direction from the first column region to the first sub-column region. | 2016-04-28 |
20160118494 | MOS FIELD-EFFECT TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF - A substrate for a metal oxide semiconductor field effect transistor, and a metal oxide semiconductor field effect transistor, are made available. The substrate encompasses: an n-doped epitaxial drift zone, a p | 2016-04-28 |
20160118495 | INTEGRATED BREAKDOWN PROTECTION - A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path. | 2016-04-28 |
20160118496 | SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S) - Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods. | 2016-04-28 |
20160118497 | METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELASTIC STRAIN RELAXATION OF THE SUBSTRATE - Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer. | 2016-04-28 |
20160118498 | HIGH DOSE IMPLANTATION FOR ULTRATHIN SEMICONDUCTOR-ON-INSULATOR SUBSTRATES - Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers. | 2016-04-28 |
20160118499 | FD DEVICES IN ADVANCED SEMICONDUCTOR TECHNIQUES - The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region. | 2016-04-28 |
20160118500 | FIN STRUCTURES AND MULTI-VT SCHEME BASED ON TAPERED FIN AND METHOD TO FORM - A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin. | 2016-04-28 |
20160118501 | THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME - The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode ( | 2016-04-28 |
20160118502 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SAME - A change in electrical characteristics in a semiconductor device including an oxide semiconductor film is inhibited, and the reliability is improved. The semiconductor device includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, a first metal oxide film over the second insulating film, and a second metal oxide film over the first metal oxide film. The first metal oxide film contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film. The second metal oxide film includes a region where the second metal oxide film and the first metal oxide film are mixed. | 2016-04-28 |
20160118503 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device may include a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the substrate to cover the gate electrode, an active layer including an oxide semiconductor disposed on the gate insulation layer, an insulating interlayer disposed on the gate insulation layer to cover the active layer, a protection structure including a plurality of metal oxide layers disposed on the insulating interlayer, and a source electrode and a drain electrode disposed on the protection structure. | 2016-04-28 |
20160118504 | THIN FILM TRANSISTOR - A thin film transistor disposed on a substrate, includes a gate, a gate insulation layer, a first source/drain, a semiconductor layer and a second source/drain. The gate is disposed on the substrate. The gate insulation layer covers the gate and the substrate. The first source/drain is disposed on the gate insulation layer. The semiconductor layer is disposed above the gate, extends from the gate insulation layer to the first source/drain, and includes a first portion disposed on the first source/drain and a second portion connected to the first portion. An electrical conductivity of the first portion is higher than that of the second portion. The second source/drain covers and is in contact with the second portion. A manufacturing method of thin film transistor is further provided. | 2016-04-28 |
20160118505 | Display Device And Semiconductor Device - An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased. | 2016-04-28 |
20160118506 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a substrate, at least one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface has an opening to expose the light sensor (or the thermal sensor). The support is disposed on the first surface. The cover is disposed on the support, such that the cover is above the light sensor (or the thermal sensor) to form a first space between the cover and the light sensor (or the thermal sensor). The plate is placed on the second surface to cover the opening, such that a second space is formed between the plate and the light sensor (or the thermal sensor). | 2016-04-28 |
20160118507 | PHOTOVOLTAIC MODULE INCLUDING INTEGRATED PHOTOVOLTAIC CELLS - A photovoltaic module and its manufacturing method. The module includes a first support wafer made of sintered silicon and a second layer of single-crystal silicon. | 2016-04-28 |
20160118508 | Method for Producing a Solar Cell - The invention relates to a method for producing a solar cell composed of crystalline silicon, as well as a solar cell of said type. The substrate of said solar cell has, in a first surface, a first doping region produced by boron diffusion and, in a second surface, a phosphorus-doped second doping region. | 2016-04-28 |
20160118509 | Light Detector Using an On-Die Interference Filter - A light detector includes a semiconductor die that provides a photo sensor. An interference filter is formed on the semiconductor die and has a pass band corresponding to a wavelength of a light emitting diode to supply filtered light in the pass band to the photo sensor. | 2016-04-28 |
20160118510 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell includes a semiconductor substrate, a boron back surface field (BSF) layer, a passivation layer, a back electrode layer and an aluminum local BSF layer. The semiconductor substrate has a front surface and a back surface opposite to each other. The boron BSF layer is disposed in the semiconductor substrate beneath the back surface. The passivation layer is disposed over the boron BSF layer and has an opening through the passivation layer. The back electrode layer is disposed in the opening. The aluminum local BSF layer is disposed in the semiconductor substrate beneath the opening and in contact with the boron BSF layer and the back electrode layer. | 2016-04-28 |
20160118511 | METHOD FOR FABRICATING A PHOTOSENSITIVE DEVICE - A method for fabricating a photosensitive device, comprising: a first step of preparing, on a substrate, at least a first photosensitive portion, active within a range of wavelengths, the first portion being surrounded by a second portion that is inactive. A material, covering the first portion, is selectively arranged into a hydrophilic layer by an electrochemical process. The second portion comprises a hydrophobic material on an upper surface opposite the substrate. The method further comprises the following steps: spraying on the upper surfaces of the first and second portions a liquid comprising a transparent material, and forming a converging lens containing the material, above the first portion. | 2016-04-28 |
20160118512 | METHOD FOR MANUFACTURING SOLAR-POWER-GENERATOR SUBSTRATE AND APPARATUS FOR MANUFACTURING SOLAR-POWER-GENERATOR SUBSTRATE - A method for manufacturing a solar-power-generator substrate by cutting out a semiconductor substrate by slicing a semiconductor ingot and then by forming a texture structure on a surface of the semiconductor substrate by performing a surface treatment on the surface of the semiconductor substrate, includes: cleaning including cleaning and removing an organic impurity and a metal impurity adhering to the surface of the semiconductor substrate with a cleaning fluid containing an oxidizing chemical; and etching including removing a damaged layer on a substrate surface generated by the slicing and forming the texture structure on the surface of the semiconductor substrate by performing anisotropic etching on the surface of the semiconductor substrate with an alkaline aqueous solution, the etching being performed subsequent to the cleaning. | 2016-04-28 |
20160118513 | COMPOSITION FOR FORMING ELECTRODE, PHOTOVOLTAIC CELL ELEMENT AND PHOTOVOLTATIC CELL - A composition for forming an electrode includes a phosphorus-containing copper alloy particle, a tin-containing particle, a specific metal element M-containing particle, a glass particle, a solvent and a resin, in which M is at least one selected from the group consisting of Li, Be, Na, Mg, K, Ca, Rb, Sr, Cs, Ba, Fr, Ra, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Pd, Ag, Cd, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Al, Ga, Ge, In, Sb, Tl, Pb, Bi and Po. | 2016-04-28 |
20160118514 | SOLAR CELL, SOLAR CELL PANEL, AND SOLAR CELL FILM - According to one embodiment, a solar cell includes a first electrode, a photoelectric conversion film, a second electrode, and a first electret. The photoelectric conversion film is provided on the first electrode. The photoelectric conversion film includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is of a first conductivity type. The second semiconductor layer is of a second conductivity type and provided on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer generate a built-in electric field. The second electrode is provided on the photoelectric conversion film. The first electret is arranged with the photoelectric conversion film in a stacking direction of the first semiconductor layer and the second semiconductor layer. The first electret generates an external electric field. The external electric field and the built-in electric field are oriented toward the same side. | 2016-04-28 |
20160118515 | BACK CONTACT TYPE SOLAR BATTERY CELL - A back contact type solar battery which provides a reduced electric power loss, free positioning of a bus bar, and a simple manufacturing process. The solar battery includes: semiconductor substrate; first conductivity type region formed on back surface side located on the opposite side of acceptance surface side of the semiconductor substrate; second conductivity type region formed on the back surface side of the semiconductor substrate; first conductivity type collecting electrode linearly formed on the first conductivity type region; and second conductivity type collecting electrode linearly formed on the second conductivity type region. The first and second conductivity type regions are alternately arranged. Each of the first and second conductivity type collecting electrodes has discontinuous places. The discontinuous places of each conductivity type are substantially aligned on straight line in arrangement direction in which the first and second conductivity type regions are alternately arranged. | 2016-04-28 |
20160118516 | PROCESS AND STRUCTURES FOR FABRICATION OF SOLAR CELLS - Contact holes of solar cells are formed by laser ablation to accommodate various solar cell designs. Use of a laser to form the contact holes is facilitated by replacing films formed on the diffusion regions with a film that has substantially uniform thickness. Contact holes may be formed to deep diffusion regions to increase the laser ablation process margins. The laser configuration may be tailored to form contact holes through dielectric films of varying thicknesses. | 2016-04-28 |
20160118517 | GROUPED NANOSTRUCTURED UNITS SYSTEM FORMING A METAMATERIAL - This invention concerns a grouped nanostructured unit system forming a metamaterial within the silicon and the manufacturing process to arrange them therein in an optimal manner. The nanostructured units are grouped and conditioned in an optimal arrangement inside the silicon material. The process comprises the modification of the elementary crystal unit together with the stress field, the electric field and a heavy impurity doping in order to form a superlattice of nanostructured units grouped in an optimal arrangement so as to improve the efficiency of the light-to-electricity conversion by means of efficient use of the kinetic energy of hot electrons and efficient collection of all electrons generated within the converter. | 2016-04-28 |
20160118518 | A BACKSHEET FOR PHOTOVOLTAIC MODULES - A backsheet for a photovoltaic module includes a support and a weather resistant layer, the weather resistant layer including a binder containing a crosslinkable group, an isocyanate crosslinking agent, and a catalyst that improves the crosslinking of the binder, wherein the catalyst is a zinc based catalyst or a bismuth based catalyst. | 2016-04-28 |
20160118519 | THIN FILM SOLAR CELL PANEL AND MANUFACTURING METHOD THEREOF - The present invention provides a thin film solar cell panel and a manufacturing method thereof. The thin film solar cell panel comprises a substrate, a first electrode disposed on the substrate. The substrate is an ultra-thin glass substrate with a thickness of 0.1-1 mm. The ultra-thin glass substrate has a bending capacity, and a minimum bending radius thereof reaches below 10 cm. The first electrode is continuously disposed on the substrate during its formation. Light transmittance of the thin film solar cell panel of the present invention is enhanced, and the thin film solar cell panel can be conveniently used to manufacture a bending solar cell component. | 2016-04-28 |
20160118520 | METHODS OF HERMETICALLY SEALING PHOTOVOLTAIC MODULES - In various embodiments, photovoltaic modules are hermetically sealed by providing a first glass sheet, a photovoltaic device disposed on the first glass sheet, and a second glass sheet, a gap being defined between the first and second glass sheets, disposing a glass powder within the gap, and heating the powder to seal the glass sheets. | 2016-04-28 |
20160118521 | MATING SYSTEM FOR PHOTOVOLTAIC ARRAY - A photovoltaic component comprising; two or more mating components spatially separated along a surface of the photovoltaic component wherein at feast one of the two or more mating components mates with a portion of one or more adjacent photovoltaic components to form a connection between one or more mating components of the one or more adjacent photovoltaic components so that a mating connection is formed between the photovoltaic component and the adjacent photovoltaic component, and wherein the at least one of the two or more mating components of the photovoltaic component and the at least one of the one or more mating components of the adjacent photovoltaic component align the photovoltaic component and the adjacent photovoltaic component relative to one another; and wherein at least one of the two or more mating components of the photovoltaic component are shaped and form a handle for carrying and/or moving the photovoltaic component. | 2016-04-28 |
20160118522 | SOLAR CELL MODULE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a solar cell module and a method for manufacturing the same. The solar cell module comprises: a substrate; and a plurality of solar cells located on the substrate, each solar cell comprising a first electrode, a second electrode, and a photoactive layer located between the first electrode and the second electrode, wherein at least a portion of a second electrode is located on a photoactive layer of a neighboring solar cell, and a conductive channel is located between the second electrode and a first electrode of the neighboring solar cell. Therefore, a solar cell module having a structure in which every layer except for electrodes is entirely formed as a thin film may be provided. In addition, a solar cell module the module efficiency of which is improved by increasing the active area of each solar cell may be provided. | 2016-04-28 |
20160118523 | SOLAR CELL MODULE AND METHOD AND DEVICE FOR REPAIRING THE SAME - A solar cell module and a method and a device for repairing the solar cell module are disclosed. The method for repairing a defective solar cell of the solar cell module includes cutting a plurality of wiring members electrically connecting the defective solar cell to a normal solar cell at a back surface of the solar cell module and forming previous wiring members of the normal solar cell, so that a cutting position of the plurality of wiring members is not seen from a front surface of the solar cell module, positioning a connection bar at the back surface of the solar cell module such that the connection bar crosses the cut previous wiring members of the normal solar cell and replaceable wiring members of a new solar cell, and electrically connecting the previous wiring members, the replaceable wiring members, and the connection bar. | 2016-04-28 |
20160118524 | STACKED INTEGRATED MULTI-JUNCTION SOLAR CELL - A stacked integrated multi-junction solar cell, having a first subcell, whereby the first subcell has a layer of an InGaP compound with a first lattice constant and a first band gap energy, and the thickness of the layer is greater than 100 nm and the layer is formed as part of an emitter and/or as part of the base and/or as part of the space charge region lying between the emitter and base, and a second subcell with a second lattice constant and a second band gap energy, and a third subcell with a third lattice constant and a third band gap energy, and a fourth subcell with a fourth lattice constant and a fourth band gap energy, and a region with a wafer bond is formed between two subcells. | 2016-04-28 |
20160118525 | III-V PHOTOVOLTAIC ELEMENTS - Solar cell structures that have improved carrier collection efficiencies at a heterointerface are provided by low temperature epitaxial growth of silicon on a III-V base. Additionally, a solar cell structure having improved open circuit voltage includes a shallow junction III-V emitter formed by epitaxy or diffusion followed by the epitaxy of Si | 2016-04-28 |
20160118526 | MULTI-JUNCTION SOLAR CELL WITH DILUTE NITRIDE SUB-CELL HAVING GRADED DOPING - A lattice-matched solar cell having a dilute nitride-based sub-cell has exponential doping to thereby control current-carrying capacity of the solar cell. Specifically a solar cell with at least one dilute nitride sub-cell that has a variably doped base or emitter is disclosed. In one embodiment, a lattice matched multi junction solar cell has an upper sub-cell, a middle sub-cell and a lower dilute nitride sub-cell, the lower dilute nitride sub-cell having doping in the base and/or the emitter that is at least partially exponentially doped so as to improve its solar cell performance characteristics. In construction, the dilute nitride sub-cell may have the lowest bandgap and be lattice matched to a substrate, the middle cell typically has a higher bandgap than the dilute nitride sub-cell while it is lattice matched to the dilute nitride sub-cell. | 2016-04-28 |
20160118527 | CHARGE COUPLED DEVICE BASED ON ATOMICALLY LAYERED VAN DER WAALS SOLID STATE FILM FOR OPTO-ELECTRONIC MEMORY AND IMAGE CAPTURE - An opto-electronic sensor may provide one or more layers of atomically layered photo-sensitive materials. The sensor may include a gate electrode layer, a dielectric layer in contact with the gate electrode layer, and a working media layer that is photo-sensitive deposited on the dielectric layer. The working media layer may provide one or more layers of one or more materials where each of the one or more layers is an atomic layer. The sensor may also include side electrodes in contact with the working media layer. | 2016-04-28 |
20160118528 | SIGNAL DISTRIBUTION IN INTEGRATED CIRCUIT USING OPTICAL THROUGH SILICON VIA - An optical through silicon via is formed in a silicon substrate of an integrated circuit. A photo detector is formed within the integrated circuit and is optically coupled to a first side of the optical through silicon via. A light generating source optically coupled to a second side of the optical through silicon via is provided. The photo detector is configured to receive a light, generated by the light generating source, propagating through the optical through silicon via. The light, generated by the light generating source, is controlled by a signal generated by a signal generating source. | 2016-04-28 |
20160118529 | SIGNAL DISTRIBUTION IN INTEGRATED CIRCUIT USING OPTICAL THROUGH SILICON VIA - An optical through silicon via is formed in a silicon substrate of an integrated circuit. A photo detector is formed within the integrated circuit and is optically coupled to a first side of the optical through silicon via. A light generating source optically coupled to a second side of the optical through silicon via is provided. The photo detector is configured to receive a light, generated by the light generating source, propagating through the optical through silicon via. The light, generated by the light generating source, is controlled by a signal generated by a signal generating source. | 2016-04-28 |
20160118530 | LASER SOLDERING SYSTEMS AND METHODS FOR JOINING CRYSTALLINE SILICON SOLAR BATTERIES - The disclosure includes a laser soldering method of connecting crystalline silicon solar batteries. Methods can include placing conductive soldering strips and crystalline silicon solar batteries on a lower press plate and aligning the conductive soldering strips on metal electrodes of crystalline silicon solar batteries. Methods can also include placing an upper press plate on the conductive soldering strips and the crystalline silicon solar batteries and vacuuming between the upper and lower press plates such that absolute pressure between the upper and lower press plates is less than atmospheric pressure. Methods can also include laser soldering the conductive soldering strips and the crystalline silicon solar batteries. | 2016-04-28 |
20160118531 | Optoelectronic Device with Modulation Doping - An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described. | 2016-04-28 |
20160118532 | LED light bulb manufacturing method - An LED light bulb manufacturing method, comprising the following steps: 1) preparing a transitional epitaxial layer on a substrate to form an epitaxial wafer; 2) putting the epitaxial wafer into a reacting furnace to undergo such process steps as silicon coating, sizing, photolithography, etching, film coating, alloying, and slice grinding, the epitaxial wafer growing by layers to form an LED wafer at a specific position and relevant circuits; the LED wafer will not be cut after the completion of the growth; obtaining product A after the LED wafer passes inspection, and die bonding a relevant component on product A, and then conducting wire bonding to obtain product B; 3) on product B, performing the process steps of sealant pouring to cover the wafer and baking, and after inspection, conducting color separation and light splitting, so as to form a finished light engine module; 4) utilizing the light engine module and light bulb accessories to assemble an LED light bulb, and aging and packaging the assembled LED light bulb to obtain a finished LED light bulb. The manufacturing method realizes large-scale and intensified production of LED lighting source products, and greatly reduces the manufacturing cost of LED light. | 2016-04-28 |
20160118533 | METHOD OF MANUFACTURING NANOSTRUCTURE SEMICONDUCTOR LIGHT EMITTING DEVICE - A method of manufacturing a nanostructure semiconductor light emitting device may include: stacking a mask layer on a conductive base layer and forming a through hole penetrating the mask layer; growing a nanocore through the through hole from the conductive base layer using precursor gas including indium-containing precursor gas in a mixed gas atmosphere of nitrogen and hydrogen; removing the mask layer; and sequentially growing an active layer and a first conductivity type semiconductor layer on a surface of the nanocore. | 2016-04-28 |
20160118534 | Semiconductor Layer Including Compositional Inhomogeneities - A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer. | 2016-04-28 |
20160118535 | Metallic Contact for Optoelectronic Semiconductor Device - A contact to a semiconductor layer in a light emitting structure is provided. The contact can include a plurality of contact areas formed of a metal and separated by a set of voids. The contact areas can be separated from one another by a characteristic distance selected based on a set of attributes of a semiconductor contact structure of the contact and a characteristic contact length scale of the contact. The voids can be configured to increase an overall reflectivity or transparency of the contact. | 2016-04-28 |
20160118536 | Semiconductor Structure with Inhomogeneous Regions - A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device. | 2016-04-28 |
20160118537 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light-emitting element comprises: a first semiconductor layer, an active layer having a multiple quantum well structure in which a plurality of well layers and a plurality of barrier layers are alternately layered, an electron block layer, and a second semiconductor layer. Among the barrier layers, an endmost barrier layer closest to the second semiconductor layer includes a first endmost barrier layer part and a second endmost barrier layer part formed on a side closer to the second semiconductor layer than the first endmost barrier layer part and having a larger band gap than that of the first endmost barrier layer part. The first endmost barrier layer part has a band gap that is larger than that of each of the well layers and is smaller than that of each barrier layer other than the endmost barrier layer. | 2016-04-28 |
20160118538 | LIGHT-EMITTING DEVICE HAVING A PATTERNED SUBSTRATE AND THE METHOD THEREOF - A light-emitting device comprises a textured substrate comprising a plurality of textured structures, wherein the textured structures and the textured substrate are both composed of sapphire; and a light-emitting stack overlaying the textured substrate, comprising a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, wherein each of the plurality of textured structures comprises a top portion having a first top-view shape, and a bottom portion parallel to the top portion and having a second top-view shape, wherein the first top-view shape comprises a circle or an ellipse, the first top-view shape comprises a first periphery and the second top-view shape comprises a second periphery, the first periphery is enclosed by the second periphery, and various distances are between each of the first periphery and the second periphery. | 2016-04-28 |
20160118539 | LIGHT EMITTING DIODE ELEMENT AND METHOD OF MANUFACTURING THE SAME - An n-type GaN layer made of n-type gallium nitride (GaN) is formed on a sapphire substrate. A plurality of island-phased layered structures are formed in random sizes between the n-type GaN layer and a p-type GaN layer that is made of p-type GaN. Each of the layered structures is configured by stacking multiple AlN layers made of aluminum nitride (AlN) and multiple InGaN layers made of indium gallium nitride (InGaN) on an AlN base layer. The respective layered structures emit lights of different wavelengths. This accordingly allows for emission of light in a wider wavelength range. | 2016-04-28 |
20160118540 | Light-Emitting Diode - A light-emitting diode includes at least an N-type layer, a light-emitting layer and a P-type layer, wherein the light-emitting layer forms a “V”-shaped indentation or pit during epitaxial process and the V pit is filled in with at least one type of metal nanoparticles to generate surface plasma coupling effect and to improve recombination probability of holes and electrons, thus improving internal quantum efficiency; further, a V pit is generated in the N-type layer during epitaxial process; surface plasma coupling effect is generated by filling metal nanoparticles in the V pit to increase light reflection, light extraction efficiency and external quantum efficiency, thereby improving light emitting efficiency of LED; and the V pit is formed directly by adjusting growth rate, thickness, temperature, pressure or doping during epitaxial process instead of etching, which causes no damage to the LED epitaxial layer, thus simplifying process and improving device stability. | 2016-04-28 |
20160118541 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, in a semiconductor light emitting device, a first electrode is provided on a first surface of the semiconductor laminated body including a light emitting layer. A joint metal layer is provided on a second surface of the semiconductor laminated body opposed to the first surface of the semiconductor laminated body. A bonding metal layer covers a first surface of the joint metal layer on a side opposite to the semiconductor laminated body and is provided on a side of the second surface of the semiconductor laminated body. A substrate provided with a second electrode is bonded to the bonding metal layer. A layer having an etching resistance property to an etchant for etching the semiconductor laminated body is formed on a side of the surface of the bonding metal layer facing to the semiconductor laminated body. | 2016-04-28 |
20160118542 | Method for Fabricating CMOS Compatible Contact Layers in Semiconductor Devices - A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer. | 2016-04-28 |
20160118543 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT EMITTING APPARATUS INCLUDING THE PACKAGE - A light emitting device may include a substrate, a light emitting structure disposed under the substrate, the light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first electrode configured to penetrate the second conductive semiconductor layer and the active layer, so as to come into contact with the first conductive semiconductor layer, a contact layer configured to come into contact with the second conductive semiconductor layer, a first insulation layer disposed between the second conductive semiconductor layer and the first electrode and between the active layer and the first electrode, the first insulation layer being provided for capping of a side portion and an upper portion of the contact layer, and a second electrode configured to penetrate the first insulation layer, so as to come into contact with the contact layer. | 2016-04-28 |
20160118544 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF FORMING ELECTRODE - A semiconductor light-emitting device having an electrode that can be manufactured by a simple method and is unlikely to deteriorate, and a method for forming the electrode are provided. The semiconductor light-emitting device according to the present invention has a semiconductor layered structure having a light-emitting layer that emits light by supplying electric power and an electrode formed on the semiconductor layered structure. The electrode has a reflection layer that reflects light exiting from the light-emitting layer, a barrier layer formed on the upper side and side surface of the reflection layer, and a pad layer formed only on the top surface of the barrier layer. | 2016-04-28 |
20160118545 | LIGHT EMITTING DEVICE WITH ANTI-TOTAL-INTERNAL-REFLECTION CAPABILITY - A light emitting device includes: a light emitting layered structure; an electrode unit connected to the light emitting layered structure and including a transparent electrode layer of a primary metal oxide which is stacked on the light emitting layered structure along a stacking direction; and a total-internal-reflection suppression material dispersed in the transparent electrode layer and containing a secondary metal oxide that is different from the primary metal oxide. The secondary metal oxide has a concentration gradient within the transparent electrode layer along the stacking direction. The light output power of the light emitting device may be increased by about 44% as compared to a conventional light emitting device. | 2016-04-28 |
20160118546 | LIGHT EMITTING DEVICE WITH ANTI-TOTAL-INTERNAL-REFLECTION CAPABILITY - A light emitting device includes: a light emitting layered structure; an electrode unit connected to the light emitting layered structure and including a transparent electrode layer of a primary metal oxide which is stacked on the light emitting layered structure along a stacking direction; and a total-internal-reflection suppression material dispersed in the transparent electrode layer and containing a secondary metal oxide that is different from the primary metal oxide. The secondary metal oxide has a concentration gradient within the transparent electrode layer along the stacking direction. The light output power of the light emitting device may be increased by about 44% as compared to a conventional light emitting device. | 2016-04-28 |
20160118547 | LIGHT-EMITTING DEVICE AND METHOD OF PRODUCING THE SAME - A light-emitting device of the present invention includes a plurality of first mounting bonding layers that are formed of a metal on a mounting substrate and disposed separately from each other in an island shape, and a plurality of light-emitting elements that are provided on the first mounting bonding layers, respectively. Each of the light-emitting elements includes a columnar support that is mounted on the first mounting bonding layer, and a light-emitting unit that is located on the top face of the support. Each of the supports has a protrusion at a portion closer to the top face on a side face of the support. | 2016-04-28 |
20160118548 | LIGHT EMITTING DEVICE - A light emitting device has a plurality of light emitting elements that are arranged with gaps between the devices on a mounting board in a first direction, a wavelength-conversion member that covers the plurality of light emitting elements, a light reflective resin. Each light emitting element has an n-type semiconductor layer, an active layer provided in a part of the n-type semiconductor layer, and a p-type semiconductor layer provided on the active layer. In a second direction which is perpendicular to the first direction, an n-side electrodes are provided at least in regions at both ends of the n-type semiconductor layer, and a p-side electrode is provided on the surface of the p-type semiconductor layer, and wherein in the second direction, the wavelength-conversion member is positioned to approximately align both sides with both active layer side faces, or to dispose its sides outward of the active layer side faces. | 2016-04-28 |
20160118549 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package includes a body, a cavity defined in the body and opened upward, a first electrode positioned in the cavity at least partly and including a first projection portion which projects upward, a second electrode positioned in the cavity at least partly and including a second projection portion which projects upward, a light emitting device positioned on the first projection portion and the second projection portion, and a bump disposed between the light emitting device and the first projection portion and between the light emitting device and the second projection portion, where the light emitting device is electrically connected to the first projection portion and the second projection portion through the bump. | 2016-04-28 |
20160118550 | LIGHT-EMITTING DEVICE WITH NEAR FULL SPECTRUM LIGHT OUTPUT - A method for providing light and a light-emitting device configured to providing light in accordance thereto is disclosed herein. The method includes emitting light in a monochromatic manner from a light source, wherein the light provided falls in a first spectrum associated with light of a blue color; covering the light source with a red phosphor composite, wherein the red phosphor composite is configured to cause the first spectrum of the light source to shift to a second, intermediary spectrum associated with light of a violet color; and producing light spanning a fuller visual light spectrum from the light of the violet color received from the red phosphor composite-covered light source. | 2016-04-28 |
20160118551 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A light emitting device is provide comprising a light emitting diode (LED) chip having a first main surface and a second main surface opposing the first main surface, and one or more side surfaces extending between the first main surface and second main surface. A plurality of electrodes is disposed on the first main surface. A wavelength conversion film is disposed on the second main surface. A mark is formed in the wavelength conversion film. The mark contains orientation information of the light emitting device, thereby enabling the light emitting device to be properly oriented on a receiving substrate. | 2016-04-28 |
20160118552 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A method of manufacturing a light emitting diode package comprises steps of: scanning a light emitting diode chip mounted on a package substrate to acquire mounting image data; generating three dimensional (3D) image data by comparing the mounting image data with mounting reference data; and forming an optical structure including a plurality of layers on the package substrate on using the 3D image data. | 2016-04-28 |
20160118553 | OPTOELECTRONIC COMPONENT AND METHOD FOR THE PRODUCTION THEREOF - An optoelectronic component includes a housing having a first cavity open toward an upper side of the housing, and a second cavity open toward the upper side of the housing, wherein the first cavity and the second cavity connect by a connecting channel, an optoelectronic semiconductor chip is arranged in the first cavity, a potting material is arranged in a region of the first cavity enclosing the optoelectronic semiconductor chip, a bond wire is arranged between an electrical contact surface of the optoelectronic semiconductor chip and a bond surface of the housing, and the bond surface is arranged in the connecting channel. | 2016-04-28 |
20160118554 | CHIP SCALE LIGHT EMITTING DEVICE PACKAGE WITH DOME - Light Emitting Devices (LEDs) are fabricated on a wafer substrate with one or more thick metal layers that provide structural support to each LED. The streets, or lanes, between individual LEDs do not include this metal, and the wafer can be easily sliced/diced into singulated self-supporting LEDs. Because these devices are self-supporting, a separate support submount is not required. Before singulation, further processes may be applied at the wafer-level; after singulation, these self-supporting LEDs may be picked and placed upon an intermediate substrate for further processing as required. In an embodiment of this invention, protective optical domes are formed over the light emitting devices at the wafer-level or while the light emitting devices are situated on the intermediate substrate. | 2016-04-28 |
20160118555 | COMPOSITIONS OF RESIN-LINEAR ORGANOSILOXANE BLOCK COPOLYMERS - Curable compositions of “resin-linear” organosiloxane block copolymers comprising a nanoparticulate filler are disclosed. In some instances, even at high loading levels, curable and solid compositions comprising “resin linear” organosiloxane block copolymers and a nanoparticulate filler exhibit melt flow and cure behavior. In addition, the nanoparticulate filler present in the curable and solid compositions comprising “resin linear” organosiloxane block copolymers have the effect of significantly in creasing the refractive index of the curable and solid compositions. | 2016-04-28 |
20160118556 | LIGHT-EMITTING DEVICE WITH LIGHT SCATTERING LAYER - In one embodiment, a light-emitting device having a reflector, a light source die, a light scattering member, a first encapsulant, and a second encapsulant is disclosed. The light scattering member may be configured to scatter light emitted from the light source die, before the light being transmitted into the second encapsulant where a lens surface is configured to collimate the light towards a first direction. The light scattering member may be light-scattering particles distributed uniformly within the first encapsulant, a roughened surface of the first encapsulant, and a deposited light scattering layer on the first encapsulant, air bubbles, or a substantially flat layer. The light scattering member may be provided outside a reflector cup. | 2016-04-28 |
20160118557 | LED PACKAGE WITH REFLECTING CUP - The present disclosure provides an LED package which includes electrodes, an LED die electrically connected with the electrodes, an encapsulation covering the LED die; and a casing surrounding the encapsulation and the LED die. The casing includes a base, a reflecting cup and a supporting portion. The reflecting cup extends from the base upwards, the reflecting cup surrounds the LED die, and the supporting portion is located inside the reflecting cup and across the electrodes. | 2016-04-28 |
20160118558 | LIGHT EMITTING DEVICE, PACKAGE, AND METHODS OF MANUFACTURING THE SAME - A light emitting device includes a package including a resin member having an inner side surface defining a recess, and a lead frame supported by the resin member and arranged at a bottom surface of the recess; and a light emitting element electrically connected to the lead frame. An outer side surface of the resin member at a portion corresponding to the recess is at least partially covered with a reflective film. | 2016-04-28 |
20160118559 | LIGHT-EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THEREOF - The present invention provides a light-emitting diode (LED) package including: a substrate on which a set of bonding pads are formed; an LED element configured to provide light of a predetermined wavelength region, having a set of chip pads formed on a top surface thereof and being attached on a top surface of the substrate; a set of gold wires connecting the bonding pads of the substrate with the chip pads of the LED element; a phosphor layer formed in a cap shape having side and top portions of a uniform thickness and being configured to surround sides and a top surface of the LED element while being spaced apart therefrom; and a filler disposed to fill a space formed between the phosphor layer and the LED element, wherein the LED element, the gold wires, and the bonding pads of the substrate are under the phosphor layer cap. | 2016-04-28 |
20160118560 | LIGHT EMITTING DIODE MODULE STRUCTURE AND MANUFACTURING METHOD THEREOF - A light emitting diode module structural and a manufacturing method thereof are disclosed. The manufacturing method includes the steps as follows. A base and a light emitting diode die are provided. The light emitting diode die may include a first semiconductor layer and a second semiconductor layer. The light emitting diode die is disposed on the base. A buffer layer is formed to cover the light emitting diode die. A first opening and a second opening are formed on the first semiconductor layer and the second semiconductor layer, respectively. The second opening exposes the second semiconductor layer by penetrating the first semiconductor layer. A conductive pattern layer is formed on the buffer layer, and is electrically connected with the first semiconductor layer and the second semiconductor layer via the first opening and the second opening, respectively. | 2016-04-28 |
20160118561 | CIRCUIT STRUCTURE OF A FLIP-CHIP LIGHT EMITTING DIODE - The invention relates to a circuit structure of a flip-chip light emitting diode. It is provided for assembling of the flip-chip light emitting diode. Each flip-chip light emitting diode has at least two electrodes. The circuit structure defines a light emitting surface on a surface of a substrate, and the light emitting surface is provided with a plurality of reflective and conductive surfaces. The reflective and conductive surface is used for assembling of the electrodes of the flip-chip light emitting diode. At least one flip-chip light emitting diode is connected in series, parallel or series-parallel on the light emitting surface, wherein the total area of the reflective and conductive surface accounts for 80% to 99% of the area of the light emitting surface. Accordingly, the circuit structure of the flip-chip light emitting diode can efficiently improve the luminous efficiency of flip-chip light emitting diode device by adding a proportion of the area of the reflective conduction surfaces on the substrate of the flip-chip light emitting diode. | 2016-04-28 |
20160118562 | WAFER LEVEL PHOTONIC DEVICE DIES STRUCTURE AND METHOD OF MAKING THE SAME - A vertical Light Emitting Diode (LED) device includes an epi structure with a first-type-doped portion, a second-type-doped portion, and a quantum well structure between the first-type-doped and second-type-doped portions and a carrier structure with a plurality of conductive contact pads in electrical contact with the epi structure and a plurality of bonding pads on a side of the carrier structure distal the epi structure, in which the conductive contact pads are in electrical communication with the bonding pads using at least one of vias and a Redistribution Layer (RDL). The vertical LED device further includes a first insulating film on a side of the carrier structure proximal the epi structure and a second insulating film on a side of the carrier structure distal the epi structure. | 2016-04-28 |
20160118563 | LIGHT EMITTING DIODE PACKAGE - A light-emitting diode package includes a package body and a light-emitting diode chip disposed on the package body. The package body includes upper conductive patterns disposed on an upper insulation substrate, a lower insulation substrate disposed on lower conductive patterns, and middle conductive patterns disposed between the upper insulation substrate and the lower insulation substrate. The package body also includes upper vias electrically connecting each of the upper conductive patterns to each of the middle conductive patterns, respectively, the upper vias being disposed in the upper insulation substrate, and lower vias electrically connecting each of the middle conductive patterns to each of the lower conductive patterns, respectively, the lower vias disposed in the lower insulation substrate. | 2016-04-28 |
20160118564 | LIGHT EMITTING DIODE CHIP HAVING ELECTRODE PAD - Disclosed herein is an LED chip including electrode pads. The LED chip includes a semiconductor stack including a first conductive type semiconductor layer, a second conductive type semiconductor layer on the first conductive type semiconductor layer, and an active layer interposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a first electrode pad located on the second conductive type semiconductor layer opposite to the first conductive type semiconductor layer; a first electrode extension extending from the first electrode pad and connected to the first conductive type semiconductor layer; a second electrode pad electrically connected to the second conductive type semiconductor layer; and an insulation layer interposed between the first electrode pad and the second conductive type semiconductor layer. The LED chip includes the first electrode pad on the second conductive type semiconductor layer, thereby increasing a light emitting area. | 2016-04-28 |
20160118565 | LED SUPPORT ASSEMBLY AND LED MODULE - An LED support assembly and an LED module are provided. The LED support assembly includes: a metal heat sink, a first ceramic substrate and a second ceramic substrate, the metal heat sink defines an upper surface; the first ceramic substrate is adapted to support a LED chip and disposed on the upper surface of the metal heat sink; the second ceramic substrate is adapted to support electrodes of the LED chip and surrounds the first ceramic substrate. | 2016-04-28 |
20160118566 | WEARABLE DEVICE HAVING THERMOELECTRIC GENERATOR - Provided are wearable devices including a thermoelectric generator. The wearable devices include a main body that has at least one opening and a thermoelectric generator that is seated in the opening. The devices include a pair of terminals that are electrically connected to an adjacent thermoelectric generator or a charge unit disposed on the main body, and a supporting member that is situated on a lower part of the thermoelectric generator and contacts the skin of a user, such that the thermoelectric generator includes a high temperature unit and a low temperature unit facing each other, and the high temperature unit is situated on the supporting member and the low temperature unit is disposed to face an outside environment. | 2016-04-28 |
20160118567 | WATER-AND-AIR-COOLED THERMOELECTRIC DEVICE - A water-and-air-cooled thermoelectric device includes water inlet pipes disposed in parallel at an upper side of the thermoelectric device and including a first hot water pipe and a first cool water pipe. Water outlet pipes are disposed in parallel at a lower side of the thermoelectric device and include a second hot water pipe and a second cool water pipe. A plurality of cool water tubes connect the first cool water pipe and the second cool water pipe. Hot water tubes are adjacent to the cool water tubes and connect the first hot water pipe and the second hot water pipe. Thermoelectric elements are disposed between the cool water tubes and the hot water tubes and convert an energy obtained by heat exchange into an electrical energy. A plurality of heat pipes are spaced apart and extend in a direction perpendicular to the hot water tubes. | 2016-04-28 |
20160118568 | Thermoelectric Element, Assembly and Module, In Particular Intended To Generate An Electric Current In A Motor Vehicle - The invention relates to a thermoelectric element comprising at least one opening and a set of apertures. The opening is designed to be in a thermal relationship with a hot source, and the apertures are designed to be in a thermal relationship with a cold source that is of a temperature that is lower than that of the hot source. The thermoelectric element is designed to generate an electric current under the action of a temperature gradient applied by the hot source and the cold source between the opening and the apertures. The invention also relates to a thermoelectric module comprising at least one thermoelectric element. | 2016-04-28 |
20160118569 | Portable Generation and Lighting Device Based on Temperature Difference - A portable lighting device with thermoelectric power generation which includes a thermoelectric power generation module ( | 2016-04-28 |
20160118570 | High Temperature Superconductors - This disclosure relates to compounds of formula (I): | 2016-04-28 |
20160118571 | MONOLITHIC CUPS FOR ULTRASOUND TRANSDUCERS AND METHODS OF MAKING ULTRASOUND TRANSDUCERS - In one aspect, ultrasound transducers are described herein comprising monolithic caps having low acoustic impedance. Such transducers can be safer to use and/or simpler to manufacture. A transducer described herein, in some embodiments, a casing, a transducer element assembly disposed in the casing, an impedance matching layer assembly positioned over the transducer element assembly, and a monolithic thermoplastic cup enclosing the inner impedance matching layer assembly, the monolithic thermoplastic cup comprising side walls extending over side walls of the casing and an impedance matching bottom wall having an acoustic impedance of 1.5 MRayls to 4.0 MRayls. | 2016-04-28 |
20160118572 | METHODS FOR MANUFACTURING ULTRASOUND TRANSDUCERS AND OTHER COMPONENTS - The disclosed technology features methods for the manufacture of electrical components such as ultrasound transducers. In particular, the disclosed technology provides methods of patterning electrodes, e.g. in the connection of an ultrasound transducer to an electrical circuit; methods of depositing metal on surfaces; and methods of making integrated matching layers for an ultrasound transducer. The disclosed technology also features ultrasound transducers produced by the methods described herein. | 2016-04-28 |
20160118573 | Piezoelectric Actuating Device and Valve Equipped Therewith - A piezoelectric actuator device, with at least one piezoelectric transducer which has at least one piezoelectric body and an electrode unit assigned to this piezoelectric body, with overall capacitance and including two electrodes lying opposite one another. At least one of the two electrodes of the electrode unit is divided into several individual sub-electrodes, spaced apart from one another and forming with the electrode lying opposite several sub-electrode pairs defining in each case a partial capacitance of the overall capacitance. A separate current-limiting resistor active during charge flow is connected in series to each sub-electrode pair. A valve, for controlling a fluid, is equipped with such an actuator device. | 2016-04-28 |
20160118574 | FERROELECTRIC CERAMICS, ELECTRONIC COMPONENT AND MANUFACTURING METHOD OF FERROELECTRIC CERAMICS - Ferroelectric ceramics including: a Pb(Zr | 2016-04-28 |
20160118575 | ELECTRONIC DEVICES HAVING SEMICONDUCTOR MAGNETIC MEMORY UNITS - A semiconductor device includes a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer; and a magnetic correction layer disposed over the resistance variable element to be separated from the resistance variable element, and having a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer. | 2016-04-28 |
20160118576 | STORAGE ELEMENT AND MEMORY - A storage element includes a magnetization fixed layer, and a magnetization free layer. The magnetization fixed layer includes a plurality of ferromagnetic layers laminated together with a coupling layer formed between each pair of adjacent ferromagnetic layers. The magnetization directions of the ferromagnetic layers are inclined with respect to a magnetization direction of the magnetization fixed layer. | 2016-04-28 |
20160118577 | PERPENDICULAR MAGNETIC RANDOM-ACCESS MEMORY (MRAM) FORMATION BY DIRECT SELF-ASSEMBLY METHOD - Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask. | 2016-04-28 |
20160118578 | MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a magnetic memory device includes forming a lower magnetic layer, a tunnel barrier layer, and an upper magnetic layer on a substrate, forming a magnetic tunnel junction (MTJ) pattern by patterning the lower magnetic layer, the tunnel barrier layer, and the upper magnetic layer, and irradiating a side wall of the MTJ pattern using a beam including an oxygen ion, wherein, in the forming of the MTJ pattern, a metal redeposition material covering the side wall of the MTJ pattern is formed and the beam is radiated to the metal redeposition material. | 2016-04-28 |
20160118579 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR PRODUCING SAME - A resistive random access memory includes two electrode layers and a resistive switching layer mounted between the two electrode layers. The resistive switching layer consists essentially of insulating material with oxygen, metal material, and mobile ions. The polarity of the mobile ions is opposite to the polarity of oxygen ions. A method for producing a resistive random access memory includes preparing a first metal layer and sputtering a resistive switching layer on the first metal layer. Surface treatment is conducted on the resistive switching layer by using a plasma containing mobile ions to dope the mobile ions into the resistive switching layer. The polarity of the mobile ions is opposite to the polarity of oxygen ions. Then, a second metal layer is sputtered on the resistive switching layer. | 2016-04-28 |
20160118580 | METHOD FOR FORMING RRAM CELL INCLUDING V-SHAPED STRUCTURE - A method of forming an RRAM cell structure is provided. The method includes forming dummy features over a substrate, and the dummy features have a gap therebetween. The method also includes depositing an oxide layer over the dummy features while forming a first V-shaped valley on the oxide layer. The method further includes partially planarizing the oxide layer while leaving the first V-shaped valley. In addition, the method includes forming a first electrode over the oxide layer while forming a second V-shaped valley on the first electrode. The method further includes forming a resistance variable layer over the first electrode in a conformal manner. The method still includes forming a second electrode over the resistance variable layer. | 2016-04-28 |
20160118581 | HETEROJUNCTION OXIDE NON-VOLATILE MEMORY DEVICE - A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer | 2016-04-28 |
20160118582 | PHASE CHANGE MEMORY CELL WITH IMPROVED PHASE CHANGE MATERIAL - A phase change memory cell. The phase change memory cell includes a substrate and a phase change material. The phase change material is deposited on the substrate for performing a phase change function in the phase change memory cell. The phase change material is an alloy having a mass density change of less than three percent during a transition between an amorphous phase and a crystalline phase. | 2016-04-28 |
20160118583 | Logic Compatible RRAM Structure and Process - A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening. | 2016-04-28 |
20160118584 | Low Form Voltage Resistive Random Access Memory (RRAM) - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion. | 2016-04-28 |
20160118585 | Resistive Switching Devices Having a Switching Layer and an Intermediate Electrode Layer and Methods of Formation Thereof - In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node. | 2016-04-28 |
20160118586 | METHOD FOR FORMING STACKED STRUCTURE - A method for forming a stacked structure includes steps of: providing a first layer; oxidizing at least a part of the first layer to form a first oxide layer on the first layer; forming a second layer on the first oxide layer; and forming a second oxide layer between the first oxide layer and the second layer by rapid thermal annealing. | 2016-04-28 |
20160118587 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device includes a substrate which includes a plurality of areas, a plurality of first electrodes disposed on the areas of the substrate, respectively, a second electrode disposed on the first electrodes, and a plurality of emitting layers disposed between the first electrodes and the second electrode. At least two of the emitting layers are disposed on all of the areas. | 2016-04-28 |
20160118588 | DIKETOPYRROLOPYRROLE POLYMER AND ORGANIC ELECTRONIC DEVICE CONTAINING SAME - The present invention relates to a diketopyrrolopyrrole polymer, which is an organic semiconductor compound for an organic electronic device, and a use thereof. The diketopyrrolopyrrole polymer according to the present invention is a novel organic semiconductor compound having high π-electron stacking by introducing an electron donor compound, and an organic electronic device employing the same has excellent charge mobility and on/off ratio. | 2016-04-28 |
20160118589 | Organic Semiconductor Film, Method for Manufacturing Same, and Transistor Structure - Provided is an organic semiconductor film with which a desired band gap can be securely achieved. In an ultrahigh vacuum film formation device ( | 2016-04-28 |
20160118590 | ORGANIC LIGHT-EMITTING DEVICES - An organic light-emitting device including a first electrode; a second electrode; and an organic layer between the first electrode and the second electrode, the organic layer including an emission layer, wherein the emission layer includes a first host represented by Formula 1 and a second host represented by one of Formulae 2-1 to 2-3: | 2016-04-28 |
20160118591 | ORGANIC ELECTROLUMINESCENT DEVICE - An organic electroluminescent device having high efficiency, low driving voltage and a long lifetime is provided by combining various materials for an organic electroluminescent device, which are excellent, as materials for an organic electroluminescent device having high efficiency and high durability, in hole and electron injection/transport performances, electron blocking ability, stability in a thin-film state and durability, so as to allow the respective materials to effectively reveal their characteristics. In the organic electroluminescent device having at least an anode, a hole injection layer, a first hole transport layer, a second hole transport layer, a light emitting layer, an electron transport layer and a cathode in this order, the second hole transport layer includes an arylamine compound represented by the following general formula (1). | 2016-04-28 |
20160118592 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device and a flat panel display apparatus, the device including a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode and including an emission layer, wherein the organic layer includes a hole transport region between the first electrode and the emission layer, the hole transport region including an auxiliary layer and at least one selected from a hole transport layer and a hole injection layer, and an electron transport region between the emission layer and the second electrode, the electron transport region including at least one selected from a hole blocking layer, an electron transport layer, and an electron injection layer, wherein the auxiliary layer includes a compound represented by Formula 1 and a compound represented by Formula 2: | 2016-04-28 |