17th week of 2016 patent applcation highlights part 50 |
Patent application number | Title | Published |
20160118093 | MULTIPLE RETRY READS IN A READ CHANNEL OF A MEMORY - An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads. | 2016-04-28 |
20160118094 | SEMICONDUCTOR APPARATUS CAPABLE OF SELF-TUNNING A TIMING MARGIN - A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal clock signal and an external clock signal, and delay an internal read command by a delay time tuned in the delay locking operation and generate a delay-locked internal command. The semiconductor apparatus may include a tuning control block configured to generate the internal read command in response to a self-tuning enable signal generated by determining a delay locking completion time of the delay-locked loop. The semiconductor apparatus may include a timing tuning block configured to generate delay control signals according to a phase difference of the delay-locked clock signal and the delay-locked internal command, and tune a delay time of the internal read command according to the delay control signals and generate a timing-tuned read command. | 2016-04-28 |
20160118095 | DIE STACK ADDRESS BUS HAVING A PROGRAMMABLE WIDTH - The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information. | 2016-04-28 |
20160118096 | APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES - Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition. | 2016-04-28 |
20160118097 | BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS - A system uses both MOS-based and bipolar-based decoding circuitry in an address decoder for MOS-based memory. The system includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data, and an address decoder including MOS-based circuitry and bipolar logic circuitry. The address decoder is configured to accept a word comprising a plurality of bits and access the array of memory cells using the word. | 2016-04-28 |
20160118098 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer. | 2016-04-28 |
20160118099 | MAGNONIC HOLOGRAPHIC MEMORY AND METHODS - An electronic device using an array of magnetic wave guides is shown. In one example a memory device is shown that utilizes spin waves and a magnet storage element that interacts with the spin waves. In one example, an electronic device is shown that utilizes both a complementary metal oxide device and a magnonic device coupled together. | 2016-04-28 |
20160118100 | DIFFERENTIAL CURRENT SENSING SCHEME FOR MAGNETIC RANDOM ACCESS MEMORY - A circuit includes first and second reference cells and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier for reading bits stored in the first reference cell and the second reference cell. | 2016-04-28 |
20160118101 | APPARATUSES AND METHODS FOR SETTING A SIGNAL IN VARIABLE RESISTANCE MEMORY - An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT memory cell to set a pulse to write the STT memory cell. An example of an apparatus includes a STT memory cell and read/write circuitry coupled to the STT memory cell to determine a read current (I | 2016-04-28 |
20160118102 | METHOD AND APPARATUS FOR WRITING TO A MAGNETIC TUNNEL JUNCTION (MTJ) BY APPLYING INCREMENTALLY INCREASING VOLTAGE LEVEL - A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ. | 2016-04-28 |
20160118103 | SEMICONDUCTOR DEVICE - The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a first comparator circuit outputs a signal DQSIN representing the difference between DQS and DQSB after the coupling of input terminals to a terminal potential and from before the start timing of a preamble of the two signals. A second comparator circuit compares the level of DQS or DQSB with a reference voltage Vref and outputs a signal ODT_DET representing the result of the comparison. A gate circuit masks the signal DQSIN with a signal EW in a masking state. A control circuit identifies the start timing of the preamble based on ODT_DET, and sets the signal EW to the masking state before the start of the preamble and to an unmasking state from the start timing of the preamble. | 2016-04-28 |
20160118104 | VOLATILE MEMORY SELF-DEFRESH - Embodiments of the inventive concept include a volatile memory device including a memory cell array, the memory cell array including multiple rows and/or banks to store data. The memory device can include an address decoder coupled to the memory cell array. The memory device can include a control logic section coupled to the address decoder. The control logic section can include a defresh logic section configured to intentionally violate, by an activate command, a row precharge time (T | 2016-04-28 |
20160118105 | SEMICONDUCTOR DEVICE - Embodiments of the present invention relate to a latch circuit (L | 2016-04-28 |
20160118106 | SEMICONDUCTOR DEVICE - It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells. | 2016-04-28 |
20160118107 | METHODS OF OPERATING SENSE AMPLIFIER CIRCUITS - A method of maintaining a voltage level of a bit line of a sense amplifier circuit includes providing a power supply voltage at a power supply node, receiving the power supply voltage from the power supply node with an NMOS transistor, and maintaining a voltage level of the bit line by supplying sufficient current with the NMOS transistor to compensate a leakage current of the bit line. The method includes receiving the voltage level of the bit line with a noise threshold control circuit, inverting the voltage level with the noise threshold control circuit, and driving a sense amplifier output with the noise threshold control circuit. | 2016-04-28 |
20160118108 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in columns and rows to form a matrix pattern includes read word lines, read bit lines, and read source lines. Each of the plurality of memory cells includes: first and second inverters which are cross-coupled to each other; a first transistor which is connected between a read bit line and a read source line and of which the gate is connected to the output terminal of the first inverter; and a second transistor which is connected in series to the first transistor and of which the gate is connected to a read word line. | 2016-04-28 |
20160118109 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a cell string including dummy memory cells and a plurality of memory cells in which n bit data is stored, and a peripherial circuit configured to store the n bit data in first memory cells, among the memory cells, store n−1 bit data in the rest of second memory cells, and store data which is not stored in the second memory cells in at least one of the dummy memory cells, among the dummy memory cells. | 2016-04-28 |
20160118110 | Simultaneous Multi-Page Commands for Non-Volatile Memories - Mechanisms are provided, in a non-volatile memory device comprising a non-volatile memory and a memory controller, for controlling an operation of the non-volatile memory device. The non-volatile memory device receives a single combined memory command for accessing the non-volatile memory. The non-volatile memory device decodes the row address and the column address for the word-line to be accessed by the single combined memory command. The non-volatile memory device accesses the word-line such that at least a most significant bit (MSB) page and a least significant bit (LSB) page are accessed simultaneously. | 2016-04-28 |
20160118111 | REDUCED LEVEL CELL MODE FOR NON-VOLATILE MEMORY - Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values. | 2016-04-28 |
20160118112 | NONVOLATILE STORAGE REFLOW DETECTION - A non-volatile storage system includes non-volatile storage elements and one or more managing circuits in communication with the non-volatile storage elements. The non-volatile storage elements are arranged in blocks including a first block reserved for system use and a second block. The first block stores a pre-determined data pattern that was written to the first block subsequent to system testing and prior to completion of manufacturing of the non-volatile storage system. Subsequent to completion of manufacturing of the non-volatile storage system, the one or more managing circuits sense information stored in the first block and determine an error metric for the sensed information with respect to the pre-determined data pattern. The one or more managing circuits determine that the system experienced an IR reflow process if the error metric was determined to satisfy the threshold. | 2016-04-28 |
20160118113 | MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINES AND DUAL-GATE BIT LINE SELECT TRANSISTORS - A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis, vertically-oriented bit lines disposed above the global bit lines, word lines disposed above the global bit lines, memory cells coupled between the vertically-oriented bit lines and the word lines, and vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines. Each vertically-oriented bit line select transistor has a width, a first control terminal and a second control terminal. The word lines and the vertically-oriented bit lines have a half-pitch, and the width of the vertically-oriented bit line select transistors is between about two times the half-pitch and about three times the half-pitch. Vertical bit lines disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. | 2016-04-28 |
20160118114 | RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY DEVICE - A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address. | 2016-04-28 |
20160118115 | MULTI-LEVEL MEMORY APPARATUS AND DATA SENSING METHOD THEREOF - A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal. | 2016-04-28 |
20160118116 | FAST READ SPEED MEMORY DEVICE - A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations. | 2016-04-28 |
20160118117 | RESISTIVE MEMORY DEVICE, RESISTIVE MEMORY SYSTEM, AND METHOD OF OPERATING RESISTIVE MEMORY DEVICE - A method of operating a resistive memory device having a plurality of word lines and a plurality of bit lines includes selecting one or more first memory cells connected to a first bit line, selecting one or more second memory cells connected to a second bit line, and simultaneously performing a reset write operation on the first and second memory cells using a first write driver. | 2016-04-28 |
20160118118 | Memory Cells, Methods of Forming Memory Cells, and Methods of Programming Memory Cells - Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another. | 2016-04-28 |
20160118119 | Memory Programming Methods and Memory Systems - Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described. | 2016-04-28 |
20160118120 | RESISTIVE MEMORY SYSTEM, DRIVER CIRCUIT THEREOF AND METHOD FOR SETTING RESISTANCE THEREOF - A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory array, a row selection circuit, a first control circuit and a second control circuit. The memory array has a plurality of resistive memory cells. The row selection circuit is used for activating the resistive memory cells. The first control circuit and the second control circuit are coupled to the resistive memory cells. When each of resistive memory cells is set, the first control circuit and the second control circuit respectively provide a set voltage and a ground voltage to the each of resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit. | 2016-04-28 |
20160118121 | Configurable Volatile Memory Data Save Triggers - A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots. | 2016-04-28 |
20160118122 | VERTICAL STRUCTURE SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes. | 2016-04-28 |
20160118123 | NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, OPERATING METHOD THEREOF - An operating method of a nonvolatile memory device includes determining whether a memory block is a selected block, and when the memory block is not the selected block, determining whether the memory block shares a block word line with the selected block. The method further includes applying an unselected block word line voltage to word lines of the memory block when the memory block shares the block word line with the selected block, and floating the word lines of the memory block when the memory block does not share the block word line with the selected block. | 2016-04-28 |
20160118124 | Direct-Transfer Marching Memory And A Computer System Using The Same - A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information of byte size or word size, the information of byte size or word size is transferred synchronously, step by step, along a direction orthogonal to a direction of the sequence of bit-level cells, each of the bit-level cells encompassing an electron-storage region configured to accumulate cell-electrons. The cell-electrons accumulated in an electron-storage region in a subject memory unit is directly transferred to an adjacent electron-storage region, which is assigned in the next memory unit adjacent to the subject memory unit, the transfer of the cell-electrons is directly controlled by control signals, without using a combinational function of a logic gate circuit. | 2016-04-28 |
20160118125 | COMPACTION PROCESS FOR A DATA STORAGE DEVICE - A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for a compaction process. The source compaction block stores data. The method may further include writing the data to a destination compaction block of the memory at a rate that is based on a number of multiple blocks of the memory associated with the compaction process. | 2016-04-28 |
20160118126 | NONVOLATILE MEMORY DEVICES AND PROGRAM METHOD THEREOF - A program method of a nonvolatile memory device is provided which includes programming memory cells to a target state using a verification voltage and an incremental step pulse, selecting memory cells, each having a threshold voltage lower than a supplementary verification voltage, from among the memory cells programmed to the target state, and applying a supplementary program voltage to the selected memory cells. The supplementary verification voltage is equal to or higher than the verification voltage, and the supplementary program voltage is equal to or lower than a program voltage provided in a program loop where a programming of the memory cells to the target state is completed. | 2016-04-28 |
20160118127 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage. | 2016-04-28 |
20160118128 | METHODS FOR REDUCING BODY EFFECT AND INCREASING JUNCTION BREAKDOWN VOLTAGE - Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of the transistor are described. The transistor may comprise an NMOS transistor that transfers a programming voltage (e.g., 24V) to a word line of a memory array during a programming operation. In some cases, a first poly shield may be positioned within a first distance of a gate of the transistor and may comprise a first polysilicon structure that is directly adjacent to the gate of the transistor. The first poly shield may be arranged in a first direction (e.g., in the channel length direction of the transistor). The first poly shield may be biased to a first voltage greater than ground (e.g., 10V) during the programming operation to reduce an increase in the threshold voltage of the transistor due to the body effect. | 2016-04-28 |
20160118129 | READ VOLTAGE ADJUSTMENT - The present disclosure includes apparatuses and methods related to adjusting read voltages of charge-trapping flash memory. An example embodiment apparatus can include a memory array and a controller coupled to the memory array. The controller is configured to adjust a read voltage used to access a portion of the memory array based on a length of time since a last WRITE operation to the portion. | 2016-04-28 |
20160118130 | PERFORMANCE ACCELERATION DURING SHUTDOWN OF A DATA STORAGE DEVICE - A storage device may include a non-volatile memory; and a controller. The controller may be configured to: operate the data storage device in a standard mode by at least throttling performance, and, responsive to detecting a power loss condition, operate the data storage device in a shutdown mode by at least disabling the throttling. | 2016-04-28 |
20160118131 | Adaptive Program Pulse Duration Based On Temperature - Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce the upshift in the threshold voltage (Vth) of erased-state memory cells. A minimum allowable program pulse duration increases with temperature to account for an increase in the attenuation of a program pulse along a word line. A program pulse duration which accounts for reduced channel boosting at relatively high temperatures is reduced as the temperature increases. An optimum program pulse duration is based on the larger of these durations. The optimum program pulse duration can also be based on factors such as a measure of program disturb or a memory hole width. Program disturb can also be reduced by easing the requirements of a verify test for the highest data state. | 2016-04-28 |
20160118132 | Low Impact Read Disturb Handling - A storage device system receives read commands from a host device and maintains a read disturb count for distinct zones of each of a plurality of non-volatile memory blocks in the storage device. The read disturb count for each zone corresponds to read operations performed in the zone and in predefined memory portions neighboring the zone. In accordance with a determination that the read disturb count for any zone satisfies predefined threshold criteria, the storage device performs a validation operation on one or more memory portions corresponding to that zone. If the validation operation is unsuccessful, the storage device resets the read disturb count for the zone and initiates a refresh operation on at least a portion of the corresponding block. If the validation operation is successful, the storage device resets the read disturb count for the zone that satisfied the predefined threshold criteria, and forgoes initiating the refresh operation. | 2016-04-28 |
20160118133 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL. | 2016-04-28 |
20160118134 | WORD LINE DEPENDENT TWO STROBE SENSING MODE FOR NONVOLATILE STORAGE ELEMENTS - A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements. | 2016-04-28 |
20160118135 | TWO-STROBE SENSING FOR NONVOLATILE STORAGE - A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements. | 2016-04-28 |
20160118136 | ERROR DETECTION METHOD - Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming operation or an erase operation. In some cases, a Control Gate Short to Substrate (CGSS) defect, in which a control gate of a NAND memory has been shorted to the substrate, may have a defect signature in which a word line shows a deviation in the number of programming loop counts associated with programming data into memory cells connected to the word line. The deviation in the number of programming loop counts may be detected by comparing a baseline programming loop count (e.g., derived from programming a set of one or more word lines prior to programming the word line with the CGSS defect) with a programming loop count associated with programming the word line with the CGSS defect. | 2016-04-28 |
20160118137 | REDUCTION OF POWER CONSUMPTION IN FLASH MEMORY - Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate estimator module may estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. A voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory. | 2016-04-28 |
20160118138 | PROGRAMMING AN ELECTRICAL FUSE WITH A SILICON-CONTROLLED RECTIFIER - Circuits for programming an electrical fuse, methods for programming an electrical fuse, and methods for designing a silicon-controlled rectifier for use in programming an electrical fuse. A programming current for the electrical fuse is directed through the electrical fuse and the silicon-controlled rectifier. Upon reaching a programmed resistance value for the electrical fuse, the silicon-controlled rectifier switches from a low-impedance state to a high-impedance state that interrupts the programming current. | 2016-04-28 |
20160118139 | SEMICONDUCTOR DEVICES - A semiconductor device may include a fuse controller and a fuse array. The fuse controller may be configured to generate internal address signals according to a level combination of repair data and may generate first and second voltage control signals in response to a rupture control signal that is enabled to rupture a predetermined fuse set for selecting a failed redundancy word line, in a test mode. The fuse array may include a plurality of fuse sets including the predetermined fuse set. Each of the plurality of fuse sets may be selected according to a level combination of the internal address signals, and the fuse array ruptures the predetermined fuse set for selecting the failed redundancy word line in response to the first and second voltage control signals to output fuse data. | 2016-04-28 |
20160118140 | SEMICONDUCTOR DEVICE - A semiconductor device includes a word line coupled to a mask ROM memory cell, a bit line pair coupled to the memory cell, a differential sense amplifier for amplifying the potential difference of the bit line pair, and a logic circuit for detecting whether the logic states of the bit line pair match or not. In this way, when there is a failure in the memory cell, it is possible to prevent the semiconductor device from passing the test as a result of the determination that the actual value is the same as the expected value in the test even if there is no potential difference in the bit line pair. | 2016-04-28 |
20160118141 | METHOD AND DEVICE FOR EVALUATING A CHIP MANUFACTURING PROCESS - A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit. | 2016-04-28 |
20160118142 | MEMORY DEVICE AND METHOD FOR TESTING RELIABILITY OF MEMORY DEVICE - A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device. | 2016-04-28 |
20160118143 | THRESHOLD VOLTAGE MARGIN ANALYSIS - The present disclosure is related to a threshold voltage margin analysis. An example embodiment apparatus can include a memory and a controller coupled to the memory. The controller is configured to determine a previous power loss of a memory to be an asynchronous power loss, and identify a portion of the memory last subject to programming operations during the determined asynchronous power loss. The controller is further configured to perform a threshold voltage (Vt) margin analysis on the portion of the memory responsive to the determined asynchronous power loss. | 2016-04-28 |
20160118144 | HYDROGEN-LITHIUM FUSION DEVICE - The Hydrogen-Lithium Fusion Device (HLFD) includes a plasma generator that generates proton-lithium plasma within a reaction chamber. The plasma generator includes a proton source and lithium source. In one implementation, bias voltage is applied within the reaction chamber. The bias voltage enables protons to fuse with lithium ions in the proton-lithium plasma, whereby energetic helium ion fusion byproducts are produced. Multiple configurations of reaction chambers containing protons and lithium ions under conditions that yield proton-lithium fusion are disclosed. | 2016-04-28 |
20160118145 | System for Regulating a Liquid in a Circuit - This invention relates to a system for regulating a liquid in a circuit able to reverse the direction of the circulation, with the system comprising: a regulating valve comprising at least one inlet and one outlet and comprising a movable obturator the position of which makes it possible to adjust the flow rate of the liquid through the valve, an expansion reservoir in communication with the liquid flowing in the circuit and intended to contain liquid and a compensating gas, characterised in that: the expansion reservoir is connected to the circuit by the intermediary of the valve and in such a way that the expansion reservoir communicates with at least one from among the inlet and the outlet of the valve regardless of the position of the obturator, with the position of the obturator being independent of the pressure of the fluid in the expansion reservoir. The invention also relates to a circuit integrating this system as well as a use of this system. | 2016-04-28 |
20160118146 | SYSTEMS AND METHOD FOR REDUCING TRITIUM MIGRATION - A system and method for reducing tritium migration. In one aspect, the invention is a method of reducing tritium mitigation from a spent nuclear fuel pool containing a body of tritiated water having an exposed surface, the method comprising hermetically sealing the exposed surface of the body of tritiated water with a cover movable between an open-state and a close-state. | 2016-04-28 |
20160118147 | Passive System for Cooling the Core of a Nuclear Reactor - A system for passively cooling nuclear fuel in a pressurized water reactor during refueling that employs gravity and alignment of valves using battery reserves or fail in a safe position configurations to maintain the water above the reactor core during reactor disassembly and refueling. A large reserve of water is maintained above the elevation of and in fluid communication with the spent fuel pool and is used to remove decay heat from the reactor core after the reaction within the core has been successfully stopped. Decay heat is removed by boiling this large reserve of water, which will enable the plant to maintain a safe shutdown condition without outside support for many days. | 2016-04-28 |
20160118148 | HEAT TRANSFER METHODS FOR NUCLEAR PLANTS - A method of transferring heat from a nuclear plant may include: connecting a heat transfer system to the nuclear plant; and using the heat transfer system to transfer heat from the nuclear plant. The heat transfer system may include: a piping system that includes first and second connectors; a heat exchanger; a pump; and a power source. The heat transfer system may not be connected to the nuclear plant during normal plant power operations. The power source may be independent of a normal electrical power distribution system for the nuclear plant. The power source may be configured to power the pump. The piping system may be configured to connect the heat exchanger and pump. The first and second connectors may be configured to connect the heat transfer system to a fluid system of the nuclear plant. | 2016-04-28 |
20160118149 | EMISSION MONITORING SYSTEM FOR A VENTING SYSTEM OF A NUCLEAR POWER PLANT AND NUCLEAR POWER PLANT HAVING THE EMISSION MONITORING SYSTEM - An emission monitoring system for a venting system of a nuclear power plant is configured for low consumption of energy while having high reliability of measurement results. The emission monitoring system has a pressure relief line connected to a containment and contains a high-pressure section, a low-pressure section, and a sampling line, which, on the inlet side, opens into the low-pressure section of the pressure relief line and is guided from there to a functional path through which steam flows. An ejector containing a pump fluid connector, a suction connector and an outlet connector is provided. A pump fluid feed line has an inlet side opening into the high-pressure section of the pressure relief line and is guided from there to the ejector and connected to the pump fluid connector. A sample return line is guided from the functional path to the ejector and connected to the suction connector. | 2016-04-28 |
20160118150 | Method and Apparatus for the Shielded Relocation of a Nuclear Component - A nuclear component transfer device that incorporates a shielded canister into the mast design of a conventional nuclear refueling machine. A moveable mast telescopes within a stationary mast which is attached to a bridge for lateral positioning. The canister allows for the addition of shielding that is positioned with the movement of the moveable mast without additional motorized components to deploy the shielding during nuclear component movement. The nuclear component is drawn up into the shielded canister as the moveable mast lifts the nuclear component. The nuclear component is then placed into a transfer cart that is also fitted with a shielded canister. The transfer is made without exposing the nuclear components resulting in completely shield movement. | 2016-04-28 |
20160118151 | COMPOSITE METAL FOAM AND METHOD OF PREPARATION THEREOF - The present invention is directed to composite metal foams comprising hollow metallic spheres and a solid metal matrix. The composite metal foams show high strength, particularly in comparison to previous metal foams, while maintaining a favorable strength to density ratio. The composite metal foams can be prepared by various techniques, such as powder metallurgy and casting. | 2016-04-28 |
20160118152 | SYSTEM AND METHOD FOR PREPARING A CONTAINER LOADED WITH WET RADIOACTIVE ELEMENTS FOR DRY STORAGE - A system for preparing a container holding radioactive waste for dry storage. In one aspect, the invention can be a system for preparing a container having a cavity loaded with radioactive elements for dry storage, the system comprising: a gas circulation system comprising a condenser module, a desiccant module, and a gas circulator module; the gas circulation system configured to form a hermetically sealed closed-loop path when operably connected to the cavity of the container; and means for adding and removing the desiccant module as part of the hermetically sealed closed-loop path. | 2016-04-28 |
20160118153 | CAPTURE, REMOVAL, AND STORAGE OF RADIOACTIVE SPECIES - A method of capturing radioactive species from an aqueous solution and removing the radioactive species for disposal, includes: contacting the aqueous solution with a first sequestration resin comprising a sequestration ligand coupled to a sulfonic acid based polymer resin backbone, to allow the first sequestration resin to capture the radioactive species; removing the first sequestration resin with the captured radioactive species from the aqueous solution; and using an acid to lower a pH of the first sequestration resin to release the radioactive species from the first sequestration resin. | 2016-04-28 |
20160118154 | SILICON/CARBON COMPOSITE, SILICON ALLOY/CARBON COMPOSITE, AND METHODS FOR PRODUCING THE SAME - A silicon/carbon composite or a silicon alloy/carbon composite is formed with a homogeneous silicon-containing thin film or silicon-containing alloy thin film on the surface of a conductive carbon material, where the composite may be used for a large-capacity electrical storage device when used as a negative electrode material for forming an electrical storage device negative electrode, and exhibits excellent charge-discharge cycle characteristics. A carbon-containing thin film is formed on a surface of a conductive carbon material by chemical vapor deposition (CVD) that utilizes a carbon-containing gas and a silicon-containing thin film or a silicon-containing alloy thin film is formed on the conductive carbon material by chemical vapor deposition (CVD) that utilizes a silicon-containing gas alone, or utilizes a silicon-containing gas and a carbon-containing gas. | 2016-04-28 |
20160118155 | CONDUCTIVE PASTE, METHOD OF PRODUCING CONDUCTIVE PATTERN, AND TOUCH PANEL - A conductive paste includes a conductive filler (A), a zwitterionic compound (B) and a thermosetting compound (C); a method of producing a conductive pattern including applying the conductive paste to obtain a coating film, drying the coating film to obtain a dried film, exposing and developing the dried film to obtain a pattern, and curing the pattern at 100 to 200° C. to obtain a conductive pattern; and an electrostatic capacitance type touch panel including as peripheral wiring the conductive pattern produced by the method of producing the conductive pattern. | 2016-04-28 |
20160118156 | METAL NANOWIRE-CONTAINING COMPOSITION - The present invention provides a metal nanowire-containing composition that has high compatibility between high preservation stability and coating suitability and that can produce a coating film having high compatibility among high conductivity, high transparency, and low turbidity and high compatibility among high abrasion resistance, water resistance, alcohol resistance, and adhesiveness to a substrate. The metal nanowire-containing composition contains a metal nanowire, a binder, a surfactant, and a solvent, wherein the binder contains a binder component (A) being a polysaccharide; and a binder component (B) being at least one selected from aqueous polyester resins, aqueous polyurethane resins, aqueous acrylic resins, and aqueous epoxy resins. | 2016-04-28 |
20160118157 | CARBON NANOTUBE COMPOSITE CONDUCTORS - Provided are composites that exhibit improved conductivity characteristics as compared to existing conductors. The disclosed conductive composites include a substrate—e.g., a wire that is surmounted by a coating of carbon nanotubes. Substrates may be metals, ceramics, polymers (conducting, non-conducting, and semiconducting) The composites may also include metallic, ceramic, or polymeric materials—such as nanoparticles—that are disposed on or even disposed within the nanotube coatings. Also provided are related methods of fabricating the disclosed composites. | 2016-04-28 |
20160118158 | CORE MATERIAL FOR VACUUM INSULATOR, COMPRISING ORGANIC SYNTHETIC FIBER, AND VACUUM INSULATOR CONTAINING SAME - There are provided a core material for vacuum insulator comprising an organic synthetic fiber, and at least one organic synthetic fiber bonded portion; and a preparation method therefor. In addition, provided is a vacuum insulator comprising the core material for vacuum insulator comprising the organic synthetic fiber, and the at least one organic synthetic fiber bonded portion. | 2016-04-28 |
20160118159 | INSULATED ELECTRICAL WIRE AND COAXIAL CABLE - An object is to provide an insulated electrical wire and a coaxial cable that have good adhesion between a conductor and an insulating layer and excellent properties such as low dielectric constant and high heat resistance, and are suitable for reducing the diameter. The present invention provides an insulated electrical wire that includes a conductor and an insulating layer covering a circumferential surface of the conductor, in which the insulating layer is composed of a resin composition that contains poly(4-methyl-1-pentene) as a main component and a melt mass flow rate of the poly(4-methyl-1-pentene) measured at a temperature of 300° C. and a load of 5 kg according to JIS-K7210:1999 is 50 g/10 min or more and 80 g/10 min or less. | 2016-04-28 |
20160118160 | Wire Structure Improvement - A wire structure improvement comprises a first ground layer on which a first insulation layer is placed and plural transmission conductors and plural ground conductors are orderly arranged in the first insulator next to the first ground layer. A second insulation layer is disposed on the transmission conductors and the ground conductors opposite to the first insulation layer, and a second ground layer is disposed on the second insulator. The first ground layer and the second ground layer are interconnected through the ground conductors. In general, the structure improvement of the wire features cost down, boosting production pace and transmission rate and diminishing electromagnetic interference, radio interference and common mode impedance. | 2016-04-28 |
20160118161 | APPARATUS AND METHOD FOR CABLE DYNAMICS SUPPRESSION VIA NON-LINEAR FLEXURES - Method and apparatus for suppressing cable dynamics in a device towed in water. The apparatus includes at least one section for suppression of motion, wherein the at least one section includes an axial motion suppression section; and the axial motion suppression section comprising equipment for the attenuation of axial vibrations in an electro-mechanical cable. The equipment is configured to produce a digressive stiffness curve. | 2016-04-28 |
20160118162 | CODING SYSTEM AND I/O MODULE OF AN AUTOMATION DEVICE HAVING SUCH A CODING SYSTEM - The invention relates to a coding system comprising at least one assembly of a plurality of individual wires, wherein one end of each individual wire is connected to a common adapter which is to be connected to an I/O module of an automation device for coupling an external device to a control unit of an automation system, and wherein the assembly of individual wires is bundled into at least two cables emanating from the common adapter, and is color-coded. | 2016-04-28 |
20160118163 | PRODUCTION METHOD FOR COATED STRING-SHAPED BODY - A method for manufacturing a covered string-like object, the method comprising a placement step of placing a string-like object on a sheet-like flexible backing, a sewing step of sewing the string-like object to the backing with an embroidery material, and a separation step of separating the backing from the string-like object. According to the method for manufacturing a string-like object, a string-like object can be easily and reliably covered with an embroidery material. | 2016-04-28 |
20160118164 | RESISTOR AND MANUFACTURING METHOD - There is provided a resistor in which a first resistive part of a resistive element that electrically conducts between a pair of electrodes formed on either end of an insulating substrate has a meandering pattern meandering on the substrate surface and a swelling pattern that has a form in which a part of the meandering pattern swells out from the stroke width of the meandering pattern, a second resistive part that is electrically connected in series to the first resistive part is shorter than the entire length of the first resistive part, and has a wider width than the stroke width of the meandering pattern, and a trimming groove is formed in at least either the swelling pattern or the second resistive part. This can improve resistance accuracy and provide a high voltage resistor with high withstand voltage property. | 2016-04-28 |
20160118165 | METAL NITRIDE MATERIAL FOR THERMISTOR, METHOD FOR PRODUCING SAME, AND FILM TYPE THERMISTOR SENSOR - Provided are a metal nitride material for a thermistor, which has a high heat resistance and a high reliability and can be directly deposited on a film or the like without firing, a method for producing the same, and a film type thermistor sensor. The metal nitride material for a thermistor consists of a metal nitride represented by the general formula: V | 2016-04-28 |
20160118166 | PTC THERMISTOR MEMBER - A PTC thermistor device has a PTC thermistor member and electrodes. The electrodes, are formed on respective surfaces of the PTC thermistor member. The PTC thermistor member contains a matrix phase, and conductive particles dispersed throughout the matrix phase. The matrix phase contains an electrically insulating first inorganic material and an electrically insulating second inorganic material. The first inorganic material undergoes phase transition in terms of crystal structure type and change in volume, at the phase transition temperature thereof. The second inorganic material is fibrous. | 2016-04-28 |
20160118167 | MAGNETODIELECTRIC Y-PHASE STRONTIUM HEXAGONAL FERRITE MATERIALS FORMED BY SODIUM SUBSTITUTION - Disclosed herein are embodiments of an enhanced resonant frequency hexagonal ferrite material and methods of manufacturing. The hexagonal ferrite material can be Y-phase strontium hexagonal ferrite material. In some embodiments, sodium can be added into the crystal structure of the hexagonal ferrite material in order to achieve high resonance frequencies while maintaining high permeability. | 2016-04-28 |
20160118168 | INCORPORATION OF OXIDES INTO FERRITE MATERIAL FOR IMPROVED RADIO RADIOFREQUENCY PROPERTIES - Disclosed herein are embodiments of an enhanced resonant frequency hexagonal ferrite material and methods of manufacturing. The hexagonal ferrite material can be Y-phase hexagonal ferrite material, such as those including strontium. In some embodiments, oxides consistent with the stoichiometry of Sr | 2016-04-28 |
20160118169 | Grain Boundary Engineering - Methods, systems, and apparatus, including computer programs encoded on computer storage media, for creating magnetic material. One of the methods may make a compound that includes at least one of: i) an amount of Nd in a range of [6.1717, 11.8917] (at. %), inclusive, ii) an amount of Pr in a range of [1.5495, 4.821] (at. %), inclusive, or iii) an amount of Dy in a range of [0.2132, 5.3753] (at. %), inclusive, and an amount of Co in a range of [0, 4.0948] (at. %), inclusive, an amount of Cu in a range of [0.0545, 0.2445] (at. %), inclusive, and an amount of Fe in a range of [81.1749, 85.867] (at. %), inclusive. | 2016-04-28 |
20160118170 | INCREASED RESONANT FREQUENCY POTASSIUM-DOPED HEXAGONAL FERRITE - Disclosed herein are embodiments of an enhanced resonant frequency hexagonal ferrite material and methods of manufacturing. The hexagonal ferrite material can be Y-phase strontium hexagonal ferrite material. In some embodiments, strontium can be substituted out for a trivalent or tetravalent ion composition including potassium, thereby providing for advantageous properties. | 2016-04-28 |
20160118171 | INCREASED RESONANT FREQUENCY ALKALI-DOPED Y-PHASE HEXAGONAL FERRITES - Disclosed herein are embodiments of an enhanced resonant frequency hexagonal ferrite material, such as Y-phase hexagonal ferrite material, and methods of manufacturing. In some embodiments, sodium or potassium can be added into the crystal structure of the hexagonal ferrite material in order to achieve improved resonant frequencies in the range of 500 MHz to 1 GHz useful for radiofrequency applications. | 2016-04-28 |
20160118172 | Superconducting Coil Device With Coil Winding And Production Method - A superconducting coil device includes a superconducting flat conductor having one or more torsional turns. The flat conductor is wound around a winding support to define multiple turns of the conductor around the support. In at least one of the turns, the flat conductor is twisted through approximately 180 degrees about a longitudinal axis of the flat conductor, to thereby switch a contact side of the flat conductor from radially inwardly facing to radially outwardly facing, or vice versa. The contact side of the flat conductor at an inner turn faces a center of the winding and, and at an outer turn faces away from the center of the winding. The inwardly-facing contact side of the strip at an inner turn may be coupled to an inner contact element, and the outwardly-facing contact side at an outer turn may be conductively coupled to an outer contact element. | 2016-04-28 |
20160118173 | REMOTE CONTROL KIT - A remote control kit includes a magnetic holder and a remote control, wherein the magnetic holder includes a magnet and a non-slip member which covers the magnet. The remote control includes a case and a ferromagnetic member therein. The magnetic holder is fixed on a wall where the remote control is ready to be placed. The ferromagnetic member of the remote control is made of a material selected form the group consisting of iron, cobalt, and nickel, and therefore the remote control can be attached onto the magnetic holder via magnetic force. | 2016-04-28 |
20160118174 | ELECTROMAGNETIC ACTUATING APPARATUS - An electromagnetic actuating apparatus, in particular a proportional magnet or switching magnet, comprising a magnet armature ( | 2016-04-28 |
20160118175 | CONVERTER UNIT, PARTICULARLY A COMBINATION CONVERTER - A converter unit includes: a housing with a moulded-on hollow cylinder that extends into the housing; a non-magnetic toroidal core supporting a first secondary winding, contacting the housing bottom concentrically with the hollow cylinder and is embedded in a solid compound; a magnetic toroidal core supporting a second secondary winding, arranged concentrically with the hollow cylinder above the non-magnetic toroidal coil; and a casting compound with which the housing opening is closed. To achieve a compact converter unit, a first planar spacing element is arranged between the first and the second secondary windings, directly contacting the first secondary winding and the second secondary winding. In addition, electrically insulating particles fill out the space between the second secondary winding and the housing wall, and the casting compound extends at least up to the particles, which lie at the top towards the housing opening. | 2016-04-28 |
20160118176 | SURFACE MOUNTABLE, TOROID MAGNETIC DEVICE - A surface mountable, toroid magnetic device is provided, the device having a potting filling the central hole of the toroid. The potting extends axially beyond the base of the toroid to form a contact surface which, in use, contacts a mounting body for the device. Heat generated by the device flows by conduction through walls of the toroid defining the central hole into the potting and thence through the contact surface into the mounting body. | 2016-04-28 |
20160118177 | MAGNETIC CORE COMPONENT AND GAP CONTROL METHOD THEREOF - There is provided a magnetic core component and the gap control method thereof. The magnetic core component includes a first magnetic component, a second magnetic component and a first gap control structure disposed therebetween. The first gap control structure includes thixotropic material and is applied on the first magnetic component and is cured, the second magnetic component is disposed on the cured first gap control structure, and a gap between the first magnetic component and the second magnetic component is controlled by an effective height of the first gap control structure. The gap control structure has minimum variability after it is cured, and its effective height can be always kept at a required gap height. | 2016-04-28 |
20160118178 | CHIP INDUCTOR - Disclosed herein is a chip inductor. The chip inductor according to the present invention includes a substrate on which a trough-hole is formed, a conductive coil that is formed on the substrate, an upper resin composite magnetic layer that is filled to surround the conductive coil so that a core is formed on a center portion of the substrate, a lower resin composite magnetic layer that is formed on a bottom portion of the substrate, and an external electrode that is formed on both sides of the upper and lower resin composite magnetic layers. | 2016-04-28 |
20160118179 | WIRELESS POWER TRANSFER DEVICE AND WIRELESS CHARGING SYSTEM HAVING SAME - According to an embodiment of the present invention, a wireless power transmitter comprises a base station configured to supply power to a portable electronic device, a coil formed in a manner of winding a wire and configured to convert a current into a magnetic flux, and a shielding unit configured to shield the base station from a magnetic field generated in the coil, wherein the coil has a triangular shape and is formed into a single layer. | 2016-04-28 |
20160118180 | TRANSFORMER WITH TWO TRANSFORMATION RATIO - A transformer includes a first winding conductor and a second winding conductor, magnetically coupled to the first winding conductor. A first transformation ratio is achieved between the second winding conductor and the first winding conductor. A first distance between the first winding conductor and the second winding conductor is higher than a distance threshold, and accordingly, a first coupling factor between the first winding conductor and the second winding conductor is lower than a coupling factor threshold. | 2016-04-28 |
20160118181 | Transformers - A transformer may comprise a winding wrapped around a magnetic core, the winding having at least one winding portion extending between the magnetic core and the exterior of the winding in radial direction. The winding may comprise at least a first conductor and at least a second conductor, arranged radially adjacent to each other in each winding portion with the interposition of an insulating layer, wherein the first conductor is arranged radially inwardly with respect to the second conductor for part of each winding portion length, and radially outwardly with respect to the second conductor for another part of each winding portion length. | 2016-04-28 |
20160118182 | ELECTRICAL CONNECTION APPARATUS - A contactless electrical connection apparatus that has a simple structure and can cover a broad spectrum is provided. The electrical connection apparatus is configured including a pair of connectors each having a conductive portion shaped as a loop that has a winding number of | 2016-04-28 |
20160118183 | COIL COMPONENT - A core of a coil component is formed of a first flange, a second flange, and a winding core connecting the first flange and the second flange to each other. A winding is wound around the winding core. The core is formed of a first part and a second part, the second part having a smaller magnetic permeability and a higher rigidity than the first part. The second part is formed of an end portion of the first flange on one side in an extension direction of the first flange and an end portion of the second flange on one side in an extension direction of the second flange. | 2016-04-28 |
20160118184 | INDUCTOR - An inductor including: a core having a winding core portion for winding a winding wire and two flange portions disposed on both ends of the winding core portion; and a winding wire wound around the winding core portion for multiple layers, the winding wire including: a forward winding layer having multiple turns on the winding core portion along a forward direction from one of the two flange portions toward the other flange portion; a backward winding layer following the forward winding layer and having at least one turn on the forward winding layer along a backward direction opposite to the forward direction; and a return winding portion following the backward winding layer and passing over the backward winding layer in the forward direction to reach the winding core portion on the forward direction side of the forward winding layer within less than 1/2 turn. | 2016-04-28 |
20160118185 | REACTOR AND MANUFACTURING METHOD OF REACTOR - A reactor ( | 2016-04-28 |
20160118186 | Hardened Inductive Device And Systems And Methods For Protecting The Inductive Device From Catastrophic Events - A hardened inductive device and systems and methods for protecting the inductive device from impact is provided. The inductive device is hardened with protective coating and/or an armor steel housing. The hardened inductive device is protected from impact by an object such as a bullet and leakage of dielectric fluid is prevented. Acoustic and vibration sensors are provided to detect the presence and impact, respectively, of an object in relation to the inductive device housing. The measurements of the acoustic and vibration sensors are compared to thresholds for sending alarms to the network control center and initiating shut-down and other sequences to protect the active part. The acoustic sensor results are utilized to determine the location of origin of the projectile. | 2016-04-28 |
20160118187 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes: a ceramic body; first and second internal electrodes disposed so as to be alternately exposed to both end surfaces of the ceramic body with each of dielectric layers; first and second external electrodes formed so as to be extended onto portions of one main surface of the ceramic body, respectively; third and fourth external electrodes formed on both side surfaces of the ceramic body, respectively, so as to be extended onto portions of both main surfaces of the ceramic body, respectively; an intermitting part connecting the third and fourth external electrodes to one another; first and second land patterns formed so as to be connected to the first and third external electrodes, respectively; and a third land pattern formed so as to be connected to both of the second and fourth external electrodes. | 2016-04-28 |
20160118188 | MULTILAYER CERAMIC CAPACITOR AND METHOD FOR PRODUCING THE SAME - A dielectric ceramic that forms dielectric ceramic layers of a multilayer ceramic capacitor contains a Ba and Ti containing perovskite compound, Ca, R (R denotes a rare earth element, such as La), M (M denotes Mn or the like), and Si. The Ca content ranges from 0.5 to 2.5 molar parts, the R content ranges from 0.5 to 4 molar parts, the M content ranges from 0.5 to 2 molar parts, and the Si content ranges from 1 to 4 molar parts, based on 100 molar parts of Ti. In perovskite crystal grains, the Ca diffusion depth is 10% or less of the average grain size of the crystal grains, and the Ca concentration in a Ca diffusion region is 0.2 to 5 molar parts higher than the Ca concentration near the center of each of the crystal grains. | 2016-04-28 |
20160118189 | TANTALUM CAPACITOR - There is provided a tantalum capacitor including: a tantalum capacitor body; a plurality of tantalum wires and an adhesive layer on a lower surface of the tantalum capacitor body; and a molding part enclosing the tantalum capacitor body, wherein the tantalum wire and the adhesive layer are connected to an anode lead frame and a cathode lead frame, respectively. | 2016-04-28 |
20160118190 | MULTILAYER CERAMIC ELECTRONIC COMPONENT AND BOARD HAVING THE SAME - There is provided a multilayer ceramic electronic component including: a multilayer ceramic capacitor (MLCC) including first and second external electrodes disposed to be spaced apart from one another on a mounting surface thereof; and first and second terminal electrodes including upper horizontal portions disposed on lower surfaces of the first and second external electrodes, lower horizontal portions disposed to be spaced apart from the upper horizontal portions downwardly, and curved vertical portions connecting one ends of the upper horizontal portions and one ends of the lower horizontal portions, having “⊂” and “⊃” shapes, and disposed on the mounting surface of the MLCC in a facing manner. | 2016-04-28 |
20160118191 | MULTILAYER CERAMIC CAPACITOR - A multilayer ceramic capacitor includes a ceramic multilayer body including dielectric ceramic layers and inner electrodes laminated with the dielectric ceramic layers interposed therebetween, wherein the dielectric ceramic layers include a perovskite compound containing Ba and Ti, and the inner electrodes (a) contain Ni as a main component, (b) include segregation with the perovskite compound containing Ba and Ti, which is scattered in the inner electrodes and embedded in the inner electrodes, in amount equal to or higher than about 2%, and (c) include columnar segregation with the perovskite compound containing Ba and Ti, which penetrates through the inner electrodes from one main surface side to the other main surface side, in an amount equal to or lower than about 5%, or do not include the columnar segregation. Further, an average thickness of the inner electrodes is equal to or smaller than about 0.4 μm. | 2016-04-28 |
20160118192 | Electronic Component - An electronic component includes a multilayer capacitor and an interposer. The multilayer capacitor includes an element body and a pair of external electrodes. The interposer includes a substrate having first and second principal faces, a pair of first electrodes disposed on the first principal face, and a pair of second electrodes disposed on the second principal face so as to be separated from the pair of first electrodes in a first direction or in a second direction. Widths of the pair of external electrodes and the pair of first electrodes are smaller than a width of the element body. The element body has a first portion covered by the external electrode, and a pair of second portions located on both sides of the first portion. The pair of second portions are separated from the interposer and overlap the pair of second electrodes when viewed from a third direction. | 2016-04-28 |