17th week of 2011 patent applcation highlights part 14 |
Patent application number | Title | Published |
20110095298 | Electronic Paper - An object of the present invention is to increase the resistance of electronic paper to external stress. The resistance to external stress is increased by providing an element formation layer, which includes an integrated circuit portion, a first electrode, a second electrode, and a charged particle-containing layer, between a first insulating film including a first structure body in which a first fibrous body is impregnated with a first organic resin, and a second insulating film including a second structure body in which a second fibrous body is impregnated with a second organic resin. | 2011-04-28 |
20110095299 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - Disclosed herein is a display device, including: a substrate; a circuit part configured to include a drive element formed over the substrate; a planarization insulating layer configured to be formed on the circuit part; an electrically-conductive layer configured to be formed on the planarization insulating layer and include a plurality of first electrodes and an auxiliary interconnect; an aperture-defining insulating layer configured to insulate the plurality of first electrodes from each other and have an aperture through which part of the first electrode is exposed; a plurality of light emitting elements configured to be formed by stacking the first electrode, an organic layer including a light emitting layer, and a second electrode in that order; and a separator configured to be formed by removing the planarization insulating layer at a position surrounding a display area in which the plurality of light emitting elements connected to the drive element are disposed. | 2011-04-28 |
20110095300 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A manufacturing method of a thin film transistor array panel includes forming a gate line on a substrate and a gate insulating layer on the gate line, forming a semiconductor on the gate insulating layer, forming a first data line and a first drain electrode on the semiconductor, forming a lower passivation layer on the first data line and the first drain electrode, forming an upper passivation layer on the lower passivation layer and a metal layer on the upper passivation layer, etching the metal layer by using a photosensitive film as a mask to form a reflecting electrode and to expose the lower passivation layer, etching the exposed lower passivation layer to form a first contact hole exposing the first drain electrode, and forming a connection assistance member connecting the first drain electrode and the reflecting electrode through the first contact hole after removing the photosensitive film. | 2011-04-28 |
20110095301 | SILICON CARBIDE SEMICONDUCTOR DEVICE - There was a problem that it was difficult to manufacture silicon carbide semiconductor devices with suppressed variations in characteristics without increasing the number of process steps. A silicon carbide semiconductor device according to the present invention includes an N type SiC substrate and an N type SiC epitaxial layer as a silicon carbide semiconductor substrate of a first conductivity type, a plurality of recesses intermittently formed in a surface of the N type SiC epitaxial layer, P type regions as second-conductivity-type semiconductor layers formed in the N type SiC epitaxial layer in the bottoms of the plurality of recesses, and a Schottky electrode selectively formed over the surface of the N type SiC epitaxial layer, wherein the plurality of recesses all have an equal depth. | 2011-04-28 |
20110095302 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device and its manufacturing method in which delay in switching and non-uniform operations are prevented and in which stresses occurring in trench regions are alleviated as much as possible. A gate electrode in a gate trench is formed of a polysilicon layer and a gate tungsten layer that is lower resistant than the polysilicon layer. Also, a source electrode is formed of source tungsten layers buried in source trenches and an AlSi layer in contact with the source tungsten layers and covering source layers and the gate electrodes with a thick insulating film interposed therebetween. | 2011-04-28 |
20110095303 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a cell region, an outer peripheral region, a field plate, an outermost peripheral ring, outer peripheral region layer, an insulator film, and a Zener diode. The semiconductor substrate has a superjunction structure. The outer peripheral region is disposed at an outer periphery of the cell region. The Zener diode is disposed on the insulator film for electrically connecting the field plate with the outermost peripheral ring. The Zener diode has a first conductivity type region and a second conductivity type region that are alternately arranged in a direction from the cell region to the outer peripheral region. | 2011-04-28 |
20110095304 | PROCESS FOR FORMING AN INTERFACE BETWEEN SILICON CARBIDE AND SILICON OXIDE WITH LOW DENSITY OF STATES - An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO | 2011-04-28 |
20110095305 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a substrate | 2011-04-28 |
20110095306 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - Disclosed are a light emitting device, a light emitting device package and a lighting system. The light emitting device of the embodiment includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first and second conductive semiconductor layers; a second electrode under the second conductive semiconductor layer; a first texture over a first region of the first conductive semiconductor layer; an A-electrode over the first region of the first conductive semiconductor layer; and a B-electrode over a second region of the first conductive semiconductor layer, wherein the B-electrode includes a pad electrode connected to a wire. | 2011-04-28 |
20110095307 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - Disclosed are a light emitting device, a light emitting device package and a lighting system. The light emitting device of the embodiment includes a light emitting structure including a first conductive semiconductor layer, an active layer over the first conductive semiconductor layer, and a second conductive semiconductor layer over the active layer; a dielectric layer over a first region of the first conductive semiconductor layer; a second electrode over the dielectric layer; and a first electrode over a second region of the first conductive semiconductor layer. | 2011-04-28 |
20110095308 | PROCESS FOR FORMING AN ELECTROACTIVE LAYER - There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes the steps of providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of −25 to 80° C. and under a vacuum in the range of 10 | 2011-04-28 |
20110095309 | SEMICONDUCTOR DEVICE - Semiconductor devices including a light emitting layer, and at least one surface plasmon metal layer in contact with the light emitting layer are provided. The light emitting layer includes an active layer having a first band gap, and one or more barrier layers having a second band gap. The first band gap is smaller than the second band gap. Methods for fabricating semiconductor devices are also provided. | 2011-04-28 |
20110095310 | SEMICONDUCTOR LIGHT EMITTING MODULE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor light emitting module and a method of manufacturing the same, which allow achieving high luminance light emission as well as lightweight and compact features. In a semiconductor light emitting module ( | 2011-04-28 |
20110095311 | Configuration of Multiple LED Module - A configuration of multiple LED modules having a plurality of LED modules that each contain a carrier that has a first main area, a second main area and at least one semiconductor layer. The first main area has a planar configuration. The LED modules also include a plurality of LED semiconductor bodies that applied on the first main area of the carrier. In addition, the multiple LED modules include a common heat sink, where the carrier of the LED modules in each case are connected to the common heat sink on the second main area. | 2011-04-28 |
20110095312 | Semiconductor Device and Method of Manufacturing the Same - An object of the present invention is to provide a semiconductor device having high operation characteristic and reliability. | 2011-04-28 |
20110095313 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A method for manufacturing light-emitting diode (LED) first provides a substrate, then a protrusive patterned layer is formed on the substrate. The protrusive patterned layer exposes portions of the substrate, and the exposed portions are defined as a plurality of exposed regions. Next, a plurality of island semiconductor multi-layer is individually formed in each exposed region of the substrate. | 2011-04-28 |
20110095314 | Light emitting device and method for enhancing light extraction thereof - A method for enhancing light extraction of a light emitting device is disclosed. The method includes the steps of: providing a site layer on the light emitting device; placing a protection layer on the site layer; forming an array of pores through the protection layer and the site layer; and growing on the site layer an oxide layer, having a plurality of rods, each of which is formed in one of the pores. The shapes of the rods can be well controlled by adjusting reactive temperature, time and N | 2011-04-28 |
20110095315 | PACKAGE SUBSTRATE FOR OPTICAL ELEMENT AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a package substrate for optical elements, including: a conductive substrate including an insulation layer formed thereon; a circuit layer which is formed on the conductive substrate | 2011-04-28 |
20110095316 | LED PACKAGE STRUCTURE - An LED package structure includes an LED die, a lead frame and a housing connecting to the lead frame. The LED die is located on a surface of the lead frame. The housing includes an inner face surrounding the LED die. The inner face has a bottom edge connected to the surface of the lead frame, a top edge and a waist line between the bottom edge and top edge. The bottom edge surrounds an area less than an area surrounded by the waist line. The area surrounded by the waist line is less than an area surrounded by the top edge. The inner face has a curved surface between the waist line and the bottom edge. | 2011-04-28 |
20110095317 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device, a light emitting device package, and a lighting system including the same. The light emitting device includes a second electrode layerelectrode, a light emitting structure, a texture, and a current spreading layer. The light emitting structure is on second electrode layerelectrode, and includes a second conductive type semiconductor layer, an active layer on the second conductive type semiconductor layer, and a first conductive type semiconductor layer on the active layer. The texture is on at least one portion of the light emitting structure. The current spreading layer is on the light emitting structure provided with the texture. | 2011-04-28 |
20110095318 | LIGHT EMITTING APPARATUS - A light emitting apparatus includes a substrate, at least one LED (light-emitting diode) die, a sealant, a cover sheet and a protecting material. The LED die is disposed on the substrate. The sealant covers the LED die and has a top surface and a side surface. The cover sheet is disposed on the top surface of the sealant. The protecting material is disposed at the side surface, and connected with the cover sheet and the substrate. Accordingly, the light emitting apparatus can prevent from moisture or gas that may affect the luminous efficiency thereof, thereby extending the lifetime of the light emitting apparatus. | 2011-04-28 |
20110095319 | LIGHT EMITTING DEVICE PACKAGE, LIGHTING MODULE AND LIGHTING SYSTEM - Disclosed are a light emitting device package and a lighting system. The light emitting device package includes a semiconductor light emitting device, a first encapsulant over the semiconductor light emitting device, and a second encapsulant having a refractive index greater than a refractive index of the first encapsulant over the first encapsulant. | 2011-04-28 |
20110095320 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Disclosed are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a light emitting structure including a second conductive semiconductor layer, an active layer over the second conductive semiconductor layer, and a first conductive semiconductor layer over the active layer dielectric layer in a cavity defined by removing a portion of the light emitting structure, and a second electrode layer over the dielectric layer. | 2011-04-28 |
20110095321 | LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - A light emitting device (LED) package includes a submount and a light emitting chip. The submount has a chip region and a supporting region over which the chip is mounted, and an encapsulating material and fluorescent material are formed over the chip. The coverage area of encapsulating and fluorescent materials is substantially coextensive with the chip or chip region, and a first area between an edge of the chip region and an edge of the supporting region is greater than a second area between the edge of the chip region and the chip. | 2011-04-28 |
20110095322 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Provided are a light emitting device and a light emitting device package. The light emitting device comprises a light emitting structure comprising a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer; a first electrode on the first conductive type semiconductor layer, the first electrode being electrically connected to the first conductive type semiconductor layer; a plurality of reflective islands on the second conductive type semiconductor layer; a second electrode on the second conductive type semiconductor layer and the plurality of reflective islands, the second electrode being electrically connected to the second conductive type semiconductor layer; and a conductive support member on the second electrode. | 2011-04-28 |
20110095323 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a first semiconductor layer comprising a plurality of vacant space parts, an active layer on the first semiconductor layer, and a second conductive type semiconductor layer on the active layer. Each of the plurality of air-lenses has a thickness less than that of the first semiconductor layer. | 2011-04-28 |
20110095324 | METHOD FOR FABRICATING MICRO AND NANO STRUCTURES - A method of forming an array of selectively shaped optical elements on a substrate, the method including the steps of providing the substrate, the substrate having an optical layer placed thereon; placing a layer of particles on the optical layer; performing an etching cycle. The cycle includes the steps of: etching the layer of particles, using a first etching process so as to reduce the size of the particles within the layer, then; simultaneously etching the optical layer and the layer of particles, using a second etching process, the further reducing particles forming a mask over areas of the optical layer to create discrete optical elements from the optical layer. | 2011-04-28 |
20110095325 | OPTOELECTRONIC SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An embodiment of the invention discloses an optoelectronic semiconductor device comprising a semiconductor system capable of performing a conversion between light energy and electrical energy; an interfacial layer formed on at least two surfaces of the semiconductor system; an electrical conductor; and an electrical connector electrically connecting the semiconductor system to the electric conductor. | 2011-04-28 |
20110095326 | SEMICONDUCTOR LIGHT EMITTING DEVICE - This invention discloses a light emitting semiconductor device including a light-emitting structure and an external optical element. The optical element couples to the light-emitting structure circumferentially. In addition, the refractive index of the external optical element is greater than or about the same as that of a transparent substrate of the light-emitting structure, or in-between that of the transparent substrate and the encapsulant material. | 2011-04-28 |
20110095327 | GROUP III NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND PRODUCTION METHOD THEREOF, AND LAMP - A group III nitride semiconductor light emitting device including an LED structure formed on top of a single crystal, base layer ( | 2011-04-28 |
20110095328 | CLOSE PROXIMITY COLLIMATOR FOR LED - A method for the manufacture of a light emitting device is provided. The method comprises the steps of: providing a substrate ( | 2011-04-28 |
20110095329 | LIGHT EMITTING DEVICE PACKAGE - Provided are a light emitting device package and a lighting system. The light emitting device package includes a light emitting device chip, at least one wire, and an encapsulating material. The light emitting device chip includes a first conductive type semiconductor layer, a second conductive type semiconductor layer on the first conductive type semiconductor layer, and an active layer between the first and second conductive type semiconductor layers. The wire is on the light emitting device chip. The encapsulating material is on the light emitting device chip out of the wire, and includes a phosphor. The wire is perpendicular to an upper surface of the light emitting device chip, at least up to a height of the encapsulating material. | 2011-04-28 |
20110095330 | OPTICAL SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING OPTICAL SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING OPTICAL SEMICONDUCTOR APPARATUS - A method for manufacturing a high quality optical semiconductor device includes: (a) preparing a growth substrate; (b) forming a semiconductor layer on the growth substrate; (c) forming a metal support made of copper on the semiconductor layer by plating; (d) separating the growth substrate from the semiconductor layer to remove the growth substrate; and (e) carrying out a thermal treatment in order to even density distributions of crystal grains and voids in the copper forming the metal support. | 2011-04-28 |
20110095331 | GROUP-III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING THE SAME, AND LAMP - Provided is a group-III nitride semiconductor light-emitting device which has a high level of crystallinity and superior internal quantum efficiency and which is capable of enabling acquisition of high level light emission output, and a manufacturing method thereof, and a lamp. An AlN seed layer composed of a group-III nitride based compound is laminated on a substrate | 2011-04-28 |
20110095332 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - A light emitting device includes a first electrode, a first semiconductor layer, an active layer; a second semiconductor layer, and a second electrode. A current blocking layer is formed on a side surface of and has a width provided within the first semiconductor layer. The thickness and width of the current blocking layer is smaller than the thickness and width of the first semiconductor layer. | 2011-04-28 |
20110095333 | HIGH-DRIVE CURRENT MOSFET - A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided. | 2011-04-28 |
20110095334 | BARRIER PHOTODETECTOR WITH PLANAR TOP LAYER - A barrier-type photo-detector is provided with a Barrier between first and second layers. One of the layers is delineated into pixels without fully removing the non-pixel portions of the delineated layer. Delineation may be accomplished through material modification techniques such as ion damage, selective doping, ion induced disordering or layer material growth. Some variations may employ partial material removal techniques. | 2011-04-28 |
20110095335 | NITRIDE SEMICONDUCTOR DEVICE - A high breakdown voltage GaN-based transistor is provided on a silicon substrate. A nitride semiconductor device including: a silicon substrate, a SiO | 2011-04-28 |
20110095336 | LATERAL HEMT AND METHOD FOR THE PRODUCTION OF A LATERAL HEMT - In one embodiment a lateral HEMT has a first layer, the first layer including a semiconducting material, and a second layer, the second layer including a semiconducting material and being at least partially arranged on the first layer. The lateral HEMT further has a passivation layer and a drift region, the drift region including a lateral width w | 2011-04-28 |
20110095337 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device reduces the on-resistance and, at the same time, raises the breakdown voltage. The drain electrode | 2011-04-28 |
20110095338 | METHODS OF FORMING PILLARS FOR MEMORY CELLS USING SEQUENTIAL SIDEWALL PATTERNING - The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed. | 2011-04-28 |
20110095339 | Semiconductor device and method for manufacturing the same - A semiconductor device has at least two main carbon-rich regions and two additional carbon-rich regions. The main carbon-rich regions are separately located in a substrate so that a channel region is located between them. The additional carbon-rich regions are respectively located underneath the main carbon-rich regions. The carbon concentrations is higher in the main carbon-rich regions and lower in the additional carbon-rich regions, and optionally, the absolute value of a gradient of the carbon concentration of the bottom portion of the main carbon-rich regions is higher than the absolute value of a gradient of the carbon concentration of the additional carbon-rich regions. Therefore, the leakage current induced by a lattice mismatch effect at the carbon-rich and the carbon-free interface can be minimized. | 2011-04-28 |
20110095340 | Soft error reduction circuit and method - In some embodiments, complementary charge-collecting diffusions (transistor diffusions, e.g., drain or source areas) are disposed close to each other. In some embodiments, dummy (“off”) transistors are incorporated to bring complementary diffusions (diffusions of the same charge type and having complementary digital logic levels) closer to each other than otherwise might be possible and thus, to enhance common-mode charge collection for the complementary diffusion areas. | 2011-04-28 |
20110095341 | METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS - Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries. | 2011-04-28 |
20110095342 | Printed Material Constrained By Well Structures And Devices Including Same - A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor. | 2011-04-28 |
20110095343 | BI-LAYER nFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT - A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions. | 2011-04-28 |
20110095344 | Method of Improving Minority Lifetime in Silicon Channel and Products Thereof - Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C. | 2011-04-28 |
20110095345 | Methods of Fabricating Field Effect Transistors Having Protruded Active Regions - Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply. | 2011-04-28 |
20110095346 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment. | 2011-04-28 |
20110095347 | VERTICAL DIODE USING SILICON FORMED BY SELECTIVE EPITAXIAL GROWTH - Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus. | 2011-04-28 |
20110095348 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d | 2011-04-28 |
20110095349 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate ( | 2011-04-28 |
20110095350 | VERTICAL TYPE INTEGRATED CIRCUIT DEVICES, MEMORY DEVICES, AND METHODS OF FABRICATING THE SAME - A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed. | 2011-04-28 |
20110095351 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a device isolation layer in a semiconductor substrate, an active region defined by the device isolation layer, the active region including a main surface and a recess region including a bottom surface that is lower than the main surface, and a gate electrode formed over the recess region, wherein a top surface of the device isolation layer adjacent to the recess region is lower than the bottom surface of the recess region. | 2011-04-28 |
20110095352 | FLASH MEMORY DEVICE AND FABRICATION METHOD THEREOF - The present invention relates to a flash memory device and a fabrication method thereof. In an embodiment, a flash memory device includes a tunnel insulating film and a floating gate laminated over an active region of a semiconductor substrate, an isolation layer formed in a field region of the semiconductor substrate and projected higher than the floating gate, a dielectric layer formed over the semiconductor substrate including the floating gate and the isolation layer, and a control gate formed on the dielectric layer. | 2011-04-28 |
20110095353 | ONE-TRANSISTOR CELL SEMICONDUCTOR ON INSULATOR RANDOM ACCESS MEMORY - Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be implemented providing for very fast program/erase operations, supported by refresh operations as used in classical DRAM technology. The memory arrays are arranged in divided bit line architectures. A gate injection, DRAM cell is described with no tunnel oxide. | 2011-04-28 |
20110095354 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region. | 2011-04-28 |
20110095355 | SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS - Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes. | 2011-04-28 |
20110095356 | NONVOLATILE MEMORY DEVICES - Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers. | 2011-04-28 |
20110095357 | Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures. | 2011-04-28 |
20110095358 | DOUBLE-SIDED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME - A semiconductor structure including a substrate of semiconductor material of a first type of conductivity; a first semiconductor layer set in direct electrical contact with the substrate on a first side of the substrate; a second semiconductor layer set in direct electrical contact with the substrate on a second side of the substrate; a first active electronic device formed in the first semiconductor layer; and a second active electronic device formed in the second semiconductor layer. | 2011-04-28 |
20110095359 | Field Boosted Metal-Oxide-Semiconductor Field Effect Transistor - A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions. | 2011-04-28 |
20110095360 | METHOD AND DEVICE INCLUDING TRANSISTOR COMPONENT HAVING A FIELD ELECTRODE - A transistor component and method of forming a transistor component. One embodiment provides a semiconductor arrangement including a semiconductor body having a at least one first trench, a first field electrode arranged in the lower trench section of the at least one first trench and being insulated from the semiconductor body by a field electrode dielectric. A dielectric layer is formed on the first field electrode in the at least one first trench, including depositing a dielectric material on a first side of the semiconductor body and on the field plate at a higher deposition rate than on sidewalls of the at least one first trench. | 2011-04-28 |
20110095361 | MULTIPLE LAYER BARRIER METAL FOR DEVICE COMPONENT FORMED IN CONTACT TRENCH - A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer. | 2011-04-28 |
20110095362 | FIELD PLATE TRENCH TRANSISTOR AND METHOD FOR PRODUCING IT - A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials. | 2011-04-28 |
20110095363 | Semiconductor Structures Employing Strained Material Layers with Defined Impurity Gradients and Methods for Fabricating Same - Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced. | 2011-04-28 |
20110095364 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region; and a metallization layer arranged with respect to the active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap; and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first part and the second part of the metallization layer. | 2011-04-28 |
20110095365 | Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method - A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device. | 2011-04-28 |
20110095366 | FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER - Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region. | 2011-04-28 |
20110095367 | ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS - Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone. | 2011-04-28 |
20110095368 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device preferably includes a first transistor, a second transistor, and an electrostatic discharge clamping circuit. The first transistor includes a first drain electrically connected to an input/output pin of a chip, a first source electrically connected to a first voltage input pin of the chip, and a first gate. The first drain is preferably an internally shrunk drain. The second transistor includes a second drain electrically connected to the input/output pin of the chip, a second source electrically connected to a second voltage input pin and a second gate. The electrostatic discharge clamping circuit is electrically connected to the first voltage input pin and the second voltage input pin. | 2011-04-28 |
20110095369 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and
| 2011-04-28 |
20110095370 | WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE - Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance. | 2011-04-28 |
20110095371 | Gate minimization threshold voltage of FET for synchronous rectification - A FET device for synchronous rectification of the present invention, a FET having no body diode, the characteristics have gate minimization threshold voltage equal or over load voltage, can be achieve FET turn on, and gate minimization threshold voltage under load voltage, can be achieve FET turn off. | 2011-04-28 |
20110095372 | Forming Inter-Device STI Regions and Intra-Device STI Regions Using Different Dielectric Materials - An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value. | 2011-04-28 |
20110095373 | SEMICONDUCTOR CHIP, STACK MODULE, AND MEMORY CARD - Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV. | 2011-04-28 |
20110095374 | METHOD, DESIGN APPARATUS, AND DESIGN PROGRAM OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A design method of a semiconductor device includes setting an inspection region of layout data generated based on circuit data, calculating an area ratio of a first area to a second area, the first area indicating an area of the inspection region, the second area indicating a sum of a surface area of a plane that a first member contacts with a second member, the second member contacting with the first member constituting a circuit element included in the inspection region, the second member further having different heat reflective properties from the first member, and arranging a dummy element in the layout data so that the area ratio is within a predetermined range in each inspection region of the layout data. | 2011-04-28 |
20110095375 | MIM TRANSISTOR - The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer. | 2011-04-28 |
20110095376 | SINGLE METAL DUAL DIELECTRIC CMOS DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate having a first region and a second region, a pMOS transistor formed over the first region and an nMOS formed over the second region. The pMOS transistor has a gate structure that includes: an interfacial layer formed over the substrate; a AlO | 2011-04-28 |
20110095377 | SEMICONDUCTOR MEMORY DEVICES - In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions. | 2011-04-28 |
20110095378 | FinFET Design with Reduced Current Crowding - An integrated circuit structure includes a substrate and a fin field-effect transistor (FinFET). The FinFET includes a fin over the substrate and having a first fin portion and a second fin portion. A gate stack is formed on a top surface and sidewalls of the first fin portion. An epitaxial semiconductor layer has a first portion formed directly over the second fin portion, and a second portion formed on sidewalls of the second fin portion. A silicide layer is formed on the epitaxial semiconductor layer. A peripheral ratio of a total length of an effective silicide peripheral of the FinFET to a total length of a fin peripheral of the FinFET is greater than 1. | 2011-04-28 |
20110095379 | SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT - A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided. | 2011-04-28 |
20110095380 | SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below. | 2011-04-28 |
20110095381 | Gate structure and method for making same - A MOS transistor having its gate successively comprising an insulating layer, a metal silicide layer, a layer of a conductive encapsulation material, and a polysilicon layer. | 2011-04-28 |
20110095382 | MEMS DEVICE - A MEMS device of an embodiment includes: a MEMS element; a first cavity region provided on the MEMS element; a second cavity region provided on a surrounding portion outside the MEMS element, the second cavity region having a lower height than the first cavity region; a third cavity region provided on a surrounding portion outside the second cavity region, the third cavity region having a lower height than the second cavity region; an insulating film provided to cover upper portions and side surfaces of the first to the third cavity regions; an opening provided in the insulating film on the first to the third cavity regions; and a sealant provided on the insulating film to seal the opening and to retain the first to the third cavity regions. | 2011-04-28 |
20110095383 | MEMS DEVICE HAVING A MOVABLE ELECTRODE - A microelectromechanical system (MEMS) device includes a semiconductor substrate, a MEMS including a fixed electrode and a movable electrode formed on the semiconductor substrate through an insulating layer, and a well formed in the semiconductor substrate below the fixed electrode. The well is one of an n-type well and a p-type well. The p-type well applies a positive voltage to the fixed electrode while the n-type well applies a negative voltage to the fixed electrode. | 2011-04-28 |
20110095384 | Single Crystal Silicon Sensor with Additional Layer and Method of Producing the Same - A SOI-based MEMS device has a base layer, a device layer, and an insulator layer between the base layer and the device layer. The device also has a deposited layer having a portion that is spaced from the device layer. The device layer is between the insulator layer and the deposited layer. | 2011-04-28 |
20110095385 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND WIRELESS TRANSMISSION SYSTEM UTILIZING THE SAME - A device, and method for manufacturing the same, including a semiconductor package which allows transmission therethrough of a radio signal, a chip which generates the radio signal and a coupler adjacent the chip and effective to radiate the radio signal to outside of the semiconductor package. | 2011-04-28 |
20110095386 | Semiconductor sensor for detecting a light radiation - A semiconductor sensor for detecting a radiation including a sensitive layer obtained in an inactive layer adapted to detect a light radiation, a portion thereof having a metal layer attached thereto, while on the remaining portion of the sensitive layer there is an overlapping scintillator. A bonding wire branches from said metal layer. Said sensor is shaped so that, according to a section of the sensor, said metal layer is at a lower height with respect to the scintillator crystal, so that the bonding wire does not interfere therewith. Such a result is obtained by tapering the thickness of said inactive layer and/or interposing a transparent layer between said sensitive layer and said scintillator crystal. | 2011-04-28 |
20110095387 | SEMICONDUCTOR DEVICES HAVING AN ENHANCED ABSORPTION REGION AND ASSOCIATED METHODS - Photosensitive semiconductor devices and associated methods are provided. In one aspect, for example, a photosensitive semiconductor device can include an electromagnetic radiation absorption layer having a thickness of less than or equal to about 200 μm, wherein the electromagnetic radiation absorption layer includes a semiconductor material and an enhanced absorption region. The electromagnetic radiation absorption layer is operable to absorb greater than or equal to about 40% of incident electromagnetic radiation having at least one wavelength greater than or equal to about 1064 nm. | 2011-04-28 |
20110095388 | AVALANCHE PHOTODIODE - The invention relates to an avalanche photodiode ( | 2011-04-28 |
20110095389 | Optoelectronic Semiconductor Device and Method of Fabrication - An optoelectronic device comprising an optically active layer that includes a plurality of domes is presented. The plurality of domes is arrayed in two dimensions having a periodicity in each dimension that is less than or comparable with the shortest wavelength in a spectral range of interest. By virtue of the plurality of domes, the optoelectronic device achieves high performance. A solar cell having high energy-conversion efficiency, improved absorption over the spectral range of interest, and an improved acceptance angle is presented as an exemplary device. | 2011-04-28 |
20110095390 | THERMOELECTRIC CONVERSION MATERIAL AND THERMOELECTRIC CONVERSION ELEMENT - The present invention provides a thermoelectric conversion material composed of an oxide material represented by chemical formula A | 2011-04-28 |
20110095391 | SCHOTTKY DIODE DEVICE AND METHOD FOR FABRICATING THE SAME - A Schottky diode device is provided, including a p-type semiconductor structure. An n drift region is disposed over the p-type semiconductor structure, wherein the n drift region comprises first and second n-type doping regions having different n-type doping concentrations, and the second n-type doping region is formed with a dopant concentration greater than that in the first n-type doping region. A plurality of isolation structures is disposed in the second n-type doping region of the n drift region, defining an anode region and a cathode region. A third n-type doping region is disposed in the second n-type doping region exposed by the cathode region. An anode electrode is disposed over the first n-type doping region in the anode region. A cathode electrode is disposed over the third n-type doping region in the cathode region. | 2011-04-28 |
20110095392 | HIGH VOLTAGE RESISTANCE COUPLING STRUCTURE - The disclosed invention provides a structure and method for providing a high lateral voltage resistance between the electrical networks, sharing a lateral plane, of conductive elements (e.g., having different high voltage potentials) comprising a coupler. In one embodiment, an integrated coupler providing a high lateral voltage resistance comprises a primary conductive element and a secondary conductive element. An isolating material is laterally configured between the electrical network of the primary conductive element and an electrical network of the secondary conductive element. The isolating material may comprise a low-k dielectric layer and prevents any lateral barrier layers (e.g., etch stop layers, diffusion barrier layers, etc.) from extending between the first conductive element and the electrical network of the second conductive element. The structure therefore provides a galvanically isolated integrated coupler which avoids electrical shorting between circuits (e.g., at barrier layers) resulting in an improved high voltage resistance. | 2011-04-28 |
20110095393 | CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS - An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer. | 2011-04-28 |
20110095394 | ANTIFUSE AND METHOD OF MAKING THE ANTIFUSE - A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse. | 2011-04-28 |
20110095395 | Inductors and Methods for Integrated Circuits - Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed. | 2011-04-28 |
20110095396 | METHOD AND STRUCTURE FOR SILICON NANOCRYSTAL CAPACITOR DEVICES FOR INTEGRATED CIRCUITS - An improved semiconductor device, including a capacitor structure. The device has a first electrode member, which has a first length and a first width. The device also has a second electrode member, which has a second length and a second width. Additionally, the device includes a capacitor dielectric material provided between the first electrode member and the second electrode member according to a specific embodiment. Depending upon the embodiment, the capacitor dielectric material is made of a suitable material or materials such as Al | 2011-04-28 |
20110095397 | Semiconductor Structures Including Dielectric Layers and Capacitors Including Semiconductor Structures - Semiconductor structures including a first conductive layer; a dielectric layer on the first conductive layer; a second conductive layer on the dielectric layer; and a crystallized seed layer in at least one of a first portion between the first conductive layer and the dielectric layer and a second portion between the dielectric layer and the second conductive layer. Related capacitors and methods are also provided herein. | 2011-04-28 |