17th week of 2015 patent applcation highlights part 16 |
Patent application number | Title | Published |
20150108491 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode package includes a lead frame, a light emitting diode chip, a wavelength conversion structure, and a filter. The light emitting diode chip is disposed on and electrically connected to the lead frame for providing a first light beam with a first wavelength. The light emitting diode chip is configured to provide a first light beam with a first wavelength. The wavelength conversion structure is disposed on the light emitting diode chip, and is configured to convert the first light beam into a second light beam with a second wavelength. The filter is disposed between the light emitting diode chip and the wavelength conversion structure. The filter allows the first light beam from the light emitting diode chip to pass therethrough to enter the wavelength conversion structure, and reflects the second light beam from the wavelength conversion structure back to the wavelength conversion structure. | 2015-04-23 |
20150108492 | LIGHT-EMITTING DIODE - A light-emitting diode (LED), including a first semiconductor layer defining several light-emitting regions and non-light-emitting regions; an active layer and a second semiconductor layer sequentially formed over the first semiconductor layer in the light-emitting regions; a transparent conductive layer formed over the second semiconductor layer; a Bragg reflector structure formed over the transparent conductive layer and including several first via holes; a metal layer formed over the Bragg reflector structure and connected to the transparent conductive layer through the first via holes; a passivation layer covering the metal layer and including several second via holes; several third via holes exposing the first semiconductor layer in the non-light-emitting regions; several first electrodes filling the third via holes and connected to the first semiconductor layer; and several second electrodes filling the second via holes and connected to the metal layer. | 2015-04-23 |
20150108493 | SILICON CARBIDE EPITAXIAL WAFER, AND PREPARATION METHOD THEREOF - According to an embodiment, there is provided a method of fabricating an epitaxial wafer, which includes preparing a wafer in a susceptor; and growing an epitaxial layer on the wafer, wherein the growing of the epitaxial layer on the wafer includes supplying a raw material into the susceptor; growing the epitaxial layer on the wafer at a first growth rate; and growing the epitaxial layer on the wafer at a second growth rate higher than the first growth rate. According to an embodiment, there is provided a silicon carbide epitaxial wafer which includes a silicon carbide wafer; and a silicon carbide epitaxial layer on the silicon carbide wafer wherein a surface defect formed on the silicon carbide epitaxial layer is 1 ea/cm | 2015-04-23 |
20150108494 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprising: a light-emitting stack; and a semiconductor layer having a first surface connecting to the light-emitting stack, a second surface opposite to the first surface, and a void; wherein the void comprises a bottom part near the first surface and an opening on the second surface, and a dimension of the bottom part is larger than the dimension of the opening. | 2015-04-23 |
20150108495 | Gallium Nitride Devices with Discontinuously Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 2015-04-23 |
20150108496 | GROUP III-N TRANSISTOR ON NANOSCALE TEMPLATE STRUCTURES - A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin. | 2015-04-23 |
20150108497 | LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING ELEMENTS - A light-emitting device including a substrate, a first electrode pad and a second electrode pad disposed on the substrate and spaced apart each other, and at least two arrays connected in parallel between the first and the second electrode pads. The at least two arrays include a first array and a second array, each of the at least two arrays include GaN-based light-emitting elements connected in series, the first electrode pad and the second electrode pad are disposed on a non-light-emitting first region of the substrate spaced apart from a light-emitting second region of the substrate, and the first electrode pad and the second electrode pad surround at least a portion of outer edges comprising a circumference of the at least two arrays. | 2015-04-23 |
20150108498 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor light emitting device includes a first nitride semiconductor layer, a nitride semiconductor light emitting layer, a second nitride semiconductor layer, a p-side electrode, and an n-side electrode. The nitride semiconductor light emitting layer is provided on the p-side region of the second face of the first nitride semiconductor layer. The second nitride semiconductor layer is provided on the nitride semiconductor light emitting layer. The p-side electrode is provided on the second nitride semiconductor layer. The n-side electrode is provided on the n-side region of the second face of the first nitride semiconductor layer. The nitride semiconductor light emitting layer has a first concave-convex face in a side of the first nitride semiconductor layer, and a second concave-convex face in a side of the second nitride semiconductor layer. | 2015-04-23 |
20150108499 | SEMICONDUCTOR DEVICES WITH GRAPHENE NANORIBBONS - Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material. | 2015-04-23 |
20150108500 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device comprises a semiconductor body of a first semiconductor material, wherein at least a part of the semiconductor body constitutes a drift zone of a first conductivity type. The semiconductor device further comprises a channel layer structure comprising a semiconductor heterojunction between first and second semiconductor layers electrically coupled to the drift zone. The first and second semiconductor layers include semiconductor materials that are different to the first semiconductor material. | 2015-04-23 |
20150108501 | SEMICONDUCTOR DEVICE - In an active region, p | 2015-04-23 |
20150108502 | HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING SAME - The present invention relates to a heat dissipation substrate, which is a composite substrate composed of two layers, and which is characterized in that a surface layer (first layer) ( | 2015-04-23 |
20150108503 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device of the present disclosure includes a semiconductor layer provided on a main surface of a substrate. A cell region is provided with a gate insulating film disposed on the semiconductor layer and a gate electrode disposed on the gate insulating film, and a wiring region is provided with a field insulating film disposed on the semiconductor layer and a gate wire disposed on the field insulating film. An end of the field insulating film has a convex shape in a cross section perpendicular to the main surface of the substrate, and an upper surface of the field insulating film is rougher than an upper surface of a portion of the gate wire below which the field insulating film is not disposed. | 2015-04-23 |
20150108504 | METHOD FOR PRODUCING 3C-SIC EPITAXIAL LAYER, 3C-SIC EPITAXIAL SUBSTRATE, AND SEMICONDUCTOR DEVICE - A 3C-SiC epitaxial layer is produced by a production method including: epitaxially growing a first 3C-SiC layer on a Si substrate; oxidizing the first 3C-SiC layer; removing an oxide film on a surface of the 3C-SiC layer; and epitaxially growing a second 3C-SiC layer on the 3C-SiC layer after the oxide film is removed. | 2015-04-23 |
20150108505 | Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice. | 2015-04-23 |
20150108506 | SINGULATING HYBRID INTEGRATED PHOTONIC CHIPS - During a fabrication technique, trenches are defined partially through the thickness of a substrate. Then, photonic integrated circuits are coupled to the substrate. These photonic integrated circuits may be in a diving-board configuration, so that they at least partially overlap the trenches. While this may preclude the use of existing dicing techniques, individual hybrid integrated photonic chips (which each include a portion of the substrate and at least one of the photonic integrated circuits) may be singulated from the substrate by: coupling a carrier to a front surface of the substrate; thinning the substrate from a back surface until the partial trenches are reached (for example, by grinding the substrate); attaching a support mechanism (such as tape) to the back surface of the substrate; removing the carrier; and then removing the support mechanism. | 2015-04-23 |
20150108507 | IMAGE SENSOR WITH DOPED SEMICONDUCTOR REGION FOR REDUCING IMAGE NOISE - A backside illuminated image sensor includes a semiconductor layer having a back-side surface and a front-side surface. The semiconductor layer includes a pixel array region including a plurality of photodiodes configured to receive image light through the back-side surface of the semiconductor layer. The semiconductor layer also includes a peripheral circuit region including peripheral circuit elements for operating the plurality of photodiodes that borders the pixel array region. The peripheral circuit elements emit photons. The peripheral circuit region also includes a doped semiconductor region positioned to absorb the photons emitted by the peripheral circuit elements to prevent the plurality of photodiodes from receiving the photons. | 2015-04-23 |
20150108508 | DISPLAY PANEL - A display panel comprising a substrate, a meshed shielding pattern, a plurality of light-emitting devices and a solar cell is provided. The substrate has a first surface and a second surface opposite to the first surface, the substrate comprises a first circuit layer disposed over the first surface and a second circuit layer disposed over the second surface. The meshed shielding pattern is disposed on first surface of the substrate to define a plurality of pixel regions over the substrate. The light-emitting devices are disposed on the first surface of the substrate and electrically connected to the first circuit layer, and at least one of the light-emitting devices is disposed in one of the pixel regions. The solar cell is disposed on the second surface of the substrate and electrically connected to the second circuit layer. | 2015-04-23 |
20150108509 | METHOD FOR PRODUCING INTERCONNECTED OPTOELECTRONIC COMPONENTS, AND INTERCONNECTED OPTOELECTRONIC COMPONENTS - The invention relates to a method for producing serially interconnected optoelectronic components as well as optoelectronic components interconnected according to the method. In a first step, an electrically non-conductive layer with optoelectronic material introduced therein and at least one first wire or thread ( | 2015-04-23 |
20150108510 | LED MODULE - The LED module includes: a light diffusing substrate having light transmissive properties; an LED chip bonded to a first surface of the light diffusing substrate with a transparent first bond in between; a color converter facing the first surface to cover the LED chip; and a mounting substrate. The color converter is made of transparent material containing phosphor which, when excited by light emitted from the LED chip, emits light having a different color from the LED chip. The mounting substrate includes a diffuse reflection layer diffusely reflecting light emitted from the LED chip and light emitted from the phosphor. The diffuse reflection layer is placed facing a second surface of the light diffusing substrate. | 2015-04-23 |
20150108511 | Optoelectronic Module and Method for Producing an Optoelectronic Module - An optoelectronic module has at least one semiconductor chip for emitting electromagnetic radiation. The semiconductor chip has a layer having a first conductivity, a layer having a second conductivity, a radiation surface and a contact surface which lies opposite the radiation surface. A contact is attached to the radiation surface. A frame made of a potting compound laterally encloses the semiconductor chip in at least some regions such that the radiation surface and the contact surface are substantially free of the potting compound. A first contact structure is arranged in at least some regions on the frame and in at least some regions on the contact surface. A second contact structure is arranged in at least some regions on the frame and in at least some regions on the contact of the radiation surface. | 2015-04-23 |
20150108512 | DISPLAY UNIT AND ELECTRONIC APPARATUS - A display unit includes a first substrate and a second substrate opposed to each other, a display element having a first electrode and a second electrode on the first substrate, an auxiliary electrode provided on a surface facing the first substrate of the second substrate, and including a plurality of films stacked in a direction from the second substrate to the first substrate, and a plurality of pillars configured to electrically connect the auxiliary electrode to the second electrode. | 2015-04-23 |
20150108513 | OVERLAY CIRCUIT STRUCTURE FOR INTERCONNECTING LIGHT EMITTING SEMICONDUCTORS - A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for controlLES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips. | 2015-04-23 |
20150108514 | FLIP-CHIP LIGHT EMITTING DIODE AND FABRICATION METHOD - A flip-chip LED includes a substrate, having a surface with a p-region metal portion and an n-region metal portion separated from each other; a p-type epitaxial layer, an active layer and an n-type epitaxial layer successively laminated on the substrate; a reflection layer between the substrate and the p-type epitaxial layer; a current blocking layer between the reflection layer and the p-type epitaxial layer and positioned to prevent the current from concentrating on the edge of the LED; an insulating protection layer cladding the LED side wall and exposing part of the side wall of the n-type epitaxial layer; a P electrode connecting the metal reflection layer and the p-region metal portion of the substrate; and an N electrode connecting the side wall of the n-type epitaxial layer and n-region metal portion of the substrate. | 2015-04-23 |
20150108515 | DISPLAY DEVICE - Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided. | 2015-04-23 |
20150108516 | LIGHT EMITTING DIODE PACKAGE STRUCTURE AND LIGHT EMITTING DIODE PACKAGE MODULE - A light emitting diode package structure includes a substrate, a light emitting diode chip, a light mixing encapsulating layer, and an ultraviolet protecting layer. The light emitting diode chip is disposed on a surface of the substrate and the light mixing encapsulating layer covers the light emitting diode chip. The ultraviolet protecting layer is adhered to a surface of the light mixing encapsulating layer such that when the ultraviolet protecting layer receives ultraviolet, the color change occurs to reflect or absorb the ultraviolet. | 2015-04-23 |
20150108517 | LIGHT EMITTING MODULE AND LIGHTING APPARATUS HAVING THE SAME - A light emitting module according to an exemplary embodiment of the present invention includes a printed circuit board (PCB) and first through m-th lighting blocks (‘m’ is an integer greater than one). The PCB has wiring patterns electrically connecting optical semiconductor devices. The first through the m-th lighting blocks are disposed on the PCB and configured to generate light. Each of the first through the m-th lighting blocks includes first through n-th lighting groups (each block includes at least one group), each of which includes optical semiconductor devices disposed on the PCB, and an electric currents configured to flow through each lighting group is substantially the same. | 2015-04-23 |
20150108518 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a nitride semiconductor light emitting element including a nitride semiconductor substrate having a polar or semipolar surface and a nitride semiconductor multilayer film stacked on the polar or semipolar surface; and a mounting section to which the element is mounted. The nitride semiconductor multilayer film includes an electron block layer. The electron block layer has a smaller lattice constant than the nitride semiconductor substrate. The mounting section includes at least a first mounting section base. The first mounting section base is located close to the nitride semiconductor light emitting element. The first mounting section base has a lower thermal expansion coefficient than the nitride semiconductor multilayer film. The first mounting section base has a lower thermal conductivity than the nitride semiconductor multilayer film. | 2015-04-23 |
20150108519 | LIGHT-EMITTING STRUCTURE - A light-emitting structure is provided, including a substrate, an LED stacked structure formed on the substrate, and a plurality of cavities formed on the substrate surrounding the LED stacked structure. The LED stacked structure comprises an N-type epitaxial layer, an illumination layer, and a P-type epitaxial layer. A portion of the N-type epitaxial layer is exposed. | 2015-04-23 |
20150108520 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a light emitting structure and first and second electrodes. The light emitting structure includes first and second conductivity type semiconductor layers and an active layer interposed therebetween. The first and second electrodes are electrically connected to the first and second conductivity type semiconductor layers. The second electrode includes a current blocking layer, a reflective part disposed on the current blocking layer, a transparent electrode layer disposed on the second conductivity type semiconductor layer, a pad electrode part disposed within a region of the current blocking layer, and at least one finger electrode part disposed at least in part on the transparent electrode layer. The transparent electrode layer can be spaced apart from the reflective part, and have an opening surrounding the reflective part. In some examples, the transparent electrode layer can further be spaced apart from the current blocking layer. | 2015-04-23 |
20150108521 | LIGHT EMITTING DEVICE - A light emitting device according to embodiments includes a light emitting element emitting light with a peak wavelength of 420˜445 nm, a first phosphor emitting light with a peak wavelength of 485˜530 nm, a second phosphor emitting light with a peak wavelength of 530˜580 nm, and a third phosphor emitting light with a peak wavelength of 600˜650 nm. The device emits light having an emission spectrum that has a local minimum value of light intensity between a wavelength of 450˜470 nm or less, the local minimum value being 60% or less of a maximum value of light intensity at a longer wavelength side from the local minimum value, and the device emits light having a color temperature of 4600 K or higher and 5400 K or less. | 2015-04-23 |
20150108522 | LED LAMPS - A high power LED lamp has a GaN chip placed over an AlGaInP chip. A reflector is placed between the two chips. Each of the chips has trenches diverting light for output. The chip pair can be arranged to produce white light having a spectral distribution in the red to blue region that is close to that of daylight. Also, the chip pair can be used to provide an RGB lamp or a red-amber-green traffic lamp. The active regions of both chips can be less than 50 microns away from a heat sink. | 2015-04-23 |
20150108523 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A reliable semiconductor light-emitting device can include a mounting board, at least one semiconductor light-emitting chip mounted on the mounting board, a wavelength converting layer having a side surface covering the light-emitting chip, and a seal member having an opening contacting the side surface of the wavelength converting layer and covering chip electrodes. The light-emitting device can also include a transparent layer disposed into the opening of the sealing member so as to be located over the light-emitting chip and within a top surface of the light-emitting chip, and can be configured to emit various mixture lights having a high uniformity by using lights emitted from the light-emitting chip and the wavelength converting layer. Thus, the disclosed subject matter can provide the reliable light-emitting device, which can emit the mixture lights including a substantially white color light from a small light-emitting surface as a light source for a headlight, etc. | 2015-04-23 |
20150108524 | Semiconductor Nanoparticle-Based Light-Emitting Devices and Associated Materials and Methods - Embodiments of the present invention relate to a formulation for use in the fabrication of a light-emitting device, the formulation including a population of semiconductor nanoparticles incorporated into a plurality of discrete microbeads comprising an optically transparent medium, the nanoparticle-containing medium being embedded in a host light-emitting diode encapsulation medium. A method of preparing such a formulation is described. There is further provided a light-emitting device including a primary light source in optical communication with such a formulation and a method of fabricating the same. | 2015-04-23 |
20150108525 | LIGHT EMITTING DIODE FOR SURFACE MOUNT TECHNOLOGY, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING LIGHT EMITTING DIODE MODULE - Provided are a light emitting diode (LED) in which a conductive barrier layer surrounding a reflective metal layer is defined by a protective insulating layer, and a method of manufacturing the same. A reflection pattern including a reflective metal layer and a conductive barrier layer is formed on an emission structure in which a first semiconductor layer, an active layer, and a second semiconductor layer are formed. The conductive barrier layer prevents diffusion of a reflective metal layer and extends to a protective insulating layer recessed under a photoresist pattern having an overhang structure during a forming process. Accordingly, a phenomenon where the conductive barrier layer is in contact with sidewalls of the photoresist pattern having an over-hang structure and the reflective metal layer forms points is prevented. Thus, LED modules having various shapes may be manufactured. | 2015-04-23 |
20150108526 | LIGHT EMITTING DIODE - A light emitting diode includes a semiconductor stacked structure, a substrate, a first electrode, a second electrode and a third electrode. The semiconductor stacked structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. An undoped semiconductor layer over the first semiconductor layer may be not removed or not completely removed to increase the strength of the semiconductor stacked structure and improve the reliability of the LED and the production yields of manufacturing process. A roughened structure (or a photonic crystal) can be formed on the undoped semiconductor layer when the semiconductor stacked structure to improve the light emitting efficiency of the LED. | 2015-04-23 |
20150108527 | LIGHT EMITTING DIODE - A light emitting diode includes a semiconductor stacked structure, a substrate, a first electrode, a second electrode and a third electrode. The semiconductor stacked structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. A light extraction layer with a roughened structure is formed on the doped semiconductor layer to improve the light emitting efficiency of LED. Furthermore, the strength of the semiconductor stacked structure can be enhanced by the light extraction layer, to improve the reliability of the LED and the production yields of manufacturing process. | 2015-04-23 |
20150108528 | LIGHT EMITTING DIODE MODULE FOR SURFACE MOUNT TECHNOLOGY AND METHOD OF MANUFACTURING THE SAME - Provided is a light emitting diode (LED) in which a side surface of a reflective metal layer has a predetermined angle, and occurrence of cracks in a conductive barrier layer formed on the reflective metal layer can be prevented. Also, an LED module using LEDs is disclosed. A reflection pattern electrically connected to a second semiconductor layer is partially exposed by patterning a first insulating layer. Accordingly, a first pad is formed through the partially opened first pad region. Also, a conductive reflection layer electrically connected to a first semiconductor layer forms a second pad region formed by patterning a second insulating layer. A second pad is formed on the second pad region. | 2015-04-23 |
20150108529 | Light Emitting Diode Package and Method of Manufacture - A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers. | 2015-04-23 |
20150108530 | THREE DIMENSIONAL LIGHT EMITTING DIODE SYSTEMS, AND COMPOSITIONS AND METHODS RELATING THERETO - A flexible layered structure is disclosed having a flexible top conductive layer, a flexible bottom heat sink layer and a flexible dielectric middle layer. The combination has a longitudinal axis and a plurality of defined positions spaced along the longitudinal axis. The defined positions can be used for aligning a circuit and/or for the placement of LED lights. The flexible layered structure can be easily bent to form a LED substrate for shining light in more than one direction while efficiently removing heat arising from the LEDs. | 2015-04-23 |
20150108531 | METHOD OF PRODUCING A COMPONENT CARRIER, AN ELECTRONIC ARRANGEMENT AND A RADIATION ARRANGEMENT, AND COMPONENT CARRIER, ELECTRONIC ARRANGEMENT AND RADIATION ARRANGEMENT - A method of producing a component carrier for an electronic component includes a lead frame section including an electrically conductive material, the lead frame section having a first contact section that forms a first electrical contact element, a second contact section that forms a second electrical contact element, and a reception region that receives the electronic component, at least the reception region and the second contact section being electrically conductively connected to one another, a thermally conductive and electrically insulating intermediate element that dissipates heat from the reception region and electrically insulates the reception region formed at least on an opposite side of the lead frame section from the reception region, and a thermal contact that thermally contacts the electronic component formed at least on a side of the intermediate element facing away from the reception region. | 2015-04-23 |
20150108532 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND FABRICATING METHOD THEREOF - A semiconductor light-emitting device including a light-emitting semiconductor structure, a transparent dielectric pattern and an electrode pattern is provided. The light-emitting semiconductor structure includes a first semiconductor layer, a second semiconductor layer disposed opposite to the first semiconductor layer and a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer. The transparent dielectric pattern is disposed above at least one portion of the light-emitting semiconductor structure. The electrode pattern is disposed above the transparent dielectric pattern. At least one cave is formed between the transparent dielectric pattern and the light-emitting semiconductor structure. The cave is disposed opposite to the electrode pattern. Moreover, a fabricating method of the semiconductor light-emitting device is also provided. | 2015-04-23 |
20150108533 | LIGHT-EMITTING DEVICE - A drop in the luminous efficiency of a light-emitting element and the occurrence of mounting problems for the light-emitting element can be prevented even in a configuration in which an ESD protection element is provided within a mounting substrate. A light-emitting device includes a light-emitting element and a mounting substrate, having a first surface on which the light-emitting element is mounted and a second surface that is opposite from the first surface, that includes a semiconductor-based electrostatic discharge protection element portion that is provided on the second surface side and is connected to the light-emitting element. | 2015-04-23 |
20150108534 | VERTICAL LIGHT EMITTING DIODE AND FABRICATION METHOD - A vertical LED with current blocking structure and its associated fabrication method involve an anisotropic conductive material and a conductive substrate with concave-convex structure. The anisotropic conductive material forms a bonding layer with vertical conduction and horizontal insulation between the concave-convex substrate and the light-emitting epitaxial layer, thereby forming a vertical LED with current blocking function. | 2015-04-23 |
20150108535 | ENCAPSULATION MEMBER AND DISPLAY DEVICE HAVING THE SAME - An encapsulation member for a display device is disclosed. In one aspect, the encapsulation layer includes a first layer, a second layer formed over the first layer, and a third layer formed over the second layer. The third layer is formed of the same material as that of the first layer. An end of at least one of the first to third layers has a curved shape. | 2015-04-23 |
20150108536 | ESD PROTECTION DEVICE - A semiconductor ESD protection device comprising a vertical arrangement of alternating conductivity type layers, wherein the layers are arranged as silicon controlled rectifier and wherein the silicon controlled rectifier is arranged as vertical device and having top and bottom opposing contacts. | 2015-04-23 |
20150108537 | HIGH-VOLTAGE VERTICAL POWER COMPONENT - A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. | 2015-04-23 |
20150108538 | CHIP, ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND FABRICATION THEREOF - An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device comprises a N+ well, a P doping region, a first N doping region, a plurality of N sub-doping regions, a first N+ doping region, a first P+ doping region, a second N+ doping region, and a second doping region. The P doping region is disposed in the N+ well. The first N doping region is disposed in the P doping region. The plurality of N sub-doping regions is disposed in parallel in the P doping region. The first N+ doping region is disposed in the first N doping region. The first P+ doping region is disposed in the first N doping region. The second N+ doping region is disposed in the P doping region. | 2015-04-23 |
20150108539 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - A fabrication method of a semiconductor device includes forming a mask insulating film having a specified thickness on the top surface of an n-type semiconductor substrate, forming an opening at a specified position in the mask insulating film, carrying out ion implantation with p-type impurity ions onto the top surface, removing a layer portion formed in the mask insulating film with the p-type impurities included by the ion implantation, and carrying out heat treatment to diffuse the p-type impurities implanted into the n-type semiconductor substrate from the opening to a depth, thereby forming the p-type isolation region. | 2015-04-23 |
20150108540 | Semiconductor Device - A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess that extends from an upper surface of the fourth semiconductor region and reaches the second semiconductor region with penetrating the fourth semiconductor region and the third semiconductor region; a control electrode, which is arranged on the insulation film on a side surface of the recess and faces the third semiconductor region; a first main electrode, which is electrically connected to the first semiconductor region, and a second main electrode, which is electrically connected to the fourth semiconductor region, wherein a ratio of a width of the recess to a width of the third semiconductor region contacting the second main electrode is 1 or larger. | 2015-04-23 |
20150108541 | SEMICONDUCTOR DEVICE - A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally. | 2015-04-23 |
20150108542 | BIPOLAR TRANSISTOR STRUCTURE HAVING SPLIT COLLECTOR REGION AND METHOD OF MAKING THE SAME - A bipolar transistor includes a substrate and a first well in the substrate, the first well having a first dopant type. The bipolar transistor further includes a split collector region in the first well. The split collector region includes a highly doped central region having a second dopant type opposite the first dopant type; and a lightly doped peripheral region having the second dopant type, the lightly doped peripheral region surrounding the highly doped central region. A dopant concentration of the lightly doped peripheral region is less than a dopant concentration of the highly doped central region. | 2015-04-23 |
20150108543 | Source/Drain Structure of Semiconductor Device - The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface. | 2015-04-23 |
20150108544 | Fin Spacer Protected Source and Drain Regions in FinFETs - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and second portion on opposite sides of the semiconductor fin. The integrated circuit device further includes a gate stack on a top surface and sidewalls of the semiconductor fin, and a semiconductor region connected to an end of the semiconductor fin. The semiconductor region includes a first semiconductor region formed of a first semiconductor material, wherein the first semiconductor region comprise faceted top surfaces, and a second semiconductor region underlying the first semiconductor region. The second semiconductor region has a higher germanium concentration than the first semiconductor region. A fin spacer is on a sidewall of the second semiconductor region, wherein the fin spacer overlaps a portion of the insulation regions. | 2015-04-23 |
20150108545 | FIN FIELD EFFECT TRANSISTORS INCLUDING MULTIPLE LATTICE CONSTANTS AND METHODS OF FABRICATING THE SAME - A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other. | 2015-04-23 |
20150108546 | METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE - An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption. | 2015-04-23 |
20150108547 | HIGH ELECTRON MOBILITY TRANSISTOR - According to example embodiments, a high electron mobility transistor (HEMT) includes a channel layer having a 2-dimensional electron gas (2DEG), a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart from each other on one of the channel layer and the channel supply layer, at least one channel depletion layer on the channel supply layer; a gate electrode on at least a part of the channel depletion layer, and at least one bridge connecting the channel depletion layer and the source electrode. The channel depletion layer is configured to form a depletion region in the 2DEG. The HEMT has a ratio of a first impedance to a second impedance that is a uniform value. The first impedance is between the gate electrode and the channel depletion layer. The second impedance is between the source electrode and the channel depletion layer. | 2015-04-23 |
20150108548 | BASE PROFILE OF SELF-ALIGNED BIPOLAR TRANSISTORS FOR POWER AMPLIFIER APPLICATIONS - According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer. | 2015-04-23 |
20150108549 | FORMATION OF A HIGH ASPECT RATIO TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT RATIO TRENCH ISOLATION REGION - Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance C | 2015-04-23 |
20150108550 | TRANSISTOR AND METHOD FOR FORMING THE SAME - A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; patterning the channel layer to form a recess; and forming a source layer in the recess, such that at least a portion of the channel layer protrudes to form the fin-type channel. | 2015-04-23 |
20150108551 | Method Of Making A FinFET Device - A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a mandrel features over a substrate, the mandrel feature and performing a coarse cut to remove one or more mandrel features to form a coarse space. After the coarse cut, the substrate is etched by using the mandrel features, with the coarse space as an etch mask, to form fins. A spacer layer is deposited to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the coarse space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the coarse space. A fine cut is performed to remove a portion of one or more mandrel features to form an end-to-end space. An isolation trench is formed in the end-to-end space and the coarse space. | 2015-04-23 |
20150108552 | SEMICONDUCTOR DEVICE - In a cross section in a channel width direction, a semiconductor layer includes a first region of which one end portion is in contact with an insulating layer and which is positioned at one side portion of the semiconductor layer; a second region of which one end portion is in contact with the other end portion of the first region and which is positioned at an upper portion of the semiconductor layer; and a third region of which one end portion is in contact with the other end portion of the second region and the other end portion is in contact with the insulating layer and which is positioned at the other side portion of the semiconductor layer. In the second region, an interface with a gate insulating film is convex and has three regions respectively having curvature radii R1, R2, and R3 that are connected in this order from the one end portion side toward the other. R2 is larger than R1 and R3. | 2015-04-23 |
20150108553 | SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer. | 2015-04-23 |
20150108554 | Advanced Forming Method and Structure of Local Mechanical Strained Transistor - Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer. | 2015-04-23 |
20150108555 | METHOD OF MANUFACTURING IMAGE SENSORS - In a method of manufacturing an image sensor, a photodiode is formed in a substrate. The substrate is etched to form an opening vertically aligned with the photodiode. A gate insulation layer and a first preliminary polysilicon layer are formed on an inner surface of opening and a front surface of substrate. A first doping process is performed on first preliminary polysilicon layer to form first polysilicon layer, and the first polysilicon layer in the opening is uniformly doped with first conductivity type impurities. A second preliminary polysilicon layer is formed on first polysilicon layer. A second doping process is performed on second preliminary polysilicon layer to form second polysilicon layer doped with first conductivity type impurities. The first and second polysilicon layers are patterned to form a buried gate electrode in the opening. The first impurity region is formed at an upper portion of substrate adjacent to buried gate electrode. | 2015-04-23 |
20150108556 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device includes a photodiode, a first transistor, a second transistor, and a third transistor. The second transistor and the third transistor have a function of retaining a charge accumulated in a gate of the first transistor. In a period during which the second transistor and the third transistor are off, a voltage level of a voltage applied to a gate of the second transistor is set to be lower than a voltage level of a source of the second transistor and a voltage level of a drain of the second transistor, and a voltage level of a voltage applied to a gate of the third transistor is set to be lower than a voltage level of a source of the third transistor and a voltage level of a drain of the third transistor. | 2015-04-23 |
20150108557 | METAL-INSULATOR-METAL CAPACITOR STRUCTURE - A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure. | 2015-04-23 |
20150108558 | SCALABLE INTEGRATED MIM CAPACITOR USING GATE METAL - According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps. | 2015-04-23 |
20150108559 | Method of Fabricating a Tunnel Oxide Layer and a Tunnel Oxide Layer for a Semiconductor Device - A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer. | 2015-04-23 |
20150108560 | VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY - Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed. | 2015-04-23 |
20150108561 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device and a method of fabricating the same. The method may include forming trenches in a substrate and lower gate patterns on the substrate between the trenches, forming sacrificial patterns filling the trenches, forming a porous insulating layer on the lower gate patterns to cover top surfaces of the sacrificial patterns, removing the sacrificial patterns through pores of the porous insulating layer to form air gaps surrounded by the trenches and the porous insulating layer, and forming a liner insulating layer on inner surfaces of the trenches through the pores of the porous insulating layer. | 2015-04-23 |
20150108562 | Three-Dimensional Charge Trapping NAND Cell with Discrete Charge Trapping Film - A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell. | 2015-04-23 |
20150108563 | MEMORY AND MANUFACTURING METHOD THEREOF - A memory comprises a substrate, a plurality of bit line stacks of alternate semiconductor layers and first insulating layers, a memory layer, a plurality of second insulating layers, and a plurality of string select structures. The bit line stacks are disposed over the substrates and arranged in parallel. Each of the bit line stacks has two opposite sidewalls. The memory layer is disposed on the sidewalls of the bit line stacks. The second insulating layers are disposed on the bit line stacks, respectively. The string select structures are disposed correspondingly to the bit line stacks. Each of the string select structures comprises a first conductive layer and two liners, the semiconductor layer is disposed on a corresponding second insulating layer, and the two liners are disposed respectively along the two opposite sidewalls of a corresponding bit line stack and connected the first conductive layer. | 2015-04-23 |
20150108564 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region. | 2015-04-23 |
20150108565 | Power Semiconductor Devices, Structures, and Related Methods - Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types. | 2015-04-23 |
20150108566 | Semiconductor Device Comprising a Transistor Gate Having Multiple Vertically Oriented Sidewalls - A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer. | 2015-04-23 |
20150108567 | METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate. | 2015-04-23 |
20150108568 | SEMICONDUCTOR STRUCTURE WITH HIGH ENERGY DOPANT IMPLANTATION - A semiconductor device has an epitaxial layer grown over a substrate, each having a first dopant type. A structure disposed within the epitaxial layer has multiple trenches, each of which has a gate and a source electrode disposed within a shield oxide matrix. Multiple mesas each isolate a pair of the trenches from each other. A body region with a second dopant type is disposed above the epitaxial layer and bridges each of the mesas. A region of elevated concentration of the first dopant type is implanted at a high energy level between the epitaxial layer and the body region, which reduces resistance spreading into a channel of the device. A source region having the first dopant type is disposed above the body region. | 2015-04-23 |
20150108569 | METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING TRENCH TERMINATION AND TRENCH STRUCTURE THEREFOR - In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape. | 2015-04-23 |
20150108570 | SEMICONDUCTOR DEVICE - A transistor having a trench gate is controlled such that values settable as on current of the transistor are not discrete. A first transistor includes a plurality of first trenches, a first gate insulating film, and a first gate electrode. The first trenches are provided on a substrate, and are arranged side by side in a plan view. The first gate insulating film is provided on at least a side face of each of the first trenches, and over each of substrate regions located between the first trenches. The first gate electrode is embedded in each of the first trenches, and is provided over each of regions of the first gate insulating film located between the first trenches. At least one of the first trenches is formed as a circular trench in a plan view. | 2015-04-23 |
20150108571 | SELF-ALIGNED MASKLESS JUNCTION BUTTING FOR INTEGRATED CIRCUITS - A method for forming a semiconductor device includes forming gate stacks on a crystalline semiconductor layer; depositing a spacer layer over a top and sidewalls of the gate stacks; recessing the semiconductor layer between the gates stacks; and depositing a non-conformal layer over the gates stacks and within the recesses such that the non-conformal layer forms a pinch point over the recesses. The non-conformal layer is etched at a bottom of the recesses through the pinch point to expose the semiconductor layer. Dopant species are implanted at the bottom of the recesses through the pinch point in the semiconductor layer. The non-conformal layer is stripped, and source and drain material is grown in the recesses. The dopant species are activated to form PN junctions to act as a junction butt between portions of the semiconductor layer. | 2015-04-23 |
20150108572 | Electrically Isolated SiGe FIN Formation By Local Oxidation - A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein. | 2015-04-23 |
20150108573 | SEMICONDUCTOR DEVICE INCLUDING VERTICALLY SPACED SEMICONDUCTOR CHANNEL STRUCTURES AND RELATED METHODS - A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures. | 2015-04-23 |
20150108574 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a Silicon-Metal-Silicon (SMS)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a Silicon On Insulator (SOI)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate. | 2015-04-23 |
20150108575 | SYSTEMS AND METHODS FOR INTEGRATING DIFFERENT CHANNEL MATERIALS INTO A CMOS CIRCUIT BY USING A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE TRANSISTOR LAYERS - A multilayer semiconductor structure having a layout footprint with a first region and a non-overlapping second region and different transistor types fabricated using different channel material. The semiconductor structure comprises a first transistor layer comprising a first type of channel material in the first region but no channel material in the second region. The semiconductor structure further comprises a second transistor layer comprising a second type of channel material in the second region but no channel material in the first region. The second transistor layer is vertically elevated above the first transistor layer. A first transistor is fabricated on the first transistor layer. A second transistor is fabricated on the second transistor layer, and the first transistor is interconnected with the second transistor to form a circuit. | 2015-04-23 |
20150108576 | METHOD FOR FABRICATING NMOS AND PMOS TRANSISTORS ON A SUBSTRATE OF THE SOI, IN PARTICULAR FDSOI, TYPE AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOT substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region. | 2015-04-23 |
20150108577 | SELECTIVE GROWTH OF A WORK-FUNCTION METAL IN A REPLACEMENT METAL GATE OF A SEMICONDUCTOR DEVICE - Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device. | 2015-04-23 |
20150108578 | AQUEOUS CLEANING TECHNIQUES AND COMPOSITIONS FOR USE IN SEMICONDUCTOR DEVICE MANUFACTURE - Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used. Other embodiments related to a semiconductor device resulting from the method. | 2015-04-23 |
20150108579 | SEMICONDUCTOR DEVICE - The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer. | 2015-04-23 |
20150108580 | METHODS OF FORMING BIPOLAR DEVICES AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH BIPOLAR DEVICES - One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures. | 2015-04-23 |
20150108581 | FINFET HAVING ISOLATION STRUCTURE AND METHOD OF FORMING THE SAME - A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, a first isolation structure over the upper surface of the substrate, and a second isolation structure. The fin structure extends along a first direction and comprising a lower portion and an upper portion. The first isolation structure surrounds the lower portion of the fin structure. The second isolation structure is at least partially embedded in the upper portion of the fin structure. | 2015-04-23 |
20150108582 | FINFET HAVING DOPED REGION AND METHOD OF FORMING THE SAME - A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure. | 2015-04-23 |
20150108583 | DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND METHODS OF MAKING SAME - One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively | 2015-04-23 |
20150108584 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first device isolation pattern defining a first active region, a second device isolation pattern defining a second active region, a first gate disposed on the first active region, the first gate including a gate insulating pattern of a first thickness and a second gate disposed on the second active region, the second gate including a gate insulating pattern of a second thickness greater than the first thickness. A top surface of the first device isolation pattern is curved down toward the first active region such that the first active region has an upper portion protruded from the top surface and rounded corners. | 2015-04-23 |
20150108585 | FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR - Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel and the substrate. Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate. The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions. | 2015-04-23 |
20150108586 | TRANSISTOR DEVICE WITH IMPROVED SOURCE/DRAIN JUNCTION ARCHITECTURE AND METHODS OF MAKING SUCH A DEVICE - One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region. | 2015-04-23 |
20150108587 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation. | 2015-04-23 |
20150108588 | RADIATION HARDENED MOS DEVICES AND METHODS OF FABRICATION - Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density. | 2015-04-23 |
20150108589 | EMBEDDED INTERLEVEL DIELECTRIC BARRIER LAYERS FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS - A semiconductor structure may be formed by forming a sacrificial gate above a substrate covered by a hard mask, depositing a first interlevel dielectric (ILD) layer above the sacrificial gate, recessing the first ILD layer to a thickness less than the height of the sacrificial gate, depositing an etch barrier layer above the first ILD layer, depositing a second ILD layer above the etch barrier layer, planarizing the second ILD layer and the etch barrier layer to expose the hard mask using the hard mask as a planarization stop, removing the hard mask and sacrificial gate to form a gate cavity, forming a replacement metal gate in the gate cavity, removing the second ILD layer, and planarizing the replacement metal gate using the etch barrier layer as a planarization stop. A supplementary electrode layer may be formed above the replacement metal gate prior to planarizing the replacement metal gate. | 2015-04-23 |
20150108590 | ANISOTROPIC DIELECTRIC MATERIAL GATE SPACER FOR A FIELD EFFECT TRANSISTOR - Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction. | 2015-04-23 |