16th week of 2018 patent applcation highlights part 52 |
Patent application number | Title | Published |
20180108695 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT - The invention relates to an optoelectronic semiconductor component ( | 2018-04-19 |
20180108696 | IMAGING DEVICE - An imaging device which does not include a color filter and does not need arithmetic processing using an external processing circuit is provided. A first circuit includes a first photoelectric conversion element, a first transistor, and a second transistor; a second circuit includes a second photoelectric conversion element, a third transistor, and a fourth transistor; a third circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and a second capacitor; the spectroscopic element is provided over the first photoelectric conversion element or the second photoelectric conversion element; and the first circuit and the second circuit is connected to the third circuit through a first capacitor. | 2018-04-19 |
20180108697 | STACKED LENS STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example. | 2018-04-19 |
20180108698 | CMOS IMAGE SENSOR - A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having a front side and a back side and a pixel region having a plurality of pixels in the front side, each pixel including a sensor element, forming a metal reflective layer in the front side of the substrate and on the pixel region, thinning the back side of the substrate, doping the thinned back side of the substrate with a dopant, and laser annealing the doped back side of the substrate. The sensor element is configured to receive incident light to the thinned back side of the semiconductor substrate. The metal reflective layer reflects heat generated in the laser annealing process to more fully activate the dopant in the back side of the substrate, thereby effectively reducing dark current and improving the device performance. | 2018-04-19 |
20180108699 | Design Method for an Image Sensor Device - A design method for an image sensor device includes providing an initial design for an image sensor device. The initial design includes a pixel array region and a through-via region disposed proximate the pixel array region. The initial design has a first length between the pixel array region and the through-via region. The initial design has a second length that is a width of the through-via region. The design method includes analyzing a ratio of the second length and the first length, and modifying the initial design to achieve a ratio of the second length and the first length within a particular range. | 2018-04-19 |
20180108700 | Receiver Array Packaging - The present disclosure relates to optical receiver systems. An example system includes a plurality of substrates disposed in an edge-to-edge array along a primary axis. Each respective substrate of the plurality of substrates includes a plurality of detector elements. Each detector element of the plurality of detector elements generates a respective detector signal in response to light received by the detector element. The plurality of detector elements is arranged with a detector pitch between adjacent detector elements of the plurality of detector elements. Each respective substrate of the plurality of substrates also includes a signal receiver circuit configured to receive the detector signals generated by the plurality of detector elements. The respective substrates of the plurality of substrates are disposed such that the detector pitch is maintained between adjacent detector elements on their respective substrates. | 2018-04-19 |
20180108701 | INFRARED DETECTOR, INFRARED DETECTION SENSOR HAVING AN INFRARED DETECTOR AND METHOD OF MANUFACTURING THE SAME - An infrared detector includes a substrate, a light blocking layer on the substrate, a lower electrode on the light blocking layer, the lower electrode electrically connected to the light blocking layer, a lower insulating layer on the light blocking layer, a first semiconductor layer on the lower insulating layer, a first source electrode and a first drain electrode on the first semiconductor layer, an upper insulating layer on the first semiconductor layer, and a first gate electrode on the upper insulating layer, the first gate electrode electrically connected to the lower electrode, where the first semiconductor layer includes a zinc and a nitrogen, and the first semiconductor layer is configured to generate electric charges by reacting with an infrared ray. | 2018-04-19 |
20180108702 | Methods of Making Semiconductor X-Ray Detector - Disclosed herein is a method of making an apparatus suitable for detecting x-ray, the method comprising: attaching a chip comprising an X-ray absorption layer to a surface of a substrate, wherein the surface is electrically conductive; thinning the chip; forming an electrical contact in the chip; bonding an electronic layer to the chip such that the electrical contact of the chip is electrically connected to an electrical contact of the electronic layer. | 2018-04-19 |
20180108703 | Vertically Integrated Image Sensor Chips and Methods for Forming the Same - A method includes bonding a Backside Illumination (BSI) image sensor chip to a device chip, forming a first via in the BSI image sensor chip to connect to a first integrated circuit device in the BSI image sensor chip, forming a second via penetrating through the BSI image sensor chip to connect to a second integrated circuit device in the device chip, and forming a metal pad to connect the first via to the second via. | 2018-04-19 |
20180108704 | WAFER LEVEL LIGHT-EMITTING DIODE ARRAY - A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes. | 2018-04-19 |
20180108705 | LIGHT-EMITTING DIODE DEVICE - A light-emitting diode device includes a substrate; a plurality of light-emitting units formed on the substrate, wherein the plurality of light-emitting units form a serially-connected array, and the serially-connected array includes: a plurality of adjacent light-emitting unit columns; a first light-emitting unit row; a second light-emitting unit row; and a third light-emitting unit row adjacent with the second light-emitting unit row; and a plurality of conductive connecting structures connecting the plurality of light-emitting units; wherein the light-emitting units in the first light-emitting unit rows having the same connecting direction; wherein the second and the third light-emitting unit rows include N light-emitting units with (N−1) times of sequentially connecting via (N−1) conductive connecting structures, and the (N−1) times of the sequentially connecting comprise (N/2) times of vertical connecting or (N/2) times of horizontal connections. | 2018-04-19 |
20180108706 | SPIN-SELECTIVE ELECTRON RELAY - Structures including a spin torque transfer magnetic tunnel junction (MTJ) stack and methods for fabricating same. A first contact is coupled with a first portion of a free layer of the MTJ stack, and a second contact is coupled with a second portion of the free layer of the MTJ stack. The free layer is laterally arranged between the first contact and the second contact. | 2018-04-19 |
20180108707 | THRESHOLD SWITCHING DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC DEVICE INCLUDING THE SAME - A threshold switching device may include: a first electrode layer; a second electrode layer; a first insulating layer interposed between the first and second electrode layers, and provided adjacent to the first electrode layer; and a second insulating layer interposed between the first and second electrode layers, and provided adjacent to the second electrode layer, wherein the first and second insulating layers contain a plurality of neutral defects, a concentration of the plurality of neutral defects being at a maximum along a first interface between the first insulating layer and the second insulating layer, and wherein the threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects. | 2018-04-19 |
20180108708 | RESISTIVE MEMORY CELL STRUCTURES AND METHODS - Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material. | 2018-04-19 |
20180108709 | Organic Light Emitting Diode Device Integrated with Color Filter Electrode and Method of Manufacturing the Same - Provided are an organic light emitting diode (OLED) device integrated with a color filter electrode, which is formed by inserting an intermediate layer having conductivity between a plurality of metal films, and a method of manufacturing the same. The OLED device includes: a first electrode layer configured to function as an anode electrode to provide holes; an organic emission layer disposed above the first electrode layer and configured to cause a reaction between the holes and electrons to generate light; and a color filter electrode layer disposed above the first electrode layer and the organic emission layer and configured to selectively transmit a color in each region, function as a cathode electrode due to conductivity thereof, and provide the electrons to the organic emission layer. | 2018-04-19 |
20180108710 | TOUCH DISPLAY PANEL - The disclosure relates to a touch display panel, including a first substrate, an organic light emitting diode (OLED) device layer, a spacer, a first touch electrode, a second touch electrode, and a second substrate opposite to the first substrate. The OLED device layer is disposed on the first substrate and has a light emitting area. The spacer is disposed on the OLED device layer and located outside the light emitting area. The first touch electrode and the second touch electrode are disposed on the OLED device layer. The first touch electrode has a first bridge part. The first bridge part of the first touch electrode is interlaced with the second touch electrode. In particular, at least a portion of the first bridge part is disposed on the spacer. | 2018-04-19 |
20180108711 | DISPLAY DEVICE AND ELECTRONIC APPARATUS - A display device includes a pixel portion including a plurality of pixels; a display switching function portion that displays an image based on light emitted from the pixel portion, and is capable of switching a three-dimensional display and a two-dimensional display of the image; and a sensor portion that detects whether or not an object comes into contact with or approaches. | 2018-04-19 |
20180108712 | DISPLAY DEVICE AND ELECTRICAL DEVICE USING THE SAME - A display device includes: a substrate comprising a first region and a second region bent relative to the first region; a plurality of first pixels at the first region, each of the first pixels comprising a first light-emitting diode (LED), the first LED comprising a pixel electrode, an emission layer for emitting light of a first color, and a counter electrode; a plurality of second pixels at the second region, each of the second pixels comprising a second LED, the second LED comprising a pixel electrode, an emission layer configured to emit the first color, and a counter electrode; and an optical resonance layer at the second region corresponding to the second LED. | 2018-04-19 |
20180108713 | Light-Emitting Device, Electronic Appliance, and Lighting Device - A light-emitting device and a lighting device each of which includes a plurality of light-emitting elements exhibiting light with different wavelengths are provided. The light-emitting device and the lighting device each have an element structure in which each of the light-emitting elements emits only light with a desired wavelength, and thus the light-emitting elements have favorable color purity. In the light-emitting element emitting light (λ | 2018-04-19 |
20180108714 | DISPLAY DEVICE AND MANUFACTURING METHOD OF A DISPLAY DEVICE - A manufacturing method of a display device according to an embodiment of the present invention includes: the display device including a protection plate having a light transmitting part facing an input or output device, and a display substrate having a display area, a light emitting film forming the step of forming an island-like light emitting film containing a light emitting material, in an area other than the display area in the display substrate; an alignment step of aligning the protection plate and the display substrate with each other; and an attaching step of attaching the protection plate to the display substrate. | 2018-04-19 |
20180108715 | ORGANIC EL DISPLAY DEVICE - An organic EL display device includes a bank having an inclined surface, a first electrode formed on the inclined surface, an organic film including a light emitting layer and directly contacting the first electrode on the inclined surface, and a second electrode directly contacting the organic film on the inclined surface. | 2018-04-19 |
20180108716 | FLEXIBLE DISPLAY - Example implementations relate to flexible displays. For example, a flexible display system may comprise a plurality of display layers, an anti-reflective layer among the plurality of display layers to reduce reflection from an underlying light emitting layer, the anti-reflective layer including a wave plate and a polarizer, and a transistor layer among the plurality of display layers. Further, at least a portion of the plurality of display layers may include properties satisfying particular geometric and force balance constraints to enable the transistor layer to maintain a neutral force in response to compression or tension of the flexible display. | 2018-04-19 |
20180108717 | DISPLAY DEVICE - A display device includes a substrate comprising a first plastic layer, a second plastic layer on the first plastic layer, and an inorganic layer between the first plastic layer and the second plastic layer, an inorganic embossed layer on the substrate and comprising a plurality of mountain parts, an organic layer on the inorganic embossed layer, an inorganic buffer layer on the organic layer, a thin film transistor on the inorganic buffer layer, and a display element electrically connected to the thin film transistor. | 2018-04-19 |
20180108718 | ORGANIC LIGHT-EMITTING DIODE PANEL AND MANUFACTURING METHOD USING THE SAME - An organic light-emitting diode panel and a manufacturing method using the same are provided in the present invention. The OLED panel includes at least a pixel. The pixel includes a anode conducting layer, an insulation layer, an emitting layer (EML), a cathode layer and a reference voltage layer. The anode conducting layer is disposed on a transparent substrate. The insulation layer is disposed on the anode conducting layer and has a first cavity and a second cavity, wherein there is a distance between the first anode layer and the bottom of second cavity. There are a hole injection layer (HIL) and a hole transmission layer (HTL). The HIL is disposed on the first anode conducting layer. The HTL is disposed on the HIL. There are a cathode layer, an electronic injection layer (EIL) and an electronic transmission layer (ETL) in the second cavity. The cathode layer is exposed by the bottom of the second cavity. The EIL is disposed on the cathode layer. The ETL is disposed on the EIL. The EML is disposed on the insulation layer. The reference voltage layer is disposed on the EML. | 2018-04-19 |
20180108719 | OLED DISPLAY DEVICE AND MANUFACTURE METHOD THEREOF - A method for manufacturing an OLED display device that includes pixel areas is provided. A first and a second substrates are provided. TFTs are arranged on the first substrate. A passivation layer is formed on the TFTs such that the passivation layer includes a concave area formed in a surface thereof to expose a part of a drain of each of the TFTs. A transparent anode is formed on the second substrate. Partition walls are arranged on the transparent anode to defined therebetween transmission holes respectively corresponding to the pixel areas. An organic layer is formed on the transparent anode and located in the transmission holes. A metal cathode is formed on the organic layer and the partition walls such that the metal cathode is receivable into the concave area and electrically engageable with the exposed part of the drain of each of the TFTs. | 2018-04-19 |
20180108720 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting diode (OLED) display device includes a substrate, a first gate electrode on the substrate, a second gate electrode on the first gate electrode and at least partially overlapping the first gate electrode, a semiconductor pattern between the first gate electrode and the second gate electrode and at least partially overlapping the first and second gate electrodes, a connecting electrode on the second gate electrode and electrically connected to the semiconductor pattern, and a pixel electrode on the connecting electrode and electrically connected to the connecting electrode. | 2018-04-19 |
20180108721 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device is provided. The organic light-emitting display device comprises a plurality of data lines, first and second sensing lines disposed on a same layer as the data lines, an insulating layer disposed on the data lines and the first and second sensing lines, and a power line disposed on the insulating layer. An area of overlap between the first sensing line and the power line is the same as an area of overlap between the second sensing line and the power line. | 2018-04-19 |
20180108722 | DISPLAY DEVICE - A display device includes a substrate having an edge portion, a display region located on the substrate and separated from the edge portion, a drive circuit region between the display region and the edge portion, a terminal region on the edge portion; and wirings in the display region, the drive circuit region, and an area between the drive circuit region and the terminal region, wherein at least one wiring of the wirings include a first conductive layer, a second conductive layer overlapping the first conductive layer in a plan view and separated from the first conductive layer, a first connection portion where the first conductive layer and the second conductive layer are electrically connected, a second connection portion where the first conductive layer and the second conductive layer are electrically connected, and the first connection portion is separated from the second connection portion. | 2018-04-19 |
20180108723 | DISPLAY DEVICE AND METHOD OF MANUFACTURING A DISPLAY DEVICE - A display device according to an embodiment of the present invention includes: a base material including a display region, and a peripheral region which is located outside the display region, at least a part of the peripheral region being a bending region; an insulating layer that is disposed on the base material, extends from the display region to a part of the peripheral region, and is located apart from an edge of the base material; at least one level difference moderating layer that is disposed under the insulating layer and extends from an edge of the insulating layer toward a side of the bending region; and at least one wiring disposed on the insulating layer and the at least one level difference moderating layer. | 2018-04-19 |
20180108724 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device includes: a substrate including a first area, a second area, and a bending portion between the first area and the second area; a pixel at the first area of the substrate; a terminal at the second area of the substrate; a first conductive line on the bending portion of the substrate and extending from the first area to the second area; a first organic layer on the first conductive line; a second inorganic layer on the first organic layer in an area other than the bending portion; and a second conductive line on the first organic layer and the second inorganic layer and overlapping the first conductive line to extend from the first area to the second area. The first conductive line and the second conductive line contact each other in at least one of the first area and the second area. | 2018-04-19 |
20180108725 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. In the present invention, a wiring including Cu is provided as an electrode or a wiring used for the display device represented by the EL display device and the liquid crystal display device. Besides, sputtering is performed with a mask to form the wiring including Cu. With such structure, it is possible to reduce the voltage drop and a deadened signal. | 2018-04-19 |
20180108726 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - An organic light-emitting display apparatus and a manufacturing method thereof. The organic light-emitting display apparatus includes a substrate, a display unit arranged on the substrate, a dam unit arranged at a periphery of the display unit and on the substrate and an encapsulating layer to encapsulate the display unit, wherein the encapsulating layer includes an organic film covering the display unit, and an inorganic film covering the organic film and the dam unit, and wherein a hardness of the dam unit is lower than that of the inorganic film. According to this, lateral moisture-proof characteristics of the organic light-emitting display apparatus are improved. | 2018-04-19 |
20180108727 | PILLAR RESISTOR STRUCTURES FOR INTEGRATED CIRCUITRY - Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. | 2018-04-19 |
20180108728 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES - Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole. | 2018-04-19 |
20180108729 | STRUCTURES TO AVOID FLOATING RESURF LAYER IN HIGH VOLTAGE LATERAL DEVICES - A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines. | 2018-04-19 |
20180108730 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to the first main surface, forming an epitaxial layer on the first main surface, the epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which the silicon carbide substrate is located, forming a trench, which includes side walls intersecting with the third main surface and a bottom portion connected to the side walls, in the epitaxial layer, widening an opening of the trench, and forming an embedded region, which has a second conductivity type different from the first conductivity type, in the trench. The epitaxial layer adjacent to the embedded region and the embedded region constitute a superjunction structure. | 2018-04-19 |
20180108731 | METHOD FOR LOCAL ISOLATION BETWEEN TRANSISTORS PRODUCED ON AN SOI SUBSTRATE, IN PARTICULAR AN FDSOI SUBSTRATE, AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench. | 2018-04-19 |
20180108732 | NOTCHED FIN STRUCTURES AND METHODS OF MANUFACTURE - The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch. | 2018-04-19 |
20180108733 | PROCESS FOR FABRICATING A FIELD EFFECT TRANSISTOR HAVING A COATING GATE - A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire. | 2018-04-19 |
20180108734 | Semiconductors With Increased Carrier Concentration - Within examples, a semiconductor device includes a first structure that includes a first doped semiconductor material of a first doping type. The semiconductor device further includes a metal in contact with the first structure, and a second structure that includes a second doped semiconductor material of the first doping type in contact with the first structure. A band off-set for majority charge carriers between the first doped semiconductor material and the second doped semiconductor material is sufficiently large for charge carriers from the second doped semiconductor material to be transferred into the first doped semiconductor material. | 2018-04-19 |
20180108735 | APPROACH TO MINIMIZATION OF STRAIN LOSS IN STRAINED FIN FIELD EFFECT TRANSISTORS - A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure. | 2018-04-19 |
20180108736 | COMPRESSIVE STRAIN SEMICONDUCTOR SUBSTRATES - A method for forming a compressively strained semiconductor substrate includes forming a lattice adjustment layer on a semiconductor substrate by forming compound clusters within an epitaxially grown semiconductor matrix. The lattice adjustment layer includes a different lattice constant than the semiconductor substrate. A rare earth oxide is grown and lattice matched to the lattice adjustment layer. A semiconductor layer is grown and lattice matched to the rare earth oxide and includes a same material as the semiconductor substrate such that the semiconductor layer is compressively strained. | 2018-04-19 |
20180108737 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction. | 2018-04-19 |
20180108738 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, including: a first conductivity-type drift region formed in the semiconductor substrate; a second conductivity-type base region formed between the upper surface of the semiconductor substrate and the drift region; a first conductivity-type accumulation region formed between the drift region and the base region and having a higher doping concentration than the drift region; and a dummy trench portion formed to penetrate the base region from the upper surface of the semiconductor substrate, wherein at least one of the accumulation region and the dummy trench portion has a suppressing structure that suppresses formation of a second conductivity-type inversion layer in a first conductivity-type region adjacent to the dummy trench portion. | 2018-04-19 |
20180108739 | HANDLE FOR SEMICONDUCTOR-ON-DIAMOND WAFERS AND METHOD OF MANUFACTURE - Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers to a carrier are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers. | 2018-04-19 |
20180108740 | METHOD FOR MAKING AN ELECTRICAL CONTACT ON A GRAPHITE LAYER, CONTACT OBTAINED BY USING SUCH A METHOD AND ELECTRONIC DEVICE USING SUCH A CONTACT - A method for manufacturing a graphite layer on an interstitial carbide layer, includes depositing a metal layer formed by one or more metals on a carbide substrate, the metal layer being able to form an interstitial carbide, the metal layer at least partially covering the carbide substrate; performing a heat treatment during which a temperature higher than the dissociation temperature of the carbide of the carbide substrate is applied; wherein the heat allows a reaction between the metal layer and the carbide substrate to form the interstitial carbide layer as well as a first part of the graphite layer at the surface of the interstitial carbide layer, and, when the metal layer only partially covers the carbide substrate, a formation of a second part of the graphite layer at the surface of the carbide substrate which is not covered with the metal layer. | 2018-04-19 |
20180108741 | Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication - A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening. | 2018-04-19 |
20180108742 | Semiconductor Device and Method of Forming the Same - A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion. | 2018-04-19 |
20180108743 | POWER ELECTRONIC AND OPTOELECTRONIC DEVICES WITH INTERDIGITATED ELECTRODES - This invention relates to interdigitated electrodes for power electronic and optoelectronic devices where field and current distribution determine the device performance. Described are geometries based on rounded asymmetrical fingers and electrode bases of varying width. Simulations demonstrate benefits for reducing self-heating and thermal power loss, which reduces overall on-state resistance and increases reverse break down voltages. | 2018-04-19 |
20180108744 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge. | 2018-04-19 |
20180108745 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF - A method for fabricating a semiconductor structure includes providing a base structure including an NMOS region, forming an interlayer dielectric layer on the base structure with a plurality of openings formed in the NMOS region through the interlayer dielectric layer, forming a high-k dielectric layer on a bottom and sidewall surfaces of each opening of the NMOS region, forming an N-type work function layer on the high-k dielectric layer in each opening of the NMOS region, forming a diffusion barrier layer on the N-type work function layer, performing a hydrogenation process on the diffusion barrier layer, and forming a metal gate electrode on the diffusion barrier layer to fill up each opening in the NMOS region. The disclosed method and semiconductor structure improve the ability of the barrier layer to protect the N-type work function layer, and thus improve the electrical performance of the semiconductor device. | 2018-04-19 |
20180108746 | THIN FILM TRANSISTORS (TFTS), MANUFACTURING METHODS OF TFTS, AND CMOS COMPONENTS - The present disclosure relates to a TFT, a manufacturing method of TFTs, and a CMOS component. The TFT includes a substrate, a LTPS layer arranged close to the substrate, a first light doping area and a second light doping area on the same layer with the LTPS layer and arranged at two opposite ends of the LTPS layer, a first heavy doping area and a second heavy doping area arranged at the same layer with the LTPS layer, a first insulation layer having a first portion and a second portion, and a gate arranged on the second portion. The first heavy doping area is arranged on one end of the first light doping area farther away from the LTPS layer, and the second heavy doping area is arranged on one end of the second light doping area farther away from the LTPS layer. | 2018-04-19 |
20180108747 | III-V SEMICONDUCTOR LAYERS, III-V SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF - In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby foaming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer. | 2018-04-19 |
20180108748 | Gate Structure and Method of Forming the Same - A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer. | 2018-04-19 |
20180108749 | TRENCH SILICIDE CONTACTS WITH HIGH SELECTIVITY PROCESS - A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions. | 2018-04-19 |
20180108750 | TECHNIQUES FOR FORMING TRANSISTORS ON THE SAME DIE WITH VARIED CHANNEL MATERIALS - Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage. | 2018-04-19 |
20180108751 | Integrated strained stacked nanosheet FET - Transistors include stress liners, with one or more semiconductor structures between the stress liners. The stress liners provide a stress on the one or more semiconductor structures. A gate is formed over and around the one or more semiconductor structures. A source and drain region is formed on the one or more semiconductor structures on opposite sides of the gate, between the stress liners. | 2018-04-19 |
20180108752 | STRESS RETENTION IN FINS OF FIN FIELD-EFFECT TRANSISTORS - Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin. | 2018-04-19 |
20180108753 | HEMTs with an AlxGa1-xN Barrier layer Grown by Plasma Enhanced Atomic Layer Deposition - In a method of manufacturing a high-electron mobility transistor (HEMT), a first Group III-V semiconductor layer is formed on a substrate. The first Group III-V semiconductor layer is patterned to form a fin and a recessed surface. A second Group III-V semiconductor layer is formed to cover a top surface and all side surfaces of the fin and the recessed surface. The second Group III-V semiconductor layer is formed by a plasma-enhanced atomic layer deposition, in which a plasma treatment is performed on every time an as-deposited mono-layer is formed. | 2018-04-19 |
20180108754 | VERTICAL TRANSISTOR WITH VARIABLE GATE LENGTH - A method includes forming a plurality of fins on a substrate. The method further includes forming a plurality of deep trenches in the substrate and interposed between each fin of the plurality of fins. The method further includes forming a doped semiconductor layer having a uniform thickness, wherein the doped semiconductor layer is formed prior to removing any fins of the plurality of fins. | 2018-04-19 |
20180108755 | FINFET LDMOS DEVICES WITH IMPROVED RELIABILITY - A finFET LDMOS semiconductor device includes a first well disposed adjacent to a second well on a substrate and a third well disposed on the substrate, wherein the second well is disposed between the first well and the third well. Additionally, the finFET LDMOS semiconductor device includes a source disposed on the first well, a fin at least partially disposed on the first well and adjacent to the source, a drain disposed on the third well, a shallow trench isolation (STI) disposed at least partially in the third well, and a STI protection structure disposed on the substrate between the second well and the third well and along a side of the STI that is closest to the source, wherein the STI protection structure is configured to discourage a drain to source current from flowing along the side of the STI that is closest to the source. | 2018-04-19 |
20180108756 | THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, DISPLAY APPARATUS - The disclosure provides a thin film transistor (TFT) and a fabrication method thereof, an array substrate and a fabrication method thereof, and a display apparatus. The fabrication method of a TFT includes: forming a protection layer in an area on an active layer between a source electrode and a drain electrode to be formed, forming a source-drain metal layer above the active layer having the protection layer formed thereon, coating a photoresist on the source-drain metal layer, and forming a photoresist reserved area corresponding to areas of the source electrode and the drain electrode to be formed and a photoresist non-reserved area corresponding to the other area; etching off the source-drain metal layer corresponding to the photoresist non-reserved area to form the source and drain electrodes and expose the protection layer above the active layer; and removing the photoresist above the source and drain electrodes and the protection layer. | 2018-04-19 |
20180108757 | POLYSILICON THIN FILM AND MANUFACTURING METHOD THEREOF, TFT AND MANUFACTURING METHOD THEREOF, AND DISPLY PANEL - A manufacturing method for a polysilicon thin film is provided. The manufacturing method for a polysilicon thin film includes forming a polysilicon layer, treating a surface of the polysilicon layer so that the surface of the polysilicon layer is electronegative, and supplying polar gas into a process chamber so that polar molecules of the polar gas are adsorbed on the surface of the polysilicon layer which is electronegative so as to form the polysilicon thin film, a surface of which has a hole density higher than an electron density. | 2018-04-19 |
20180108758 | SELF-ALIGNED CHANNEL-ONLY SEMICONDUCTOR-ON-INSULATOR FIELD EFFECT TRANSISTOR - In one example, a field effect transistor includes a fin. The fin includes a conducting channel formed from semiconductor-on-insulator and source/drain regions formed on opposite ends of the conducting channel, wherein the source/drain regions are formed from a material other than semiconductor-on-insulator. A gate is wrapped around the conducting channel, between the source/drain regions. In another example, a method for fabricating a field effect transistor includes forming a fin on a wafer. The fin includes a conducting channel formed from semiconductor-on-insulator and source/drain regions formed on opposite ends of the conducting channel, wherein the source/drain regions are formed from a material other than semiconductor-on-insulator. A gate is also formed between the source/drain regions and wraps around the conducting channel. | 2018-04-19 |
20180108759 | THIN FILM TRANSISTOR, FABRICATION METHOD THEREOF, AND ARRAY SUBSTRATE - A thin film transistor, a fabrication method thereof, and an array substrate are provided. The fabrication method includes: forming a semiconductor layer and a photoresist layer on a substrate, dividing the substrate, the semiconductor layer and the photoresist layer into a first, second and third regions; performing ladder exposure on the photoresist layer, then developing, completely removing the photoresist layer of the first region and partly removing the photoresist layer of the second region; removing the semiconductor layer of the first region, and forming a pattern including an active region; thinning the photoresist layer: completely removing the photoresist layer of the second region, and partly removing a part of the photoresist layer of the third region; allowing the active region of the second region to be metalized and forming an ohmic contact layer; removing the photoresist layer of the third region; and forming a pattern including a source and a drain. | 2018-04-19 |
20180108760 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor. | 2018-04-19 |
20180108761 | TUNNEL FIELD-EFFECT TRANSISTOR (TFET) WITH LATERAL OXIDATION - A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials. | 2018-04-19 |
20180108762 | BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath. | 2018-04-19 |
20180108763 | SEMICONDUCTOR-ON-INSULATOR LATERAL HETEROJUNCTION BIPOLAR TRANSISTOR HAVING EPITAXIALLY GROWN INTRINSIC BASE AND DEPOSITED EXTRINSIC BASE - After forming a trench extending through an insulator layer and an underlying top semiconductor portion that is comprised of a first semiconductor material and a dopant of a first conductivity type to define an emitter and a collector on opposite sides of the trench in the top semiconductor portion, an intrinsic base comprising a second semiconductor material having a bandgap less than a bandgap of the first semiconductor material and a dopant of a second conductivity type opposite the first conductivity type is formed in a lower portion the trench by selective epitaxial growth. The intrinsic base protrudes above the top semiconductor portion and is laterally surrounded by entire top semiconductor portion and a portion of the insulator layer. An extrinsic base is then formed on top of the intrinsic base to fill a remaining volume of the trench by a deposition process. | 2018-04-19 |
20180108764 | SEMICONDUCTOR DEVICE - In an active region, a MOS gate of an IGBT is provided on a front surface side of a semiconductor substrate. In an edge termination region, a Zener diode is provided on the front surface of the semiconductor substrate, via a field oxide film. The semiconductor substrate is one of semiconductor chips formed by cutting, into individual chips, a diffused wafer that includes a p | 2018-04-19 |
20180108765 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device. | 2018-04-19 |
20180108766 | VERTICAL POWER COMPONENT - A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate. | 2018-04-19 |
20180108767 | METHOD FOR MANUFACTURING A HEMT TRANSISTOR AND HEMT TRANSISTOR WITH IMPROVED ELECTRON MOBILITY - A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer. | 2018-04-19 |
20180108768 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device disclosed herein includes: a GaN carrier transit layer formed on a substrate; a barrier layer formed on the carrier transit layer; a first recess and a second recess formed in the barrier layer; a first InAlN layer and a second InAlN layer formed in the first recess and the second recess respectively, a composition ratio of In in the InAlN layers being equal to or more than 17% and equal to or less than 18%; a source electrode formed on the first InAlN layer; a drain electrode formed on the second InAlN layer; and a gate electrode formed on the barrier layer. | 2018-04-19 |
20180108769 | FORMING STRAINED CHANNEL WITH GERMANIUM CONDENSATION - A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin. | 2018-04-19 |
20180108770 | SELF-ALIGNED GATE CUT WITH POLYSILICON LINER OXIDATION - A method of forming a semiconductor device that includes forming a gate structure over a plurality of fin structures, wherein the gate structure provides a first fill pinch off between the fin structures separated by a first pitch; and forming a material stack of a silicon containing layer, and a dielectric layer over the plurality of fin structures, wherein the dielectric provides a second fill pinch off between fin structures separated by a second pitch. The silicon containing layer is converted into an oxide material layer. The second dielectric that provides the second fill pinch off is removed, and an opening is etched in a remaining silicon containing layer exposed by removing the second fill pinch off. An underlying gate cut region is etched in the gate structure using the opening in the remaining portion of the silicon containing layer. | 2018-04-19 |
20180108771 | APPROACH TO MINIMIZATION OF STRAIN LOSS IN STRAINED FIN FIELD EFFECT TRANSISTORS - A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure. | 2018-04-19 |
20180108772 | SPLIT FIN FIELD EFFECT TRANSISTOR ENABLING BACK BIAS ON FIN TYPE FIELD EFFECT TRANSISTORS - A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode. | 2018-04-19 |
20180108773 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display device are provided. The array substrate includes a base substrate and a gate metal layer, an active layer and a source/drain metal layer disposed on the base substrate; the gate metal layer includes a gate line and a storage electrode line that extends in parallel to the gate line; the active layer includes a first pattern taken as a channel region of a thin-film transistor (TFT) and a second pattern at least partially overlapped with the storage electrode line in a thickness direction of the base substrate, or the source/drain metal layer includes a data line pattern and a metal layer pattern at least partially overlapped with the storage electrode line in the thickness direction of the base substrate. | 2018-04-19 |
20180108774 | Semiconductor Device and Method for Manufacturing Same - A semiconductor device includes an n+ type silicon carbide substrate, an n− type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type. | 2018-04-19 |
20180108775 | STRUCTURE OF SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN STRUCTURES - Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region. | 2018-04-19 |
20180108776 | VERTICAL TRANSISTORS STRESSED FROM VARIOUS DIRECTIONS - A vertical transistor includes a semiconductor substrate, and fin(s) over the semiconductor substrate (n-type fin(s) and/or p-type fin(s)), the fin(s) acting as vertical transistor channels for vertical transistors. Each of the fin(s) is lattice mismatched at one or more interface(s), being stressed from below, from above, from fin sidewalls or combination(s) thereof. The vertical transistors can be realized by providing a semiconductor substrate, forming stressed fin(s) of vertical transistor(s) acting as vertical transistor channels, the stressed fin(s) being lattice mismatched at one or more interfaces and being stressed from below, above, sidewalls or combination(s) thereof. | 2018-04-19 |
20180108777 | SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND EPITAXIAL MATERIALS - A semiconductor device includes a first gate stack over a substrate. The semiconductor device further includes a first epitaxial (epi) material in the substrate on a first side of the first gate stack. The first epi material includes a first upper surface having a first crystal plane. The semiconductor device further includes a second epi material in the substrate on a second side of the first gate stack opposite the first side. The second epi material includes a second upper surface having a second crystal plane, and the first crystal plane is different from the second crystal plane. | 2018-04-19 |
20180108778 | FORMATION OF FINFET JUNCTION - A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET. | 2018-04-19 |
20180108779 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region. | 2018-04-19 |
20180108780 | THIN FILM TRANSISTOR AND MANUFACTURE METHOD THEREOF - The disclosure provides a thin film transistor (TFT) and a manufacture method thereof. The TFT includes: a substrate; a gate electrode, formed on the substrate; a gate insulating layer, formed on the gate electrode; a semiconductor layer, formed on the gate insulating layer and corresponding to the gate electrode; a pixel electrode, disposed on the same layer with the semiconductor layer; an ohmic contact layer, formed on the same layer with the semiconductor layer and formed on the same layer with the pixel electrode; a source electrode and a drain electrode, disposed on the ohmic contact layer. According to the TFT and the manufacture method thereof of the exemplary embodiments of the disclosure, the pixel electrode and the semiconductor layer are formed on the same layer, the semiconductor layer and the pixel electrode can be produced by only one mask, which can reduce mask consumption and processes. | 2018-04-19 |
20180108781 | LIGHT EMITTING DIODE DISPLAY SUBSTRATE, A METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - A light emitting diode display substrate, a method of manufacturing the same, and a display device are provided. The method includes: forming a planarization layer and a photoresist layer in sequence on a substrate on which a thin film transistor is formed, a light sensitivity of the planarization layer being higher than a light sensitivity of the photoresist layer; etching the planarization layer and the photoresist layer simultaneously, such that a pixel defining pattern is formed through a removed portion of the photoresist layer, and an anode via pattern is formed at a position of the planarization layer corresponding to the pixel defining pattern; forming an anode pattern layer on the substrate on which the above steps were performed, wherein the anode pattern layer comprises a plurality of anodes, such that the planarization layer located at edges of the anode via pattern covers edges of the anodes. | 2018-04-19 |
20180108782 | MANUFACTURING METHOD OF TFT SUBSTRATE AND TFT SUBSTRATE - The invention provides a manufacturing method of TFT substrate and a TFT substrate. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching. | 2018-04-19 |
20180108783 | PREPARATION METHODS FOR SEMICONDUCTOR LAYER AND TFT, TFT, ARRAY SUBSTRATE - Embodiments of the present disclosure provide preparation methods for a semiconductor layer and a TFT, a TFT and an array substrate. The preparation method for a semiconductor layer: includes forming a silicon dioxide film on a substrate; forming sidewalls at two ends of the semiconductor layer to be formed by patterning process; performing amination treatment on the sidewalls so that an aminosiloxane monolayer self-assembly is formed on the surface of the sidewalls; carboxylating a carbon nanotube solution and making the carboxylated carbon nanotube solution on the surface of the substrate with the sidewalls formed to form a carbon nanotube film; removing portions of the carbon nanotube film other than the portion between the sidewalls to form a semiconductor layer. | 2018-04-19 |
20180108784 | LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A low temperature poly-silicon thin film transistor includes at least an interlayer dielectric layer formed of a material including silicon oxide and silicon nitride, in such a way that the interlayer dielectric layer includes a depression region channel in a stepped form. A source metal layer and a drain metal layer are formed in the depression region channel in the stepped form. | 2018-04-19 |
20180108785 | SEMICONDUCTOR DEVICE - High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed. | 2018-04-19 |
20180108786 | ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE - An array substrate, a liquid crystal display panel and a liquid crystal display device are disclosed. The present invention designs that a width of the gate electrode is less than a width of an active layer of a thin-film transistor, and is greater than a width of a channel. Through shortening the width of the gate electrode, decreasing an overlapping region between the source electrode and the gate electrode and between the drain electrode and the gate electrode, a parasitic capacitance between the source electrode, the drain electrode and the gate electrode is reduced in order to increase the display quality. | 2018-04-19 |
20180108787 | PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE - A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure. A dielectric spacer having a graded composition is present in direct contact with the gate structure. The dielectric spacer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires. | 2018-04-19 |
20180108788 | Schottky Diode and Method for Its Manufacturing - The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas. | 2018-04-19 |
20180108789 | METHOD FOR MANUFACTURING AN EDGE TERMINATION FOR A SILICON CARBIDE POWER SEMICONDUCTOR DEVICE - A method for manufacturing an edge termination structure for a silicon carbide power semiconductor device having a central region and an edge region is provided. The following manufacturing steps are performed: a) providing an n-doped silicon carbide substrate, b) epitaxially growing a silicon carbide n-doped drift layer on the substrate, which has a lower doping concentration than the substrate, c) creating at least one p-doped termination layer by implanting a second ion up to a maximum termination layer depth and annealing on the first main side, d) forming a doping reduction layer having a depth range, which doping reduction layer comprises at least one doping reduction region, wherein a depth of a doping concentration minimum of the doping reduction layer is greater than the maximum termination layer depth, wherein for the creation of each doping reduction region: implanting a first ion with an implantation energy in the drift layer at least in the edge region, wherein the first ion and the at least one implantation energy are chosen such that the doping reduction layer depth range is less than 10 μm, e) annealing the doping reduction layer, wherein step d) and e) are performed such that the doping concentration of the drift layer is reduced in the doping reduction layer. | 2018-04-19 |
20180108790 | TRANSPARENT CONDUCTIVE ELECTRODE FOR THREE DIMENSIONAL PHOTOVOLTAIC DEVICE - A photovoltaic device includes a substrate layer having a plurality of three-dimensional structures formed therein providing a textured profile. A first electrode is formed over the substrate layer and extends over the three-dimensional structures including non-planar surfaces. The first electrode has a thickness configured to maintain the textured profile, and the first electrode includes a transparent conductive material having a dopant metal activated within the transparent conductive material. A continuous photovoltaic stack is conformally formed over the first electrode, and a second electrode is formed on the photovoltaic stack. | 2018-04-19 |
20180108791 | METAL-ASSISTED ETCH COMBINED WITH REGULARIZING ETCH - In an aspect of the disclosure, a process for forming nanostructuring on a silicon-containing substrate is provided. The process comprises (a) performing metal-assisted chemical etching on the substrate, (b) performing a clean, including partial or total removal of the metal used to assist the chemical etch, and (c) performing an isotropic or substantially isotropic chemical etch subsequently to the metal-assisted chemical etch of step (a). In an alternative aspect of the disclosure, the process comprises (a) performing metal-assisted chemical etching on the substrate, (b) cleaning the substrate, including removal of some or all of the assisting metal, and (c) performing a chemical etch which results in regularized openings in the silicon substrate. | 2018-04-19 |
20180108792 | SOLAR CELL - A solar cell comprising a semiconductor substrate, an intrinsic semiconductor layer, a second conductive type semiconductor layer, a transparent conductive layer, a metal electrode, a light reflective unit, and a transparent packaging layer. The semiconductor substrate has an illuminated surface, which includes an effective absorption region and an ineffective absorption region. The intrinsic semiconductor layer is formed on the illuminated layer. The second conductive type semiconductor layer is formed on the intrinsic semiconductor layer. The transparent conductive layer is formed on the second conductive type semiconductor layer. The metal electrode is located on the transparent conductive layer. The light reflective unit is located on the ineffective absorption region and has a first inclined reflective surface. The transparent packaging layer is located on the transparent conductive layer, the metal electrode, and the light reflective unit. | 2018-04-19 |
20180108793 | LIFTOFF PROCESS FOR EXFOLIATION OF THIN FILM PHOTOVOLTAIC DEVICES AND BACK CONTACT FORMATION - A method for forming a back contact on an absorber layer in a photovoltaic device includes forming a two dimensional material on a first substrate. An absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) is grown over the first substrate on the two dimensional material. A buffer layer is grown on the absorber layer on a side opposite the two dimensional material. The absorber layer is exfoliated from the two dimensional material to remove the first substrate from a backside of the absorber layer opposite the buffer layer. A back contact is deposited on the absorber layer. | 2018-04-19 |
20180108794 | SPACE-QUALIFIED SOLAR CELL MODULE WITH INTERCONNECTION OF NEIGHBORING SOLAR CELLS ON A COMMON BACK PLANE - A space-qualified solar cell assembly comprising a plurality of space-qualified solar cells mounted on a support, the support comprising a plurality of conductive vias extending from the top surface to the rear surface of the support. Each one of the plurality of space-qualified solar cells is placed on the top surface with the first contact of a first polarity of the space-qualified solar cell electrically connected to the first conductive via. A second contact of a second polarity of each space-qualified solar cell can be connected to a second conductive via so that the first and second conductive portions form terminals of opposite conductivity type. The space-qualified solar cells on the module can be interconnected to form a string or an electrical series and/or parallel connection by suitably interconnecting the terminal pads of the vias on the back side of the module. | 2018-04-19 |