16th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120091469 | Semiconductor Devices Having Shallow Junctions - Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer. | 2012-04-19 |
20120091470 | Programmable Gate III-Nitride Power Transistor - A III-nitride semiconductor device which includes a charged floating gate electrode. | 2012-04-19 |
20120091471 | LIGHTLY DOPED SILICON CARBIDE WAFER AND USE THEREOF IN HIGH POWER DEVICES - A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 10 | 2012-04-19 |
20120091472 | SILICON CARBIDE SUBSTRATE - A first circular surface is provided with a first notch portion having a first shape. A second circular surface is opposite to the first circular surface and is provided with a second notch portion having a second shape. A side surface connects the first circular surface and the second circular surface to each other. The first notch portion and the second notch portion are opposite to each other. The side surface has a first depression connecting the first notch portion and the second notch portion to each other. | 2012-04-19 |
20120091473 | ELECTRONIC DEVICE WHICH PERFORMS AS LIGHT EMITTING DIODE AND SOLAR CELL - An electronic device performing as a light emitting diode and a solar cell, and which comprises: a solar cell unit including a first electrode layer, an energy-level compensation layer formed on the first electrode layer, a photoelectric-conversion layer formed on the energy level compensation layer, and a shared electrode layer formed on the photoelectric-conversion layer; and a light emitting diode unit including the shared electrode layer, and a light emitting layer formed on the shared electrode layer and a second electrode layer formed on the light emitting layer, wherein a LUMO energy-level of the energy-level compensation layer is smaller than a work function of the first electrode layer and is larger than a LUMO energy level of the photoelectric-conversion layer, thereby increasing the generating efficiency of the solar cell unit or the luminous efficiency of the light emitting diode unit due to high electron mobility among the respective layers. | 2012-04-19 |
20120091474 | NOVEL SEMICONDUCTOR AND OPTOELECTRONIC DEVICES - A light-emitting integrated wafer structure, comprising: three overlying layers, wherein each of the three overlying layers emits light at a different wavelength and wherein at least one of the three overlying layers is transferred to the light-emitting integrated wafer structure using one of atomic species implants assisted cleaving, laser lift-off, etch-back, or chemical-mechanical-polishing (CMP). | 2012-04-19 |
20120091475 | Method of treating the surface of a soda lime silica glass substrate, surface-treated glass substrate, and device incorporating the same - Certain example embodiments of this invention relate to methods of treating the surface of a soda lime silica glass substrate, e.g., a soda lime silica alkali ion glass substrate, and the resulting surface-treated glass articles. More particularly, certain example embodiments of this invention relate to methods of removing a top surface portion of a glass substrate using ion sources. During or after removal of this portion, the glass may then be coated with another layer, to be used as a capping layer. In certain example embodiments, the glass substrate coated with a capping layer may be used as a color filter and/or TFT substrate in an electronic device. In other example embodiments, the glass substrate with the capping layer thereon may be used in a variety of display devices. | 2012-04-19 |
20120091476 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting unit and a submount. The light emitting unit has a plurality of light emitting diodes (LEDs), and the submount has a plurality of conductive contacts on a side thereof. The LEDs are coupled to the conductive contacts in various electrical connection manners, such that the LEDs are connected in series or/and in parallel. | 2012-04-19 |
20120091477 | Organic Light Emitting Diode Display - An organic light emitting diode (OLED) display comprises: a substrate; a display unit formed on the substrate and including an organic light emitting element; an interception layer positioned at the outside of the display unit on the substrate; and a thin film encapsulation layer which is formed with a stacked film of an inorganic film and an organic film, which has an end portion contacting the interception layer, and which covers the entire display unit and at least a part of the interception layer. | 2012-04-19 |
20120091478 | LIGHT EMITTING DEVICE HAVING A PLURALILTY OF LIGHT EMITTING CELLS AND PACKAGE MOUNTING THE SAME - A light emitting device includes a plurality of light emitting cells which are formed on a substrate and each of which has an N-type semiconductor layer and a P-type semiconductor layer located on a portion of the N-type semiconductor layer. The plurality of light emitting cells are bonded to a submount substrate. Heat generated from the light emitting cells can be easily dissipated, so that a thermal load on the light emitting device can be reduced. Since the plurality of light emitting cells are electrically connected using connection electrodes or electrode layers formed on the submount substrate, it is possible to provide light emitting cell arrays connected to each other in series. Further, it is possible to provide a light emitting device capable of being directly driven by an AC power source by connecting the serially connected light emitting cell arrays in reverse parallel to each other. | 2012-04-19 |
20120091479 | ELECTROOPTIC DEVICE AND ELECTRONIC APPARATUS - Pixel electrodes having reflectivity are arranged at a predetermined pitch in a matrix form on an effective display region on an opposed surface of an element substrate. A first conductive pattern which is formed by the same layer as the pixel electrodes is provided on an ineffective display region which is at an outer side with respect to the effective display region and at an inner side with respect to a sealing region when seen from the above. A second conductive pattern which is formed by the same layer as the pixel electrodes is provided on the sealing region. An area density of the second conductive pattern is smaller than an area density of the first conductive pattern when seen from the above. | 2012-04-19 |
20120091480 | LIGHT-EMITTING DEVICE - A light-emitting device includes a substrate, a plurality of light-emitting elements mounted on one surface of the substrate, a first glass film provided to one surface of the substrate and having a plurality of apertures that form a light-reflecting frame surrounding the perimeter of each the light-emitting elements, and a second glass film provided to the other surface of the substrate. A coefficient of thermal expansion of the second glass film is greater than that of the substrate when a coefficient of thermal expansion of the first glass film is greater than that of the substrate, and a coefficient of thermal expansion of the second glass film is less than that of the substrate when a coefficient of thermal expansion of the first glass film is less than that of the substrate. | 2012-04-19 |
20120091481 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device includes a light-emitting element and a support substrate. The light-emitting element has an insulating layer and first and second vertical conductors passing through the insulating layer. The support substrate has a substrate part and first and second through electrodes and is disposed on the insulating layer. The first through electrode passes through the substrate part with one end connected to an opposing end of the first vertical conductor, while the second through electrode passes through the substrate part with one end connected to an opposing end of the second vertical conductor. The opposing ends of the first and second vertical conductors are projected from a surface of the insulating layer and connected to the ends of the first and second through electrode inside the support substrate. | 2012-04-19 |
20120091482 | ORGANIC EL ELEMENT, METHOD FOR MANUFACTURING THE SAME, AND ORGANIC EL DISPLAY DEVICE | 2012-04-19 |
20120091483 | ORGANIC LIGHT-EMITTING PANEL AND MANUFACTURING METHOD THEREOF, AND ORGANIC DISPLAY DEVICE - A non-light-emitting cell | 2012-04-19 |
20120091484 | Display device and organic light emitting diode display - A display device includes: a display substrate; a display formed on the display substrate; an encapsulation substrate affixed to the display substrate by an adhering layer surrounding the display, the display substrate including a composite member including a resin matrix and a plurality of carbon fibers and an insulation member attached to an edge of the composite member and forming a through hole; a metal layer positioned on a side of the encapsulation substrate facing the substrate; and a conductive connector filling the through hole and contacting the metal layer. The composite member is stacked with at least two layers with different sizes, and the insulation member contacts sides of the at least two layers and has the same thickness as the composite member. | 2012-04-19 |
20120091485 | LIGHT EMITTING DEVICE - A light emitting diode device comprises a light source and a gas vent device. The gas vent device comprises a base having a collector, wherein a conversion element is located inside the collector. A portion of heat generated from the light source is transferred into thermal energy to gasify the conversion element and the other portion is dissipated via the gas vent device. Therefore, the light emitting device is able to provide illuminant and gasify the conversion element simultaneously. | 2012-04-19 |
20120091486 | PHOSPHOR AND LIGHT EMITTING DEVICE - The present invention provides a phosphor, including a constituent having the formula Ca | 2012-04-19 |
20120091487 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode package comprises a substrate and a lens. The substrate comprises two electrodes and a LED chip disposed thereon, wherein the LED chip electrically connects to one of the electrodes via a conductive wire. The connection between the conductive wire and the corresponding electrode is covered by an encapsulation. The lens is located on the substrate and covers the encapsulation. Moreover, the substrate comprises at least two tunnels inside the covering of the lens penetrating the substrate. A collector is located between the substrate and the lens, wherein a transparent layer is formed inside the collector by injecting fluid material through the tunnels or directly injecting fluid material into the collector. A method for manufacturing the light emitting diode package is also provided. | 2012-04-19 |
20120091488 | METHOD FOR MANUFACTURING A STRUCTURE WITH A TEXTURED SURFACE FOR AN ORGANIC LIGHT-EMITTING DIODE DEVICE, AND STRUCTURE WITH A TEXTURED SURFACE - A method for manufacturing a structure having a textured surface, including a substrate made of mineral glass having a given texture, for an organic-light-emitting-diode device, the method including supplying a rough substrate, having a roughness defined by a roughness parameter Ra ranging from 1 to 5 μm over an analysis length of 15 mm and with a Gaussian filter having a cut-off frequency of 0.8 mm; and depositing a liquid-phase silica smoothing film on the substrate, the film being configured to smooth the roughness sufficiently and to form the textured surface of the structure. | 2012-04-19 |
20120091489 | SUBSTRATE FOR MOUNTING LIGHT-EMITTING ELEMENTS, LIGHT-EMITTING DEVICE, AND METHOD FOR MANUFACTURING SAME - A frame body surrounding a perimeter of each light-emitting element is provided one surface of a substrate. Glass films having apertures are formed on the substrate by glass printing to form the frame body. | 2012-04-19 |
20120091490 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - Provided is a light-emitting device including: a nitride semiconductor light-emitting element ( | 2012-04-19 |
20120091491 | Radiation-Emitting Optical Component - A radiation-emitting semiconductor component, having a layer structure which includes an active layer which, in operation, emits radiation with a spectral distribution, and electrical contacts for applying a current to the layer structure, includes a coating layer which at least partially surrounds the active layer and holds back a short-wave component of the emitted radiation. | 2012-04-19 |
20120091492 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURE - A light emitting device includes a conductive support layer, a light emitting structure layer on the conductive support layer, a first transparent conductive layer and a second transparent conductive layer disposed between the conductive support layer and the light emitting structure layer, and an electrode on the light emitting structure layer. | 2012-04-19 |
20120091493 | SEMICONDUCTOR CHIP ASSEMBLY WITH BUMP/BASE/LEDGE HEAT SPREADER, DUAL ADHESIVES AND CAVITY IN BUMP - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal. | 2012-04-19 |
20120091494 | COMPOSITE LUMINESCENT MATERIAL FOR SOLID-STATE SOURCES OF WHITE LIGHT - A composite luminescent material for solid white light sources that include a light-emitting diode radiating in the 430-480 nm range and a mixture of at least two phosphors, one of which has yellow-orange luminescence in the 560-630 nm range, while the other one belongs to the group of aluminates of alkali-earth metals, activated by europium, different in that the second phosphor represents at least one light storage phosphor, virtually unexcitable by the light-emitting diode primary radiation and having a long afterglow. Cerium-activated yttrium-aluminate and/or terbium-aluminate garnets of various compositions, with the general formula (Ln) | 2012-04-19 |
20120091495 | LIGHT REFLECTING SUBSTRATE AND PROCESS FOR MANUFACTURE THEREOF - A light reflecting substrate comprises at least: an insulating layer and a metal layer disposed in contact with the insulating layer. The total reflectivity of light in the wavelength range of more than 320 nm and not more than 700 nm is not less than 50% and the total reflectivity of light in the wavelength range of 300 nm to 320 nm is not less than 60%. The light reflecting substrate further improves the emission power of the light-emitting device when used as the substrate therefor. | 2012-04-19 |
20120091496 | SUBMOUNT AND MANUFACTURING METHOD THEREOF - A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency. | 2012-04-19 |
20120091497 | Light Emitting Device - Embodiments relate to a light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises: a substrate; a light emitting structure over the substrate, the light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, wherein the first conductive type semiconductor layer is partially exposed; a first region having a first concentration and provided at a region of the second conductive type semiconductor layer; a second region having a second concentration and provided at another region of the second conductive type semiconductor layer; and a second electrode over the second conductive type semiconductor layer. | 2012-04-19 |
20120091498 | METHOD FOR FORMING A LIGHT-EMITTING CASE AND RELATED LIGHT-EMITTING MODULE - A method for manufacturing a light-emitting case includes forming a flat panel light emitting diode, and covering the flat panel light emitting diode with transparent plastic material. The transparent plastic material has properties of flexibility, high gas-resistance and water-resistance. When the light-emitting case is forced, the shape of the light-emitting case can be changed. | 2012-04-19 |
20120091499 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND PROCESS FOR PRODUCTION THEREOF - The present invention provides a semiconductor light-emitting element comprising an electrode part excellent in ohmic contact and capable of emitting light from the whole surface. An electrode layer placed on the light-extraction side comprises a metal part and plural openings. The metal part is so continuous that any pair of point-positions in the part is continuously connected without breaks, and the metal part in 95% or more of the whole area continues linearly without breaks by the openings in a straight distance of not more than ⅓ of the wavelength of light emitted from an active layer. The average opening diameter is of 10 nm to ⅓ of the wavelength of emitted light. The electrode layer has a thickness of 10 nm to 200 nm, and is in good ohmic contact with a semiconductor layer. | 2012-04-19 |
20120091500 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A light emitting device uses a conductive bonding agent in bonding a package and a cap, and the light emitting device is a non-air tight and can be manufactured stably, with an improved yield. A method of manufacturing the light emitting device includes a step of bonding a cap having a frame portion to a package having a light emitting element mounted in a recess of the package to cover an opening of the recess. In the step of bonding, a metal bonding agent having greater wettability to the frame portion than to the package is partially disposed to the package or the frame portion, and extended along the frame portion so that ends of the metal bonding agent are joined to each other. With this, a space is defined at a joining portion where the ends of the metal bonding agent are joined, and the package and the frame portion are bonded. | 2012-04-19 |
20120091501 | Low triggering voltage DIAC structure - In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node. | 2012-04-19 |
20120091502 | SEMICONDUCTOR DEVICE HAVING PLURAL INSULATED GATE SWITCHING CELLS AND METHOD FOR DESIGNING THE SAME - In a semiconductor device including a plurality of insulated gate switching cells each of which has a gate electrode, an emitter electrode that is commonly provided to cover the plurality of insulated gate switching cells, and a bonding wire connected to the emitter electrode, a gate driving voltage being applied to the gate electrode of each insulated gate switching cell so that emitter current flows through the emitter electrode, mutual conductance of each insulated gate switching cell is varied in accordance with the distance from the connection portion corresponding to the bonding position of the bonding wire so that the emitter current flowing through the emitter electrode is substantially equal among the plurality of insulated gate switching cells. | 2012-04-19 |
20120091503 | HIGH-VOLTAGE ESD PROTECTION DEVICE - The present invention discloses a high-voltage ESD protection device including a silicon controlled rectifier and a first PNP transistor. The silicon controlled rectifier includes a high-voltage P-well and N-well; a first N+ and P+ diffusion region are formed in the high-voltage P-well; a second N+ and P+ diffusion region are formed in the high-voltage N-well. The first PNP transistor comprises an N-type buried layer; a low-voltage N-well formed in the N-type buried layer; and a base, emitter and collector formed in the low-voltage N-well. The base and emitter are shorted together; the collector is shorted to the second N+ diffusion region and the second P+ diffusion region; the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal. The high-voltage ESD protection device can effectively adjust the ESD trigger voltage and improve the snapback sustaining voltage after the device is switched on. | 2012-04-19 |
20120091504 | METHOD OF FORMING AN ESD PROTECTION DEVICE AND STRUCTURE THEREFOR - In one embodiment, a bi-directional ESD device is formed to have a third harmonic at frequencies no less than about one gigahertz wherein the third harmonic has a magnitude that is no greater than about minus thirty five dBm. | 2012-04-19 |
20120091505 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes an element isolation insulating film formed on a substrate, an element region and a dummy pattern region demarcated by the element isolation insulating film on the substrate, a first epitaxial crystal layer formed on the substrate within the element region, and a second epitaxial crystal layer formed on the substrate within the dummy pattern region. The first epitaxial crystal layer is made up of crystals that have a different lattice constant from that of the crystals that constitute the substrate. The second epitaxial crystal layer is made up of the same crystals as the first epitaxial crystal layer. The (111) plane of the substrate that includes any points on the interface between the second epitaxial crystal layer and the substrate is surrounded by the element isolation insulating film in a deeper region than the second epitaxial crystal layer. | 2012-04-19 |
20120091506 | Method and Structure for pFET Junction Profile With SiGe Channel - A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed. | 2012-04-19 |
20120091507 | STRUCTURE OF HETEROJUNCTION FIELD EFFECT TRANSISTOR AND A FABRICATION METHOD THEREOF - An improved structure of heterojunction field effect transistor (HFET) and a fabrication method thereof are disclosed. The improved HFET structure comprises sequentially a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a Schottky capping layer formed by a higher energy gap material, a tunneling layer formed by a lower energy gap material, a first etching stop layer, and a first n type doped layer. The fabrication method is a multiple selective etching process, which comprises steps of: etching the n type doped layer by using a first etching process to form a first indentation; etching first etching stop layer by using a second etching process to form a second indentation located under the first indentation; etching the tunneling layer by using a third etching process to form a third indentation located under the second indentation, wherein the said first, second and third indentations form a single gate groove, in which the gate electrode can form a Schottky contact with the Schottky capping layer that is made of a higher energy gap material. | 2012-04-19 |
20120091508 | COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device includes: a compound semiconductor layer; a source electrode; a drain electrode; a gate electrode; a field plate; and a low-conductivity region. The low-conductivity region is arranged within a region immediately below the field plate in a region where the two-dimensional carrier gas layer is formed, and has lower conductivity than a region above which the field plate or the gate electrode is not arranged in the region where the two-dimensional carrier gas layer is formed. | 2012-04-19 |
20120091509 | SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region. | 2012-04-19 |
20120091510 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, MASK FOR SEMICONDUCTOR MANUFACTURE, AND OPTICAL PROXIMITY CORRECTION METHOD - An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area ( | 2012-04-19 |
20120091511 | MULTI-FIN DEVICE BY SELF-ALIGNED CASTLE FIN FORMATION - The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W | 2012-04-19 |
20120091512 | MICROSYSTEM FOR ANALYZING BLOOD - The present disclosure utilizes the MEMS (Micro Electro Mechanical Systems) process and packaging method to produce a microsystem for analyzing blood which is capable of detecting several kinds of ions. The microsystem for analyzing blood has a miniaturized reference electrode, so size of the microsystem can be greatly reduced. The microsystem further has a gate detecting area larger than a conventional planar ISE or a conventional ISFET does, so interference with signals can be avoided, and packaging difficulty and blood leakage can be reduced. Therefore, the microsystem is thin and small, reacts rapidly, and has a high accuracy, and a high compatibility with IC (integrated circuit) process. In addition, the microsystem has high stability of long-term potential, low offset-potential characteristics, low alternating current impedance, high stability of dynamic reference potential, low electrochemical noises and high reproducibility of the electrode. | 2012-04-19 |
20120091513 | SEMICONDUCTOR SWITCH DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR SWITCH DEVICE - A semiconductor switch device and a method of manufacturing the semiconductor switch device are provided. The semiconductor switch device includes semiconductor elements on a single semiconductor substrate. At least one of the semiconductor elements constitutes a switch circuit and at least one other of the semiconductor elements constitutes a logic (connection) circuit. Each semiconductor element includes a recess, a gate electrode in the recess, a drain electrode, and a source electrode. In one representative aspect, the gate electrode in the switch circuit can have a rectangular external shape in section, and the gate electrode in the connection circuit has a shape in section other than rectangular. | 2012-04-19 |
20120091514 | Semiconductor Junction Diode Device And Method For Manufacturing The Same - A semiconductor junction diode device structure and a method for manufacturing the same are provided, where a gate of the diode device structure is directly formed on the substrate, a P-N junction is formed in the semiconductor substrate, a first contact is formed on the gate, and a second contact is formed on the doped region at both sides of the gate, the first contact and the second contact acting as cathode/anode of the diode device, respectively. The diode device of this structure occupies a small area, and its forming process may be integrated in a gate-last integration process of MOSFET devices, which needs no additional mask and costs and has a high integration level. | 2012-04-19 |
20120091515 | Semiconductor Devices Having Backside Illuminated Image Sensors - A semiconductor substrate includes a photodiode on a support substrate. An insulating layer is provided between the support substrate and the semiconductor substrate. A first conductive pattern is provided in the insulating layer. A first through electrode penetrates the support substrate to be in contact with the first conductive pattern. | 2012-04-19 |
20120091516 | Lateral Floating Coupled Capacitor Device Termination Structures - Voltage termination structures include one or more capacitively coupled trenches, which can be similar to the trenches in the drift regions of the active transistor. The capacitively coupled trenches in the termination regions are arranged with an orientation that is either parallel or perpendicular to the trenches in the active device drift region. The Voltage termination structures can also include capacitively segmented trench structures having dielectric lined regions filled with conducting material and completely surrounded by a silicon mesa region. The Voltage termination structures can further include continuous regions composed entirely of an electrically insulating layer extending a finite distance vertically from the device surface. | 2012-04-19 |
20120091517 | SCRATCH PROTECTION FOR DIRECT CONTACT SENSORS - In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed. | 2012-04-19 |
20120091518 | SEMICONDUCTOR DEVICE, METHOD FOR FORMING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device includes a semiconductor substrate having a first groove, a word line in the first groove, and a buried insulating film in the first groove. The buried insulating film covers the word line. The buried insulating film comprises a silicon nitride film. | 2012-04-19 |
20120091519 | METHOD AND APPARATUS FOR IMPROVING CAPACITOR CAPACITANCE AND COMPATIBILITY - A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces. | 2012-04-19 |
20120091520 | SEMICONDUCTOR DEVICE, METHOD FOR FORMING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect. | 2012-04-19 |
20120091521 | MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF - Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at one end of the substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion. For other embodiments, thicknesses of respective control gates of the memory cells and/or thicknesses of the dielectrics between successively adjacent control gates may increase as the distances of the respective control gates/dielectrics from the opposing end of the substantially vertical portion increase. | 2012-04-19 |
20120091522 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition. | 2012-04-19 |
20120091523 | TRENCH MOSFET WITH TRENCH CONTACT HOLES AND METHOD FOR FABRICATING THE SAME - A trench MOSFET with trench contact holes and a method for fabricating the same are disclosed. The MOSFET includes an N type substrate, an N type epitaxial layer on the substrate; a P well region on top of the epitaxial layer; a source region formed on the P well region; an oxide layer on the source region; a plurality of trenches which traverse the source region and the P well region and contact the epitaxial layer; a gate oxide layer and polysilicon formed in the trenches; a source contact hole and a gate contact hole, wherein the source contact hole and the gate contact hole have a titanium metal layer, a titanium nitride layer, and tungsten metal sequentially, respectively; a P+ implanted region; a source electrode formed above the source contact hole and a gate electrode formed above the gate contact hole. | 2012-04-19 |
20120091524 | LDMOS DEVICE STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention discloses an LDMOS device structure, including a MOS transistor cell, wherein an isolation region is formed on each outer side of both a source region and a drain region of the MOS transistor cell; each isolation region includes a plurality of isolation trenches and isolates the MOS transistor cell from its surroundings; the height of the isolation region is smaller than that of a gate of the MOS transistor cell. The present invention also discloses a manufacturing method of the LDMOS device structure, including forming isolation trenches by lithography and etching processes, then forming isolation regions of SiO | 2012-04-19 |
20120091525 | Split Gate Oxides for a Laterally Diffused Metal Oxide Semiconductor (LDMOS) - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a split gate oxide architecture to form the gate oxide. The gate oxide includes a first gate oxide having a first thickness and a second gate oxide having a second thickness. | 2012-04-19 |
20120091526 | ULTRA HIGH VOLTAGE MOS TRANSISTOR DEVICE - An ultra high voltage MOS transistor device includes a substrate having a first conductivity type and a first recess formed thereon, a gate positioned on the first recess, and a pair of source region and drain region having a second conductivity type formed in two sides of the gate, respectively. | 2012-04-19 |
20120091527 | LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) TRANSISTORS - Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region. | 2012-04-19 |
20120091528 | FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD OF MANUFACTURING SAME - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure. | 2012-04-19 |
20120091529 | HIGH VOLTAGE RESISTOR - Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities. | 2012-04-19 |
20120091530 | Low trigger voltage electrostatic discharge NFET in triple well CMOS technology - An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type. | 2012-04-19 |
20120091531 | Flexible Integration of Logic Blocks with Transistors of Different Threshold Voltages - An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions. | 2012-04-19 |
20120091532 | Semiconductor Devices Including Buried-Channel-Arrray Transistors - Provided is a semiconductor device in which a short margin between a storage contact plug and a bit line contact plug may be increased. The device includes a substrate including isolation regions and active regions defined by the isolation regions, gates disposed in the substrate and configured to intersect the active regions and define source regions and drain regions in the active regions, an interlayer insulating layer disposed on the substrate, bit line contact plugs configured to penetrate the interlayer insulating layer and contact the drain regions, and first bit line structures and second bit line structures disposed on the interlayer insulating layer. The first bit line structures include first bit line conductive patterns and first bit line spacers covering sidewalls of the first bit line conductive patterns. The second bit line structures include second bit line conductive patterns configured to contact the bit line contact plugs to be substantially parallel to the first bit line conductive patterns and first bit line spacers covering sidewalls of the second bit line conductive patterns and sidewalls of the bit line contact plugs. | 2012-04-19 |
20120091533 | SEMICONDUCTOR DEVICES INCLUDING ETCHING STOP FILMS - A semiconductor device may include a substrate including an NMOS region and a PMOS region. A gate structure can include a gate pattern and a spacer pattern, where the gate structure is on the substrate. A first etching stop film can be on the substrate in the NMOS region and a second etching stop film can be on the substrate in the PMOS region. A contact hole can penetrate the first and second etching stop films and a contact plug can be in the contact hole. A thickness of the first etching stop film can be greater than a thickness of the second etching stop film. Related methods are also disclosed. | 2012-04-19 |
20120091534 | SEMICONDUCTOR DEVICE WITH STRAIN - A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region. | 2012-04-19 |
20120091535 | Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach - By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches. | 2012-04-19 |
20120091536 | CMOS STRUCTURE AND LATCH-UP PREVENTING METHOD OF SAME - A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants. | 2012-04-19 |
20120091537 | SEMICONDUCTOR DEVICE - In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors. | 2012-04-19 |
20120091538 | FINFET AND METHOD OF FABRICATING THE SAME - The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin. | 2012-04-19 |
20120091539 | FACET-FREE SEMICONDUCTOR DEVICE - An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free. | 2012-04-19 |
20120091540 | STRAINED STRUCTURE OF A P-TYPE FIELD EFFECT TRANSISTOR - In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity | 2012-04-19 |
20120091541 | MIXED METAL OXIDES - The present invention relates to a mixed metal oxide of formula SrM1-xTixO3 wherein x is 0>x>1 and M is Hf or Zr, such as a strontium-hafnium-titanium oxide orstrontium-zirconium-titanium oxide, and to a functional device comprising the mixed metal oxide. | 2012-04-19 |
20120091542 | METHODS FOR THE DEPOSITION OF TERNARY OXIDE GATE DIELECTRICS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include introducing a first metal source, a second metal source and an oxygen source into a chamber and then forming a ternary oxide film comprising a first percentage of the first metal, a second percentage of the second metal, and a third percentage of oxygen. | 2012-04-19 |
20120091543 | ELECTROMECHANICAL TRANSDUCER AND METHOD OF MANUFACTURING THE SAME - An electromechanical transducer includes multiple elements each including at least one cellular structure, the cellular structure including: a semiconductor substrate, a semiconductor diaphragm, and a supporting portion for supporting the diaphragm so that a gap is formed between one surface of the substrate and the diaphragm. The elements are separated from one another at separating locations of a semiconductor film including the diaphragm. Each of the elements includes in a through hole passing through a first insulating layer including the supporting portion and the semiconductor substrate: a conductor which is connected to the semiconductor film including the diaphragm; and a second insulating layer for insulating the conductor from the semiconductor substrate. | 2012-04-19 |
20120091544 | COMPONENT HAVING A MICROMECHANICAL MICROPHONE STRUCTURE, AND METHOD FOR ITS PRODUCTION - A component having a robust, but acoustically sensitive microphone structure is provided and a simple and cost-effective method for its production. This microphone structure includes an acoustically active diaphragm, which functions as deflectable electrode of a microphone capacitor, a stationary, acoustically permeable counter element, which functions as counter electrode of the microphone capacitor, and an arrangement for detecting and analyzing the capacitance changes of the microphone capacitor. The diaphragm is realized in a diaphragm layer above the semiconductor substrate of the component and covers a sound opening in the substrate rear. The counter element is developed in a further layer above the diaphragm. This further layer generally extends across the entire component surface and compensates level differences, so that the entire component surface is largely planar according to this additional layer. This allows a foil to be applied on the layer configuration of the microphone structures exposed in the wafer composite, which makes it possible to dice up the components in a standard sawing process. | 2012-04-19 |
20120091545 | SEMICONDUCTOR COMPONENT HAVING A MICROMECHANICAL MICROPHONE STRUCTURE - A simple and cost-effective form of implementing a semiconductor component having a micromechanical microphone structure, including an acoustically active diaphragm as a deflectable electrode of a microphone capacitor, a stationary, acoustically permeable counterelement as a counter electrode of the microphone capacitor, and means for applying a charging voltage between the deflectable electrode and the counter electrode of the microphone capacitor. In order to not impair the functionality of this semiconductor component, even during overload situations in which contact occurs between the diaphragm and the counter electrode, the deflectable electrode and the counter electrode of the microphone capacitor are counter-doped, at least in places, so that they form a diode in the event of contact. In addition, the polarity of the charging voltage between the deflectable electrode and the counter electrode is such that the diode is switched in the blocking direction. | 2012-04-19 |
20120091546 | Microphone - A microphone comprises a substrate ( | 2012-04-19 |
20120091547 | RESONATOR AND PRODUCTION METHOD THEREOF - A resonator using the MEMS technology is provided which improves the accuracy of a shape of electrodes so as avoid a short circuit that would otherwise be caused between input and output electrodes to thereby increase the reliability thereof. A resonator includes a substrate | 2012-04-19 |
20120091548 | FERROMAGNETIC TUNNEL JUNCTION STRUCTURE, AND MAGNETO-RESISTIVE ELEMENT AND SPINTRONICS DEVICE EACH USING SAME - Disclosed is a ferromagnetic tunnel junction structure which is characterized by having a tunnel barrier layer that comprises a non-magnetic material having a spinel structure. The ferromagnetic tunnel junction structure is also characterized in that the non-magnetic material is substantially MgAl | 2012-04-19 |
20120091549 | FORMATION OF EMBEDDED MICRO-LENS - Provided is an image sensor device. The image sensor device includes a pixel formed in a substrate. The image sensor device includes a first micro-lens embedded in a transparent layer over the substrate. The first micro-lens has a first upper surface that has an angular tip. The image sensor device includes a color filter that is located over the transparent layer. The image sensor device includes a second micro-lens that is formed over the color filter. The second micro-lens has a second upper surface that has an approximately rounded profile. The pixel, the first micro-lens, the color filter, and the second micro-lens are all at least partially aligned with one another in a vertical direction. | 2012-04-19 |
20120091550 | SPECTROSCOPY AND SPECTRAL IMAGING METHODS AND APPARATUS - The invention pertains to a new type of standing wave filter in which the detector is located within the cavity, rather than outside the cavity and methods of manufacturing such a filter. | 2012-04-19 |
20120091551 | METHOD OF MANUFACTURING A MULTITUDE OF MICRO-OPTOELECTRONIC DEVICES, AND MICRO-OPTOELECTRONIC DEVICE - A wafer stack that is diced to produce a multitude of micro-optoelectronic devices includes a first wafer including a semiconductor material; a second wafer including an optically transparent material; a multitude of light sensor arrangements in the semiconductor material of the first wafer for each of the micro-optical devices; the second wafer structured to form a multitude of micro-optical elements therein for each of the micro-optoelectronic devices; and a wafer stack produced wafer bonding, the wafer stack including the first wafer and the second wafer arranged above same, each of the micro-optical elements arranged and structured such that different portions of light incident on the micro-optical element are directed onto different light sensor elements of a light sensor arrangement at least partly arranged below the micro-optical element. | 2012-04-19 |
20120091552 | OPTICAL DEVICES BASED ON NON-PERIODIC SUB-WAVELENGTH GRATINGS - Various embodiments of the present invention are directed to optical devices comprising planar lenses. In one aspect, an optical device includes two or more planar lenses ( | 2012-04-19 |
20120091553 | Method for Detecting the Repackaging of an Integrated Circuit after it has been Originally Packaged, and Corresponding Integrated Circuit - An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged. | 2012-04-19 |
20120091554 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a trench that defines an active region of a line type; burying an insulating film in the trench; and removing a portion of the active region of a line type to form a separated active region. The method improves the process for forming an active region using a Spacer patterning Technology (SPT), thereby preventing characteristic defects of the device and improving the operating characteristic. | 2012-04-19 |
20120091555 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate. | 2012-04-19 |
20120091556 | VERTICAL SILICIDE E-FUSE - An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor. | 2012-04-19 |
20120091557 | ANTI-FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An anti-fuse of a semiconductor device and a method for manufacturing the same are disclosed. In order to achieve stable operation of the anti-fuse, a gate rupture prevention film is formed between a gate pattern and a source/drain junction region and a gate oxide film is formed at both ends of a lower edge of the gate pattern. Therefore, when applying a voltage, the overlapped gate oxide film is ruptured so that a current level is stabilized and the anti-fuse is stably operated. | 2012-04-19 |
20120091558 | SHIELD-MODULATED TUNABLE INDUCTOR DEVICE - A semiconductor device is presented here. The semiconductor device includes an integrated inductor formed on a semiconductor substrate, a transistor arrangement formed on the semiconductor substrate to modulate loop current induced by the integrated inductor, dielectric material to insulate the integrated inductor from the transistor arrangement, and a controller coupled to the transistor arrangement. The controller is used to select conductive and nonconductive operating states of the transistor arrangement. A conductive operating state of the transistor arrangement allows formation of induced loop current in the transistor arrangement, and a nonconductive operating state of the transistor arrangement inhibits formation of induced loop current in the transistor arrangement. | 2012-04-19 |
20120091559 | Capacitor and Method for Making Same - A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth. | 2012-04-19 |
20120091560 | MIM Capacitors in Semiconductor Components - Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance. | 2012-04-19 |
20120091561 | MEMS DEVICES - A method of manufacturing a MEMS device comprises forming a MEMS device element ( | 2012-04-19 |
20120091562 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, and possessing a recess which is defined on the upper surface; and a semiconductor chip mounted to the upper surface of the substrate, having one surface which faces the upper surface and the other surface which faces away from the one surface, and warped in a smile shape such that a warped edge portion of the semiconductor chip is inserted into the recess. | 2012-04-19 |
20120091563 | METHOD FOR INSULATING A SEMICONDUCTOR MATERIAL IN A TRENCH FROM A SUBSTRATE - A semiconductor structure is disclosed. In one embodiment, the trench is formed in a substrate, including an upper portion and a lower portion, the upper portion including a lateral dimension larger than a lateral dimension of the lower portion. The lower portion is lined with a first insulating layer and is at least partially filled with a semiconductor material. The first insulating layer extends into the upper portion. A second insulating layer covers, at least partially, the substrate, a portion of the first insulating layer extending into the upper portion and the semiconducting material in the lower portion. | 2012-04-19 |
20120091564 | SEMICONDUCTOR COMPONENT WITH MARGINAL REGION - A semiconductor wafer is disclosed. One embodiment provides at least two semiconductor components each having an active region, and wherein at least one zone composed of porous material is arranged between the active regions of the semiconductor components. | 2012-04-19 |
20120091565 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 2012-04-19 |
20120091566 | SEMICONDUCTOR APPARATUS AND METHOD OF FABRICATION FOR A SEMICONDUCTOR APPARATUS - The invention relates to a semiconductor apparatus and a method of fabrication for a semiconductor apparatus, whereby the semiconductor apparatus includes a semiconductor layer and a passivation layer arranged on a surface of the semiconductor layer and serving for passivating the semiconductor layer surface, whereby the passivation layer comprises a chemically passivating passivation sublayer and a field-effect-passivating passivation sublayer, which are arranged one above the other on the semiconductor layer surface. | 2012-04-19 |
20120091567 | Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVs in Peripheral Region of the Die - A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV. | 2012-04-19 |
20120091568 | MIXED WIRE SEMICONDUCTOR LEAD FRAME PACKAGE - One embodiment includes an encapsulated semiconductor package having a lead frame with die pad surrounded by a plurality of first and second leadfingers. A semiconductor chip including chip contact pads on its upper active surface is attached to the die pad. A plurality of first bond wires, incoluding a first electrically conductive material, extend between the chip contact pads and the plurality of first leadfingers. A plurality of second bond wires, including a second electrically conductive material, extend between a chip contact pad and a second leadfinger. The semiconductor package further includes a plurality of electrically conducting means attached to the second leadfingers. | 2012-04-19 |