16th week of 2013 patent applcation highlights part 38 |
Patent application number | Title | Published |
20130095546 | DIGESTER SYSTEM - A manure mixture within an anaerobic digestion tank stratifies to form a liquid effluent layer and a sludge layer. Liquid effluent from the liquid effluent layer is withdrawn from the tank through a height adjustable valve. The height adjustable valve is adapted to automatically adjust the position of its intake end within the liquid effluent layer in response to the level of the sludge layer detected by a sludge meter located within the tank. Liquid effluent withdrawn from the tank is passed through a heat exchange system including at least one heat exchanger. Heat from the heat exchanger is transferred to the liquid effluent to produce heated liquid effluent. The heated liquid effluent is reintroduced back into the digestion tank such that the temperature of the manure mixture within the tank is maintained within a suitable temperature range for anaerobic digestion of the manure mixture. Additionally, the heated liquid effluent is sprayed in an upwards direction so as to effect mixing of the manure mixture within the tank. | 2013-04-18 |
20130095547 | METHOD FOR SELECTIVE CONJUGATION OF ANALYTES TO ENZYMES WITHOUT UNWANTED ENZYME-ENZYME CROSS-LINKING - A method of preparing an analyte-enzyme conjugate where the enzyme contains free, surface-accessible carboxyl moieties without generating undesired, cross-linked enzymes, while preserving the functionality of the enzyme. The method involves treating an enzyme with a blocking agent such that the free carboxyl moieties become non-reactive prior to the conjugation reaction with the desired analyte. The invention is further directed to analyte-enzyme conjugates prepared by the inventive method and to kits which contain an analyte-enzyme conjugate prepared by the methods herein for the detection and/or quantitation of an analyte in a sample. | 2013-04-18 |
20130095548 | ACTIVATED SIALIC ACID DERIVATIVES FOR PROTEIN DERIVATISATION AND CONJUGATION - Derivatives of PSAs are synthesised, in which a reducing and/or non-reducing end terminal sialic acid unit is transformed into a N-hydroxysuccinimide (NHS) group. The derivatives may be reacted with substrates, for instance substrates containing amine or hydrazine groups, to form non-cross-linked/crosslinked polysialylated compounds. The substrates may, for instance, be therapeutically useful drugs, peptides or proteins or drug delivery systems. | 2013-04-18 |
20130095549 | TWEAK RECEPTOR - The present invention provides the TWEAK receptor and methods for identifying and using agonists and antagonists of the TWEAK receptor. In particular, the invention provides methods of screening for agonists and antagonists and for treating diseases or conditions mediated by angiogenesis, such as solid tumors and vascular deficiencies of cardiac or peripheral tissue. | 2013-04-18 |
20130095550 | POLYNUCLEOTIDES HAVING PROMOTER ACTIVITY - The present invention relates to isolated polynucleotides having promoter activity the use of the isolated polynucleotides for the production of a polypeptide. The invention also relates to nucleic acid constructs, vectors, and host cells comprising the polynucleotides as well as methods of producing a desired polypeptide using the polypeptide having promoter activity. | 2013-04-18 |
20130095551 | METHOD FOR CHANGING CONFORMATION OF GLOBULAR PROTEINS - A method for changing conformation of globular proteins is provided. The method controls the concentration of the globular proteins and the adsorption time of the globular proteins from the aqueous solution to the air/liquid interface, so that the main conformation of the globular proteins in a protein monolayer can be changed into β-sheet or α-helix. Meanwhile, the protein monolayer having the conformation of β-sheet or α-helix can be vertically deposited and transferred onto a substrate for various applications according to needs. The present invention can change three-dimensional structures of biological molecules and remain original functions thereof without additionally using any physical/chemical treatment to change the conformation of the globular proteins. | 2013-04-18 |
20130095552 | NOROVIRUS AND SAPOVIRUS ANTIGENS - Immunogenic compositions that elicit immune responses against Norovirus and Sapovirus antigens are described. In particular, the invention relates to polynucleotides encoding one or more capsid proteins or other immunogenic viral polypeptides from one or more strains of Norovirus and/or Sapovirus, coexpression of such immunogenic viral polypeptides with adjuvants, and methods of using the polynucleotides in applications including immunization and production of immunogenic viral polypeptides and viral-like particles (VLPs). Methods for producing Norovirus- or Sapovirus-derived multiple epitope fusion antigens or polyproteins and immunogenic compositions comprising one or more immunogenic polypeptides, polynucleotides, VLPs, and/or adjuvants are also described. The immunogenic compositions of the invention may also contain antigens other than Norovirus or Sapovirus antigens, including antigens that can be used in immunization against pathogens that cause diarrheal diseases, such as antigens derived from rotavirus. | 2013-04-18 |
20130095553 | POLYPEPTIDE HAVING OR ASSISTING IN CARBOHYDRATE MATERIAL DEGRADING ACTIVITY AND USES THEREOF - The invention relates to a polypeptide which comprises the amino acid sequence set out in SEQ ID NO: 2 or an amino acid sequence encoded by the nucleotide sequence of SEQ ID NO: 1, or a variant polypeptide or variant polynucleotide thereof, wherein the variant polypeptide has at least 76% sequence identity with the sequence set out in SEQ ID NO: 2 or the variant polynucleotide encodes a polypeptide that has at least 76% sequence identity with the sequence set out in SEQ ID NO: 2. The invention features the full length coding sequence of the novel gene as well as the amino acid sequence of the full-length functional polypeptide and functional equivalents of the gene or the amino acid sequence. The invention also relates to methods for using the polypeptide in industrial processes. Also included in the invention are cells transformed with a polynucleotide according to the invention suitable for producing these proteins. | 2013-04-18 |
20130095554 | MODIFIED FAMILY 5 CELLULASES AND USES THEREOF - The present invention relates to a modified Family 5 cellulase comprising a substitution of an amino acid at position 363 with a non-native alanine, serine or threonine, said position determined from alignment of the modified Family 5 cellulase with amino acids 71-397 of a | 2013-04-18 |
20130095555 | Hyperglycosylated Human Coagulation Factor IX - The invention relates to hyperglycosylated human coagulation factor IX polypeptides, to processes for preparing said polypeptides, to pharmaceutical compositions comprising said polypeptides and to the use of the compounds for the treatment of diseases alleviated by human coagulation factor IX, in particular, but not exclusively hemophilia. | 2013-04-18 |
20130095556 | NOVEL VESICULAR STOMATITIS VIRUS AND VIRUS RESCUE SYSTEM - The present relation relates to recombinant vesicular stomatitis virus for use as prophylactic and therapeutic vaccines as well as the preparation and purification of immunogenic compositions which are formulated into the vaccines of the present invention. | 2013-04-18 |
20130095557 | IMMORTALIZED AVIAN CELL LINES - This invention relates to immortalized avian cells, including those deposited under accession numbers 09070701, 09070702, and 09070703 at the ECACC, and to the use of these cells for the production of viruses. The cells according to the invention are particularly useful for the production of recombinant viral vectors which can be used for the preparation of therapeutic and/or prophylactic compositions for the treatment of animals and more particularly humans. | 2013-04-18 |
20130095558 | PROCESS FOR PRODUCING RECOMBINANT HUMAN ENDOSTATIN ADENOVIRUS - This invention discloses a production process for recombinant human endostatin adenovirus in order to optimize the procedure for small batch and mass industrialization. Exemplary process include steps of: (1) fermentation of eukaryotic cells (HEK293 cells) in the condition of 37° C. and 5% CO | 2013-04-18 |
20130095559 | Composite Material for Absorbing and Remediating Contaminants and Method of Making Same - The mat is formed of a saprophytic fungal strain and/or budding yeast, and a mass of particles wherein the fungus is characterized in producing an enzyme capable of breaking down polycyclic aromatic hydrocarbons. In a second embodiment, a mass of pellets is made from the mat for use in absorbing liquid animal waste. | 2013-04-18 |
20130095560 | Method of Producing Tissue Culture Media Derived from Plant Seed Material and Casting of Mycological Biomaterials - A culture/gelling liquid is formed of a mixture of seed matter and water that is inoculated with a desired cell or tissue strain. The culture/gelling liquid is combined with a substrate in order to be formed into molds, and incubated until a member is formed. The substrate may also be pre-colonized. | 2013-04-18 |
20130095561 | BIOLOGICAL H2S REMOVAL SYSTEM AND METHOD - The present invention provides a biological H | 2013-04-18 |
20130095562 | OIL RELEASE WITH AMINO ACID-BASED COMPOUNDS HAVING A LONG CHAIN N-ACYL GROUP - Chemical compounds that are N-acyl amino acids or derivatives thereof having long chain N-acyl groups were found to have oil-releasing activity. Solutions containing these compounds may be introduced into oil reservoirs or onto oil-contaminated surface sites to release oil from oil-coated surfaces. The released oil may be recovered for further processing or waste disposal. | 2013-04-18 |
20130095563 | METHOD AND SYSTEM FOR DETECTING AN ANALYTE - Aspects and embodiments are directed to methods and systems of detecting an analyte present in the environment. More particularly, this disclosure relates to methods and systems of detecting a threatening or dangerous analyte that may increase survivability of an individual or group of individuals. | 2013-04-18 |
20130095564 | CELL SEPARATING APPARATUS AND CELL SEPARATING METHOD - A cancer cell separating apparatus includes: a flow channel including an antibody fixation area having antibodies which bind specifically to cancer cells fixed thereon, wherein the cancer cells and non-cancer cells are separated using a difference in velocity of movement between the cancer cells and the non-cancer cells in cell slurry introduced into the flow channel. | 2013-04-18 |
20130095565 | miRNA-Regulated Differentiation-Dependent Self-Deleting Cassette - Targeting constructs and methods of using them are provided for differentiation-dependent modification of nucleic acid sequences in cells and in non-human animals. Targeting constructs comprising a promoter operably linked to a recombinase are provided, wherein the promoter drives transcription of the recombinase in an differentiated cell but not an undifferentiated cell. Promoters include Blimp1, Prm1, Gata6, Gata4, Igf2, Lhx2, Lhx5, and Pax3. Targeting constructs with a cassette flanked on both sides by recombinase sites can be removed using a recombinase gene operably linked to a 3′-UTR that comprises a recognition site for an miRNA that is transcribed in undifferentiated cells but not in differentiated cells. The constructs may be included in targeting vectors, and can be used to automatically modify or excise a selection cassette from an ES cell, a non-human embryo, or a non-human animal. | 2013-04-18 |
20130095566 | Flux Balance Analysis With Molecular Crowding - Methods are provided herein for: calculating cell growth rates in various environments and genetic backgrounds; calculating the order of substrate utilization from a defined growth medium; calculating metabolic flux reorganization in various environments and at various growth rates; and calculating the maximum metabolic rate and optimal metabolite concentrations and enzyme activities by applying a computational optimization method to a kinetic model of a metabolic pathway. The optimization methods use intracellular molecular crowding parameters and/or well as kinetic rates to assist in modeling metabolic activity. | 2013-04-18 |
20130095567 | DIRECTED DIFFERENTIATION AND MATURATION OF PLURIPOTENT CELLS INTO HEPATOCYTE LIKE CELLS BY MODULATION OF WNT-SIGNALLING PATHWAY - Provided are improved methods using Glycogen synthase kinase 3 (GSK3) inhibitors by which endodermal cells, notably endodermal cells derived from human pluripotent stem cells (hPS), such as but not limited to hiPS-cells and hES-cells may be differentiated into hepatocyte like cells. The specific modulation of wingless integration gene (WNT)-signalling pathway and use of GSK3 inhibitors achieve direct differentiation and maturation of hepatocytes derived from human pluripotent stem (hPS) cells. GSK-3 inhibitors, when added to the growth medium at certain developmental stages, leads to more mature and functional features for the hepatocyte like cells as well as more pure and homogenous populations of hepatocyte like cells. Provided are also hepatocyte like cells obtained by these methods as well as compositions comprising them. | 2013-04-18 |
20130095568 | MESODERM AND DEFINITIVE ENDODERM CELL POPULATIONS - The present invention provides cell populations that are enriched for mesendoderm and mesoderm, and cell populations that are enriched for endoderm. The cell populations of the invention are useful for generating cells for cell replacement therapy. The present invention further provides a method of generating hepatocytes, cell populations enriched for hepatocytes, and a method of hepatocyte replacement therapy. | 2013-04-18 |
20130095569 | PREGNANCY-ASSOCIATED PLASMA PROTEIN-A2 (PAPP-A2) POLYNUCLEOTIDES - The present invention provides pregnancy associated plasma protein A2 (PAPP-A2), its nucleotide and amino acid sequences antisense molecules to the nucleotide sequences which encode PAPP-A2, expression vectors for the production of purified PAPP-A2, antibodies capable of binding specifically to PAPP-A2, hybridization probes or oligonucleotides for the detection of PAPP-A2-encoding nucleotide sequences, genetically engineered host cells for the expression of PAPP-A2, and methods for screening for pathologies in pregnant and non-pregnant patients. Methods for screening for altered focal proliferation states in pregnant and/or non-pregnant patients, which include detecting levels of PAPP-A2, are also described. | 2013-04-18 |
20130095570 | SUGAR ANALYSIS DEVICE AND ANALYSIS METHOD - Disclosed is a method separation analysis of reducing sugars with enhanced sensitivity and an analytical apparatus therefore employing the post-column fluorescence detection/boric acid complex anion exchange method. The method disclosed is a method for analysis of reducing sugars using the post-column fluorescence detection/boric acid complex anion exchange method, and characterized in that a back-pressure generator is installed in the flow path between the heater, which is for causing a reaction by heating a sample separated by column chromatography with a basic amino acid, and a fluorometric detector. | 2013-04-18 |
20130095571 | THE METHOD FOR QUICK AND SIMULTANEOUS DETERMINATION OF 16 INORGANIC ANIONS AND ORGANIC ACIDS IN TOBACCO - The present invention discloses a method for quick and simultaneous determination of 16 inorganic anions and organic acids in tobacco by ion chromatography The retention behavior of inorganic anions and organic acids on the anion exchange column was investigated using potassium hydroxide produced by EGC-II KOH eluent autogenerator as eluent. The optimized gradient elution condition was obtained. The samples were prepared through extraction, filtration and dilution before analysis. The separation was performed on an anion exchange column. The time of the gradient elution program was 50 mins. Under the optimized conditions, the calibration of peak area for all the analytes were linear in the ranges of 10 | 2013-04-18 |
20130095572 | ANALYSIS DEVICE, ANALYSIS SYSTEM AND ANALYSIS METHOD - An analysis device of performing predetermined analysis processing to a sample. The analysis device includes: a first analysis unit, a second analysis unit and a simple analysis unit to perform at first analysis process to the sample, a second analysis process to the sample and a short-time analysis process to the sample, by which an analysis result is given in a shorter time than by the first analysis process, respectively; and a judging unit to judge, before a result of the first analysis process is given, whether or not to perform the second analysis process on a basis of a result of the first analysis process. | 2013-04-18 |
20130095573 | Magnetic Microspheres For Use In Fluorescence-Based Applications - Microspheres, populations of microspheres, and methods for forming microspheres are provided. One microsphere configured to exhibit fluorescent and magnetic properties includes a core microsphere and a magnetic material coupled to a surface of the core microsphere. About 50% or less of the surface of the core microsphere is covered by the magnetic material. The microsphere also includes a polymer layer surrounding the magnetic material and the core microsphere. One population of microspheres configured to exhibit fluorescent and magnetic properties includes two or more subsets of microspheres. The two or more subsets of microspheres are configured to exhibit different fluorescent and/or magnetic properties. Individual microspheres in the two or more subsets are configured as described above. | 2013-04-18 |
20130095574 | METHOD FOR PRODUCING MICROPARTICLES - Silicon microcarriers suitable for fluorescent assays as a well as a method of producing such microcarriers are provided. The method includes the steps of providing a SOI wafer having a bottom layer of monocristalline silicone, an insulator layer and a bottom layer of monocristalline silicon, delineating microparticles, etching away the insulator layer and then depositing an oxide layer on the wafer still holding the microparticles before finally lifting-off the microparticles. | 2013-04-18 |
20130095575 | Methods for Fractionation, Analysis and Collection of Microvesicles From Patient Samples - A methods are provided for the flow cytometry profiling of microvesicles, including exosomes. | 2013-04-18 |
20130095576 | TRANSFORMER SIGNAL COUPLING FOR FLIP-CHIP INTEGRATION - Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor. | 2013-04-18 |
20130095577 | SYSTEM AND METHOD FOR MEASURING LAYER THICKNESS AND DEPOSITING SEMICONDUCTOR LAYERS - Described herein is a method and apparatus for measuring the thickness of a deposited semiconductor material. A colorimeter has an optical source that illuminates a portion of a deposited semiconductor material with optical radiation, a sensor that collects and measures color information related to reflected radiation from the deposited semiconductor material, and a processor that receives the color information related to the reflected radiation from the sensor and calculates a thickness of the semiconductor material. The processor may control a semiconductor material deposition apparatus. | 2013-04-18 |
20130095578 | APPARATUS AND METHOD FOR THE PRODUCTION OF PHOTOVOLTAIC MODULES - Embodiments of the invention may provide a system for the production of photovoltaic modules that comprises at least a first work line having a plurality of positioning stations in which a series of first processing operations are performed and a second work line consisting of at least a positioning station in which at least a second processing operation is performed. The process sequence may include, for example, printing a layer material used to form one or more electric contacts on a base layer, and then positioning photovoltaic cells and various layers of insulating material in a desired orientation over the base layer to form a photovoltaic module. | 2013-04-18 |
20130095579 | METHOD AND APPARATUS FOR THE FORMATION OF SOLAR CELLS WITH SELECTIVE EMITTERS - Methods and apparatus for forming solar cells with selective emitters are provided. A method includes positioning a substrate on a substrate receiving surface. The substrate has a surface comprising a first patterned heavily doped region having a first dopant concentration that defines the selective emitters, and a second doped emitter region having a second dopant concentration that is less than the first dopant concentration, wherein the second doped emitter region surrounds the first patterned heavily doped region. The method further comprises determining a position of the first patterned heavily doped region by using a Fourier transform to process a filtered optical image, aligning one or more distinctive elements in a screen printing mask with the first patterned heavily doped region by using information received from the determined position of the first patterned heavily doped region, and depositing a layer of material on a portion of the first patterned heavily doped region. | 2013-04-18 |
20130095580 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method for formation of a semiconductor device including a first mono-crystalline layer comprising first transistors and first alignment marks, the method comprising forming a doped layer within a wafer, forming a second mono-crystalline layer on top of the first mono-crystalline layer by transferring at least a portion of the doped layer using layer transfer step, and processing second transistors on the second mono-crystalline layer comprising a step of forming a gate dielectric, wherein the second transistors are horizontally oriented. | 2013-04-18 |
20130095581 | THICK WINDOW LAYER LED MANUFACTURE - A LED die and method for bonding, dicing, and forming the LED die are disclosed. In an example, the method includes forming a LED wafer, wherein the LED wafer includes a substrate and a plurality of epitaxial layers disposed over the substrate, wherein the plurality of epitaxial layers are configured to form a LED; bonding the LED wafer to a base-board to form a LED pair; and after bonding, dicing the LED pair, wherein the dicing includes simultaneously dicing the LED wafer and the base-board, thereby forming LED dies. | 2013-04-18 |
20130095582 | Method for Manufacturing Sealed Structure - A method for manufacturing a sealed structure in which few cracks are generated is provided. Scan with the laser beam is performed so that there is no difference in an irradiation period between the middle portion and the perimeter portion of the glass layer and so that the scanning direction is substantially parallel to the direction in which solidification of the glass layer after melting proceeds. More specifically, in a region where the beam spot is overlapped with the glass layer, scan is performed with a laser beam having a beam spot shape whose width in a scanning direction is substantially uniform. Further, as a laser beam with which the glass layer is irradiated, a laser beam (a linear laser beam) having a linear beam spot shape with a major axis and a minor axis which is orthogonal to the major axis. | 2013-04-18 |
20130095583 | METHOD FOR MANUFACTURING LED - A method for manufacturing an LED is disclosed. Firstly, a base with two leads is provided. The base has a cavity defined in a top face thereof and two holes defined in two lateral faces thereof. The two holes communicate the cavity with an outside environment. A chip is fixed in the cavity and electrically connected to the two leads. A cover is placed on the top face of the base to cover the cavity. An encapsulation liquid is filled into the cavity through one hole until the encapsulation liquid joins a bottom face of the cover. Finally, the encapsulation liquid is cured to form an encapsulant. A top face of the cover functions as a light emergent face of the LED. | 2013-04-18 |
20130095584 | LIGHT EMITTING DISPLAY AND METHOD OF MANUFACTURING THE SAME - The present invention is to provide an organic light emitting display and a method of manufacturing the same, the light emitting display including: a first substrate on which a plurality of light emitting devices are formed; a second substrate disposed to face the first substrate; a dam member disposed between the first substrate and the second substrate to surround the plurality of light emitting devices; an inorganic sealing material disposed between the first substrate and the second substrate on an outward side of the dam member and attaching the first substrate and the second substrate; and a filling material provided between the first substrate and the second substrate on an inward side of the dam member and formed of at least one inert liquid selected from the group consisting of perfluorocarbon and fluorinert. | 2013-04-18 |
20130095585 | MULTI-FIELD ARRANGING METHOD OF LED CHIPS UNDER SINGLE LENS - A multi-field arranging method of LED chips under a single lens includes the steps of: setting a first concentric circle on a bottom of a hemispherical lens, wherein the first concentric circle is centered at an axis of the hemispherical lens; equidistantly arranging plural first LED chips on the first concentric circle; setting a second concentric circle, which is also centered at the same axis as the first concentric circle, and the second concentric circle is larger than the first concentric circle in radius; and equidistantly arranging plural second LED chips and plural third LED chips on the second concentric circle. The present invention allows the LED chips to present symmetrical light patterns through the hemispherical lens, thereby obtaining a light field with evener color mixture and evener color temperature distribution in every illuminating direction. | 2013-04-18 |
20130095586 | METHOD OF CUTTING LIGHT EMITTING ELEMENT PACKAGES EMPLOYING CERAMIC SUBSTRATE, AND METHOD OF CUTTING MULTILAYERED OBJECT - A method of cutting light emitting element packages includes preparing a ceramic substrate having a surface on which a plurality of light emitting element chips are mounted and a light-transmitting material layer is formed to cover the plurality of light emitting element chips; partially removing the light-transmitting material layer between the plurality of light emitting element chips along a cutting line by using a mechanical cutting method; and separating individual light emitting element packages by cutting the ceramic substrate along the cutting line by using a laser cutting method. | 2013-04-18 |
20130095587 | METHODS FOR MANUFACTURING THIN FILM TRANSISTOR AND DISPLAY DEVICE - The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias. | 2013-04-18 |
20130095588 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor. Each of the first thin film transistor and the second thin film transistor includes a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer. Each of the layers of the first thin film transistor has a light-transmitting property. Materials of the gate electrode layer, the source electrode layer and the drain electrode layer of the first thin film transistor are different from those of the second transistor, and each of the resistances of the second thin film transistor is lower than that of the first thin film transistor. | 2013-04-18 |
20130095589 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - In an array substrate capable of improving the quality of displayed images and a method for manufacturing the array substrate, the array substrate includes a base substrate, a first conductive pattern including a gate line and a first light-blocking pattern, a semiconductor layer overlapping the light-blocking pattern, a second conductive pattern including a data line and a storage line overlapping the first light-blocking pattern, and a pixel electrode overlapping the storage line to form a storage capacitor. The first conductive pattern may further include a second light-blocking pattern overlapping the semiconductor layer which is formed under the data line. The first and second light-blocking patterns block light proceeding toward the semiconductor layer formed under the storage line and under the data line, respectively, so that the semiconductor layer may be prevented from being excited by light energy. | 2013-04-18 |
20130095590 | LIQUID CRYSTAL DISPLAY AND METHOD OF FABRICATING THE SAME TO HAVE TFT'S WITH PIXEL ELECTRODES INTEGRALLY EXTENDING FROM ONE OF THE SOURCE/DRAIN ELECTRODES - A liquid crystal display (LCD) includes thin film transistors (TFTs) each having spaced apart source/drain electrodes and an oxide-type semiconductive film disposed over and between the source/drain electrodes to define an active layer. Each of the source/drain electrodes includes a portion of a subdivided transparent conductive layer where one subdivision of the transparent conductive layer continues from within its one of the source/drain electrodes to define an optically exposed pixel-electrode that is reliably connected integrally to the one source/drain electrode. Mass production costs can be reduced and production reliability increased because a fewer number of photolithographic masks can be used to form the TFTs. | 2013-04-18 |
20130095591 | MANUFACTURING METHOD OF SOLID STATE LIGHT EMITTING ELEMENT - A manufacturing method of a solid state light emitting element is provided. A plurality of protrusion structures separated to each other are formed on a first substrate. A buffer layer is formed on the protrusion structures and fills the gaps between protrusion structures. An epitaxial growth layer is formed on the buffer layer to form a first semiconductor stacking structure. The first semiconductor stacking structure is inverted to a second substrate, so that the first semiconductor epitaxial layer and the second substrate are connected to form a second semiconductor stacking structure. The buffer layer is etched by a first etchant solution to form a third semiconductor stacking structure. A second etchant solution is used to permeate through the gaps between the protrusion structures, so that the protrusion structures are etched completely. The first substrate is removed from the third semiconductor stacking structure to form a fourth semiconductor stacking structure. | 2013-04-18 |
20130095592 | METHOD FOR FABRICATING ORGANIC EL DEVICE - Forming an adhesive layer on a part of a surface of the flexible substrate; forming a magnetic material layer on the surface of the flexible substrate in a part other than the part on which the adhesive layer is formed; temporarily holding, using magnetic force, the flexible substrate on which the adhesive layer and the magnetic material layer are formed, above an inflexible substrate having magnetic property; fixing the flexible substrate with the inflexible substrate via the adhesive layer; forming a layer composing an organic EL unit on the flexible substrate temporarily held using the magnetic force and fixed via the adhesive layer; removing the part in which the flexible substrate and the inflexible substrate are fixed via the adhesive layer; separating the flexible substrate from the inflexible substrate; and separating the magnetic material layer from the flexible substrate separated from the inflexible substrate are included. | 2013-04-18 |
20130095593 | GAS SENSOR AND MANUFACTURING METHOD THEREOF - A gas sensor manufacturing method comprises the following steps: providing a SOI substrate, including an oxide layer, a device layer, and a carrier, wherein the oxide layer is disposed between the device layer and the carrier; etching the device layer to form an integrated circuit region, an outer region, a trench and at least one conducting line; coating or imprinted a sensing material on the integrated circuit region; and etching the carrier and the oxide layer to form a cavity up to the gap so as to form a film structure which is suspended in the cavity by the cantilevered connecting arm. | 2013-04-18 |
20130095594 | SOLID STATE IMAGING DEVICE AND FABRICATION METHOD FOR THE SAME - A solid state imaging device includes a circuit unit formed on a substrate and a photoelectric conversion unit. The photoelectric conversion circuit includes a lower electrode layer placed on the circuit unit, a compound semiconductor thin film of chalcopyrite structure which is placed on the lower electrode layer and functions as an optical absorption layer, and an optical transparent electrode layer placed on the compound semiconductor thin film. The lower electrode layer, the compound semiconductor thin film, and the optical transparent electrode layer are laminated one after another on the circuit unit. | 2013-04-18 |
20130095595 | METHOD FOR PRODUCING A PHOTOVOLTAIC SOLAR CELL - A method for producing a photovoltaic solar cell, including the following steps: A. texturizing a front ( | 2013-04-18 |
20130095596 | METHOD FOR TEXTURING SILICON SURFACE TO CREATE BLACK SILICON FOR PHOTOVOLTAIC APPLICATIONS - The surface of silicon is textured to create black silicon on a nano-micro scale by electrochemical reduction of a silica layer on silicon in molten salts. The silica layer can be a coating, or a layer caused by the oxidation of the silicon. | 2013-04-18 |
20130095597 | METHOD OF MANUFACTURING PHOTOELECTRIC DEVICE - A method of manufacturing a solar cell including providing a semiconductor substrate having a first conductivity type; performing a first deposition process that includes forming a first doping material layer having a second conductivity type different from the first conductivity type; performing a drive-in process that includes heating the substrate having the first doping material layer thereon; performing a second deposition process after performing the drive-in process and including forming a second doping material layer on the first doping material layer, wherein the second doping material layer has the second conductivity type; locally heating portions of the substrate, the first doping material layer, and the second doping material layer with a laser to form a contact layer at a first surface of the substrate; and forming a first electrode on the contact layer and a second electrode on a second surface of the substrate opposite to the first surface. | 2013-04-18 |
20130095598 | BACK-SURFACE FIELD STRUCTURES FOR MULTI-JUNCTION III-V PHOTOVOLTAIC DEVICES - A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. | 2013-04-18 |
20130095599 | PHOTOVOLTAIC DEVICE USING NANO-SPHERES FOR TEXTURED ELECTRODES - An electronic device includes a substrate and a plurality of particles anchored to the substrate. An electrode material is formed over the particles and configured to form peaks over the particles. One or more operational layers are fog led over the electrode material for performing a device function. | 2013-04-18 |
20130095600 | METHOD FOR MANUFACTURING SOLAR CELL - Methods for manufacturing a solar cell are provided. The method may include forming a lower electrode on a substrate, forming a light absorption layer on the lower electrode, forming a buffer layer on the light absorption layer, and forming a window layer on the buffer layer. The window layer may include an intrinsic layer and the transparent electrode which have electric characteristics different from each other, respectively. The intrinsic layer and the transparent electrode may be formed by a sputtering process using a single target formed of metal oxide doped with impurities. | 2013-04-18 |
20130095601 | DEPOSITION CHAMBER CLEANING SYSTEM AND METHOD - An in-situ method of cleaning a vacuum deposition chamber can include flowing at least one reactive gas into the chamber. | 2013-04-18 |
20130095602 | ATYPICAL KESTERITE COMPOSITIONS - This invention relates to processes for making kesterite compositions with atypical Cu:Zn:Sn:S ratios and/or kesterite compositions with unusually small coherent domain sizes. This invention also relates to these kesterite compositions and their use in preparing CZTS films. | 2013-04-18 |
20130095603 | METHOD FOR THE TREATMENT OF A METAL CONTACT FORMED ON A SUBSTRATE - The invention relates to a method for obtaining a metal contact on a substrate, comprising the following steps: (a) depositing a metal pattern in the form of a paste formed from a mixture of a metal power and a solvent, (b) heating the assembly formed in step (a) in order to evaporate the solvent, and (c) annealing same in order to form a metal contact between the metal pattern and the substrate. The invention is characterised in that it also includes a step (d) in which the metal contact is heated by laser at an energy density of between 0.5 J/cm | 2013-04-18 |
20130095604 | METHOD FOR PRODUCING A METAL CONTACT STRUCTURE OF A PHOTOVOLTAIC SOLAR CELL - A method for producing a metal contact structure of a photovoltaic solar cell, including: applying an electrically non-conductive insulating layer to a semiconductor substrate, applying a metal contact layer to the insulating layer, and generating a plurality of local electrically conductive connections between the semiconductor substrate and the contact layer right through the insulating layer. The metal contact layer is formed using two pastes containing metal particles: the first paste containing metal particles is applied to local regions, and the second paste containing metal particles is applied covering at least the regions covered with the first paste and partial regions located therebetween. By global heating the semiconductor substrate the first paste penetrates the insulating layer and forms an electrically conductive contact directly with the semiconductor substrate, whereas the second paste does not penetrate the insulating layer and is electrically conductively connected to the semiconductor substrate via the first paste. | 2013-04-18 |
20130095605 | LEAVING SUBSTITUENT-CONTAINING COMPOUND, ORGANIC SEMICONDUCTOR MATERIAL FORMED THEREFROM, ORGANIC ELECTRONIC DEVICE, ORGANIC THIN-FILM TRANSISTOR AND DISPLAY DEVICE USING THE ORGANIC SEMICONDUCTOR MATERIAL, METHOD FOR PRODUCING FILM-LIKE PRODUCT, PI-ELECTRON CONJUGATED COMPOUND AND METHOD FOR PRODUCING THE PI ELECTRON CONJUGATED COMPOUND - A leaving substituent-containing compound represented by General Formula (I), wherein the leaving substituent-containing compound can be converted to a compound represented by General Formula (Ia) and a compound represented by General Formula (II), by applying energy to the leaving substituent-containing compound, in General Formulas (I), (Ia) and (II), X and Y each represent a hydrogen atom or a leaving substituent, where one of X and Y is the leaving substituent and the other is the hydrogen atom; Q | 2013-04-18 |
20130095606 | Fabrication Method for ZnO Thin Film Transistors Using Etch-stop Layer - A method is provided for fabricating a thin film transistor. A plurality of layers is deposited on a substrate. The plurality of layers includes a conductive gate contact layer, a gate insulator layer, an undoped channel layer, an etch-stop layer, and a conductive contact layer. The etch-stop layer is positioned between the conductive contact layer and the undoped channel layer. A portion of the conductive contact layer is selectively removed while removal of a portion of the undoped channel layer is prevented by the etch-stop layer during the selective removal. A portion of the etch-stop layer is selectively removed and an exposed portion of the etch-stop layer is converted from a conductor to an insulator by oxidizing the exposed portion of the etch-stop layer in air. A portion of remaining layers of the plurality of layers is selectively removed to form the thin film transistor. | 2013-04-18 |
20130095607 | Methods and Apparatus For Alignment In Flip Chip Bonding - Methods and apparatus for alignment in a flip chip bonding. A method includes attaching an integrated circuit having connector terminals to a bonding arm, the bonding arm having a chuck for attaching the integrated circuit at the backside surface, the bonding arm having a plurality of CCD imagers mounted thereon; receiving a substrate having pads corresponding to the connector terminals; using the bonding arm, positioning the integrated circuit proximal to the substrate; aligning the integrated circuit connector terminals with the pads on the substrate using the CCD imagers on the bonding arm; positioning the connector terminals in contact with the pads on the substrate; and performing a solder reflow to attach the integrated circuit to the substrate. An apparatus includes a bonding arm with a chuck for carrying a component and CCD imagers mounted on the arm for alignment. | 2013-04-18 |
20130095608 | Methods for Forming 3DIC Package - A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening. | 2013-04-18 |
20130095609 | Device and Method for Manufacturing a Device - A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity. | 2013-04-18 |
20130095610 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds. | 2013-04-18 |
20130095611 | Packaging Methods for Semiconductor Devices - Packaging methods for semiconductor devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates. | 2013-04-18 |
20130095612 | WAFER LEVEL PACKAGING METHOD OF ENCAPSULATING THE BOTTOM AND SIDE OF A SEMICONDUCTOR CHIP - A chip-scale packaging method, with bottom and side of a semiconductor chip encapsulated, includes the following steps: attaching backside of a thinned semiconductor wafer to a dicing tape; separating individual chips by cutting from front side of the wafer at scribe line but not cut through the dicing tape; flipping and attaching the wafer onto a top surface of a double-sided tape, then removing the dicing tape; attaching bottom surface of the double-sided tape on a supporting plate; filling the space between adjacent chips and covering the whole wafer backside with a molding material; flipping the whole structure and remove the supporting plate; placing solder balls at corresponding positions on electrodes of each chip and performing backflow treatment; finally separating individual chip packages by cutting through molding material at the space between adjacent chip packages with molding material encapsulating the bottom and side of each individual semiconductor chip. | 2013-04-18 |
20130095613 | FABRICATION METHOD OF SEMICONDUCTOR DEVICES AND FABRICATION SYSTEM OF SEMICONDUCTOR DEVICES - In aspects of the invention, a holding stage of a pick up system can include a first stage on which a semiconductor chip is mounted with an adhesive sheet put in between, a second stage supporting the first stage, and an evacuation pipe. The first stage can be provided with a plurality of grooves, projections each being formed with side walls of adjacent grooves, and air holes connected to the grooves. The semiconductor chip can be mounted on the first stage so that the whole end portion of the semiconductor chip does not position on one groove. Then, a closed space surrounded by the adhesive sheet and the first and second stages and can be evacuated to make the semiconductor chip held on the projections. Thereafter, the semiconductor chip can be picked up by a collet. | 2013-04-18 |
20130095614 | WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS - A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads. | 2013-04-18 |
20130095615 | MANUFACTURING METHOD OF PACKAGE STRUCTURE - A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer. | 2013-04-18 |
20130095616 | METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE - A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer. | 2013-04-18 |
20130095617 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility, A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current. | 2013-04-18 |
20130095618 | THIN FILM TRANSISTOR SUBSTRATE, LIQUID CRYSTAL DISPLAY HAVING THE SAME, AND METHOD OF MANUFACTURING THE SAME - In a thin film transistor, first and second thin film transistors are connected to an N | 2013-04-18 |
20130095619 | PERFORMANCE AND REDUCING VARIATION OF NARROW CHANNEL DEVICES - Embodiment of the present invention provides a method of forming transistors such as narrow channel transistors. The method includes creating a transistor region in a substrate; the transistor region being separated from rest of the substrate, by one or more shallow trench isolation (STI) regions formed in the substrate, to include a channel region, a source region, and a drain region; the STI regions having a height higher than the transistor region of the substrate; and the channel region having a gate stack on top thereof; forming spacers at sidewalls of the STI regions above the transistor region; creating recesses in the source region and the drain region with the spacers preserving at least a portion of material of the substrate underneath the spacers along sidewalls of the STI regions; and epitaxially growing source and drain of the transistor in the recesses. | 2013-04-18 |
20130095620 | METHODS OF FORMING HIGHLY SCALED SEMICONDUCTOR DEVICES USING A DISPOSABLE SPACER TECHNIQUE - In one example, a method disclosed herein includes the steps of forming a first liner layer above a substrate and above gate structures for both a PMOS transistor and an NMOS transistor, and, after forming extension implant regions and halo implant regions, forming a first spacer proximate the gate structures of both the PMOS and NMOS transistors, forming deep source/drain implant regions in the substrate for the PMOS and NMOS transistors, removing the first spacer and, after removing the first spacer, forming a layer of material between the adjacent gate structures, wherein the layer of material occupies at least the space formerly occupied by the first spacer. | 2013-04-18 |
20130095621 | Method of Manufacture of a Passive High-Frequency Image Reject Mixer - A passive implementation of an image reject mixer (IRM), capable of operating at very high frequency, is manufactured in a variety of silicon processes. The IRM comprises a quad MOS multiplier and a lumped-element hybrid, resulting in a passive IRM, operative at radio frequencies (RF) of tens of GHz with an intermediate frequency (IF) of several GHz. The RF+ and RF− signals are provided to two quad MOS multipliers. A local oscillator signal (LO) is used to provide LO+ and LO− signals to one of the multipliers and by providing the LO to a phase shifter, generated are a ninety degree shifted LO+ and LO− signals provided to the other multiplier. Providing the hybrids with the outputs of both multipliers and selecting an appropriate IF signal from each of the hybrids ensures the proper operation of the passive IRM. | 2013-04-18 |
20130095622 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Methods of manufacturing a semiconductor device are provided. Patterns having a recess region defined therebetween are formed on a substrate, and then a silicon precursor having an organic ligand is provided on the substrate to absorb silicon on sidewalls and a bottom surface of the recess region to form a silicon monolayer on the patterns having the recess region defined therebetween. A silicon layer without void and cutting is formed on the silicon monolayer. | 2013-04-18 |
20130095623 | VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE - A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate. | 2013-04-18 |
20130095624 | MANUFACTURING PROCESS OF A POWER ELECTRONIC DEVICE INTEGRATED IN A SEMICONDUCTOR SUBSTRATE WITH WIDE BAND GAP AND ELECTRONIC DEVICE THUS OBTAINED - An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions. | 2013-04-18 |
20130095625 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate. | 2013-04-18 |
20130095626 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device, includes: and forming, on an upper face of a silicon substrate, a plurality of concave portions extending in a first direction, performing, in a gas that contains fluorine or a fluoride, plasma processing on the silicon substrate in which the concave portions are formed. The method further includes performing, in a gas that contains hydrogen, thermal processing on the silicon substrate after completion of performing the plasma processing; forming an insulating film on an inner face of the concave portions after completion of performing the thermal processing; and forming a conductive film on the insulating film. | 2013-04-18 |
20130095627 | Methods of Forming Source/Drain Regions on Transistor Devices - The present disclosure is directed to various methods of forming source/drain regions for transistor devices. In one example, a method disclosed herein includes the steps of forming a gate electrode structure for a transistor above a semiconducting substrate, performing a first etching process to define a plurality of initial cavities in the substrate proximate the gate structure for the transistor and after forming the initial cavities, performing an anneal process. The method continues with the steps of, after performing the anneal process, performing a second etching process on the initial cavities to define a plurality of final cavities and forming a semiconductor material in the final cavities. | 2013-04-18 |
20130095628 | MASK ROM FABRICATION METHOD - A mask ROM fabrication method which comprises steps: sequentially forming a gate dielectric layer and a first photoresist layer on a substrate; letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm; doping the substrate to form a plurality of embedded bit lines having a width of 243-365 nm; removing the first photoresist layer; sequentially forming a polysilicon layer and a second photoresist layer on the gate dielectric layer; and letting the light pass through a second phase shift mask to photolithographically form a plurality of polysilicon word lines on the polysilicon layer. Thereby is reduced the line width of mask ROM to 243-365 nm and decreased the area of mask ROM. | 2013-04-18 |
20130095629 | Finfet Parasitic Capacitance Reduction Using Air Gap - Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers. | 2013-04-18 |
20130095630 | THRESHOLD MISMATCH AND IDDQ REDUCTION USING SPLIT CARBON CO-IMPLANTATION - An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon implant and a zero-degree carbon implant that is substantially perpendicular to a top surface of the integrated circuit. The split carbon co-implant is done at the LDD and halo implant steps. | 2013-04-18 |
20130095631 | BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME - Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap. | 2013-04-18 |
20130095632 | Enhanced Work Function Layer Supporting Growth of Rutile Phase Titanium Oxide - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO | 2013-04-18 |
20130095633 | METHODS OF MANUFACTURING VARIABLE RESISTANCE MEMORY AND SEMICONDUCTOR DEVICE - Disclosed herein a method of manufacturing a variable resistance memory, which comprises: forming a conductive plug on a substrate; forming a variable resistance film above the substrate, the variable resistance film covering a top surface of the conductive plug; forming an insulating interlayer above the substrate, the insulating interlayer covering a top surface of the conductive plug; forming a hole in the insulating interlayer by removing a part of the insulating interlayer disposed above the conductive plug; and forming a first electroconductive film in the hole extending from a top surface of the insulating interlayer so as to be in contact with the variable resistance film and to be electrically connected with the conductive plug via the variable resistance film. | 2013-04-18 |
20130095634 | VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a method for manufacturing a variable resistance nonvolatile storage device, which prevents electrical conduction between lower electrodes and upper electrodes of variable resistance elements in the memory cell holes. The method includes: forming lower copper lines; forming a third interlayer insulating layer; forming memory cell holes in the third interlayer insulating layer, an opening diameter of upper portions of the memory cell holes being smaller than bottom portions; forming a metal electrode layer on the bottom of each memory cell holes by sputtering; embedding and forming a variable resistance layer in each memory cell hole; and forming upper copper lines connected to the variable resistance layer embedded and formed in each memory cell hole. | 2013-04-18 |
20130095635 | METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - A method for fabricating a nonvolatile memory device includes forming a first insulation layer and a first conductive layer on a substrate including a first region and a second region, forming a first isolation trench in the first region by etching the first conductive layer, the first insulation layer, and the substrate, forming a first isolation layer filled in the first isolation trench, forming a second insulation layer and a conductive capping layer, etching the capping layer and the second insulation layer, forming a second conductive layer, and forming first gate patterns by etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the first region, and forming a second isolation trench in the second region by etching the second conductive layer, the first conductive layer, the first insulation layer, and the substrate. | 2013-04-18 |
20130095636 | PROCESS FOR PRODUCING AT LEAST ONE DEEP TRENCH ISOLATION - A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation. | 2013-04-18 |
20130095637 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including forming a mask layer on a semiconductor substrate; forming a trench in the semiconductor substrate using the mask layer as an etch mask; forming a first layer in the trench; and performing a first thermal treatment process on the first layer such that the first thermal treatment process is performed under an atmosphere that includes ozone and water vapor and transforms the first layer into a second layer. | 2013-04-18 |
20130095638 | Method of Fabricating Integrated Circuits - A method of fabricating integrated circuits is provided in which sacrificial material is provided on a first surface of a substrate to define structural elements, integrated circuit material is provided on the sacrificial material to provide integrated circuit structures as defined by the structural elements, the sacrificial material is removed from the first surface of the substrate to provide partially fabricated integrated circuits defined by the integrated circuit structures, a carrier handle is attached to the partially fabricated integrated circuits, and the substrate is thinned from a second surface of the substrate opposite the first surface to provide the fabricated integrated circuits. | 2013-04-18 |
20130095639 | FILM FOR BACK SURFACE OF FLIP-CHIP SEMICONDUCTOR, DICING-TAPE-INTEGRATED FILM FOR BACK SURFACE OF SEMICONDUCTOR, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, AND FLIP-CHIP SEMICONDUCTOR DEVICE - The present invention relates to a film for back surface of flip-chip semiconductor, which is to be formed on a back surface of a semiconductor element flip-chip connected onto an adherend, wherein an amount of shrinkage of the film for back surface of flip-chip semiconductor due to thermal curing is 2% by volume or more and not more than 30% by volume relative to a total volume of the film for back surface of flip-chip semiconductor before the thermal curing. According to the film for back surface of flip-chip semiconductor according to the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, in the film for back surface of flip-chip semiconductor according to the present invention, since an amount of shrinkage due to thermal curing is 2% by volume or more relative to a total volume of the film for back surface of flip-chip semiconductor before the thermal curing, a warp of a semiconductor element to be generated at the time of flip-chip connecting the semiconductor element onto an adherend can be effectively suppressed or prevented. | 2013-04-18 |
20130095640 | REUSABLE SUBSTRATES FOR ELECTRONIC DEVICE FABRICATION AND METHODS THEREOF - Substrates for electronic device fabrication and methods thereof. A reusable substrate with at least a plurality of grooves for electronic device fabrication includes a substrate body made of one or more substrate materials and including a top planar surface, the top planar surface being divided into a plurality of planer regions by the plurality of grooves, the plurality of grooves including a plurality of bottom planar surfaces. Each of the plurality of grooves includes a bottom planar surface and two side surfaces, the bottom planar surface being selected from the plurality of bottom planar surfaces, the two side surfaces being in contact with the top surface and the bottom surface. The bottom planar surface is associated with a groove width from one of the two side surfaces to the other of the two side surfaces, the groove width ranging from 0.1 μm to 5 mm. | 2013-04-18 |
20130095641 | Method Of Manufacturing Gallium Nitride Film - A method of manufacturing a gallium nitride (GaN) film in which defects in a GaN film that grows can be reduced. The method includes the step of growing a GaN nano-rod on a substrate, the nano-rod having a circumferential groove in an outer periphery thereof, and the step of growing a GaN film on the GaN nano-rod. | 2013-04-18 |
20130095642 | JUNCTION LEAKAGE REDUCTION THROUGH IMPLANTATION - Provided is a method of fabricating a semiconductor device. The method includes forming a first III-V family layer over a substrate. The first III-V family layer includes a surface having a first surface morphology. The method includes performing an ion implantation process to the first III-V family layer through the surface. The ion implantation process changes the first surface morphology into a second surface morphology. After the ion implantation process is performed, the method includes forming a second III-V family layer over the first III-V family layer. The second III-V family layer has a material composition different from that of the first III-V family layer. | 2013-04-18 |
20130095643 | METHODS FOR IMPLANTING DOPANT SPECIES IN A SUBSTRATE - Methods for processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include implanting a dopant species into the one or more regions of the substrate using a first dopant precursor comprising a hydride of the dopant species; and implanting the dopant species into the one or more regions of the substrate using a second dopant precursor comprising fluorine and the dopant species. In some embodiments, the first and second dopant precursors may be provided simultaneously. In some embodiments, the first dopant precursor may be provided for a first time period, followed by providing the first dopant precursor and the second dopant precursor for a second period of time. In some embodiments, the flow of the first dopant precursor and the flow of the second dopant precursor may be alternated until a desired implant level is reached. | 2013-04-18 |
20130095644 | PLANARIZATION PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION - The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature. | 2013-04-18 |
20130095645 | MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration. | 2013-04-18 |