16th week of 2013 patent applcation highlights part 25 |
Patent application number | Title | Published |
20130094246 | BACKLIGHT UNIT AND DISPLAY DEVICE HAVING THE SAME - A backlight unit, a display module and a display device capable of effectively distributing heat inside, the display device including a display panel, a bottom sash disposed at a rear side of the display panel, a plurality of light emitting diodes (LEDs) configured to provide the display panel with light, at least one printed circuit board (PCB) which is disposed at an edge of a front surface of the bottom sash and on which the plurality of LEDs are mounted, and at least one heat radiation sheet mounted on the bottom sash to distribute heat emitted from the plurality of LEDs. | 2013-04-18 |
20130094247 | CONTROLLER FOR A SWITCHED MODE POWER CONVERTER - A switched mode power converter controller outputs a switch control signal for a switch, receives sensed voltage and primary current input signals, and includes a constant current mode controller to process voltage input signals and generate output control signals for controlling converter peak current and/or switching frequency operational; a constant voltage mode controller processes the voltage input signal and generates output control signals for converter peak current and/or switching frequency operational parameters; a primary peak current adjuster processes primary current input and output control signals from the current and voltage mode controllers to configure the switch control signal to turn off the switch; a switching frequency adjuster processes output control signals from the current and voltage controllers to configure the switch control signal to turn on the switch. The constant current controller is enabled if the constant voltage controller signals represent operation with maximum peak current and switching frequency. | 2013-04-18 |
20130094248 | Regulating Controller for Controlled Self-Oscillating Converters Using Bipolar Junction Transistors - A power converter controller and methods for its operation are provided that can control a self-oscillating power converter that uses a Bipolar Junction Transistor (BJT) as a switch by manipulating the current flowing in a control winding. The controller is able to determine the optimum time to remove a short circuit applied to the control winding, as well as being able to determine the optimum time to pass current through the control winding. The controller can further draw power from the power converter using the control winding. The controller is capable of maintaining the midpoint voltage of the power converter in the case that the converter has more than one switch. The controller estimates the output power of the converter without requiring a connection to the secondary side of the converter transformer. The controller further controls entry and exit into a low-power mode in which converter oscillations are suppressed. | 2013-04-18 |
20130094249 | SECONDARY SIDE SYNCHRONOUS RECTIFICATION CONTROL CIRCUIT AND SWITCHING CONVERTER - A secondary side synchronous rectification control circuit is disclosed. The control circuit includes an inverted amplifier, a first comparator, and a driving unit. The inverted amplifier has an input end for receiving a drain source voltage signal from a synchronous rectification transistor and outputting an inverted amplification signal. The first comparator receives the inverted amplification signal and a first reference voltage for outputting a first comparison signal. The driving unit receives the first comparison signal and generates a driving signal according to the first comparison signal, for controlling the conduction status of the synchronous rectification transistor. The drain source voltage of the synchronous rectification transistor in the present invention is inverted amplified by an inverted amplifier, and it is connected to a comparator for generating the driving signal. The errors and defects of the turn-off timing of the driving signal may be solved and eliminated. | 2013-04-18 |
20130094250 | DOWN CONVERTER - A down converter for converting an input DC voltage (Vin) into a lower output DC voltage (Vout). The down converter has on the primary side ( | 2013-04-18 |
20130094251 | SELF-DRIVEN SYNCHRONOUS RECTIFIER DRIVE DIRCUIT, METHOD OF OPERATION THEREOF AND POWER CONVERTER INCORPORATING THE SAME - A drive circuit for a synchronous rectifier, a method of driving a synchronous rectifier and a power converter incorporating the drive circuit or the method. In one embodiment, the drive circuit includes: (1) a first drive circuit stage configured to derive a timing for at least one drive signal from a secondary winding of a transformer coupled to the synchronous rectifier and (2) a second drive circuit stage, coupled to the first drive circuit stage and configured to employ a substantially stable voltage source to provide power for the at least one drive signal and apply the at least one drive signal to at least one control terminal of at least one synchronous rectifier switch in the synchronous rectifier. | 2013-04-18 |
20130094252 | FORWARD TYPE DC-DC CONVERTER - With the use of a voltage across a secondary winding of a transformer, a DC output voltage and a conduction time width of a current in the DC reactor on the secondary side circuit in an immediately preceding period, the turning-on time width and the turning-off time width of a synchronous rectification MOSFET in the secondary side circuit of the transformer are obtained by calculations, without receiving any signals from a primary side circuit, to thereby carry out control of a synchronous rectification circuit in a forward DC-DC converter with the time in which a current flows in a diode reduced to the minimum. | 2013-04-18 |
20130094253 | Control Circuit for Offline Power Converter without Input Capacitor - The present invention provides a control circuit for a power converter. The control circuit includes a switching circuit, an input-voltage detection circuit and a current-limit threshold. The switching circuit generates a switching signal coupled to switch a transformer of the power converter for regulating an output of the power converter in response to a feedback signal. The input-voltage detection circuit generates a control signal when an input voltage of the power converter is lower than a low-input threshold. The feedback signal is generated in response to the output of the power converter. A maximum duty of the switching signal is increased in response to the control signal. The current-limit threshold is for limiting a maximum value of a switching current flowing through the transformer. The current-limit threshold is increased in response to the control signal. An input of the power converter doesn't connect with electrolytic bulk capacitors. | 2013-04-18 |
20130094254 | METHODS AND POWER CONTROLLERS FOR PRIMARY SIDE CONTROL - Power controllers and related primary-side control methods are disclosed. A disclosed power controller has a comparator and an ON-triggering controller. The comparator compares a feedback voltage with an over-shot reference voltage. Based on an inductance-coupling effect, the feedback voltage represents a secondary-side voltage of a secondary winding. Coupled to the comparator, the ON-triggering controller operates a power switch at about a first switching frequency when the feedback voltage is lower than the over-shot reference voltage. The ON-triggering controller operates the power switch at about a second switching frequency when the feedback voltage exceeds the over-shot reference voltage. The second switching frequency is less than the first switching frequency. | 2013-04-18 |
20130094255 | POWER FACTOR CORRECTION CIRCUIT CAPABLE OF ESTIMATING INPUT CURRENT AND CONTROL METHOD FOR THE SAME - A power factor correction circuit and a control method thereof uses a power factor controller to generate a compensation current signal according to an input voltage of an AC-DC conversion circuit and a filter capacitor value. An estimation current signal is generated by summing up the compensation current signal and an inductor current signal of the AC-DC conversion circuit. And then, a pulse width modulation signal is outputted to the AC-DC conversion circuit according to the estimation current signal. The filter capacitor value is chosen from a capacitor value of a capacitor connected to the AC power source, an input capacitor value of the AC-DC conversion circuit, or sum of both the capacitor values. Therefore the estimation current signal approaches an input current signal of the power factor correction circuit to increase the power factor at the input terminals of the power factor correction circuit and decrease a harmonic distortion. | 2013-04-18 |
20130094256 | Power Conversion Device Using a Wave Propagation Medium and Operating Method Thereof - The present solution relates operation of a power conversion device ( | 2013-04-18 |
20130094257 | COMPOSITE AC-TO-DC POWER CONVERTER USING MIDPOINT METHOD - A 24-pulse and 18-pulse composite AC-to-DC converter is a converter using two or more conversion methods in parallel. The converter may include a main rectifier receiving at least a portion of an input AC signal, an autotransformer having an output voltage with lower amplitude than the input AC signal, and a plurality of auxiliary bridge rectifiers, each receiving the output from each leg of the autotransformer. In one embodiment of the invention, the main rectifier may receive a substantial portion of the load current, allowing each of the auxiliary bridge rectifiers to be generally smaller than the main rectifier. | 2013-04-18 |
20130094258 | ACTIVE FRONT END POWER CONVERTER WITH DIAGNOSTIC AND FAILURE PREVENTION USING PEAK DETECTOR WITH DECAY - Active front end power conversion systems are presented having a peak detector with adjustable decay providing a signal to an overload protection component to selectively discontinue rectifier switching control signals for protection of active rectifier switches during unbalanced line voltage conditions. | 2013-04-18 |
20130094259 | CONTROL APPARATUS OF POWER INVERTER CIRCUIT - It provides the effective power conversion control technique which it can control which it made use of a characteristic (nature) of each A/D converter in. It comprises the third control part including the third operating circuit it inputs signal from third A/D converter inputting the detecting signal which is different from the detecting signal which is the same as the detecting signal or the detecting signal and above third A/D converter, and to generate the third operating signal, and the above actuating management circuit manages the actuating of an above first control part and the second above control part and the third above control part. | 2013-04-18 |
20130094260 | Multi-Level DC/AC Converter - The multi-level DC/AC converter, comprising: an input ( | 2013-04-18 |
20130094261 | Photovoltaic Power Converters - Photovoltaic power converter systems and methods are described. In one example, a method for use in operating a solar power converter includes sampling a DC link voltage of a DC link during a first cycle of an alternating output voltage of a second stage at one instance when the alternating output voltage is crossing zero volts in a first direction. A voltage difference a voltage difference between the DC link voltage sampled during the first cycle and a DC link voltage sampled during a previous cycle when the alternating output voltage was crossing zero volts in the first direction is determined. A DC link power is estimated based at least in part on the determined voltage difference. The AC power output by the second stage in a second cycle is controlled based at least in part on the estimated DC link power. | 2013-04-18 |
20130094262 | System and Method for Exchangeable Capacitor Modules for High Power Inverters and Converters - A method of and system for monitoring condition of a large capacitor connected across an output of a rectifier circuit in an operating electrical power transmission circuit in order to anticipate capacitor failure and facilitate appropriate corrective action is disclosed. The method includes measuring a ripple voltage on the capacitor and ripple current through the capacitor, determining from a representative signal whether the signal exceeds a predetermined threshold; and sending an output to a controller on a system operator if the signal exceeds the predetermined threshold. The ripple current and ripple voltage measurements may be provided as inputs to a digital to analog converter which produces and sends the representative signal to a microprocessor to generate the output to the controller. | 2013-04-18 |
20130094263 | POWER SUPPLY DEVICE - A power supply device includes an input connector, an alternating current (AC)/direct current (DC) converter, a plurality of voltage converters, and a plurality of output connectors corresponding to the voltage converters. The input connector is electrically connected to a power supply. The AC/DC converter converts an AC electric potential provided by the power supply to a DC electric potential, and the voltage converters convert the DC electric potential generated by the AC/DC converter to DC electric potentials having predetermined effective values and output the DC electric potentials from the output connectors, respectively. | 2013-04-18 |
20130094264 | STATIC VAR COMPENSATOR WITH MULTILEVEL CONVERTER - A static synchronous compensator for use in reactive power compensation, the static synchronous compensator comprising at least one primary compensator limb including first and second DC terminals, and an AC terminal for connection in use to an AC network, the or each primary compensator limb defining first and second limb portions, each limb portion-including at least one switching element connected in series with a chain-link converter-between a respective one of the first and second DC terminate and the AC terminal, the switching elements of the first and second limb portions being operable to switch the respective chain-link converters in and out of circuit between the respective DC terminal and the AC terminal and the chain-link converters being operable to generate a voltage waveform at the AC terminal; and a secondary compensator limb including at least one DC link capacitor connected between the first and second DC terminals, the secondary compensator limb being connected in parallel with the or each primary compensator limb. | 2013-04-18 |
20130094265 | INTEGRATED INVERTER APPARATUS AND METHOD OF OPERATING THE SAME - An integrated inverter apparatus and a method of operating the same are disclosed. The integrated inverter apparatus includes at least two inverter units and a control unit. The inverter units are electrically connected in parallel to each other. At least one of the inverter units has a plurality of field-effect transistor (FET) switches and at least another one of the inverter units has a plurality of insulated gate bipolar transistor (IBGT) switches. The control unit is electrically connected to the inverter units to control the transistor switches of the corresponding inverter units when an optimal efficiency of the integrated inverter apparatus is reached at different operation conditions of the inverter units. | 2013-04-18 |
20130094266 | VOLTAGE INVERTER AND METHOD OF CONTROLLING SUCH AN INVERTER - A voltage inverter capable of operating in the event of a short-circuit or open-circuit fault. The voltage inverter includes: a load having three phases, each phase having a first terminal and a second terminal; first and second cells each including three branches connected together in parallel, each branch including two switches connected in series and a mid-point positioned between the two switches, each first terminal of each of the phases being connected to one of the mid-points of the first cell and each second terminal of each of the phases being connected to one of the mid-points of the second cell; and a DC voltage source, the first and second cells each being connected to the DC voltage source via two electrical isolators. | 2013-04-18 |
20130094267 | EVEN-LEVEL INVERTER - There is provided an even-level inverter, including: a voltage-dividing circuit dividing input DC power into an even number of voltage levels; a plurality of switching devices connected to individual nodes of the voltage-dividing circuit having the even number of voltage levels; and a bidirectional switching device connected to the individual nodes of the voltage-dividing circuit through at least one of the plurality of switching devices and including at least two transistors. According to the present invention, the bidirectional switching device is implemented without a diode to thereby reduce conduction loss caused due to an anti-parallel diode included in the related art bidirectional switching device, and a neutral point of the voltage-dividing circuit is electrically separated from the switching devices to thereby control reactive power. | 2013-04-18 |
20130094268 | Method and Apparatus for Controlling an Inverter Using Pulse Mode Control - A method and apparatus for controlling an inverter includes operating the inverter in a one of a normal run mode or a pulse mode depending on one or more criteria. When operating in the pulse mode, the inverter generates a sinusoidal output pulse waveform including a plurality of pulses having a determined pulse width. The pulse width is less than a half-wave period of a full-cycle sinusoidal waveform and may be determined as function of, for example, the output power of the inverter, a grid voltage, and/or other criteria. | 2013-04-18 |
20130094269 | Power Conversion Apparatus - A power conversion apparatus includes a smoothing capacitor module having a plurality of one and the other DC terminals arranged in a state of being laminated with each other, a flow channel forming body for forming a cooling medium flow channel that allows a cooling medium to flow along the capacitor module, and a plurality of power semiconductor modules each including a module case having a cooling surface, DC terminals projecting in one direction in a laminated state from the module case, and an AC terminal projecting in one direction from the module case. The power semiconductor modules are fixed to the flow channel forming body so that the cooling surface of the module case of the power semiconductor module is inserted into the cooling medium flow channel and comes into contact with the cooling medium flowing within the flow channel forming body. | 2013-04-18 |
20130094270 | Frequency converter and receiver that uses the frequency converter - The present invention is applied to a frequency converter used for a receiver. The frequency converter according to the present invention includes an LO signal generator ( | 2013-04-18 |
20130094271 | CONNECTION OF MULTIPLE SEMICONDUCTOR MEMORY DEVICES WITH CHIP ENABLE FUNCTION - A system comprising a plurality of memory devices coupled by a common bus to a controller has a single serially coupled enable signal per channel. Each memory device or chip comprises a serial enable input and enable output and a register for storing a device identifier, e.g., chip ID. The memory devices are serially coupled by a serial enable link, for assertion of a single enable signal to all devices. This parallel data and serial enable configuration provides reduced per-channel pin count, relative to conventional systems that require a unique enable signal for each device. In operation, commands on the common bus targeting an individual device are asserted by adding an address field comprising a device identifier to each command string, preferably in an initial identification cycle of the command. Methods are also disclosed for initializing the system, comprising assigning device identifiers and obtaining a device count, prior to normal operation. | 2013-04-18 |
20130094272 | DEVICE - A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit. | 2013-04-18 |
20130094273 | 3D MEMORY AND DECODING TECHNOLOGIES - A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection. | 2013-04-18 |
20130094274 | METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE - An object of the present invention is to provide a novel method for driving a semiconductor memory device. | 2013-04-18 |
20130094275 | STABILIZATION OF RESISTIVE MEMORY - The present disclosure includes apparatuses and methods including stabilization of resistive memory. A number of embodiments include applying a programming signal to a resistive memory cell, wherein the programming signal includes a first portion having a first polarity and a second portion having a second polarity, wherein the second polarity is opposite the first polarity. | 2013-04-18 |
20130094276 | APPARATUSES AND METHODS FOR DETERMINING STABILITY OF A MEMORY CELL - Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing another pulse to the memory cell or otherwise stressing the cell. The another pulse may be of an opposite polarity to the set or reset pulses already applied. If the memory cell is no longer in the target state after providing the another pulse, additional set or reset pulses may be applied to achieve a stable state. | 2013-04-18 |
20130094277 | RESISTIVE MEMORY APPARATUS, LAYOUT STRUCTURE, AND SENSING CIRCUIT THEREOF - Provided is a resistive memory apparatus including a plurality of memory areas each including a main memory cell array coupled to a plurality of word lines and a reference cell array coupled to a plurality of reference word lines. Each of the memory areas shares a bit line driver/sinker with an adjacent memory area. | 2013-04-18 |
20130094278 | Non-Volatile Memory Cell Containing an In-Cell Resistor - A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode. | 2013-04-18 |
20130094279 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with a lower-layer circuit including a transistor formed over a semiconductor substrate, and a memory cell array formed in an interconnection layer above the semiconductor substrate. Respective memory cells of the memory cell array are provided with a variable resistor element formed in the interconnection layer serving as a memory element. The memory cell array includes a first region directly underneath the memory cells, the first region being a region where a via for electrical coupling with the memory cell is not formed. The lower-layer circuit is disposed in such a way as to overlap at least a part of the first region. | 2013-04-18 |
20130094280 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of Operating - A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating. | 2013-04-18 |
20130094281 | METHOD FOR MEASURING DATA RETENTION CHARACTERISTIC OF RESISTIVE RANDOM ACCESS MEMORY DEVICE - A method for measuring data retention characteristic of an RRAM device includes: a) controlling a temperature of a sample stage to maintain the RRAM device at a predetermined temperature; b) setting the RRAM device to a high-resistance state or a low-resistance state; c) measuring data retention time by applying a predetermined voltage to the RRAM device so that a resistive state failure of the RRAM device occurs; d) repeating the steps a)-c) to perform a plurality of measurements; e) calculating a resistive state failure probability F(t) of the RRAM device from the data retention time in the plurality of measurements; and f) fitting the resistive state failure probability F(t), and calculating predicted data retention time t | 2013-04-18 |
20130094282 | MULTI-BIT SPIN-MOMENTUM-TRANSFER MAGNETORESISTENCE RANDOM ACCESS MEMORY WITH SINGLE MAGNETIC-TUNNEL-JUNCTION STACK - A magneto resistive random access memory system includes a first magnetic-tunnel-junction device coupled to a first bit-line, a second magnetic-tunnel-junction device coupled to a second bit-line, a selection transistor coupled to the first and second bit-lines and a word-line coupled to the selection transistor. | 2013-04-18 |
20130094283 | Apparatus, System, and Method for Writing Multiple Magnetic Random Access Memory Cells with a Single Field Line - A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity. | 2013-04-18 |
20130094284 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - Provided are a magneto resistive effect element with a stable magnetization direction perpendicular to a film plane and with a controlled magnetoresistance ratio, and a magnetic memory using the magneto resistive effect element. Ferromagnetic layers | 2013-04-18 |
20130094285 | PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level. | 2013-04-18 |
20130094286 | DETERMINING OPTIMAL READ REFERENCE AND PROGRAMMING VOLTAGES FOR NON-VOLATILE MEMORY USING MUTUAL INFORMATION - Approaches for operating a memory device comprising memory cells are disclosed. Optimal values for one or more of programming voltages used to program memory cells of the memory device and read reference voltages used to read the memory cells are determined using a mutual information function, I(X; Y), where X represents data values programmed to the memory cells and Y represents data values read from the memory cells. The read reference and/or programming voltages used for reading and/or programming the memory cells are adjusted using the optimal values. | 2013-04-18 |
20130094287 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a bit line, a first cell string and a second cell string. The first cell string includes a first selecting transistor connected to the bit line in series and having a threshold voltage greater than a first reference voltage, a second selecting transistor having a threshold voltage smaller than a second reference voltage, cell transistors and a ground selecting transistor. The second cell string includes a third selecting transistor connected to the bit line in series and having a threshold voltage smaller than the first reference voltage, a fourth selecting transistor having a threshold voltage greater than the second reference voltage, cell transistors and a ground selecting transistor. A channel region of the first selecting transistor has an enhancement mode and a first conductive type. A channel region of the third selecting transistor has a depletion mode and a second conductive type. | 2013-04-18 |
20130094288 | CATEGORIZING BIT ERRORS OF SOLID-STATE, NON-VOLATILE MEMORY - Bit errors affecting cells of a solid-state, non-volatile memory are assigned to at least a first or a second category based on a relative amount of voltage shift that caused the respective bit errors in the respective cells. A reference voltage used to access the respective cells is adjusted to manage the respective bit errors of the first category. Additional corrective measures are taken to manage the respective bit errors of the second category. | 2013-04-18 |
20130094289 | DETERMINATION OF MEMORY READ REFERENCE AND PROGRAMMING VOLTAGES - Symmetrical or asymmetrical noise distributions for voltages corresponding to symbols that can be stored in multi-level memory cells (MLCs) of a memory device are used to determine read reference and/or programming voltages. The read reference voltages and/or programming voltages for the MLCs are jointly determined using the symmetrical distributions and a maximum likelihood estimation (MLE) and/or by determining at least one of the read reference voltages and the programming voltages using the asymmetrical distributions. | 2013-04-18 |
20130094290 | SHIFTING CELL VOLTAGE BASED ON GROUPING OF SOLID-STATE, NON-VOLATILE MEMORY CELLS - Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells. | 2013-04-18 |
20130094291 | SEMICONDUCTOR MEMORY DEVICE - At least one of a plurality of columns is an LM column for storing LM flag data indicating a progression state of a write operation. Each of column control circuits performs an LM address scan operation for confirming whether the LM column exists in a corresponding memory core or not. Each of the column control circuits stores a result of that LM address scan operation in a register. In various kinds of operations after the LM address scan operation, each of the column control circuits executes an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is first data, and omits executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is second data. | 2013-04-18 |
20130094292 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD OF THE SAME - A method is provided for programming a multi-level cell flash memory device. The programming method includes programming a first memory cell of the multi-level call flash memory device to one of first through i-th program states, wherein i is a positive integer, by applying a first program pulse to the first memory cell in a first type programming operation, and programming a second memory cell to one of i+1-th through j-th program states, wherein j is an integer equal to or greater than three, by applying a second program pulse to the second memory cell in a second type programming operation. At least one of a second step voltage, a second bit-line forcing voltage and a second verification operation of the second type programming operation is different from a first step voltage, a first bit-line forcing voltage, and a first verification operation of the first type programming operation, respectively. | 2013-04-18 |
20130094293 | MEMORY DEVICE AND METHOD OF READING DATA FROM MEMORY DEVICE - A method is provided for reading data from memory cells, including at least one victim cell and at least one aggressor cell, using an element graph. The method includes defining function nodes corresponding to probability density functions with respect to a first physical characteristic of the at least one victim cell and a second physical characteristic of the at least one aggressor cell, defining variable nodes corresponding to at least one first data value stored in the at least one victim cell and at least one second data value stored in the at least one aggressor cell, and defining edges connecting the function nodes and the variable nodes. | 2013-04-18 |
20130094294 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE - Disclosed are a program method and a nonvolatile memory device. The method includes receiving program data to be programmed in memory cells; reading the memory cells to judge an erase state and at least one program state; performing a state read operation in which the at least one program state is read using a plurality of state read voltages; and programming the program data in the memory cells using a plurality of verification voltages having different levels according to a result of the state read operation. Also disclosed are methods using a plurality of verification voltages selected based on factors which may affect a threshold voltage shift or other characteristic representing the data of a memory cell after programming. | 2013-04-18 |
20130094295 | MEMORY DEVICE IN PARTICULAR EXTRA ARRAY CONFIGURED THEREIN FOR CONFIGURATION AND REDUNDANCY INFORMATION - Disclosed herein is a device that includes a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction, and a plurality of second word lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines. | 2013-04-18 |
20130094296 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. | 2013-04-18 |
20130094297 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device. | 2013-04-18 |
20130094298 | STORAGE DEVICES WITH SOFT PROCESSING - A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states. | 2013-04-18 |
20130094299 | Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory - Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits. | 2013-04-18 |
20130094300 | READING DEVICES FOR MEMORY ARRAYS - A reading device for a memory array is provided. The memory array comprises memory cell columns. The reading device comprises first sensing amplifier groups, a second sensing amplifier group, and an output unit. Each first sensing amplifier groups selectively generates a first sensing output signal. The second sensing amplifier group generates a second sensing output signal. The output unit selectively outputs one of the second sensing output signal and the first sensing output signals according to a page address signal. In a reading operation period, the reading device reads data from a column group to the first sensing amplifier groups. In the reading operation period, when the page address signal indicates an initial input address, initial address data read from the specific column set corresponding to the initial input address among the column group is transmitted to the second sensing amplifier group to generate the second sensing output signal. | 2013-04-18 |
20130094301 | INTERFACES AND DIE PACKAGES, AND APPARTUSES INCLUDING THE SAME - A memory device includes a die package including a plurality of memory dies, an interface including an interface circuit, and a memory controller to control the interface with control data received from at least one die. The interface is to divide and multiplex an IO channel between the package and the controller into more than one channel using the data received from the at least one die. The interface includes a control input buffer to receive an enable signal through a control pad, a first input buffer to receive first data through a first IO pad in response to a first state of the enable signal, and a second input buffer to receive second data through a second IO pad in response to a second state of the enable signal. The interface further includes an input multiplexer to multiplex the first data and the second data to provide input data. | 2013-04-18 |
20130094302 | INTEGRATED CIRCUIT CHIP AND SEMICONDUCTOR MEMORY DEVICE - An integrated circuit chip includes an internal circuit configured to generate output data, an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the integrate circuit chip, and a signal output circuit configured to invert or not to invert the output data in response to the inversion signal and output the inverted or non-inverted output data. | 2013-04-18 |
20130094303 | Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory - Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits. | 2013-04-18 |
20130094304 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes: a driving voltage generation unit configured to generate a driving voltage of a core bias line included in a memory cell current path; a comparison unit configured to compare a voltage level of the core bias line with a predetermined limit level in response to a virtual negative read signal; and a compensation driving unit configured to compensation-drive the core bias line in response to an output signal of the comparison unit. | 2013-04-18 |
20130094305 | DEVICE FOR SUPPLYING A HIGH ERASE PROGRAM VOLTAGE TO AN INTEGRATED CIRCUIT - The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor. | 2013-04-18 |
20130094306 | INTEGRATED CIRCUIT COMPRISING A NON-DEDICATED TERMINAL FOR RECEIVING AN ERASE PROGRAM HIGH VOLTAGE - The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals. | 2013-04-18 |
20130094307 | BIT LINE VOLTAGE BIAS FOR LOW POWER MEMORY DESIGN - In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV. | 2013-04-18 |
20130094308 | NEGATIVE WORD LINE DRIVER FOR SEMICONDUCTOR MEMORIES - A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line. | 2013-04-18 |
20130094309 | TRACKING BIT CELL - A memory macro includes a tracking circuit and a plurality of memory cells. The tracking circuit has tracking transistors configured to receive a tracking voltage value. Each memory cell of the plurality of memory cells has memory transistors configured to receive a cell voltage value different from the tracking voltage value. The tracking circuit is configured to generate a tracking signal based on which a reading signal of a memory cell of the plurality of memory cells is generated. | 2013-04-18 |
20130094310 | METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 2013-04-18 |
20130094311 | DYNAMIC PHASE SHIFTER AND STATICIZER - A dynamic phase shifter and staticizer circuit and method includes a clock domino configured to receive a phase memory signal from a memory array and a clock signal and output the intermediate signal, and a staticizer configured to receive the intermediate signal from the clock domino and the clock signal and output a static memory signal. The static memory signal is shifted by one clock cycle from the phase memory signal. Setup and holding is done with respect to the clock edge, shifting the output of the clock domino, and the received phase memory signal can borrow into the next cycle when being sampled. The phase memory signal is converted from a half-cycle in length to the static memory signal that is a full-cycle in length. | 2013-04-18 |
20130094312 | VOLTAGE SCALING DEVICE OF SEMICONDUCTOR MEMORY - A voltage scaling device of a semiconductor memory device, the voltage scaling device including: a delay tester for determining the number of delay cells of a delay locked loop (DLL) required to cumulatively delay a clock signal having a constant frequency, and which is input to the DLL, by one clock period; a temperature sensor for measuring the temperature of the semiconductor memory device; and a voltage regulator for regulating a supply voltage of a voltage source which provides a chip voltage to the semiconductor memory device in response to the temperature measured by the temperature sensor and a locking value corresponding to the number of delay cells calculated by the delay tester. | 2013-04-18 |
20130094313 | COLLISION PREVENTION IN A DUAL PORT MEMORY - A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row. | 2013-04-18 |
20130094314 | SRAM POWER REDUCTION THROUGH SELECTIVE PROGRAMMING - A method of programming a memory array having plural subarrays is disclosed. (FIG. | 2013-04-18 |
20130094315 | STATIC RANDOM ACCESS MEMORY TEST STRUCTURE - A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of V | 2013-04-18 |
20130094316 | MEMORY SYSTEM - A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other. | 2013-04-18 |
20130094317 | REFRESH CONTROL CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS - A refresh control circuit of a semiconductor apparatus includes: a first bank refresh counter configured to increase or decrease a logic value of a first refresh address signal when a first bank address signal is enabled during a refresh operation, a second bank refresh counter configured to increase or decrease a logic value of a second refresh address signal when a second bank address signal is enabled during the refresh operation, a bank selection unit configured to generate first and second bank select signals in response to the first and second bank address signals during the refresh operation, and a row selection unit configured to generate first and second row select signals in response to the first and second refresh address signals and the first and second bank select signals. | 2013-04-18 |
20130094318 | Energy Efficient Processor Having Heterogeneous Cache - A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells. | 2013-04-18 |
20130094319 | Method and Apparatus of Addressing A Memory Integrated Circuit - A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes. | 2013-04-18 |
20130094320 | ADDRESS TRANSFORMING CIRCUITS INCLUDING A RANDOM CODE GENERATOR, AND RELATED SEMICONDUCTOR MEMORY DEVICES AND METHODS - Address transforming methods are provided. The methods may include generating a power-up signal when a semiconductor memory device is powered-up. The methods may further include generating a randomized output signal in response to the power-up signal. The methods may additionally include transforming bits of a first address in response to the randomized output signal to generate a second address. | 2013-04-18 |
20130094321 | SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER TO CONTROL OUTPUT TIMING OF DATA AND DATA PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage. | 2013-04-18 |
20130094322 | Apparatus and method for processing of a food, and in particular for the processing of dough - An apparatus and method for processing a foodstuff comprises a closed conveyor path, a conveyor device, and a treatment chamber. The conveyor path includes an inlet and an outlet. The conveyor device is positioned within the closed conveyor path and configured to receive the foodstuff from the inlet. The conveyor device is further configured to convey the foodstuff along the closed conveyor path toward the outlet. The treatment chamber is positioned within the closed conveyor path downstream of the conveyor device for receiving the foodstuff from the conveyor device. The treatment chamber includes a rotatably driven first kneading shaft configured to collide the foodstuff within the treatment chamber. | 2013-04-18 |
20130094323 | MIXER FOR PULP-AND FIBER-CONTAINING BEVERAGES - A device for mixing a pulp- and/or fiber-containing fluid which comprises an apparatus for moving the fluid free from shearing, and a corresponding method. | 2013-04-18 |
20130094324 | SOLUTION MAKING SYSTEM AND METHOD - A solution making system and apparatus are described. The solution maker mixes a chemical or slurry with a solvent to a desired concentration. The concentration of the solution is monitored by one or more methods. Based upon this measurement, the concentration of the solution may be adjusted. | 2013-04-18 |
20130094325 | LOOK-AHEAD SEISMIC WHILE DRILLING - A method of evaluating a formation of interest, comprises collecting a data set comprising signals received at a plurality of receivers signals from a source on a bottom-hole assembly at a position in a borehole, processing the data set so as to create a virtual trace received at a virtual receiver located at the source position, and using the virtual trace to generate an image or measurement containing information about the formation of interest. The source may or may not be a drill bit and the data can be collected at several different source positions. | 2013-04-18 |
20130094326 | SYSTEM AND METHOD FOR SEISMOLOGICAL SOUNDING - Systems and methods for seismological sounding with acoustic signals and, more particularly, systems and methods for performing geophysical surveys using spread spectrum acoustic waves generated by non-impulsive sources. A spread spectrum signal is generated and coupled to a medium that is to be sounded for propagation of an acoustic wave through the medium. One or more return signals are received from the medium that are generated by interaction between the acoustic wave and the medium. The return signals are possessed to obtain seismic sounding data describing the structural features of the medium. | 2013-04-18 |
20130094327 | ACOUSTIC WAVE ACQUIRING APPARATUS AND CONTROL METHOD THEREOF - The present invention provides an acoustic wave acquiring apparatus including: a probe configured to receive an acoustic wave from an object through an object holding unit that holds the object; an acoustic matching material holding unit configured to form a space, which holds an acoustic matching material, between the object holding unit and the probe; a scanning unit configured to allow the probe to scan in a first direction on the surface of the object holding unit, and in a second direction crossing the first direction; and a supplying unit configured to supply the acoustic matching material to the space by using a predetermined supply-amount pattern, wherein the supplying unit uses different supply-amount patterns in the case where the probe scans in the first direction and in the case where the probe scans in the second direction. | 2013-04-18 |
20130094328 | METHOD FOR CONTROLLING TRANSDUCERS OF AN ULTRASONIC PROBE, CORRESPONDING COMPUTER PROGRAM AND ULTRASONIC PROBE DEVICE - A method for controlling ultrasonic transducers of an ultrasonic probe for inspecting an object includes: iterated at least twice, receiving from the transducers new measurement signals; measuring echoes due to reflections of ultrasonic waves on the object, the ultrasonic waves having emission delays with respect to one another, the emission delays having been determined from initial emission delays and all complementary emission delays determined previously; determining new complementary emission delays from the new measurement signals; controlling the transducers so they emit ultrasonic waves to the object, the ultrasonic waves having emission delays with respect to one another, the emission delays having been determined from the initial emission delays and all the complementary emission delays determined previously. | 2013-04-18 |
20130094329 | CHANNEL IMPULSE RESPONSE ESTIMATION - A human-machine interface system adapted to track movement of an object in air is disclosed. In one aspect, the human-machine interface includes an acoustic transmitter, an acoustic receiver, and logic configured to apply a calculated inverse matrix of an impulse signal transmitted by the acoustic transmitter to a signal received by the acoustic receiver, wherein movement of the object is used to control the machine. | 2013-04-18 |
20130094330 | METHODS AND APPARATUS FOR PASSIVE DETECTION OF OBJECTS IN SHALLOW WATERWAYS - A method and system for detecting watercraft in shallow waterways. In one example, an underwater detection system includes an underwater power source, an acoustic sensor, a controller coupled to the power source and to the acoustic sensor and configured to detect a watercraft of interest based on acoustic signals generated by the watercraft of interest and received by the acoustic sensor, and a retractable communications system. The retractable communications system is configured to deploy a transmitter to the surface of the shallow water to report detection of a watercraft in the waterway and to retract the transmitter to a safe depth below the surface of the shallow waterway when not actively communicating. | 2013-04-18 |
20130094331 | SOUND GENERATION SYSTEM, ULTRASONIC WAVE EMITTING DEVICE, AND ULTRASONIC WAVE EMITTING METHOD - Disclosed are a sound generation system, an ultrasonic wave emitting device, and an ultrasonic wave emitting method which utilize the principle of parametric speakers (which uses the difference between frequencies of two ultrasonic waves) and which are capable of allowing target persons in a prescribed area to hear a sound only when a mobile body approaches said prescribed area. An alert system ( | 2013-04-18 |
20130094332 | System and Method for Using an Impact-Activated Device for Repelling Sharks from Marine Geophysical Survey Equipment - Disclosed are methods and systems for using an impact-activated device for repelling sharks from marine geophysical survey equipment. An embodiment discloses a marine geophysical survey system, comprising: marine geophysical survey equipment configured to be located in a body of water when in operation; and an impact-activated device coupled to the marine geophysical equipment, wherein the impact-activated device comprises a circuit configured to release a shark repellent in response to a pre-determined impact on the impact-activated device. | 2013-04-18 |
20130094333 | TIMEPIECE DISPLAY PLATE - A timepiece display plate, while obtaining reflection light having metal texture, allows partial light as a transmissive light to transmit to a solar cell and easily adapt to various types of dial plates. A timepiece display plate ( | 2013-04-18 |
20130094334 | DATA PROCESSING SYSTEM HAVING DATA REPRODUCTION INDEPENDENT OF DATA PROCESSING - A processing unit performs a method including controlling a reading-out of data from a first storage medium at a predetermined read-out data rate to produce inputted data, and controlling a compression of the inputted data to produce first compressed data of a first compressed format. The method includes controlling a storage of the first compressed data in a second storage medium at a faster writing data rate than the predetermined read-out data rate, controlling a reading-out of second compressed data of a second compressed format from the second storage medium, and controlling a decompression of the second compressed data to produce decompressed data. The method also includes controlling simultaneously the storage of the first compressed data in the second storage medium, the reading-out of the second compressed data from the second storage medium, and audibly reproducing the decompressed data. The first compressed format is different from the second compressed format. | 2013-04-18 |
20130094335 | OPTICAL DISC DRIVE AND METHOD OF DRIVING THE SAME - Provided is a multi-functional optical disc drive that includes an interface that connects a front-end of the optical drive to a back-end, and also connects the front-end of the optical drive to an external device. The optical drive also includes a controller that selectively controls connection to the back-end or the external device. | 2013-04-18 |
20130094336 | MEDIA TRANSPORTATION MECHANISM, METHOD OF CONTROLLING A MEDIA TRANSPORTATION MECHANISM, AND MEDIA PROCESSING DEVICE - A media transportation mechanism has: a storage unit that stores disc-shaped media with a center hole in a stack; a transportation arm that moves vertically and has a gripping member to hold a medium stored in the storage unit, and a separating member that moves radially to the medium from the hole of the medium; and a transportation arm drive member that sets the ascent speed of the transportation arm to a first speed, and to a second speed that is slower than the first speed, when moving the transportation arm vertically up while the gripping member holds the medium. | 2013-04-18 |
20130094337 | OPTICAL READ/WRITE APPARATUS AND READ APPARATUS - In one embodiment, the optical read/write apparatus includes a plurality of optical pickups arranged to cross tracks of an optical storage medium and a control section. On finding the data that has been written by any of those optical pickups inaccurate or on detecting any defect at a location where data is going to be written by any of the optical pickups, the control section instructs another one of the optical pickups to write that data on a different track from a track on which the data should have been written. | 2013-04-18 |
20130094338 | OPTICAL PICKUP AND OPTICAL READ/WRITE APPARATUS - An optical pickup includes: a light source; a first diffractive element which diffracts light polarized in a particular direction; an objective lens; a lens actuator which shifts the objective lens so that the magnitude of shift from its initial position in a tracking direction has an upper limit of 0.3 mm to 0.6 mm; a wave plate; a second diffractive element which has two diffraction regions configured to diffract light polarized in a direction that intersects with the particular direction at right angles and which splits the write beam reflected from the optical storage medium through each diffraction region into a transmitted light beam and at least one diffracted light beam; and a photodetector which detects the transmitted light beam, the diffracted light beams that have left the two diffraction regions, and the read beam reflected from the optical storage medium. | 2013-04-18 |
20130094339 | OBJECTIVE LENS, OPTICAL PICKUP DEVICE, AND OPTICAL DISC DEVICE - Provided is an objective lens including a diffraction portion provided on a laser beam incident plane or output plane. The diffraction portion includes first second, and third diffraction regions, wherein first laser beams corresponding to a first optical disc having a first transmissive layer are condensed on a data recording portion of the first optical disc, second laser beams corresponding to a second optical disc having a second transmissive layer thicker than the first transmissive layer are condensed on a data recording portion of the second optical disc, and third laser beams corresponding to a third optical disc having a third transmissive layer thicker than the second transmissive layer are condensed on a data recording portion of the third optical disc. An evaluation parameter calculated on the basis of an in-plane efficiency distribution function has a value corresponding to a symbol error rate that is less than a predetermined value. | 2013-04-18 |
20130094340 | DATA PROTECTION SYSTEM - The present invention provides systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format. The present invention also provides systems and methods for protecting data stored on data storage medium so that the data may be recovered without errors. | 2013-04-18 |
20130094341 | OPTICAL PICKUP AND OPTICAL DISK APPARATUS - According to one embodiment, an optical pickup configured to record and to reproduce on a layer of a disk, including, a light source configured to emit a laser beam, an objective lens including a variable use magnification and configured to focus the laser beam on the layer, a collimator lens configured to change the magnification of the objective lens by moving along an optical axis direction, and a liquid crystal module configured to generate spherical aberration to cancel a coma aberration which may occur because an object point and an image point of the objective lens at the use magnification do not exist on an optical axis of the objective lens. | 2013-04-18 |
20130094342 | SPINDLE MOTOR AND DISK DRIVE APPARATUS - A spindle motor includes a stationary portion and a rotating portion. The rotating portion includes a magnet arranged around a central axis extending in a vertical direction. The stationary portion includes a base member and a magnetic member arranged below the magnet and fixed to the base member. The base member includes an upper surface extending out perpendicularly or substantially perpendicularly to the central axis, and a wall surface extending in an axial direction. The magnetic member includes an annular plate portion arranged on the base member and a projecting portion arranged to extend downward from the plate portion. At least a portion of the projecting portion is arranged to be in contact with the wall surface. An adhesive is arranged between the plate portion and the upper surface of the base member and between the projecting portion and the wall surface. | 2013-04-18 |
20130094343 | INFORMATION RECORDING MEDIUM, INFORMATION REPRODUCTION APPARATUS AND INFORMATION RECORDING APPARATUS - According to one embodiment, an information recording medium characterized by including, a first servo layer, a second servo layer, and a data layer, the information recording medium further including, a first spiral track and a second spiral track formed between the first servo layer and the second servo layer and spiraling in opposite directions. | 2013-04-18 |
20130094344 | CDD PRECODING FOR OPEN LOOP SU MIMO - A method for data transmission, comprises the steps of modulating data to be transmitted via a transmitter into a plurality of modulated symbols, generating a codebook comprising a plurality of codewords, selecting a codeword from the codebook as a precoding matrix by a predetermined cycling selection, precoding the modulated symbols with the precoding matrix selected, and transmitting the precoded modulated symbols. | 2013-04-18 |
20130094345 | DYNAMICALLY SELECTING METHODS TO REDUCE DISTORTION IN MULTI-CARRIER MODULATED SIGNALS RESULTING FROM HIGH PEAK-TO-AVERAGE POWER RATIOS - In one embodiment, an algorithm dynamically selects a method for reducing distortion in a multi-carrier modulated signal, such as an orthogonal frequency division multiplexing (OFDM) signal. The algorithm directs a transmitter to transmit peak-to-average power ratio (PAPR)-reduction signals over reserved tones (i.e., frequencies) if reserved tones are available. If reserved tones are not available, then the algorithm directs the transmitter to transmit PAPR-reduction symbols over free tones if free tones are available. If the free tones for this transmitter are used by adjacent transmitters, then interference-reduction techniques may be used to reduce interference with the adjacent transmitters. If reserved tones and free tones are not available, then the transmitter may use an alternative method to reduce distortion, such as successive clipping and filtering. In another embodiment, the transmitter may transmit PAPR-reduction symbols over both free and reserved tones, if available. | 2013-04-18 |