16th week of 2013 patent applcation highlights part 13 |
Patent application number | Title | Published |
20130093046 | LOW IMPEDANCE GATE CONTROL METHOD AND APPARATUS - According to one embodiment of a module, the module includes a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output. The chips are spaced apart from one another and have a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips. The module further includes a plurality of capacitors coupled in parallel between ground and the common supply voltage, and a transverse electromagnetic (TEM) transmission line medium coupled to the common output of the chips and having a current flow direction perpendicular to the combined width of the chips. | 2013-04-18 |
20130093047 | Metal-Oxide-Metal Capacitor Structure - A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material. | 2013-04-18 |
20130093048 | Deposited Material and Method of Formation - A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period. | 2013-04-18 |
20130093049 | High Productivity Combinatorial Dual Shadow Mask Design - Dual shadow mask design can overcome the size and resolution limitations of shadow masks to provide capacitor structures with small effective areas. The capacitor structures have bottom and top electrode layers patterned using shadow masks, sandwiching a dielectric layer. The effective areas of the capacitors are the overlapping areas of the top and bottom electrodes, thus allowing small area sizes without subjected to the size limitation of the electrodes. The dual shadow mask design can be used in conjunction with high productivity combinatorial processes for screening and optimizing dielectric materials and fabrication processes. | 2013-04-18 |
20130093050 | Integrated Circuitry, Methods Of Forming Capacitors, And Methods Of Forming Integrated Circuitry Comprising An Array Of Capacitors And Circuitry Peripheral To The Array - A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture. | 2013-04-18 |
20130093051 | Asymmetric MIM Capacitor for DRAM Devices - A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO | 2013-04-18 |
20130093052 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A RESISTOR AND METHOD OF FORMING THE SAME - The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures. | 2013-04-18 |
20130093053 | TRENCH TYPE PIP CAPACITOR, POWER INTEGRATED CIRCUIT DEVICE USING THE CAPACITOR, AND METHOD OF MANUFACTURING THE POWER INTEGRATED CIRCUIT DEVICE - A trench-type PIP capacitor having a small step at the end part of the capacitor without increasing manufacturing cost, and a power integrated circuit device that uses such a trench-type PIP capacitor are disclosed. A method of manufacturing the power integrated circuit device also is disclosed. A trench-type PIP capacitor has a construction, in the surface region of a semiconductor substrate, comprising an isolating insulation layer formed on an inner wall of a trench and a first polysilicon that fills the trench through the isolating insulation layer and becomes a lower electrode. Since this construction has a small step formed at the end region of the capacitor, a metal layer for wiring does not need to be made excessively thick, allowing a fine structure of the metal layer. Therefore, the power IC provided with such a trench-type PIP capacitor can have a fine structure. | 2013-04-18 |
20130093054 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a first insulation layer on or over a semiconductor substrate, metal patterns on or over the first insulation layer, a thin film resistor pattern disposed on or over the metal patterns, and an anti-reflection layer between the thin film resistor pattern and the metal patterns. | 2013-04-18 |
20130093055 | Semiconductor Device and Manufacturing Method of the Same - Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a metal head pattern on the first insulation layer, the metal head pattern including an inclined side surface, a thin film resistor pattern on the metal head pattern, a second insulation layer on the metal head pattern and the thin film resistor pattern, an upper metal line on the second insulation layer, a first via connecting the lower metal line to the upper metal line, and a second via connecting the metal head pattern to the upper metal line. | 2013-04-18 |
20130093056 | Semiconductor Device and Method of Manufacturing the Same - Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a second insulation layer on the first insulation layer, the second insulation layer including a metal head pattern, a thin film resistor pattern on the metal head pattern, a third insulation layer on the thin film resistor pattern, an upper metal line on the third insulation layer, a first via passing through the first, second, and third insulation layers to connect the lower metal line to the upper metal line, and a second via passing through the third insulation layer and the thin film resistor pattern to connect the metal head pattern to the upper metal line. | 2013-04-18 |
20130093057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductive type semiconductor layer formed on a substrate; a first conductive type embedded layer formed between the substrate and the semiconductor layer; a second conductive type well formed on the semiconductor layer; a first conductive type first contact layer that is positioned on the semiconductor layer, separate from the well; a second conductive type second contact layer formed on the well; a first conductive type third contact layer formed on the well between the first and second contact layers; and a first conductive type deep layer formed between the embedded layer and the first contact layer and in contact with the first contact layer. A minimum point in the effective impurity concentration profile along a straight line that extends in a vertical direction and passes through the embedded layer and the second part exists between the embedded layer and the first part. | 2013-04-18 |
20130093058 | P-Type Silicon Single Crystal and Method Of Manufacturing The Same - Silicon wafers having a resistivity >6 Ωcm and axially uniform resistivity are grown by the Czochralski method from a melt containing boron as the main dopant, an n-type first sub-dopant with a segregation coefficient lower than boron, and a p-type second sub-dopant with a segregation coefficient lower than the first sub-dopant. | 2013-04-18 |
20130093059 | Bonded Substrate And Method Of Manufacturing The Same - A bonded substrate, the surface roughness of which is reduced, and a method of manufacturing the same. The bonded substrate includes a base substrate and an intermediate layer disposed on the base substrate. The intermediate layer has a greater bubble diffusivity than the base substrate. A thin film layer is bonded onto the intermediate layer, and has a different chemical composition from the base substrate. | 2013-04-18 |
20130093060 | METHOD FOR PRODUCING SILICON WAFER AND SILICON WAFER - A silicon wafer and method for producing a silicon wafer, including at least: a first heat treatment process in which rapid heat treatment is performed on the wafer by using a rapid heating/cooling apparatus in an atmosphere containing at least one of nitride film formation atmospheric gas, rare gas, and oxidizing gas at a temperature higher than 1300° C. and lower than or equal to a silicon melting point for 1 to 60 seconds; and a second heat treatment process in which temperature and atmosphere are controlled to suppress generation of a defect caused by a vacancy in the wafer and rapid heat treatment is performed on the wafer. Therefore, RIE defects such as oxide precipitates, COPs, and OSFs are not present at a depth of at least 1 μm from the surface, which becomes a device fabrication region, and the lifetime is 500 μsec or longer. | 2013-04-18 |
20130093061 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate; an underlying wiring on the semiconductor substrate; a resin film extending to the semiconductor substrate and the underlying wiring, and having a first opening on the underlying wiring; a first SiN film on the underlying wiring and the resin film, and having a second opening in the first opening; an upper layer wiring on the underlying wiring and part of the resin film; and a second SiN film on the upper layer wiring and the resin film, and joined to the first SiN film on the resin film. The upper layer wiring includes a Ti film, connected to the underlying wiring via the first and second openings, and an Au film on the Ti film. The first and second SiN films circumferentially protect the Ti film. | 2013-04-18 |
20130093062 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess. | 2013-04-18 |
20130093063 | BONDED SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A bonded substrate having a plurality of grooves and a method of manufacturing the same. The method includes the following steps of implanting ions into a first substrate, thereby forming an ion implantation layer, bonding the first substrate to a second substrate having a plurality of grooves in one surface thereof such that the first substrate is bonded to the one surface, and cleaving the first substrate along the ion implantation layer. | 2013-04-18 |
20130093064 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process. | 2013-04-18 |
20130093065 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an N-type drift layer; a P-type anode layer above the N-type drift layer; an N-type cathode layer below the N-type drift layer; a first short lifetime layer between the N-type drift layer and the P-type anode layer; and a second short lifetime layer between the N-type drift layer and the N-type cathode layer. A carrier lifetime in the first and second short lifetime layers is shorter than a carrier lifetime in the N-type drift layer. A carrier lifetime in the N-type cathode layer is longer than the carrier lifetime in the N-type drift layer. | 2013-04-18 |
20130093066 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer. | 2013-04-18 |
20130093067 | WAFER LEVEL APPLIED RF SHIELDS - An embodiment of a method of forming an on-chip RE shield on an integrated circuit chip in accordance with the present disclosure includes providing a wafer level integrated circuit component wafer having a front side and a back side before singulation; applying a resin metal layer on a back side of the wafer; and then separating the wafer into discrete RF shielded components. It is this resin metal layer on the back side that acts effectively as the RF shield, after singulation, i.e. separation of the wafer, into discrete RF shielded components. | 2013-04-18 |
20130093068 | Semiconductor Device and Method of Forming Air Gap Adjacent to Stress Sensitive Region of the Die - A semiconductor device is made by mounting an insulating layer over a temporary substrate. A via is formed through the insulating layer. The via is filled with conductive material. A semiconductor die has a stress sensitive region. A dam is formed around the stress sensitive region. The semiconductor die is mounted to the conductive via. The dam creates a gap adjacent to the stress sensitive region. An encapsulant is deposited over the semiconductor die. The dam blocks the encapsulant from entering the gap. The temporary substrate is removed. A first interconnect structure is formed over the semiconductor die. The gap isolates the stress sensitive region from the first interconnect structure. A shielding layer or heat sink can be formed over the semiconductor die. A second interconnect structure can be formed over the semiconductor die opposite the first interconnect structure. | 2013-04-18 |
20130093069 | PACKAGE STRUCTURE AND THE METHOD TO FABRICATE THEREOF - The invention discloses a package structure made of the combination of a metallic substrate and a lead frame. In one embodiment, a recess is formed in the metallic substrate and a first conductive element having at least one first I/O terminal is bonded in the recess. A lead frame is formed on the metallic substrate and comprises a plurality of electrical connections to connect with said at least one first I/O terminal of the first conductive element. In another embodiment, another conductive element is disposed in the vacancy of the lead frame. The invention also discloses a method for manufacturing a package structure made of the combination of a metallic substrate and a lead frame. | 2013-04-18 |
20130093070 | SEMICONDUCTOR DEVICE CAPABLE OF SWITCHING OPERATION MODES - A semiconductor device includes a substrate, a first pad that is formed above the substrate, a second pad that is formed above the substrate, an external terminal that is connected with the second pad, and a circuit that judges whether or not the first pad is connected with the external terminal, wherein a distance between the first pad and a side of the substrate opposed to the external terminal is different from a distance between the second pad and the side. | 2013-04-18 |
20130093071 | OPTICAL MODULE WITH A LENS ENCAPSULATED WITHIN SEALANT AND METHOD FOR MANUFACTURING THE SAME - A method to manufacture an optical module is disclosed, wherein the optical module has an optically active device on a lead frame and a lens co-molded with the active device and the lead frame by a transparent resin as positioning the lens with respect to the lead frame. The molding die of the present invention has a positioning pin to support the lens during the molding. Because the lead frame is aligned with the molding die, the precise alignment between the active device on the lead frame and the lens is not spoiled during the molding. | 2013-04-18 |
20130093072 | LEADFRAME PAD DESIGN WITH ENHANCED ROBUSTNESS TO DIE CRACK FAILURE - A leadframe includes a die pad and a protective wall surrounding the die pad. A semiconductor die is situated on the die pad. Indentations are formed on the four inner corners of the protective wall adjacent the corners of the semiconductor die. | 2013-04-18 |
20130093073 | HIGH THERMAL PERFORMANCE 3D PACKAGE ON PACKAGE STRUCTURE - A package on package (PoP) structure is disclosed. The PoP structure includes a top package and a bottom package disposed thereunder. The top package includes a first substrate and a first die mounted onto the first substrate. The first substrate has a thermal conductivity which is more than 70 W/(m×K). The bottom package includes a second substrate and a second die mounted onto the second substrate. An upper surface of the second die is in thermal contact with a lower surface of the first substrate. | 2013-04-18 |
20130093074 | MULTI-DIE INTEGRATED CIRCUIT STRUCTURE WITH HEAT SINK - An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die. | 2013-04-18 |
20130093075 | Semiconductor Device Package and Method - An embodiment is a structure. The structure comprises a substrate, a chip, and a reinforcement component. The substrate has a first surface, and the first surface comprises depressions. The chip is over and attached to the first surface of the substrate. The reinforcement component is over a first area of the first surface of the substrate. The first area is not under the chip. The reinforcement component has a portion disposed in at least some of the depressions in the first area. | 2013-04-18 |
20130093076 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package. | 2013-04-18 |
20130093077 | POST-PASSIVATION INTERCONNECT STRUCTURE - A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region. | 2013-04-18 |
20130093078 | Process for Forming Package-on-Package Structures - A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material. | 2013-04-18 |
20130093079 | Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. | 2013-04-18 |
20130093080 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes. | 2013-04-18 |
20130093081 | IC CHIP PACKAGE AND CHIP-ON-GLASS STRUCTURE USING THE SAME - An IC chip package and a chip-on-glass structure using the same are provided. The IC chip package includes an IC chip having a circuit surface, and plural copper (Cu) bumps formed on the circuit surface. Moreover, a non-conductive film (NCF) could be formed on the circuit surface to cover the Cu bumps. The chip-on-glass structure includes a glass substrate, plural electrodes such as aluminum (Al) electrodes formed on the glass substrate, and a conductive film formed on the electrodes. The conductive film contains a number of conductive particles. When the IC chip package is coupled to the glass substrate, the Cu bumps can be coupled to the corresponding electrodes via conductive particles. | 2013-04-18 |
20130093082 | SEMICONDUCTOR DEVICE, ELECTRODE MEMBER, AND ELECTRODE MEMBER FABRICATION METHOD - A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved. | 2013-04-18 |
20130093083 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted. | 2013-04-18 |
20130093084 | Wafer-Level Chip Scale Package with Re-Workable Underfill - A package includes a printed circuit board (PCB), and a die bonded to the PCB through solder balls. A re-workable underfill is dispensed in a region between the PCB and the die. | 2013-04-18 |
20130093085 | DUAL INTERLOCK HEATSINK ASSEMBLY FOR ENHANCED CAVITY PBGA PACKAGES, AND METHOD OF MANUFACTURE - A semiconductor package is provided, including a laminate substrate with an aperture sized to receive a semiconductor die. Through-holes in the substrate are filled with a thermally conductive adhesive. A first heat spreader is attached to the by the adhesive, and a semiconductor die is positioned in the aperture with a back face in thermal contact with the heat spreader. Wire bonds couple the die to electrical traces on the substrate. A second heat spreader is attached by the adhesive to the substrate over the die, directly opposite the first heat spreader. A portion of the second heat spreader is encapsulated in molding compound. Openings in the second heat spreader admits molding compound to fill the space around the die between the heat spreaders. Heat is transmitted from the die to the first spreader, and thence, via the through-holes and conductive paste, to the second heat spreader. | 2013-04-18 |
20130093086 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased. | 2013-04-18 |
20130093087 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds. | 2013-04-18 |
20130093088 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds. | 2013-04-18 |
20130093089 | Interconnect Structure With An Electromigration and Stress Migration Enhancement Liner - An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material. | 2013-04-18 |
20130093090 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C. | 2013-04-18 |
20130093091 | Three-Dimensional Vertical Interconnecting Structure and Manufacturing Method Thereof - The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring. The three-dimensional vertically interconnected structure of the present invention enhances the strength of the electric interconnection and the adhesion between adjacent layers of chips, and in the meantime the disclosed fabricating method simplifies the process difficulty and therefore improves the yield. | 2013-04-18 |
20130093092 | ELECTRONIC DEVICE AND METHOD FOR PRODUCING SAME - An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench being filled with the interconnection pattern; a metal film on a surface of the interconnection pattern, the metal film having a higher elastic modulus than Cu; a second insulating film on the first insulating film; and a via plug composed of Cu and arranged in the second insulating film, the via plug being in contact with the metal film. | 2013-04-18 |
20130093093 | SEMICONDUCTOR DEVICE WITH DAMASCENE BIT LINE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (SNC) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap. | 2013-04-18 |
20130093094 | Method and Apparatus for Die Assembly - Methods and apparatus for die assembly. A method includes forming a trench extending from an active surface of a semiconductor substrate comprising a plurality of integrated circuit dies having connector terminals extending from the active surface, the trench extending into, but not through, the semiconductor substrate; forming a protective layer overlying the active surface of the semiconductor substrate and the trench, and covering the lower portion of the connector terminals; opening a pre-dicing opening in the protective layer and within the trench; applying a tape over the active surface of the semiconductor wafer, the protective layer and the connector terminals; and performing an operation on a backside of the semiconductor substrate to remove material until the pre-dicing opening is exposed on the backside of the semiconductor wafer. An apparatus includes a semiconductor substrate with integrated circuits and a protective layer surrounding connector terminals of integrated circuits. | 2013-04-18 |
20130093095 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor having a semiconductor substrate, a first electrode formed on one surface of the semiconductor substrate, and a second electrode formed on an opposite surface of the semiconductor substrate. A first conductive member is in contact with the first electrode. A second conductive member is in contact with the second electrode. A third conductive member is in contact with the second conductive member and extends along the first conductive member. An insulating member provides insulation between the first conductive member and the third conductive member. The third conductive member is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member. The semiconductor device is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member. | 2013-04-18 |
20130093096 | SEMICONDUCTOR DEVICE - A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern. | 2013-04-18 |
20130093097 | Package-On-Package (PoP) Structure and Method - A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL. | 2013-04-18 |
20130093098 | THROUGH SUBSTRATE VIA STRUCTURES AND METHODS OF FORMING THE SAME - The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill. | 2013-04-18 |
20130093099 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having first and second chips stacked upon each other includes first, second and third through vias positioned on a same vertical lines in the first and second chips and formed through the first and second chips. A first input/output circuit connected with the second through via of the first chip. A second input/output circuit connected with the second through via of the second chip. The second through via of the second chip is connected with the first through via of the first chip. | 2013-04-18 |
20130093100 | Semiconductor Device and Method of Forming Conductive Pillar Having an Expanded Base - A semiconductor device has a first semiconductor die and conductive vias in the first semiconductor die. The conductive vias can be formed by extending the vias partially through a first surface of the first semiconductor die. A portion of a second surface of the first semiconductor die is removed to expose the conductive vias. A plurality of conductive pillars is formed over the first surface the first semiconductor die. The conductive pillars include an expanded base electrically connected to the conductive vias. A width of the expanded base of the conductive pillars is greater than a width of a body of the conductive pillars. A conductive layer is formed over a second surface of the first semiconductor die. The conductive layer is electrically connected to the conductive vias. A second semiconductor die is mounted to the first semiconductor die with a second conductive pillar having an expanded base. | 2013-04-18 |
20130093101 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device is provided. The semiconductor device includes a package substrate; a first semiconductor chip mounted on the package substrate and adapted to include a plurality of first bonding pads arranged in a first order on an upper surface; a second semiconductor chip arranged on the first semiconductor chip and adapted to include a plurality of second bonding pads arranged in the first order on an upper surface; and first bonding wires configured to connect each of the plurality of first bonding pads and the plurality of second bonding pads. | 2013-04-18 |
20130093102 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME - Semiconductor packages are provided. The semiconductor package includes a package substrate. A semiconductor chip structure is mounted on the package substrate and includes a plurality of semiconductor chips. A molding member covers the semiconductor chip structure and the package substrate. The plurality of semiconductor chips are vertically stacked and stepped toward one direction. A thickness of an uppermost semiconductor chip of the plurality of semiconductor chips is greater than an average thickness of the other semiconductor chips thereunder. Related methods are also provided. | 2013-04-18 |
20130093103 | Layered Semiconductor Package - Provided is a layered semiconductor package. The present invention comprises: a substrate having a first connection pad and a second connection pad on the upper surface thereof; a first cascade chip-layered body mounted on the substrate in which a plurality of first semiconductor chips are layered in a stepped form so as to expose a first bonding pad to the outside; at least one spacer layered on the upper surface of the uppermost semiconductor chip of the first chip-layered body so as to expose a bonding pad of the uppermost semiconductor chip; a second cascade chip-layered body mounted on the upper surface of the spacer in which a plurality of second semiconductor chips are layered in a stepped form so as to expose a second bonding pad to the outside; a first conductive wire for electrically connecting the first bonding pad of the first semiconductor chip and the first connection pad of the substrate; and a second conductive wire for electrically connecting the second bonding pad of the second semiconductor chip and the second connection pad of the substrate. | 2013-04-18 |
20130093104 | BOND PAD STRUCTURE AND FABRICATING METHOD THEREOF - A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening. | 2013-04-18 |
20130093105 | SEALING FILM AND A SEMICONDUCTOR DEVICE USING THE SAME - A method for sealing electrodes on a semiconductor device using a sealing film which includes a resin layer having a flow within the range of 150 to 1800 μm at 80° C., or having a resin layer with a viscosity within the range of 10,000 to 100,000 Pa·s in a B-stage state at 50 to 100° C. in thermosetting viscoelasticity measurement, and containing: (A) both (a1) a high-molecular-weight component including crosslinking functional groups and having a weight-average molecular weight of 100,000 or more and a Tg within the range of −50 to 50° C. and (a2) a thermosetting component including an epoxy resin as a main component, (B) a filler having an average particle size within the range of 1 to 30 μm, and (C) a colorant. | 2013-04-18 |
20130093106 | DEVICE FOR GASSING LIQUIDS - The invention relates to a device for gassing liquids, in particular for aerating sewage and the like, comprising a lower housing element ( | 2013-04-18 |
20130093107 | Fish and Game Washer - It is designed to wash and clean meat. When meat is put in a 5 gallon bucket and water source connected and turned on. Air is sucked in to mix with water. This makes the meat float up from the bottom and begin to toss and tumble, which takes loose scales, feathers, blood and debris over the top of bucket. This leaves the meat clean in 5 to 15 minutes, depending on the load. Therefore you don't have to mess up kitchen sink. It is good for washing other things, including fruits in vegetables. | 2013-04-18 |
20130093108 | APPARATUS FOR DISTRIBUTING A FRAGRANCE USING A FAN - This application is directed to a fragrance dispenser attachably connected to a fan comprising: a housing having openings defined in the housing; a fragrance reservoir included in the housing for receiving a fragrance medium containing a fragrance; a cover operably associated with the opening for restricting airflow into the fragrance reservoir; and, a cover actuator operably connected to the cover having an open position allowing airflow into and out of the fragrance reservoir for dispensing a fragrance and a closed position for restricting airflow into and out of the fragrance reservoir. | 2013-04-18 |
20130093109 | Retroreflective Sheet Structure - A retroreflective sheet structure ( | 2013-04-18 |
20130093110 | Vesicle-Containing Composition And Production Method Thereof - To provide a vesicle-containing composition wherein a perfume component is stably incorporated in the vesicle bilayer membrane composed of a silicone surfactant and to provide a simple production method of the vesicle-containing composition wherein a perfume component is stably incorporated. A vesicle-containing composition comprising; (A) a perfume, (B) a silicone oil, (C) a silicone surfactant, (D) one or more selected from the group consisting of ethanol, propylene glycol, dipropylene glycol, and 1,3-butylene glycol, and (E) water; wherein the (C) silicone surfactant forms vesicles, and the (A) perfume and the (B) silicone oil are present in the vesicle bilayer membrane. | 2013-04-18 |
20130093111 | Apparatus and Method for the Production of Particles - An apparatus for the production of particles of a substance by dynamic precipitation of the substance from a fluid solution containing the substance dissolved in a fluid solvent. The apparatus is characterized by comprising A) a first main flow line FL | 2013-04-18 |
20130093112 | PROCESS FOR PRODUCING A PRODUCT - A method for production of a molded article from a base substance in a device for mixing of the base substance with a solvent is provided. The method includes mixing a base substance to produce a molding solution with the solvent and at least partially removing the solvent from the mixture; and feeding the molding solution to a device for further processing of a product and diluting the molding solution before further processing. In embodiments, the diluent is introduced to the device before a discharge device and/or in the discharge device. | 2013-04-18 |
20130093113 | IMPRINT APPARATUS AND ARTICLE MANUFACTURING METHOD USING SAME - An imprint apparatus transfers a pattern formed on a mold to a resin on a substrate. The imprint apparatus includes a shape correction mechanism configured to apply a force to the mold to thereby deform a pattern region formed on the mold; a heating mechanism configured to heat a substrate-side pattern region formed on the substrate to thereby deform the substrate-side pattern region; and a control unit configured to obtain information regarding a difference between shapes of the pattern region formed on the mold and the substrate-side pattern region and control the shape correction mechanism and the wafer heating mechanism so as to reduce the difference between the shapes of the pattern region formed on the mold and the substrate-side pattern region based on the obtained information. | 2013-04-18 |
20130093114 | BLEND OF PLASTICS WITH WOOD PARTICLES - A blend of plastics with wood particles. | 2013-04-18 |
20130093115 | METHOD OF MAKING A FLOOR TILE WITH OVERMOLDED PADS - A plastic floor tile is formed by molding a body of a first polymer compound and overmolding features onto the body from a second polymer compound. The compounds may be different from each other in hardness and/or color. The overmolded features may include raised pads on the upper surface of the tile. The pads on the upper surface may be injection-molded from the lower surface through through-holes, which are smaller in area than the area of the pads. | 2013-04-18 |
20130093116 | METHOD OF MAKING A FLOOR TILE WITH ELASTOMER JACKETED SUPPORT MEMBERS - A modular plastic floor tile is formed by molding a body of a first polymer compound and overmolding features onto the body from a second polymer compound. The compounds may be different from each other in hardness and/or color. The overmolded features may include skins on the sides and bottoms of support member cores disposed below the tile lower surface. | 2013-04-18 |
20130093117 | METHOD FOR EMBOSSING A TIP COVER OF A CIGARETTE TIP | 2013-04-18 |
20130093118 | USE OF THERMOPLASTIC COMPOSITION COMPRISING POLYETHER-BLOCK COPOLYAMIDES AS ADDITIVE - The present invention discloses the use in rotomolding or slush molding applications of a composition comprising a polyolefin, a processing aid and optionally a UV-stabilizer. | 2013-04-18 |
20130093119 | PROCESSES FOR PRODUCING THERMOSTABLE POLYHYDROXYALKANOATE AND PRODUCTS PRODUCED THEREFROM - Compositions comprising polyhydroxyalkanoate with improved thermostability are disclosed. Processes for producing thermostable polyhydroxyalkanoates with acids having a pKa of between 3-10 are further disclosed, as well as uses of such thermostable polyhydroxyalkanoates. | 2013-04-18 |
20130093120 | MOLDING SURFACE-HEATING APPARATUS AND MOLDING METHOD - In a molding surface-heating apparatus, eddy current is generated in a mold by an electromagnetic induction, and a molding surface of the mold is heated by the eddy current. The molding surface-heating apparatus is provided with a conductive member and a coil. The conductive member is electrically connected to and disconnected from a surface of the mold. The coil supplies a magnetic flux to the conductive member and the mold such that the magnetic flux generates the eddy current that crosses the conductive member and the mold and the eddy current passes through the molding surface. | 2013-04-18 |
20130093121 | PRODUCTION METHOD FOR ANISOTROPIC BONDED MAGNET AND PRODUCTION APPARATUS FOR SAME - A method for production of an anisotropic bonded magnet includes: aligning magnetic pole bodies which include an even number of permanent magnets arranged uniformly around an outer periphery of an annular cavity filled with magnetic raw material, aligning magnetic fields to cause rare-earth anisotropic magnet powder to be semi-radially aligned; compressively molding the semi-radially aligned magnet raw material to obtain an annular compact; discharging the compact from the annular cavity; demagnetizing causing the aligning magnetic pole bodies to relatively move only in circumferential direction with respect to the compact after the molding step thereby to apply demagnetization magnetic fields to the compact. The demagnetization magnetic fields are applied from the aligning magnetic pole bodies with opposite poles to those during the alignment step, and the demagnetization magnetic fields are in directions for cancelling the magnetization of the compact caused by the aligning magnetic fields. | 2013-04-18 |
20130093122 | LIQUID SILANE-BASED COMPOSITIONS AND METHODS FOR PRODUCING SILICON-BASED MATERIALS - Described herein are synthesis schemes and methods for producing silicon based nanostructures and materials, including compositions and methods for synthesis of silicon-based nanowires and composites from three-component and four-component liquid silane/polymer inks. Materials and methods for producing silicon based micro and nanofibers that can be used in a variety of applications including material composites, electronic devices, sensors, photodetectors, batteries, ultracapacitors, and photosensitive substrates, and the like. | 2013-04-18 |
20130093123 | CASE FOR ENCLOSING A PERSONAL ELECTRONIC DEVICE MANUFACTURED FROM A POLYURETHANE OR SILICON COMPOUND AND METHOD FOR MAKING SAME - A method for manufacturing a case with a cavity for retaining a personal electronic device is disclosed. The case comprises a thin film outer layer and a soft inner layer. The method employs a transparent mold that allows a reactive compound to be cured in the mold. The thin film outer layer may be preformed and placed in the mold or it may be formed in the mold. The reactive compound is placed within the thin film inner layer and then the top portion of the mold is inserted to form the cavity. Ultraviolet light may be transmitted through the mold and used to cure the reactive compound. | 2013-04-18 |
20130093124 | UV Curing Method And An Assembly Therefor - It is presented a method for producing a cured polymer structure from a polymer compound which is UV curable and partly UV transparent. The method comprises injecting the polymer compound into a mould ( | 2013-04-18 |
20130093125 | IN-MOLD LABELING SYSTEMS WITH POLYMERIC LABEL RECEPTOR AND IN-MOLD LABELING METHODS THEREWITH - An in-mold labeling system includes a molding apparatus having a first mold half and a second mold half that opposes the first mold half, the mold halves defining at least one mold cavity contained within a cavity wall. The in-mold labeling system further comprises a polymeric label receptor fixed to at least a portion of the cavity wall of the at least one mold cavity. The polymeric label receptor has a tacky contact face facing the inside of the at least one mold cavity when the molding apparatus is in the closed position. During a molding process, the tacky contact face of the polymeric label receptor receives a mold-side face of a label. The label is held in position against the tacky contact face during the molding process by surface tension between the mold-side face of the label and the tacky contact face of the polymeric label receptor. | 2013-04-18 |
20130093126 | MOLD MADE OF A COMPOSITE MATERIAL AND PROCESS EMPLOYING THIS MOLD - A mold for manufacturing products made of composite materials, which comprises at least one functional portion made of a composite material joined to at least one interface made of a composite material which projects at least partially around the functional portion, said mold being provided with one or more mechanic fastening devices for the coupling with at least another mold. | 2013-04-18 |
20130093127 | DEVICE FOR GENERATING A HOLLOW PLASTIC PROFILE - A device for generating a hollow plastic profile, in particular a plastic tube, having an air guidance system for interior cooling of the tube, wherein said device allows for a more simple design, improved process properties, and better tube quality. The device according to the invention comprises an extrusion die ( | 2013-04-18 |
20130093128 | METHODS OF PRODUCING ANODES FOR SOLID OXIDE FUEL CELLS - Disclosed are methods of producing Ni/YSZ porous anode bodies for solid oxide fuel cells. According to the methods, a small amount of a nickel compound or salt is used as a pore former. Upon heating in air, the nickel compound or salt is decomposed into nickel oxide and releases gases, resulting in volume shrinkage. Therefore, Ni/YSZ porous bodies having a uniform pore size and reduction products thereof can be produced in an economical manner. | 2013-04-18 |
20130093129 | METHOD OF FORMING A SOLID OXIDE FUEL CELL - A method for forming a solid oxide fuel cell (SOFC) article includes forming a SOFC unit cell in a single, free-sintering process, wherein the SOFC unit cell is made of an electrolyte layer, an interconnect layer, a first electrode layer disposed between the electrolyte layer and the interconnect layer. The electrolyte layer of the SOFC unit cell is in compression after forming. | 2013-04-18 |
20130093130 | METHOD FOR PRODUCING CERAMIC LAMINATE - The present invention provides a method for producing a ceramic laminate capable of preventing coming-off of materials and warpage of the ceramic laminate by a heat treatment at a relatively-low temperature, and a ceramic laminate produced by the production method. Disclosed is a method for producing a ceramic laminate having a layer structure in which two or more layers are laminated, including: a step of producing a laminate including a first layer and a second layer, the first layer containing a solid electrolyte and the second layer containing at least composite particles obtained by covering an electrode active material with the solid electrolyte; and a step of performing a heat treatment on the laminate including the first and second layers at a temperature of 500° C. or more and less than 700° C. | 2013-04-18 |
20130093131 | SINTERED COMPOSITE SLIDING PART AND PRODUCTION METHOD THEREFOR - A process for producing a sintered composite sliding part having an outer member made of an Fe-based wear resistant sintered member in which a hard phase is dispersed in a matrix at 15 to 70% by volume and an inner member made of a stainless ingot steel. The matrix is made of an Fe-based alloy including 11 to 35% by mass of Cr, and the hard phase is formed by precipitating and dispersing at least one selected from the group consisting of intermetallic compounds, metallic silicides, metallic carbides, metallic borides, and metallic nitrides in an alloy matrix made of at least one selected from the group consisting of Fe, Ni, Cr, and Co. The outer member is formed with a hole, the inner member is closely fitted into the hole, and the outer member and the inner member are diffusion bonded together. | 2013-04-18 |
20130093132 | GAS SPRING ASSEMBLY AND METHOD OF ASSEMBLING SAME - A gas spring assembly includes an end member, a piston assembly and a flexible sleeve secured therebetween. An end closure secures an end of the flexible sleeve to the piston assembly. A connector fitting connects the end closure to a support post of the piston assembly. The connector fitting includes a fitting passage and a first annular groove. A jounce bumper assembly is supported on the connector fitting. The jounce bumper assembly includes a bumper body and a bumper mount. The bumper mount includes securement pin having a second annular groove. A retaining member is received within the first and second annular grooves such that the jounce bumper assembly can freely rotate relative to the connector fitting while substantially restricting axial displacement of the jounce bumper assembly relative to the piston assembly during such rotation. | 2013-04-18 |
20130093133 | Piping Slider - A piping slider includes: a cavity in which a pipe-shaped part of an adherend is accommodatable; a slit that intercommunicates the cavity with an outside; a connector to which a belt is connected; a grip member in which the cavity and the slit are provided; a key member insertable into the slit; and a lock mechanism that restricts a displacement between the key member and the grip member when the key member is inserted into the slit, where an opening width of the slit is greater than a minimum width of the pipe-shaped part, and an opening width when the key member is inserted to the slit is smaller than the minimum width of the pipe-shaped part. | 2013-04-18 |
20130093134 | SHEET STORAGE APPARATUS AND IMAGE FORMATION SYSTEM USING THE APPARATUS - To provide a sheet storage apparatus for enabling sheets that are carried out of an image formation apparatus or the like on the upstream side to be loaded and stored in a predetermined position with a correct posture neatly at high speed, a sheet discharge roller and a reverse roller spaced a distance are disposed in a sheet discharge outlet and a tray, a kick member is provided to be swingable in a vertical direction passing a sheet discharge path of a sheet discharged from the sheet discharge outlet, and a posture of the kick member is controlled by shift means. The shift means controls the kick member among a waiting posture retracted upward from the sheet discharge path, an engagement posture for imposing a load on the sheet to engage, and an actuation posture dropping onto the tray together with the sheet. | 2013-04-18 |
20130093135 | SLIDING TANDEM MEDIA FEEDER IN A PRINTER - In a tandem media supply, two vertical stacks of media sheets are stored. The first stack is positioned on a lift plate that rises as top sheets are removed from the stack of media. When the first stack is exhausted, the second stack is moved by an actuator towards a position where the lift plate was loaded with the first stack of media sheets. Movement of the second stack displaces a biased gate to decouple the lift plate from a drive member that elevated the lift plate. The lift plate drops under the effect of gravity to a position where the second stack of media sheets moves onto the lift plate. Once the second stack is on the lift plate, a biasing force returns the biased gate to a position that enables the drive member to elevate the lift plate. | 2013-04-18 |
20130093136 | JAM SENSING AT DOCUMENT FEEDING STATION - A method for preventing damage to a document by a document transport apparatus provides a member for receiving the document as a stack of sheets to be serial fed to a feeding station. At least two spaced-apart microphones are disposed at the feeding station and responsive to audio to produce signals representing audio energy received by each microphone respectively. The energy received from each microphone is compared to determine if it is ambient noise or if it indicates that two attached sheets are being fed or a single sheet is being damaged. The document transport apparatus is shut off to prevent damage to documents when it has been determined that two attached sheets are being fed or that a single sheet is being damaged. | 2013-04-18 |
20130093137 | Novelty device for communication between a human being and universal consciousness - Novelty device for communication between a human being and universal consciousness (Universal Mind) is a mechanical device with a Central body, suspended on several substantially upright supports, so that the Central body can move (swing) in horizontal plane. The upright supports are attached to a stationary frame. A diagram is attached to the same stationary frame. The diagram displays symbols, numbers, pictures and the like. A clear transparent surface with a colored dot indicator is attached to the moving Central body. In communication, the user holds the frame in his or her hands, observes the movements of the dot indicator over the diagram and interprets the dialog. | 2013-04-18 |
20130093138 | APPARATUSES FOR USE AS TARGETS AND METHODS OF MAKING SAME - A target comprising an outer shell and a volume of closed cell foam within the outer shell. In a preferred embodiment, the target is a towable target for being towed behind a powered vehicle. | 2013-04-18 |
20130093139 | TARGET GAME AND METHOD OF PLAYING A TARGET GAME - A target game including at least one target and at least one projectile. The at least one target is constructed of a flexible and self-supporting material. The at least one target is able to be configured in a first orientation and a second orientation. In the first orientation, the at least one target is generally planar. In the second orientation, the at least one target is generally conical. | 2013-04-18 |
20130093140 | Soft Skin Metal Seal and Technique of Manufacture - A seal assembly between a wellhead housing having a bore and a casing hanger, has an inner seal leg for sealing against hanger and an outer seal leg for sealing against housing. An extension extends downward from outer seal leg and is connected to a nose ring having a downward facing shoulder that rests on the hanger shoulder to provide a reaction point for setting operations. A sealing surface on the seal legs is heat treated to obtain a lower localized yield strength to provide improved sealing while maintaining mechanical load capability. | 2013-04-18 |
20130093141 | Weather Strip Seal for an Automotive Vehicle, and its Manufacturing Method - The invention provides a weather strip seal for an automotive vehicle which is provided for sealing between a first structure and a second structure made of a vehicle framework having a flange protruding from an adjacent framework surface, and to a method for manufacturing such a strip seal. The weather strip seal includes a clamping means for clamping on the flange comprising an outer clamping portion having a first branch and a second branch and an inner clamping portion incorporating separate gripping clips mounted along the length of and against said outer clamping portion by an outer part of each clip, and in contact with the flange by inner gripping means of each clip, a first sealing portion sealingly presses against said first structure and which extends from said first branch, and a second sealing portion presses against said adjacent framework surface and extending on said second branch. | 2013-04-18 |
20130093142 | Tool attachment - In a tool attachment, for fastening to an handheld machine tool equipped with a tool holding fixture, having an output shaft and a base body, which forms an inner cavity and on whose outer circumference an axially displaceable locking sleeve is situated, for releasing at least one associated locking element against a spring force of a spring element, which has a clamping ring, in the inner cavity, a anti-rotation locking unit is configured for the rotationally locked fastening of the base body to a fastening unit associated with the handheld machine tool, the anti-rotation locking unit and the fastening unit having complementary geometric forms, which are configured to engage with each other for the detachable rotationally locked fastening of the base body on the fastening unit; and the at least one associated locking element being situated in the vicinity of the anti-rotation locking unit. | 2013-04-18 |
20130093143 | Method and Device for Gripping a Cable - A device for gripping a cable includes a device body, one or more gripping elements, and a gripping element housing configured to support the one or more gripping elements. The gripping element housing is rotatably coupled to the device body such that rotation of the gripping element housing relative to the device body about a longitudinal axis causes the one or more gripping elements to move radially relative to the longitudinal axis. The gripping elements may be configured such that they do not rotate relative to the gripping element housing. The gripping elements may also be configured such that they move only in a radial direction relative to the longitudinal axis, or alternatively such that they move both radially and longitudinally relative to the longitudinal axis. | 2013-04-18 |
20130093144 | LOCKING CHUCK - A chuck including a body with a nose section defining an axial bore formed therein, a plurality of jaws movably disposed with respect to the body, and a sleeve rotatably mounted about the body so that rotation of the sleeve moves the jaws relative to the axial bore. A bearing has a first race, a second race, and at least one bearing element disposed therebetween, one of the first race and the second race defining a ratchet and the other defining a pawl biased toward the ratchet. A biasing element is disposed between the pawl and the sleeve. The biasing element exerts a biasing force on the pawl toward the ratchet and the ratchet and the pawl prevent the second race from rotating in the opening direction with respect to the first race when engaged. | 2013-04-18 |
20130093145 | ELECTROSTATIC CHUCK - An electrostatic chuck comprises a ceramic dielectric body having an electrode formed on a surface of the ceramic dielectric body; a ceramic substrate supporting the ceramic dielectric body; and a first bonding agent bonding the ceramic dielectric body to the ceramic substrate. The first bonding agent has a first major agent including an organic material, a first amorphous filler including an inorganic material, and a first spherical filler including an inorganic material. The first amorphous filler and the first spherical filler are dispersion-compounded in the first major agent. The first major agent, the first amorphous filler, and the first spherical filler are made of an electrically insulating material. An average diameter of the first spherical filler is greater than a maximum value of a minor axis of all of the first amorphous filler. A thickness of the first bonding agent is equal to or greater than the average diameter of the first spherical filler. | 2013-04-18 |