16th week of 2013 patent applcation highlights part 12 |
Patent application number | Title | Published |
20130092946 | TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - The present invention provides a TFT-LCD array substrate having a gate-line metal layer, a data-line metal layer crossing the gate-line metal layer and a plurality of layers covering a periphery of the gate-line metal layer and the data-line metal layer; the gate-line metal layer has first gate lines and second gate lines parallel and alternately arranged, the date-line metal layer has first data lines and second data lines parallel and alternately arranged; the first gate line and the second gate line are electrically connected; the first data line and the second data line are electrically connected. The present invention further provides a manufacturing method of the TFT-LCD array substrate. Implementing the TFT-LCD array substrate and the manufacturing method can reduce the occurrence of line-broken in the active array of TFT-LCD, increase the aperture ratio of the product and enhance yield rate of the products. | 2013-04-18 |
20130092947 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING - In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion. | 2013-04-18 |
20130092948 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - The semiconductor device having flip chip structure includes: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the insulating substrate or disposed so as to pass through the insulating substrate; a semiconductor chip disposed in flip chip configuration on the insulating substrate and comprising a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a surface of the semiconductor substrate, and a drain pad electrode disposed on a back side surface of the semiconductor substrate; agate connector disposed on the gate pad electrode; and a source connector disposed on the source pad electrode. The gate connector, the gate pad electrode and the signal wiring electrode are bonded, and the source connector, the source pad electrode and the power wiring electrode are bonded, by using solid phase diffusion bonding. | 2013-04-18 |
20130092949 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×10 | 2013-04-18 |
20130092950 | NITRIDE SEMICONDUCTOR GROWTH SUBSTRATE AND MANUFACTURING METHOD OF THE SAME, NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE AND NITRIDE SEMICONDUCTOR ELEMENT - A nitride semiconductor growth substrate includes a principal surface including a C-plane of a sapphire substrate, and a convex portion that is formed on the principal surface, has a cone or pyramid shape or a truncated cone or pyramid shape, is disposed to form a lattice pattern in a top view thereof, and includes a side surface inclined at an angle of less than 90 degrees relative to the principal surface. The convex portion has a height of 0.5 to 3 μm from the principal surface. A distance between adjacent ones of the convex portion is 1 to 6 μm. The side surface of the convex portion has a surface roughness (RMS) of not more than 10 nm. | 2013-04-18 |
20130092951 | GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate. | 2013-04-18 |
20130092952 | SEMICONDUCTOR DEVICE - A transistor which includes an electron transit layer and an electron supply layer which are stacked in a thickness direction of a substrate; an electron transit layer formed over the substrate in parallel to the electron transit layer and the electron supply layer; an anode electrode which forms a Schottky junction with the electron transit layer; and a cathode electrode which forms an ohmic junction with the electron transit layer are provided. The anode electrode is connected to a source of the transistor, and the cathode electrode is connected to a drain of the transistor. | 2013-04-18 |
20130092953 | EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE - Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a plurality of lamination units being continuously laminated. The lamination unit includes: a composition modulation layer formed of a first and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein; a termination layer formed on an uppermost portion of the composition modulation layer, the termination layer acting to maintain the compressive strain existing in the composition modulation layer; and a strain reinforcing layer formed on the termination layer, the strain reinforcing layer acting to enhance the compressive strain existing in the composition modulation layer. | 2013-04-18 |
20130092954 | Strained Silicon Channel Semiconductor Structure and Method of Making the Same - A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased. | 2013-04-18 |
20130092955 | LIGHT EMITTING DIODE AND FABRICATING METHOD THEREOF - A light-emitting diode (LED) and fabricating method thereof. The method includes: providing a first substrate and forming an epitaxial portion on the first substrate; forming at least one reflection layer on the epitaxial portion; forming a metal barrier portion on the reflection layer; etching the epitaxial portion and the barrier portion by a first etching process, so as to form a plurality of epitaxial layers and a plurality of metal barrier layers, an etch channel is formed between adjacent epitaxial layers, and each metal barrier layer enwraps a corresponding reflection layer and covers all of a surface of a corresponding epitaxial layer; forming a first bonding layer on the metal barrier layer; and forming a second substrate on the first bonding layer and removing the first substrate. | 2013-04-18 |
20130092956 | SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - Single crystal substrates are made of silicon carbide, and each have a first front-side surface and a first backside surface opposite to each other. A support substrate has a second front-side surface and a second backside surface opposite to each other. A connection layer has silicon carbide as a main component, and lies between the single crystal substrates and the support substrate for connecting each of the first backside surfaces and the second front-side surface such that each of the first backside surfaces faces the second front-side surface. | 2013-04-18 |
20130092957 | SELF-ALIGNED SILICIDATION FOR REPLACEMENT GATE PROCESS - A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer. | 2013-04-18 |
20130092958 | NORMALLY-OFF III-NITRIDE METAL-2DEG TUNNEL JUNCTION FIELD-EFFECT TRANSISTORS - Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures. | 2013-04-18 |
20130092959 | LIGHT RECEIVING AND EMITTING DEVICE - A light emitting device includes: a light emitting unit and a light receiving unit which are provided on a same substrate, wherein the light emitting unit includes an active layer sandwiched between a first clad layer and a second clad layer, a first electrode electrically connected to the first clad layer, and a second electrode electrically connected to the second clad layer. | 2013-04-18 |
20130092960 | Multi-Die LED Package - A light-emitting device comprising (a) a submount having front and back sides and including a ceramic layer; (b) an array of light-emitting diodes (LEDs) on the front side; and (c) a lens overmolded on the submount and covering the LED array. In some embodiments, the submount comprises at least two electrically-conductive contact pads on the front side, and each LED in the array is secured with respect to one of the contact pads. | 2013-04-18 |
20130092961 | LIGHT EMITTING DEVICE MODULE - According to example embodiments, a light emitting device (LED) module includes a substrate, a LED on the substrate, a first reflector on the substrate, and a phosphor structure contacting the first reflector. The first reflector may surround the LED from a plan view. The first reflector may have a width at a middle portion of the reflector that is smaller than a width at a bottom portion of the reflector. The LED module may obtain a desired view angle depending on various applications by adjusting a height of the first reflector and/or a difference between the height of first reflector and a height of a phosphor structure. | 2013-04-18 |
20130092962 | LIGHT EMITTING DEVICE (LED), MANUFACTURING METHOD THEREOF, AND LED MODULE USING THE SAME - A light emitting device (LED), a manufacturing method thereof, and an LED module using the same. The LED may include a first semiconductor layer, an active layer, and a second semiconductor layer formed sequentially on a light-transmitting substrate, a first electrode formed in a region exposed by removing a part of the first semiconductor layer, a second electrode formed on the second semiconductor layer, a passivation layer formed on the first electrode and the second electrode to expose a region of the first electrode and a region of the second electrode, a first bump formed in a first region including the first electrode exposed through the passivation layer, and extended to another region of the second electrode on which the passivation layer is formed, and a second bump formed in a second region including the second electrode exposed through the passivation layer. | 2013-04-18 |
20130092963 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - A load, a transistor which controls a current value supplied to the load, a capacitor, a power supply line, and first to third switches are provided. After a threshold voltage of the transistor is held by the capacitor, a potential in accordance with a video signal is inputted and a voltage that is the sum of the threshold voltage and the potential is held. Accordingly, variation in current value caused by variation in threshold voltage of the transistor can be suppressed. Therefore, a desired current can be supplied to a load such as a light emitting element. In addition, a display device with a high duty ratio can be provided by changing a potential of the power supply line. | 2013-04-18 |
20130092964 | HIGHLY RELIABLE PHOTOLUMINESCENT MATERIALS HAVING A THICK AND UNIFORM TITANIUM DIOXIDE COATING - Described herein are coated photoluminescent materials and methods for preparing such coated photoluminescent materials. More particularly, provided herein are phosphors coated with titanium dioxide, methods for preparing phosphors coated with titanium dioxide, and solid-state light emitting devices which include phosphors coated with titanium dioxide. | 2013-04-18 |
20130092965 | LIGHT EMITTING DEVICE - An object of the present invention is to provide a light emitting device exhibiting a superior emission efficiency which enables easy adjustment of an emission spectrum. | 2013-04-18 |
20130092966 | Optoelectronic Component and Method for Producing an Optoelectronic Component and a Compound Structure - An optoelectronic component includes a housing. At least one semiconductor chip is arranged in the housing. The semiconductor chip includes an active layer suitable for producing or detecting electromagnetic radiation. A casting compound at least partially surrounds the semiconductor chip. Reflective particles are embedded in the casting compound. | 2013-04-18 |
20130092967 | LED DEVICE AND METHOD FOR MANUFACTURING SAME - An object of the present invention is to provide an LED device which prevents a sealing material from being colored even under high-temperature and high-humidity environment, and suppresses the decrease in luminescent efficiency. | 2013-04-18 |
20130092968 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride-based semiconductor light-emitting device | 2013-04-18 |
20130092969 | TL retrofit LED module inside sealed glass tube - This invention relates to a light emitting diode device ( | 2013-04-18 |
20130092970 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light-emitting device of the invention includes: a semiconductor layer including a light-emitting layer and having a first major surface and a second major surface opposite to the first major surface; a phosphor layer facing to the first major surface; an interconnect layer provided on the second major surface side and including a conductor and an insulator; and a light-blocking member provided on a side surface of the semiconductor layer and being opaque to light emitted from the light-emitting layer. | 2013-04-18 |
20130092971 | LIGHT EMITTING DIODE PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) packaging structure includes a substrate, a first transparent plastic layer, a second transparent plastic layer, an LED chip, fluorescent glue covering the LED chip and packaging plastic covering the substrate, the first transparent plastic layer and the fluorescent glue. The first and second transparent plastic layers are provided on the substrate. The LED chip is provided in the first enclosed flat pattern and the second enclosed flat pattern encloses the second transparent plastic layer. The first transparent plastic layer is higher than the LED chip and the second transparent plastic layer is higher than the first transparent plastic layer. The LED packaging structure does not require a leadframe and provides a broad emission angle of light. | 2013-04-18 |
20130092972 | Organic Light Emitting Diode Display and Method for Manufacturing the Same - An organic light emitting diode (OLED) display includes: a substrate; an organic light emitting diode formed on the substrate; a first inorganic layer formed on the substrate and covering the organic light emitting diode; an intermediate layer formed on the first inorganic layer and covering an area relatively smaller than the first inorganic layer; and a second inorganic layer formed on the first inorganic layer and the intermediate layer, and contacting the first inorganic layer at an edge thereof while covering a relatively larger area than the intermediate layer. A third inorganic layer may be formed on the second inorganic layer so as to contact the second inorganic layer at an edge thereof. At least one of the first, second and third inorganic layers is formed by an atomic layer deposition (ALD) method. | 2013-04-18 |
20130092973 | ENCAPSULATING SHEET AND OPTICAL SEMICONDUCTOR ELEMENT DEVICE - An encapsulating sheet is formed from an encapsulating resin composition which contains an encapsulating resin and silicone microparticles, and the mixing ratio of the silicone microparticles with respect to the encapsulating resin composition is 20 to 50 mass %. | 2013-04-18 |
20130092974 | SILICONE RESIN SHEET, CURED SHEET, AND LIGHT EMITTING DIODE DEVICE AND PRODUCING METHOD THEREOF - A silicone resin sheet is formed from a resin composition containing a thermosetting silicone resin and microparticles. The complex viscosity thereof at a frequency of 10 Hz is 80 to 1000 Pa·s and the tan δ thereof at a frequency of 10 Hz is 0.3 to 1.6 obtained by a dynamic viscoelastic measurement at a frequency of 0.1 to 50 Hz at 30° C.; a rate of frequency increase of 10 Hz/min; and a distortion of 1% in a shear mode. | 2013-04-18 |
20130092975 | Methods of Fabricating Optoelectronic Devices Using Semiconductor-Particle Monolayers and Devices Made Thereby - Methods of fabricating optoelectronic devices, such as photovoltaic cells and light-emitting devices. In one embodiment, such a method includes providing a substrate, applying a monolayer of semiconductor particles to the substrate, and encasing the monolayer with one or more coatings so as to form an encased-particle layer. At some point during the method, the substrate is removed so as to expose the reverse side of the encased-particle layer and further processing is performed on the reverse side. When a device made using such a method has been completed and installed into an electrical circuit the semiconductor particles actively participate in the photoelectric effect or generation of light, depending on the type of device. | 2013-04-18 |
20130092976 | A SEMICONDUCTOR POWER DEVICE INTEGRATRED WITHIMPROVED GATE SOURCE ESD CLAMP DIODES - A trench semiconductor power device integrated with four types of ESD clamp diodes for optimization of total perimeter of the ESD clamp diodes, wherein the ESD clamp diodes comprise multiple back to back Zener diodes with alternating doped regions of a first conductivity type next to a second conductivity type, wherein each of the doped regions has a closed ring structure. | 2013-04-18 |
20130092977 | POWER SEMICONDUCTOR DIODE, IGBT, AND METHOD FOR MANUFACTURING THEREOF - A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region. | 2013-04-18 |
20130092978 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductor type; a first semiconductor layer of a second conductor type, on the front of the semiconductor layer; a second semiconductor layer of the second conductor type, on the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductor type, on the second semiconductor layer and having a lower impurity concentration than the second semiconductor layer; a first semiconductor region of the first conductor type, in a surface layer of the third semiconductor layer; a second semiconductor region of the second conductor type, in a surface layer of the first semiconductor region; an input electrode contacting the second semiconductor region; a control electrode disposed above part of the first semiconductor region with an insulating film therebetween; and an output electrode disposed on the back of the semiconductor layer. | 2013-04-18 |
20130092979 | SEMICONDUCTOR DEVICE WITH AN ELECTRODE INCLUDING AN ALUMINUM-SILICON FILM - A semiconductor device, including a silicon substrate having a first major surface and a second major surface, a front surface device structure formed in a region of the first major surface, and a rear electrode formed in a region of the second major surface. The rear electrode includes, as a first layer thereof, an aluminum silicon film that is formed by evaporating or sputtering aluminum-silicon onto the second major surface, the aluminum silicon film having a silicon concentration of at least 2 percent by weight and a thickness of less than 0.3 μm. | 2013-04-18 |
20130092980 | PHOTODETECTOR STRUCTURES INCLUDING CROSS-SECTIONAL WAVEGUIDE BOUNDARIES - A photodetector structure can include a silicon substrate and a silicon layer on the silicon substrate, that can include a first portion of an optical transmission medium that further includes a silicon cross-sectional transmission face. A germanium layer can be on the silicon substrate and can include a second portion of the optical transmission medium, adjacent to the first portion can include a germanium cross-sectional transmission face butt-coupled to the silicon cross-sectional transmission face. | 2013-04-18 |
20130092981 | SIGE HBT HAVING A POSITION CONTROLLED EMITTER-BASE JUNCTION - A SiGe HBT having a position controlled emitter-base junction is disclosed. The SiGe HBT includes: a collector region formed of an N-doped active region; a base region formed on the collector region and including a base epitaxial layer, the base epitaxial layer including a SiGe layer and a capping layer formed thereon, the SiGe layer being formed of a SiGe epitaxial layer doped with a P-type impurity, the capping layer being doped with an N-type impurity; and an emitter region formed on the base region, the emitter region being formed of polysilicon. By optimizing the distribution of impurities doped in the base region, a controllable position of the emitter-base junction and adjustability of the reverse withstanding voltage thereof can be achieved, and thereby increasing the stability of the process and improving the uniformity within wafer. | 2013-04-18 |
20130092982 | PARTIAL BURIED CHANNEL TRANSFER DEVICE FOR IMAGE SENSORS - Embodiments of an image sensor pixel that includes a photosensitive element, a floating diffusion region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The floating diffusion region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region. The transfer device includes a buried channel device including a buried channel gate disposed over a buried channel dopant region. The transfer device also includes a surface channel device including a surface channel gate disposed over a surface channel region. The surface channel device is in series with the buried channel device. The surface channel gate has the opposite polarity of the buried channel gate. | 2013-04-18 |
20130092983 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE SAME - A plurality of photoelectric conversion elements including a first photoelectric conversion element, a second photoelectric conversion element, and a third photoelectric conversion element, are arranged in a photoelectric conversion apparatus of the present invention. Provided, between the first photoelectric conversion element and the second photoelectric conversion element, is a first semiconductor region of a first conductivity type and of a first width in which a signal charge is a minor charier. And, provided, between the first photoelectric conversion element and the third photoelectric conversion element, is a second semiconductor region of the first conductivity type in a higher impurity concentration and of a second width narrower than the first width at a position deeper in a semiconductor substrate rather than a depth of the first semiconductor region. | 2013-04-18 |
20130092984 | FINFET DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins. | 2013-04-18 |
20130092985 | Spacer for Semiconductor Structure Contact - An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1. | 2013-04-18 |
20130092986 | SEMICONDUCOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured. | 2013-04-18 |
20130092987 | MOS TRANSISTOR WITH NO HUMP EFFECT - A MOS transistor formed in an active area of a semiconductor substrate and having a polysilicon gate doped according to a first conductivity type, the gate including two lateral regions of the second conductivity type. | 2013-04-18 |
20130092988 | SELF-ALIGNED SILICIDE FORMATION ON SOURCE/DRAIN THROUGH CONTACT VIA - According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process. | 2013-04-18 |
20130092989 | Embedded Transistor - An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. | 2013-04-18 |
20130092990 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE AND ELECTRONIC DEVICE - When writing a signal current from a current source to a current source circuit, noise occurs in some cases in a wiring through which a current flows, which may cause a potential of the wiring to be outside the normal range. As the potential does not turn back within the normal range easily at this time, writing to the current source circuit is delayed. According to the invention, when the potential becomes outside the normal range due to noise occurring in a wiring through which a current flows when writing a signal current from a current source to a current source circuit, a current is supplied from other than the current source, thereby the potential of the wiring can turn back within the normal range rapidly. | 2013-04-18 |
20130092991 | STRUCTURE AND METHOD FOR SINGLE GATE NON-VOLATILE MEMORY DEVICE HAVING A CAPACITOR WELL DOPING DESIGN WITH IMPROVED COUPLING EFFICIENCY - The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode. | 2013-04-18 |
20130092992 | REPLACEMENT GATE MULTIGATE TRANSISTOR FOR EMBEDDED DRAM - A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor. | 2013-04-18 |
20130092993 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact. | 2013-04-18 |
20130092994 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region. | 2013-04-18 |
20130092995 | ELECTRICAL ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND MANUFACTURING METHOD THEREOF - An electrical erasable programmable read-only memory (EEPROM) including a floating transistor formed on a semiconductor substrate and a tunneling transistor formed on a semiconductor substrate and configured to erase electrons trapped in the floating transistor. The tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion. The EPROM maintains a small cell size without any additional mask process, and is useable as an MTP EEPROM because electrical erasure is enabled. In addition, the adjustment of the width of a gate constituting the tunneling transistor ensures an improved degree of freedom to adjust an erasure voltage can be enhanced. | 2013-04-18 |
20130092996 | NAND FLASH MEMORY DEVICES - NAND flash memory device includes a common bit line, a first cell string including a first string selecting transistor having a first gate length, a second string selecting transistor having a second gate length, first cell transistors each having a third gate length and a first ground selecting transistor having a fourth gate length, a second cell string including a third string selecting transistor having the first gate length, a fourth string selecting transistor having the second gate length, second cell transistors each having the third gate length and a second ground selecting transistor having the fourth gate length and a common source line commonly connected to end portions of the first and second ground selecting transistors included in the first and second cell strings. At least one of the first gate length and the second gate length is smaller than the fourth gate length. | 2013-04-18 |
20130092997 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer. | 2013-04-18 |
20130092998 | Memory Devices Capable Of Reducing Lateral Movement Of Charges - Memory devices are provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell. | 2013-04-18 |
20130092999 | NONVOLATILE STORAGE DEVICE - A nonvolatile storage device includes a tunnel insulating film disposed on a surface of a semiconductor substrate and a charge trap layer disposed in contact with an upper surface of the tunnel insulating film. The charge trap layer includes a second charge trap film disposed in contact with the upper surface of the tunnel insulating film and a first charge trap film disposed in contact with an upper surface of the second charge trap film. | 2013-04-18 |
20130093000 | VERTICAL TRANSISTOR HAVING AN ASYMMETRIC GATE - A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate. | 2013-04-18 |
20130093001 | POWER MOSFET DEVICE STRUCTURE FOR HIGH FREQUENCY APPLICATIONS - This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device. | 2013-04-18 |
20130093002 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate. | 2013-04-18 |
20130093003 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third. diffusion layers are the same. | 2013-04-18 |
20130093004 | SEMICONDUCTOR DEVICE INCLUDING DUMMY PILLAR NEAR INTERMEDIATE PORTION OF SEMICONDUCTOR PILLAR GROUP - A semiconductor device includes a semiconductor pillar group having semiconductor pillars which are formed in a first direction with a space left therebetween. A dummy pillar is disposed near a particular semiconductor pillar in the semiconductor pillar group in a second direction perpendicular to the first direction that is any one of the semiconductor pillars which are positioned in an intermediate portion exclusive of both end portions. Gate insulating films are formed on outer circumferential surfaces of the semiconductor pillars. One gate insulating film is formed on a part of an outer circumferential surface of the dummy pillar. Formed over side faces of the semiconductor pillars and over a side face of the dummy pillar via the gate insulating films, gate electrodes fill gaps between the semiconductor pillars and a gap between the particular semiconductor pillar and the dummy pillar. | 2013-04-18 |
20130093005 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Three-dimensional (3D) semiconductor memory devices are provided. According to the 3D semiconductor memory device, a gate structure includes gate patterns and insulating patterns alternately stacked on a semiconductor substrate. A vertical active pattern penetrates the gate structure. A gate dielectric layer is disposed between a sidewall of the vertical active pattern and each of the gate patterns. A semiconductor pattern is disposed on the gate structure and is connected to the vertical active pattern. A string drain region is formed in a portion of the semiconductor pattern and is spaced apart from the vertical active pattern. | 2013-04-18 |
20130093006 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor layer, an insulating film, a gate electrode, a drain electrode, and a source electrode. The semiconductor layer includes an active layer and is formed on a semi-insulating semiconductor substrate, and a tapered recess area having an inclined sidewall is formed on a surface of the semiconductor layer. The insulating film is formed on the semiconductor layer and has a through hole for exposing the recess area. The through hole has a tapered sidewall which is inclined at an angle smaller than the sidewall of the recess area. The gate electrode is formed so as to fill the recess area and the through hole. The drain electrode and the source electrode are formed at positions on opposite sides of the recess area on the semiconductor layer. | 2013-04-18 |
20130093007 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region. | 2013-04-18 |
20130093008 | TRENCH MOSFET DEVICE AND METHOD FOR FABRICATING THE SAME - A trench Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device is disclosed. The trench MOSFET device includes a substrate, a body region, a source region, a dielectric layer, a metal layer, a contact hole, and a trench structure. The substrate includes a substrate layer and an epitaxial layer formed on the substrate layer; the body region is formed in the epitaxial layer; and the source region is formed in the body region of the epitaxial layer. Further, the dielectric layer is formed on the epitaxial layer; the metal layer is formed on the dielectric layer; and the contact hole is formed in the dielectric layer to connect the source region with the metal layer. In addition, the trench structure is formed in the epitaxial layer, and the trench structure includes a first trench that is a pectinate trench including a plurality of tooth trenches and a bar trench interconnecting the plurality of tooth trenches. | 2013-04-18 |
20130093009 | METHOD OF MANUFACTURING NMOS TRANSISTOR WITH LOW TRIGGER VOLTAGE - A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source. | 2013-04-18 |
20130093010 | High-Voltage Mosfets Having Current Diversion Region in Substrate Near Fieldplate - To limit or prevent current crowding, various HV-MOSFET embodiments include a current diversion region disposed near a drain region of an HV-MOSFET and near an upper surface of the semiconductor substrate. In some embodiments, the current diversion region is disposed near a field plate of the HV-MOSFET, wherein the field plate can also help to reduce or “smooth” electric fields near the drain to help limit current crowding. In some embodiments, the current diversion region is a p-doped, n-doped, or intrinsic region that is at a floating voltage potential. This current diversion region can push current deeper into the substrate of the HV-MOSFET (relative to conventional HV-MOSFETs), thereby reducing current crowding during ESD events. By reducing current crowding, the current diversion region makes the HV-MOSFETs disclosed herein more impervious to ESD events and, therefore, more reliable in real-world applications. | 2013-04-18 |
20130093011 | High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a substrate. The high voltage device includes: a gate, a source and drain, a drift region, and a mitigation region. The gate is formed on an upper surface of the substrate. The source and drain are located at both sides of the gate below the upper surface respectively, and the source and drain are separated by the gate. The drift region is located at least between the gate and the drain. The mitigation region is formed below the drift region, and the drift region has an edge closer to the source. A vertical distance between this edge of the drift region and the mitigation region is less than or equal to five times of a depth of the drift region. | 2013-04-18 |
20130093012 | HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain. | 2013-04-18 |
20130093013 | HIGH VOLTAGE TRANSISTOR AND MANUFACTURING METHOD THEREFOR - A high-voltage transistor may include a semiconductor substrate, and a gate electrode formed on and/or over the semiconductor substrate. Further, the high-voltage transistor may include source/drain regions formed on and/or over the semiconductor substrate at one side of the gate electrode, and impurity layers having a super junction structure and formed on and/or over a boundary of a drift region disposed below the gate electrode. | 2013-04-18 |
20130093014 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a laterally double diffused metal oxide semiconductor (LDMOS) transistor formed on a partial region of a epitaxial layer of a first conductive type, a bipolar transistor formed on another partial region of the epitaxial layer of the first conductive type, and a guard ring formed between the partial region and the another partial region. The guard ring serves to restrain electrons generated by a forward bias operation of the LDMOS transistor from being introduced into the bipolar transistor. | 2013-04-18 |
20130093015 | HIGH VOLTAGE MOS TRANSISTOR - A high voltage metal oxide semiconductor (HVMOS) transistor ( | 2013-04-18 |
20130093016 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An LDMOS device may include at least one of a second conduction type buried layer and a first conduction type drain extension region. An LDMOS device may include a second conduction type drain extension region configured to be formed in a portion of the first conduction type drain extension region. The second conduction type drain extension region may include a gate pattern and a drain region. An LDMOS device may include a first conduction type body having surface contact with the second conduction type drain extension region and may include a source region. An LDMOS device may include a first guard ring formed around the second conduction type drain extension region. An LDMOS device may include a second guard ring configured to be formed around the first guard ring and configured to be connected to a different region of the second conduction type buried layer. | 2013-04-18 |
20130093017 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An LDMOS device includes a second conduction type buried layer, a first conduction type drain extension region configured to be formed on and/or over a region of the second conduction type buried layer, a second conduction type drain extension region configured to be formed in a partial region of the first conduction type drain extension region, a first conduction type body, a first guard ring configured to be formed around the second conduction type drain extension region and configured to include a second conduction type impurity layer, and a second guard ring configured to be formed around the first guard ring and configured to include a high-voltage second conduction type well and a second conduction type impurity layer. Further, the second conduction type impurity layer of the first guard ring and the second conduction type impurity layer of the second guard ring operate as an isolation. | 2013-04-18 |
20130093018 | CARBON IMPLANT FOR WORKFUNCTION ADJUSTMENT IN REPLACEMENT GATE TRANSISTOR - A method includes providing a wafer that has a semiconductor layer having an insulator layer disposed on the semiconductor layer. The insulator layer has openings made therein to expose a surface of the semiconductor layer, where each opening corresponds to a location of what will become a transistor channel in the semiconductor layer disposed beneath a gate stack. The method further includes depositing a high dielectric constant gate insulator layer so as to cover the exposed surface of the semiconductor layer and sidewalls of the insulator layer; depositing a gate metal layer that overlies the high dielectric constant gate insulator layer; and implanting Carbon through the gate metal layer and the underlying high dielectric constant gate insulator layer so as to form in an upper portion of the semiconductor layer a Carbon-implanted region having a concentration of Carbon selected to establish a voltage threshold of the transistor. | 2013-04-18 |
20130093019 | FINFET PARASITIC CAPACITANCE REDUCTION USING AIR GAP - A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed. | 2013-04-18 |
20130093020 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks. | 2013-04-18 |
20130093021 | CARBON IMPLANT FOR WORKFUNCTION ADJUSTMENT IN REPLACEMENT GATE TRANSISTOR - A transistor includes a semiconductor body having a channel formed in the semiconductor body; a high dielectric constant gate insulator layer disposed over a surface of an upper portion of the channel; and a gate metal layer disposed over the high dielectric constant gate insulator layer. The channel contains Carbon implanted through the gate metal layer, the high dielectric constant gate insulator layer and the surface to form in the upper portion of the channel a Carbon-implanted region having a substantially uniform concentration of Carbon selected to establish a voltage threshold of the transistor. | 2013-04-18 |
20130093022 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor area includes a transistor area comprising a transistor formed in the transistor area at a transistor level, wherein a gate of the transistor is formed at a gate level; a first metal line formed across the transistor area at a first level higher than the transistor level to supply a power voltage to the transistor; and a gate metal line formed at the gate level to supply the power voltage to the transistor area, and the gate metal line is electrically coupled to the first metal line. | 2013-04-18 |
20130093023 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulated gate field effect transistor, a second insulated gate field effect transistor, a bipolar transistor, a first element isolation structure formed on a main surface above a pn junction formed between an emitter region and a base region, a second element isolation structure formed on the main surface above a pn junction formed between the base region and a collector region, and a third element isolation structure formed on the main surface opposite to the second element isolation structure relative to the collector region, in which the semiconductor device further includes a bipolar dummy electrode formed on at least one of the first element isolation structure, the second element isolation structure and the third element isolation structure and having a floating potential. | 2013-04-18 |
20130093024 | STRUCTURE AND METHOD FOR INTEGRATING FRONT END SiCr RESISTORS IN HiK METAL GATE TECHNOLOGIES - An integrated circuit having a replacement HiK metal gate transistor and a front end SiCr resistor. The SiCr resistor replaces the conventional polysilicon resistor in front end processing and is integrated into the contact module. The first level of metal interconnect is located above the SiCr resistor. First contacts connect to source/drain regions. Second contacts electrically connect the first level of interconnect to either the SiCr resistor or the metal replacement gate. | 2013-04-18 |
20130093025 | PULSE OUTPUT CIRCUIT, DISPLAY DEVICE, AND ELECTRONIC DEVICE - An object of the present invention is to suppress deterioration in the thin film transistor. A plurality of pulse output circuits each include first to eleventh thin film transistors is formed. The pulse output circuit is operated on the basis of a plurality of clock signals which control each transistor, the previous stage signal input from a pulse output circuit in the previous stage, the next stage signal input from a pulse output circuit in the next stage, and a reset signal. In addition, a microcrystalline semiconductor is used for a semiconductor layer serving as a channel region of each transistor. Therefore, degradation of characteristics of the transistor can be suppressed. | 2013-04-18 |
20130093026 | SELECTIVE FIN-SHAPING PROCESS USING PLASMA DOPING AND ETCHING FOR 3-DIMENSIONAL TRANSISTOR APPLICATIONS - A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin. | 2013-04-18 |
20130093027 | LAYOUT DATA CREATION DEVICE FOR CREATING LAYOUT DATA OF PILLAR-TYPE TRANSISTOR - A layout data creation device includes a transistor adjustment unit. The transistor adjustment unit divides a pillar-type transistor including a plurality of unit pillar-type transistors into the unit pillar-type transistors groups. The unit pillar-type transistors can be placed in a placement area. The number of the unit pillar-type transistors in each group is an integer. The transistor adjustment unit generates sub-pillar-type transistors that are placed in the placement area. | 2013-04-18 |
20130093028 | INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME - An integrated circuit includes at least one first gate electrode of at least one active transistor. The integrated circuit further includes at least one first dummy gate electrode and at least one second dummy gate electrode. The integrated circuit further includes at least one guard ring disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode. An ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode or the at least one second dummy gate electrode. | 2013-04-18 |
20130093029 | PROCESS FOR PREPARING A BERYLLIUM OXIDE LAYER ON A SEMICONDUCTOR SUBSTRATE - A process for creating a beryllium oxide film on the surface of a semiconductor material is disclosed. The process is useful for making gate dielectric layers for metal-oxide-semiconductor (MOS) devices, particularly III-V semiconductor devices. | 2013-04-18 |
20130093030 | UNATTACHED CONTAINED SEMICONDUCTOR DEVICES - An unattached, contained semiconductor device includes a semiconductor die, for example a MEMS pressure sensor die. The semiconductor die is unattached from the interior cavity of a surrounding containment body in that the semiconductor die is free of adherence to the containment body to mitigate packaging stress and strain between the containment body and the semiconductor die. | 2013-04-18 |
20130093031 | SYSTEMS AND METHODS FOR AIR-RELEASE IN CAVITY PACKAGES - A housing for integrated devices that includes an air-release mechanism is disclosed. This is achieved, in various embodiments, by forming a vent hole in a package substrate, and arranging a package lid over the package substrate. The vent hole allows air to be released from within the cavity package, thereby ensuring that the package lid remains stably affixed to the package substrate despite increased temperatures during processing. The vent hole may be sealed upon mounting the package onto a mounting substrate. | 2013-04-18 |
20130093032 | SEMICONDUCTOR TRENCH INDUCTORS AND TRANSFORMERS - Semiconductor trench inductor and transformer structures are provided, which include thin film conductive layers and magnetic layers formed within trenches etched in semiconductor substrates. Semiconductor trench devices effectively provide vertical oriented inductor and transformer structures whereby conductive coils and magnetic layers are vertically oriented on edge within trenches, thereby providing a space-saving compact design, and which allows the conductive layers within the trench to be enclosed by magnetic material, thereby providing a density of magnetic material that increases the storable energy density. | 2013-04-18 |
20130093033 | THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS - The invention relates to a method of initiating molecular bonding, comprising bringing one face ( | 2013-04-18 |
20130093034 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE - According to one embodiment, there is provided a solid-state imaging device including a first photoelectric conversion layer and a color filter. The color filter includes a multi-layer interference filter and a guided mode resonant grating. The guided mode resonant grating includes a plurality of diffraction gratings and a plurality of inter-grating regions. The plurality of diffraction gratings are formed of a material having a first index of refraction and periodically arrayed at least one-dimensionally. The plurality of inter-grating regions are arranged between at least the plurality of diffraction gratings. Each of the plurality of inter-grating regions includes an insulating film region and an air gap region. The insulating film region is formed of a material having a second index of refraction lower than the first index of refraction. | 2013-04-18 |
20130093035 | PHOTO DETECTOR AND INTEGRATED CIRCUIT - The photo detector ( | 2013-04-18 |
20130093036 | METHOD OF FABRICATING BACKSIDE-ILLUMINATED IMAGE SENSOR - Provided is a method of fabricating a backside illuminated image sensor that includes providing a device substrate having a frontside and a backside, where pixels are formed at the frontside and an interconnect structure is formed over pixels, forming a re-distribution layer (RDL) over the interconnect structure, bonding a first glass substrate to the RDL, thinning and processing the device substrate from the backside, bonding a second glass substrate to the backside, removing the first glass substrate, and reusing the first glass substrate for fabricating another backside-illuminated image sensor. | 2013-04-18 |
20130093037 | INFARED SENSOR - The infrared sensor includes: an infrared sensor chip in which a plurality of pixel portions each including a temperature-sensitive portion formed of a thermopile is disposed in an array on one surface side of a semiconductor substrate; and an IC chip that processes an output signal of the infrared sensor chip. A package includes a package main body on which the infrared sensor chip and the IC chip are mounted to be arranged side-by-side, and a package cover that has a lens transmitting infrared rays and is hermetically bonded to the package main body. The package is provided therein with a cover member that includes a window hole through which infrared rays pass into the infrared sensor chip and equalizes amounts of temperature change of hot junctions and cold junctions among the pixel portions, the temperature change resulting from heating of the IC chip. | 2013-04-18 |
20130093038 | Schottky Diode - An embodiment is a semiconductor structure. The semiconductor structure comprises a p-type region in a substrate; a first n-type well in the p-type region; a first p-type well in the p-type region; and a second p-type well in the first p-type well. A concentration of a p-type impurity in the first p-type well is less than a concentration of a p-type impurity in the second p-type well. Additional embodiments further comprise further n-type and p-type wells in the substrate. A method for forming a semiconductor structure is also disclosed. | 2013-04-18 |
20130093039 | HIGH-K DIELECTRIC AND SILICON NITRIDE BOX REGION - Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer. | 2013-04-18 |
20130093040 | SHALLOW TRENCH ISOLATION STRUCTURE HAVING A NITRIDE PLUG - A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates. | 2013-04-18 |
20130093041 | Semiconductor Device and Method for Manufacturing the Same - The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device. | 2013-04-18 |
20130093042 | TSV Formation Processes Using TSV-Last Approach - A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad. | 2013-04-18 |
20130093043 | ARRAY AND MOAT ISOLATION STRUCTURES AND METHOD OF MANUFACTURE - An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region. | 2013-04-18 |
20130093044 | SEMICONDUCTOR DEVICE - A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal. | 2013-04-18 |
20130093045 | VERTICALLY ORIENTED SEMICONDUCTOR DEVICE AND SHIELDING STRUCTURE THEREOF - The present disclosure involves a semiconductor device. The semiconductor device includes a substrate; a capacitor disposed over the substrate; an inductor disposed over the substrate and having a coil feature surrounding the capacitor; and a shielding structure over the substrate and configured around the coil feature. | 2013-04-18 |