16th week of 2014 patent applcation highlights part 48 |
Patent application number | Title | Published |
20140106515 | AMORPHOUS SILICON THIN FILM TRANSISTOR-LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - In an amorphous silicon thin film transistor-liquid crystal display device and a method of manufacturing the same, gate patterns including a gate line and a gate electrode are formed on an insulation substrate having a display region and a driving circuit region on which a plurality of shift resistors are formed. A gate insulating film, active layer patterns and data patterns including source/drain electrodes are formed successively on the substrate. A passivation layer on the substrate has a first contact hole exposing a drain electrode of the display region and second and third contact holes respectively exposing a gate electrode and source/drain electrode of a first transistor of each of the shift resistors. Electrode patterns on the passivation layer include a first electrode connected to the drain electrode of the display region through the first contact hole and a second electrode connecting the gate electrode to the source/drain electrode of the first transistor through the second and third contact holes. The gate driving circuit including the shift resistors and the wirings are integrated on the insulating substrate without an additional process, thereby simplifying the manufacturing process. | 2014-04-17 |
20140106516 | SELF-DOPED OHMIC CONTACTS FOR COMPOUND SEMICONDUCTOR DEVICES - A compound semiconductor device is manufactured by forming an III-nitride compound semiconductor device structure on a silicon-containing semiconductor substrate, the III-nitride compound semiconductor device structure including a GaN alloy on GaN and a channel region arising near an interface between the GaN alloy and the GaN. One or more silicon-containing insulating layers are formed on a surface of the III-nitride compound semiconductor device structure adjacent the GaN alloy, and a contact opening is formed which extends through the one or more silicon-containing insulating layers to at least the GaN alloy. A region of GaN is regrown in the contact opening, and the regrown region of GaN is doped exclusively with Si out-diffused from the one or more silicon-containing insulating layers to form an ohmic contact which is doped only with the Si out-diffused from the one or more silicon-containing insulating layers. | 2014-04-17 |
20140106517 | SEMICONDUCTOR DEVICES WITH MINIMIZED CURRENT FLOW DIFFERENCES AND METHODS OF SAME - A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device. | 2014-04-17 |
20140106518 | NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers. | 2014-04-17 |
20140106519 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF - A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness. | 2014-04-17 |
20140106520 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method with high productivity is disclosed with improved trade-off relationship between auto-doping and breakdown in alignment mark form. First to sixth epitaxial layers are grown sequentially on Si {100} main surface of an arsenic doped substrate using multilayer epitaxial technology. Epitaxial growth conditions of the first to sixth epitaxial layers are growth at atmospheric pressure and a temperature of 1,150° C. to 1,180° C., with epitaxial growth rate of 2.2 to 2.6 μm/minute. An alignment mark of depressed form whose bottom surface is the Si {100} plane is formed in the arsenic doped substrate. Every time one of the first to sixth epitaxial layers is grown on the main surface of the arsenic doped substrate, an alignment mark of depressed form is formed in the outermost epitaxial layer by a portion above the alignment mark of the layer below being transformed. | 2014-04-17 |
20140106521 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface. | 2014-04-17 |
20140106522 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 2014-04-17 |
20140106523 | Vertical Super-Thin Body Semiconductor on Dielectric Wall Devices and Methods of Their Fabrication - The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices. | 2014-04-17 |
20140106524 | DIODE ISOLATED DRAIN EXTENDED NMOS ESD CELL - An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed. | 2014-04-17 |
20140106525 | METHOD OF FORMING PN FLOATING GATE NON-VOLATILE STORAGE ELEMENTS AND TRANSISTOR HAVING N+ GATE - Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+. | 2014-04-17 |
20140106526 | METHOD OF MANUFACTURING FLASH MEMORY CELL - A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively. | 2014-04-17 |
20140106527 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed. | 2014-04-17 |
20140106528 | FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS - A method of forming a fin field effect transistor (finFET) includes forming a plurality of fins of varying heights on a substrate and forming a first gate structure on one or more fins of a first height to form a first finFET structure and a second gate structure on one or more fins of a second height to form a second finFET structure. The method includes epitaxially forming an epitaxial fill material on the one or more fins of the first finFET structure and the second finFET structure. The epitaxial fill material of the first finFET structure has a same height as the epitaxial fill material of the second finFET structure. | 2014-04-17 |
20140106529 | FINFET DEVICE WITH SILICIDED SOURCE-DRAIN REGIONS AND METHOD OF MAKING SAME USING A TWO STEP ANNEAL - A thermal annealing flow process includes the steps of: depositing a metal or metal alloy on a silicon semiconductor structure, performing a first annealing of a rapid thermal anneal (RTA) type to produce a metal rich phase in a portion of the silicon semiconductor structure, removing unreacted metal or metal alloy and performing a second annealing as a millisecond annealing at a temperature that is below a melt temperature of the silicon material present in the silicon semiconductor structure. | 2014-04-17 |
20140106530 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film ( | 2014-04-17 |
20140106531 | FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK - A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure. | 2014-04-17 |
20140106532 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME AND ESD CIRCUIT - A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region. | 2014-04-17 |
20140106533 | MEMORY CELLS AND METHODS OF FORMING MEMORY CELLS - Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour. | 2014-04-17 |
20140106534 | Methods Of Forming A Programmable Region That Comprises A Multivalent Metal Oxide Portion And An Oxygen Containing Dielectric Portion - A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base. The other of the multivalent metal oxide material or oxygen-containing dielectric material is formed over the treated outer surface. A second conductive structure is formed over the other of the multivalent metal oxide material or oxygen-containing dielectric material. | 2014-04-17 |
20140106535 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element. | 2014-04-17 |
20140106536 | Cylindrical Embedded Capacitors - A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate. | 2014-04-17 |
20140106537 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively. | 2014-04-17 |
20140106538 | DUMMY PATTERN DESIGN FOR THERMAL ANNEALING - The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region. | 2014-04-17 |
20140106539 | SEMICONDUCTOR ISOLATION STRUCTURE AND METHOD OF MANUFACTURE - A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described. | 2014-04-17 |
20140106540 | METHOD AND DEVICE FOR SLICING A SHAPED SILICON INGOT USING LAYER TRANSFER - A method for slicing a crystalline material ingot includes providing a crystalline material boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in a first crystallographic direction extending from the first end-face to the second end-face. The method also includes cutting the crystalline material boule substantially through a first crystallographic plane in parallel to the axis to separate the crystalline material boule into a first portion with a first surface and a second portion with a second surface. The first surface and the second surface are planar surfaces substantially along the first crystallographic plane. The method further includes exposing either the first surface of the first portion or the second surface of the second portion, and performing a layer transfer process to form a crystalline material sheet from either the first surface of the first portion or from the second surface of the second portion. | 2014-04-17 |
20140106541 | MICROCHIP CHARGE PATTERNING - A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid. | 2014-04-17 |
20140106542 | LASER AND PLASMA ETCH WAFER DICING WITH PARTIAL PRE-CURING OF UV RELEASE DICING TAPE FOR FILM FRAME WAFER APPLICATION - Methods and systems of laser and plasma etch wafer dicing using UV-curable adhesive films. A method includes forming a mask covering ICs formed on the wafer. The semiconductor wafer is coupled to a film frame by a UV-curable adhesive film. A pre-cure of the UV-curable adhesive film cures a peripheral portion of the adhesive extending beyond an edge of the wafer to improve the exposed adhesive material's resistance to plasma etch and reduce hydrocarbon redeposition within the etch chamber. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the ICs. A center portion of the UV-curable adhesive is then cured and the singulated ICs detached from the film. | 2014-04-17 |
20140106543 | LASER PROCESSING METHOD FOR WAFER - A wafer processing method divides a wafer into a plurality of individual devices along a plurality of crossing division lines formed on the front side of the wafer. The wafer has a substrate, a functional layer formed on the front side of the substrate, and a film formed on the back side of the substrate. The method includes a modified layer forming step of applying a laser beam having a wavelength transmitting through the substrate and the functional layer and reflecting on the film along the division lines from the side of the functional layer. The laser beam is first focused at a virtual point set outside the substrate beyond the film and is reflected on the film to focus the beam inside the substrate, thereby forming a modified layer inside the substrate along each division line. | 2014-04-17 |
20140106544 | SEMICONDUCTOR WAFER WITH ASSISTING DICING STRUCTURE AND DICING METHOD THEREOF - A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed. | 2014-04-17 |
20140106545 | LASER PROCESSING METHOD FOR WORKPIECE - During the performance of a laser processing step of applying a laser beam to a wafer to form modified layers inside the wafer respectively along division lines, a predetermined one of the modified layers already formed is imaged by a camera from the back side of the wafer with predetermined timing, and a positional deviation of the predetermined modified layer from the corresponding division line is detected to calculate a correction value. Then, the correction value is added to data on applied position of the laser beam to thereby make the applied position of the laser beam coincide with each division line. Accordingly, a positional deviation of the modified layer to be formed after this correction from each division line can be suppressed. | 2014-04-17 |
20140106546 | Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication - Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures. | 2014-04-17 |
20140106547 | EPITAXY OF HIGH TENSILE SILICON ALLOY FOR TENSILE STRAIN APPLICATIONS - Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×10 | 2014-04-17 |
20140106548 | Fabrication of III-Nitride Semiconductor Device and Related Structures - A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods. | 2014-04-17 |
20140106549 | LOW TEMPERATURE GST PROCESS - A deposition process to form a conformal phase change material film on the surface of a substrate to produce a memory device wafer comprises providing a substrate to a chamber of a deposition system; providing an activation region; introducing one or more precursors into the chamber upstream of the substrate; optionally introducing one or more co-reactants upstream of the substrate; activating the one or more precursors; heating the substrate; and depositing the phase change material film on the substrate from the one or more precursors by chemical vapor deposition. The deposited phase change material film comprises Ge | 2014-04-17 |
20140106550 | ION IMPLANTATION TUNING TO ACHIEVE SIMULTANEOUS MULTIPLE IMPLANT ENERGIES - A method of ion implantation is disclosed. A beam of ions is accelerated to a first energy level. The beam of ions is decelerated from the first energy level to produce a contamination beam of ions via an ion collision process. The ions of the contamination beam are implanted in a substrate to obtain a selected dopant profile in the substrate. | 2014-04-17 |
20140106551 | BACK CONTACT SOLAR CELLS WITH EFFECTIVE AND EFFICIENT DESIGNS AND CORRESPONDING PATTERNING PROCESSES - Laser based processes are used alone or in combination to effectively process doped domains for semiconductors and/or current harvesting structures. For example, dopants can be driven into a silicon/germanium semiconductor layer from a bare silicon/germanium surface using a laser beam. Deep contacts have been found to be effective for producing efficient solar cells. Dielectric layers can be effectively patterned to provide for selected contact between the current collectors and the doped domains along the semiconductor surface. Rapid processing approaches are suitable for efficient production processes. | 2014-04-17 |
20140106552 | Method Of Fabricating MEMS Transistors On Far Back End Of Line - A MEMS transistor for a FBEOL level of a CMOS integrated circuit is disclosed. The MEMS transistor includes a cavity within the integrated circuit. A MEMS cantilever switch having two ends is disposed within the cavity and anchored at least at one of the two ends. A gate and a drain are in a sidewall of the cavity, and are separated from the MEMS cantilever switch by a gap. In response to a voltage applied to the gate, the MEMS cantilever switch moves across the gap in a direction parallel to the plane of the FBEOL level of the CMOS integrated circuit into electrical contact with the drain to permit a current to flow between the source and the drain. Methods for fabricating the MEMS transistor are also disclosed. In accordance with the methods, a MEMS cantilever switch, a gate, and a drain are constructed on a far back end of line (FBEOL) level of a CMOS integrated circuit in a plane parallel to the FBEOL level. The MEMS cantilever switch is separated from the gate and the drain by a sacrificial material, which is ultimately removed to release the MEMS cantilever switch and to provide a gap between the MEMS cantilever switch and the gate and the drain. | 2014-04-17 |
20140106553 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND AN INTERMEDIATE PRODUCT FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE - According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer ( | 2014-04-17 |
20140106554 | Methods of Forming Gated Devices - Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors. | 2014-04-17 |
20140106555 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation. The sidewall isolation is removed in a portion of the trench. A gate dielectric is formed on the laid open sidewall. A gate electrode is formed adjacent to the date dielectric. The upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate. The gate oxide is removed above the gate electrode. An isolation is formed simultaneously on the gate electrode and the semiconductor substrate such that the absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1. | 2014-04-17 |
20140106556 | METHOD FOR MANUFACTURING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE - A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element. The method additionally includes annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer, and subsequently removing the first metal layer/stack and the second metal layer/stack. The method further includes forming a third metal layer/stack in the first and second predetermined areas. | 2014-04-17 |
20140106557 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench. | 2014-04-17 |
20140106558 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate. | 2014-04-17 |
20140106559 | SYSTEM AND METHOD FOR FORMING AN ALUMINUM FUSE FOR COMPATIBILITY WITH COPPER BEOL INTERCONNECT SCHEME - A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse. | 2014-04-17 |
20140106560 | DEBOND INTERCONNECT STRUCTURES - The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress. | 2014-04-17 |
20140106561 | Graphene Barrier Layers for Interconnects and Methods for Forming the Same - Embodiments described herein provide interconnect barrier layers and methods for forming such barriers. A dielectric body having a trench formed in a surface thereof is provided. A first layer is formed above the dielectric body within the trench. The first layer includes amorphous carbon. A second layer is formed above the first layer. The second layer includes a metal. The dielectric body, the first layer, and the second layer are heated to convert at least some of the amorphous carbon to graphene. | 2014-04-17 |
20140106562 | Barrier Layer for Copper Interconnect - A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide. | 2014-04-17 |
20140106563 | Stress Reduction Apparatus - A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer. | 2014-04-17 |
20140106564 | ADDITIVE CONDUCTOR REDISTRIBUTION LAYER (ACRL) - A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device. | 2014-04-17 |
20140106565 | Methods For Atomic Layer Etching - Provided are methods of etching a substrate using atomic layer deposition apparatus. Atomic layer deposition apparatus including a gas distribution plate with a thermal element are discussed. The thermal element is capable of locally changing the temperature of a portion of the surface of the substrate to vaporize an etch layer deposited on the substrate. | 2014-04-17 |
20140106566 | Method For Etching an Ultra Thin Film - A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer. | 2014-04-17 |
20140106567 | METHODS OF FORMING FINE PATTERNS IN SEMICONDUCTOR DEVICES - Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure. | 2014-04-17 |
20140106568 | METHOD OF FORMING OPENING ON SEMICONDUCTOR SUBSTRATE - The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer. | 2014-04-17 |
20140106569 | METHOD OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICE FABRICATED USING THE SAME - According to example embodiments of inventive concepts, a method of fabricating a 3D semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth. | 2014-04-17 |
20140106570 | COMPOSITION FOR FORMING ORGANIC HARD MASK LAYER FOR USE IN LITHOGRAPHY CONTAINING POLYMER HAVING ACRYLAMIDE STRUCTURE - Whereas, conventionally, ashing had been used at the time of removal, the present invention provides a material for forming an organic hard mask that can be removed by an alkaline aqueous solution, and thus can be expected to reduce damage to the substrate at the time of the removal. A composition for forming an organic hard mask layer comprising: a polymer (A) including a structural unit of Formula (1) and a structural unit of Formula (2); a crosslinkable compound (B) including at least two of blocked isocyanate groups, methylol groups, or C | 2014-04-17 |
20140106571 | BIASING SYSTEM FOR A PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a process chamber housing defining a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate plasma in the process chamber, and a biasing system. The biasing system is configured to bias the platen to attract ions from the plasma towards the workpiece during a first processing time interval and configured to bias the platen to repel ions from the platen towards interior surfaces of the process chamber housing during a cleaning time interval. The cleaning time interval is separate from the first processing time interval and occurring after the first processing time interval. | 2014-04-17 |
20140106572 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING DEVICE - A plasma processing method for a plasma processing device is provided. The plasma processing device includes a reaction chamber, multiple Radio Frequency (RF) power supplies with different RF frequency outputs apply RF electric fields to the reaction chamber, the output of at least one pulse RF power supply has multiple output states, and the processing method includes a match frequency obtaining step and a pulse processing step. In the match frequency obtaining step, the output state of the pulse RF power supply is switched to make the reaction chamber have multiple impedances to simulate the impedances in the pulse processing step. The output frequencies of the variable frequency RF power supply are adjusted to match the simulated impedances. The adjusted output frequencies are stored as match frequencies. In the subsequent pulse processing step, the fast switched impedances are instantly matched by the stored match frequencies. | 2014-04-17 |
20140106573 | Substrate Processing Apparatus and Method of Manufacturing Semiconductor Device - A substrate processing apparatus includes a substrate processing chamber including a plasma generation space where a plasma is generated and a substrate processing space where a substrate is placed during a substrate process; an inductive coupling structure outside the plasma generation space wherein a sum of electrical lengths of a coil of the inductive coupling structure and a waveform adjustment circuit connected to the coil is an integer multiple of a wavelength of an applied power; a substrate mounting table in the substrate processing space and supporting the substrate including grooves having high aspect ratios with a silicon-containing layer disposed thereon; a substrate transfer port at a wall of the substrate processing chamber; a substrate mounting table elevator moving the substrate mounting table upward/downward; an oxygen gas supply system to supply an oxygen-containing gas into the plasma generation space; and an exhaust unit exhausting gas from the substrate processing chamber. | 2014-04-17 |
20140106574 | GAPFILL OF VARIABLE ASPECT RATIO FEATURES WITH A COMPOSITE PEALD AND PECVD METHOD - Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps. | 2014-04-17 |
20140106575 | DIRECTED SELF-ASSEMBLY OF BLOCK COPOLYMERS USING LASER ANNEALING - Methods for performing directed self-assembly (DSA) of block copolymer (BCP) material on a substrate are disclosed. The BCP is disposed over a patterned neutral layer made from a random copolymer. The BCP is annealed with a laser to induce the directed self-assembly. The scan type may include single scan, multiple scan, or multiple scan with overlap. A variety of power settings and dwell times may be used within a single wafer to achieve multiple heating conditions within a single wafer. | 2014-04-17 |
20140106576 | INORGANIC POLYSILAZANE, SILICA FILM-FORMING COATING LIQUID CONTAINING SAME, AND METHOD FOR FORMING SILICA FILM - Disclosed is an inorganic polysilazane that undergoes less shrinkage during a calcination step in an oxidizing agent such as water vapor and is less prone to allow a silica film to suffer from the formation of cracks or peel off from a semiconductor substrate, and a silica film-forming coating liquid containing the inorganic polysilazane, and also provides an inorganic polysilazane and a silica film-forming coating liquid containing the same. The value of A/(B+C) is 0.9-1.5 and the value of (A+B)/C is 4.2-50. A=peak area within the range of from 4.75 ppm to less than 5.4 ppm. B=peak area within the range of from 4.5 ppm to less than 4.75 ppm. Peak area within the range of from 4.2 ppm to less than 4.5 ppm is represented by C in a | 2014-04-17 |
20140106577 | METHOD AND APPARATUS OF FORMING SILICON NITRIDE FILM - Provided is a method of forming a silicon nitride film on an object to be processed, which includes: supplying a silicon raw material gas into a processing chamber; and supplying a nitridant gas into the processing chamber, wherein supplying the silicon raw material gas includes an initial supply stage in which the silicon raw material gas is initially supplied and a late supply stage following the initial supply stage, wherein a first internal pressure of the processing chamber defined in the initial supply stage is lower than a second internal pressure of the processing chamber defined in the late supply stage. | 2014-04-17 |
20140106578 | Pierced flexible circuit and compression joint - An electrical interconnect system comprises: a flexible circuit having thereon a plurality of electrical contact pads; a contact strip comprising a plurality of electrical contacts aligned with respective pads on the flexible circuit; a compression member to engage the contacts with the pads; and, pierced areas on said pads to enhance the mechanical engagement between the contacts and the pads. | 2014-04-17 |
20140106579 | Compression connector system - An electrical interconnect system comprises: a clamping collar having a slot for receiving a bifurcated flexible circuit; a contact strip comprising a plurality of electrical contacts aligned with respective pads on the bifurcated flexible circuit when the legs of the bifurcated area are spread apart; and, a compression latch member to engage the clamping collar and compress the pads against their respective contacts on the contact strip. | 2014-04-17 |
20140106580 | RELAY, RELAY MODULE HAVING THE SAME, AND ELECTRICAL JUNCTION BOX - An object of the present invention is to provide a relay able to reduce a receiving space in a fitting direction between a terminal and a terminal fitting. A relay includes: a relay main body of which outer shape is in a rectangular parallelepiped shape; and four plate-shaped terminals projected from the relay main body and configured to be fitted with terminal fittings | 2014-04-17 |
20140106581 | COAXIAL CONNECTOR AND CONNECTOR UNIT - A coaxial connector is adapted to hold a connection object having a ground conductor and a signal conductor and is adapted to be fitted to a mating connector. The coaxial connector has a shell for holding the connection object. The shell comprises a first shell portion having a barrel-shaped shell contact portion, a second shell portion having shell connecting portions, positioning portions for positioning the connection object so that a contact portion of the signal conductor of the connection object is located inside the barrel-shaped shell contact portion as seen in a fitting direction of the coaxial connector and the mating connector, and fixing portions for fixing the connection object. | 2014-04-17 |
20140106582 | SYSTEM INTERCONNECT FOR INTEGRATED CIRCUITS - An electronic device for transmitting data is described herein. In some examples, the electronic device includes a package substrate, and a plurality of integrated circuits to be coupled to the package substrate, at least one integrated circuit comprising a topside connector or an edge connector to be coupled to a cable that is to couple to a cable receptacle. | 2014-04-17 |
20140106583 | GROUND INLAYS FOR CONTACT MODULES OF RECEPTACLE ASSEMBLIES - A receptacle assembly includes a receptacle housing and a contact module received in the housing. The contact module includes a tray having a cavity defined by inner surfaces of the tray. Ground inlays are received in the cavity along corresponding inner surfaces. The ground inlays have ground slats and ground flanges extending from the ground slats. A frame assembly is received in the cavity of the tray between the ground inlays. The frame assembly is electrically shielded by the ground inlays and has a plurality of receptacle signal contacts arranged in differential pairs carrying differential signals. The ground slats extend along opposite sides of corresponding pairs of the receptacle signal contacts and the ground flanges extend between pairs of the receptacle signal contacts. | 2014-04-17 |
20140106584 | PORTABLE ELECTRONIC DEVICE - A portable electronic device, for inserting and connecting an electrical connector, includes a housing assembly, an electrical socket disposed in the housing assembly and having a slot, a cover plate and an elastic member. The slot is used for inserting and connecting the electrical connector. The cover plate is pivotally connected to the second casing, and is adapted to pivot relative to the housing assembly between a first position and a second position. When the cover plate is at the second position, the cover plate and the housing assembly form an opening. When the cover plate is at the first position, the cover plate covers a part of the area of the opening and shields a part of the electrical socket. The elastic member is connected to both the second casing and the cover plate, and makes the cover plate to be located in the first position. | 2014-04-17 |
20140106585 | CONNECTOR DEVICE - A connector device is provided in which a fitting force acts on a female connector and a male connector by operating a lever from a fitting start operation position to a fitting end operation position. The connector device includes a semi-fitting detection portion and a pressing portion. The semi-fitting detection portion is located at a non-projecting position below a peripheral surface of a frame of the female connector and is shifted to a projecting position to project from the peripheral surface of the frame by a pressing force. The pressing portion is provided in the male connector, presses and shifts the semi-fitting detection portion to the projecting position when located at a fitting halfway position before a fitting end position, and stops pressing the semi-fitting detection portion when located at the fitting end position so as to shift the semi-fitting detection portion to the non-projecting position. | 2014-04-17 |
20140106586 | CHARGING PLUG WITH CONTACT-FREE SWITCH DEVICE - The invention relates to a charging plug for connection to a charging socket of a device which is intended to be charged, for example, a motor vehicle which is at least partially driven by electrical energy, or a device which provides charging energy. In order to prevent the charging plug from prematurely becoming defective as a result of corrosion or electro migration, there is provision according to the invention for a switching device of the charging plug to be arranged partially inside and partially outside an enclosed conduction chamber. | 2014-04-17 |
20140106587 | Cooled Power Connector with Shut Off Valve, Induction Heating System, and Cable for use with Connector - A connector for simultaneously connecting and disconnecting electrical and fluid paths is disclosed. The connector comprises an internal valve which activates fluid flow when the two sides of the connector are connected together to provide an electrical connection and deactivates the fluid flow when the connectors are disconnected. The connector bodies can be constructed of metal or other conductive materials providing an electrical connection, and can include holes or apertures to provide fluid paths through the connector bodies. Valves can be included in both mating connectors to prevent or allow fluid flow from both sides of the flow path. | 2014-04-17 |
20140106588 | CONNECTOR - A connector includes a plurality of connection terminals, a housing, an installing part and a sealing member. Cables are connected to the connection terminals. The housing holds the connection terminals. The installing part is formed by a part of the housing, and is fitted into a mounting hole of a connection counterpart. The sealing member is provided in the installing part, and seals between the installing part and the mounting hole. Connecting tab parts provided in the connection terminals are connected to a terminal block provided at the connection counterpart side. The connection terminals includes a confluent connection terminal including a plurality of cable connecting parts to which a plurality of the cables are connected and one of the connecting tab parts. | 2014-04-17 |
20140106589 | ELECTRICAL CONNECTOR COMPRISING A SEALING ELEMENT AND ASSEMBLY PROCESS - An electrical connector includes a connector body, the connector body having a plurality of seats for a plurality of terminal contacts. The electrical connector also includes at least one sealing element received in the connector body in a plane transverse to conductors associated with the plurality of terminal contacts, so as to provide a seal around the conductors. The connector body is provided with a guide passage for slidingly mounting a sealing layer within the connector body, by moving the sealing layer parallel to a plane thereof, in such a way that the sealing layer can be inserted into the connector body after the plurality of terminal contacts along with the respective conductors have been received in the connector body. The sealing layer engages slidingly around the conductors until a final mounting position is reached. | 2014-04-17 |
20140106590 | MULTI-FUNCTIONAL TRANSFER CONNECTOR FOR CONNECTING WITH DIFFERENT RECEPTACLES - A multi-functional transfer connector for connecting with different receptacles includes a first insulative housing ( | 2014-04-17 |
20140106591 | ELECTRICAL CONNECTOR ASSEMBLY, AND CONNECTOR FOR SUCH ASSEMBLY - The electrical connector assembly includes a first connector having a first housing, a second connector having a second housing, and a cover movably mounted on the housing. The housing of the second connector is movably mounted on the housing of the first connector. A lock that may be actuated is movably mounted on one of the housings. In the initial position of the cover, the cover covers or shields the lock. In the final position of the cover, the cover does not shield the lock. | 2014-04-17 |
20140106592 | COAXIAL CABLE CONNECTOR HAVING ELECTRICAL CONTINUITY MEMBER - A coaxial cable connector comprising a connector body; a post engageable with the connector body, wherein the post includes a flange; a nut, axially rotatable with respect to the post and the connector body, the nut having a first end and an opposing second end, wherein the nut includes an internal lip, and wherein a second end portion of the nut corresponds to the portion of the nut extending from the second end of the nut to the side of the lip of the nut facing the first end of the nut at a point nearest the second end of the nut, and a first end portion of the nut corresponds to the portion of the nut extending from the first end of the nut to the same point nearest the second end of the nut of the same side of the lip facing the first end of the nut; and a continuity member disposed within the second end portion of the nut and contacting the post and the nut, so that the continuity member extends electrical grounding continuity through the post and the nut is provided. | 2014-04-17 |
20140106593 | ELECTRICAL CONNECTOR ASSEMBLY AND METHOD OF ASSEMBLING THE SAME - An electrical connector assembly includes an insulating housing having a number of housing segments, a number of contacts received in the housing segments, a number of caps covering on the housing segments respectively and a number of clips assembled on the caps. Each of the caps includes a retaining mechanism defining an arm for operating by a user and a latch engaging the housing segment. Each of the clips is assembled on the arms of at least two caps so as to operate two caps together. | 2014-04-17 |
20140106594 | REPLACEABLE CONNECTOR - A connector includes a connector body, two or more connector pads within the connector body, and a releasable attachment mechanism for attaching the connector to a mobile computer. The connector may include a seal positioned around the outer edge of the connector body. The connector typically includes two or more connector pins each in contact with a respective connector pad. | 2014-04-17 |
20140106595 | Connecting Device and Combination of the Same and Expansion Card - A connecting device includes a riser bracket, a positioning mechanism and a riser card. The positioning mechanism has a plurality of standoffs and a latch disposed on the riser bracket. Each standoff has a head, a shoulder and a neck interconnecting the head and the shoulder. The latch is movable between a locking position for locking the riser card and a releasing position. The riser card is formed with a plurality of through holes corresponding in position to the standoffs. Each through hole has a large hole portion for extension of the head of a respective standoff and a small hole portion having an inner diameter that is equal to an outer diameter of the neck of the respective standoff. | 2014-04-17 |
20140106596 | Plug Arrangement for Connecting Electrical Conductors With An Electrical Assembly - A connector arrangement for connecting the bare ends of a plurality of insulated conductors to a horizontal row of first contacts arranged on an electrical device, respectively, including a main housing having a side portion containing a chamber in which the electrical device is mounted, a connector housing pivotally connected with the main housing for pivotal movement about a vertical pivot axis between engaged and disengaged positions, the connector housing supporting a horizontal row of conductor contacts arranged to engage the first contacts when the contact housing is in the engaged position, and a manually-operable locking arrangement for locking the connector housing in the engaged position. The locking arrangement includes a locking projection fixed to the main housing, a catch member movably connected with the connector housing, and an actuating member for displacing the catch member between locked and unlocked positions relative to the locking projection. | 2014-04-17 |
20140106597 | Connector Assembly With Chamber Block And Contact Position Assurance - A plug type connector is provided with chamber block. The chamber block includes a receiving chamber and a recess that intersects with the receiving chamber. The receiving chamber extends a length of the chamber block and includes a contact securing member with a catch. The recess includes an opening into which the catch protrudes into. | 2014-04-17 |
20140106598 | SPRING LOCK TYPE CONNECTOR AND METHOD OF ASSEMBLING IT - A spring lock connector has a male connector (M) with a cylindrical front receptacle ( | 2014-04-17 |
20140106599 | ELECTRICAL CONNECTOR HAVING IMPROVED RESILIENT CONTACT SO AS TO REALIZE BETTER RETAINING EFFECT - An electrical connector includes an insulative housing, a plurality of first contacts arranged in a side-by-side manner, and a resilient contact retained in the housing. The housing defines a mating face, a blocking face and a mating cavity disposed between the mating face and the blocking face. Each first contact defines a first contacting portion projecting into the mating cavity. The resilient contact defines a blocking piece abutting against the blocking face, a retaining leg extending out of the mating cavity, and latching arms extending into the mating cavity from the blocking piece. The latching arms can be easily released from a mating connector so as to realize a better retaining effect. | 2014-04-17 |
20140106600 | LEVER CONNECTOR - A lever connector includes a female connector, a male connector and a layer. The female connector includes a frame having a flange portion protruding toward a straight direction perpendicular to a direction in which the female connector and the male connector are to be fitted with each other. The flange portion includes a locking portion with flexibility. The lever includes a locked portion locked with the locking portion in a normal fitted state. The locking portion does not abut on a hole edge of an attachment hole formed on a panel in a state where the locked portion is locked with the locking portion, and abuts on the hole edge of the attachment hole in a state where the locked portion is not locked with the locking portion. | 2014-04-17 |
20140106601 | ELECTRICAL CONNECTOR AND SQUIB CONNECTION DEVICE - An electrical connector of the present invention includes a housing, an electrical terminal, and a moving member that has a moving member body and a detection portion. The housing is provided with a first step portion, and the detection portion is provided with a second step portion. When the moving member is at a first position, the second step portion comes into contact with the first step portion so as to prevent the moving member from moving forward. When the mating portion is completely fitted into a retainer, the detection portion becomes displaced toward the counter mating side due to being pressed by the retainer or the inflator housing, and the second step portion becomes separated from the first step portion so as to permit the moving member to move forward. Also, a squib connection device of the present invention includes this electrical connector. | 2014-04-17 |
20140106602 | SPRING LOCK TYPE CONNECTOR - A spring lock type connector has a male connector (M) with a front receptacle ( | 2014-04-17 |
20140106603 | SPRING LOCK CONNECTOR - A spring lock connector includes a female connector (F) with a lock arm ( | 2014-04-17 |
20140106604 | AIRFLOW GUIDE MEMBER AND CARD SOCKET ASSEMBLY WITH AIRFLOW GUIDE MEMBER - A card socket assembly includes a card socket and a non-conductive airflow guide member. The card socket includes a main body defining a slot, and two latches rotatably connected to opposite ends of the main body. The airflow guide member includes a main plate and an airflow guide plate. A bottom of the main plate is inserted into the slot of the card socket. Two notches are defined in a first end and a second end of the main plate opposite to the first end, to receive the latches. The airflow guide plate is formed on the first end of the main plate, and includes an airflow guide portion slanted relative to the main plate, to guide airflow away from the card socket. | 2014-04-17 |
20140106605 | RETENTION DEVICE AND ELECTRICAL CONNECTOR ASSEMBLY USED THEREOF - A retention device ( | 2014-04-17 |
20140106606 | VEHICLE TRANSMISSION AND CHARGE DEVICE - The vehicle transmission and charge device contains a casing, a power conversion module, a cable winding device, and at least a transmission cable. The casing has a number of openings and an axle, and a tongue piece. The power conversion module is inside the casing and contains a transformer module, a power input connector, and a power plug. The cable winding device is inside the casing and contains a wheel base, an elastic element, and a winding module. The winding module contains a power output connector and a circuit board. The transmission cable has one end electrically connected to the winding module and the other end connected to a head piece after running through an opening of the casing. A cigarette lighter plug is connected to the power input connector, and then plugged into a cigarette lighter receptacle of a vehicle. | 2014-04-17 |
20140106607 | ELECTRICAL CONNECTION BOX - An electrical connection box includes a bracket insertion member having an insertion hole for receiving an insertion plate of a fixing bracket on an automobile. The insertion hole includes edge insertion holes into which edges of the insertion plate of the fixing bracket are inserted. Additionally, a guide surface is formed on an opening of each edge insertion hole such that the guide surface extends obliquely out from the opining in directions opposite to the direction of insertion of the insertion plate into the insertion hole. Each guide surface extends out in the direction along which the edge insertion holes oppose each other and in directions orthogonal to the direction along which the edge insertion holes oppose each other. The dimension W between the outer edge of each opening and the outer edge of the respective guide surface is no less than the thickness t of the insertion plate. | 2014-04-17 |
20140106608 | Methods And Systems For Displaying A Product - A display system may include a retaining puck for retaining a product, the retaining puck including a main body having a side surface and a bracket recess, wherein at least a portion of the side surface is continuous except for the bracket recess, and a bracket having a mounting flange configured to mate with the bracket recess, wherein the mounting flange is received by the bracket recess, and an outer surface of the mounting flange is aligned with the continuous portion of the side surface of the main body. | 2014-04-17 |
20140106609 | Staggered Charging System - A consumer electronic system for holding and providing power to any number of consumer electronic devices includes any number of cradles in a staggered configuration, such that, displays of consumer electronic devices in each of the cradles are each visible without being substantially blocked by other consumer electronic devices. In one embodiment, the consumer electronic system for holding and providing power comprises multiple sub-systems, each having one or more cradles, such that, the sub-systems are joined to produce a consumer electronic system for holding and providing power to the desired number of possible consumer electronic devices at one time. | 2014-04-17 |
20140106610 | TABLE COUPLING SYSTEM WITH POWER AND DATA - A work surface coupling system has power and data capability with an elongate housing defining an internal passageway and having first and second coupling regions for coupling to one or more work surface. The housing may be a one-piece unit or multi-piece assembly, and can support at least one power or data outlet positioned therealong. The internal passageway unobtrusively supports a plurality of electrical conductors associated with power or data outlets. Optional features include one or more removable side panels, laterally-extending support pads, an accessory mounting surface, and various work surface accessories such as shelving, privacy panels, and lighting. | 2014-04-17 |
20140106611 | CONNECTOR PLUG HAVING AN LED ACTIVATED BY AN USER'S TOUCH - An improved apparatus for charging a cell phone battery in the dark. An LED and its control circuitry including a control switch are included in a USB connector to automatically illuminate a cell phone and its charging port or receptacle or jack, which happen to be located in an unlit or pitch black space, when a user attempts to insert a USB connector plug into the charging port for purposes of charging the battery. The LED is automatically energized by the user's mere touching of the overmold of the USB connector at its flat or bottom side, without otherwise manually operating the control switch, and thereby eliminating hunting in the dark for a control switch on the USB connector. This apparatus is useful with both standard charging equipment and with dongle charging equipment. | 2014-04-17 |
20140106612 | COAXIAL CABLE CONNECTOR WITH INTEGRAL CONTINUITY CONTACTING PORTION - A coaxial cable connector for coupling an end of a coaxial cable to a terminal is disclosed. The connector has a coupler adapted to couple the connector to a terminal, a body assembled with the coupler and a post assembled with the coupler and the body. The post is adapted to receive an end of a coaxial cable. The coupler, the body or the post has an integral, monolithic contacting portion. When the connector is coupled to the terminal and a coaxial cable is received by the body, the contacting portion provides for electrical continuity from an outer conductor of the coaxial cable through the connector to the terminal other than by a separate component. The contacting portion is formable and forms to a contour of at least one of the body and the coupler when the body at least partially assembles with the coupler. | 2014-04-17 |
20140106613 | COAXIAL CABLE CONNECTOR WITH INTEGRAL RFI PROTECTION - A coaxial cable connector for coupling an end of a coaxial cable to a terminal is disclosed. The connector has a coupler adapted to couple the connector to a terminal, a body assembled with the coupler and a post assembled with the coupler and the body. The post is adapted to receive an end of a coaxial cable. The post has an integral contacting portion that is monolithic with at least a portion of the post. When assembled the coupler and post provide at least one circuitous path resulting in RF shielding such that RF signals external to the coaxial cable connector are attenuated, such that the integrity of an electrical signal transmitted through coaxial cable connector is maintained regardless of the tightness of the coupling of the connector to the terminal. | 2014-04-17 |
20140106614 | COAXIAL CABLE CONNECTOR WITH A COMPRESSIBLE FERRULE - A coaxial connector for coupling an end of a coaxial cable to a terminal is disclosed. The coaxial cable connector includes a body, a retainer, a coupler, a ferrule, and a shell. The retainer engages the body and rotatably engages the coupler. The ferrule slidingly engages at least a portion of the retainer and at least one portion of the body. The ferrule engages at least a portion of the cable outer conductor. The shell slidingly engages at least a portion of the rear end of the body. A sealing ring engages the rear end of the body. Upon compression of the coaxial cable connector the sealing ring engages the jacket of the coaxial cable. | 2014-04-17 |