16th week of 2014 patent applcation highlights part 22 |
Patent application number | Title | Published |
20140103912 | STEERING ANGLE SENSOR FOR MOTOR VEHICLES - A steering angle sensor for motor vehicles for determining the steering angle of a steering element of a steering wheel assembly, which is rotatable during a steering movement is provided. The steering angle sensor comprises a rotatably mounted drive element which during a rotary movement of the steering element likewise performs a rotary movement, and a rotatably mounted driven element which is in engagement with the drive element and is driven by the same The steering angle is determined by detecting the rotary movement and/or the angle of rotation of the driven element. The drive element and/or the driven element include elastic means via which the drive element and the driven element are braced against each other. | 2014-04-17 |
20140103913 | POSITION SENSOR MODULE - A position sensor module ( | 2014-04-17 |
20140103914 | DISPLACEMENT DETECTION APPARATUS - A displacement detection apparatus includes a scale unit and a detection head unit. The scale unit has a reference track unit and sub-track units, the pitch directions of these units being different from one another. The detection head unit has three or more detection units configured to read scales of the reference track unit and the sub-track units and to output signals in accordance with the read scales. The three detection units detect displacement in two orthogonal directions on a plane parallel to a plane along which the detection head unit moves. | 2014-04-17 |
20140103915 | Intelligent Field Shaping for Magnetic Speed Sensors - The present disclosure provides for techniques to improve the sensitivity of magnetic sensor systems. One embodiment of a magnetic sensor system includes a magnetic biasing body comprised of a hard magnetic material and including a recess therein. The recess corresponds to a magnetic flux guidance surface of the magnetic biasing body. The magnetic sensor system also includes a magnetic sensing element arranged in or proximate to the recess. A magnetic flux concentrator, which is made of a soft magnetic material, is disposed in the recess between the magnetic flux guidance surface and the magnetic sensing element. Other techniques are also described. | 2014-04-17 |
20140103916 | ACCELERATOR OPENING DEGREE DETECTION DEVICE - An accelerator opening degree detection device is equipped with: a rotor that is attached to the shaft of a handlebar and rotates in conjunction with the operation of an accelerator grip; magnets attached to the rotor; magnetic sensors that detect the magnetic force of the magnets; a case that houses the rotor and the magnetic sensors, and is attached to the handlebar; and a sensor holder to which the magnetic sensors are attached, and which is housed in the case on the opposite side of the rotor with respect to the accelerator grip. The sensor holder has an inner diameter protruding part that protrudes at a location opposing the magnets, this location being on the inside of the rotor in the circumferential direction, and the magnet sensors are arranged on the inner diameter protruding part. | 2014-04-17 |
20140103917 | SHEET CONDUCTANCE/RESISTANCE MEASUREMENT SYSTEM - An apparatus for testing of electrical or physical properties of a material include a single coil sensor mounted adjacent to a sample of the material. Sheet conductance of a wide variety of materials may be measured using the single coil to determine if the material conforms to generally accepted standards for the use to which the material will be put. In some examples, the material is a semiconductor wafer or flat panel. In other examples, the material is the body tissue of a patient. A non-invasive technique using the apparatus is also disclosed for monitoring the health of patient tissue such as musculature, and/or to determine whether healthy circulation is present, by measuring the conductance of the patient tissue in response to a magnetic field applied by the single coil. The single coil may be hand held, or it may be movable using an automated positioning system under computer control. | 2014-04-17 |
20140103918 | CURRENT SENSOR - A current sensor includes a first current path, a second current path disposed parallel to the first current path, and a pair of first magnetic sensors. The first current path has a pair of main surfaces and includes a plate-shaped first region. The second current path has a pair of main surfaces and includes a plate-shaped second region. The first magnetic sensors are arranged on the respective main surfaces in the first region such that sensing axes of the first magnetic sensors are parallel to the respective main surfaces in the first region. The first magnetic sensors are configured to sense a magnetic field generated by a target current flowing through the first region. The second region is placed such that the main surfaces in the second region are perpendicular to the sensing axes of the first magnetic sensors. | 2014-04-17 |
20140103919 | MAGNETO-OPTIC SURFACE - A magneto-optic surface includes a support; at least two moving elements; each of the moving elements including at least one anchoring point to the support and at least one moving part movable with respect to the support, the moving part including at least one magnetic part; the support and the moving elements being laid out in such a way that under the effect of an external magnetic field, at least one of the moving elements moves with respect to the support such that the optical properties of the magneto-optic surface are modified. | 2014-04-17 |
20140103920 | MAGNETIC FIELD DETECTION DEVICE AND METHOD FOR DETECTING A MAGNETIC FIELD - A magnetic field detection device and a corresponding method for detecting a magnetic field. The magnetic field detection device includes a coil core, a receiving coil coupled to the coil core, a plurality of electrically separated field coils coupled to the coil core, an excitation unit for generating a magnetic field excitation via a particular excitation current of the plurality of field coils coupled to the coil core and an evaluation unit for evaluating a magnetic field signal received via a receiving coil coupled to the coil core. | 2014-04-17 |
20140103921 | CIRCUIT AND METHOD FOR BIASING A PLATE-SHAPED SENSOR ELEMENT OF SEMICONDUCTOR MATERIAL - Circuit and method for biasing a plate-shaped sensor element ( | 2014-04-17 |
20140103922 | DIFFERENTIAL TRANSFORMER TYPE MAGNETIC SENSOR AND IMAGE FORMING APPARATUS - A differential transformer type magnetic sensor includes a drive coil, a reference coil, and a detection coil. These coils are formed by repeating a linear pattern that is formed on the first surface, penetrates the board, is formed on the second surface, penetrates the board, and returns to the first surface. The reference coil is disposed at a side of one end of the drive coil, and the detection coil is disposed at a side of the other end of the drive coil. Induced current flows to each of the reference coil and the detection coil due to magnetic flux generated as drive current flows to the drive coil. The reference coil and the detection coil are electrically connected so that a direction of the induced current flowing along the reference coil and a direction of the induced current flowing along the detection coil are opposite to each other. | 2014-04-17 |
20140103923 | Using Single Continuous Pulses for Manipulating Water and Fat Signals in Magnetic Resonance Imaging - A method for manipulating magnetic resonance signals of a first chemical species and a second chemical species includes determining a time required to have spins of protons corresponding to the first chemical species acquire a phase shift of 90 degrees relative to spins of protons corresponding to second chemical species. A first pulse portion having a pulse amplitude and a first constant phase is defined. A second pulse portion having the pulse amplitude and a second constant phase, the second constant phase being different from said first constant phase by a multiple of 90 degrees is also defined. Next, a single continuous composite pulse is generated by concatenating the first pulse portion and the second pulse portion, wherein the single continuous composite pulse has a duration such that a time difference between center of the first pulse portion and center of the second pulse portion corresponds to the determined time. Then, the single continuous composite pulse is applied to a plurality of radio frequency coils. | 2014-04-17 |
20140103924 | Heteronuclear Nuclear Magnetic Resonance Fingerprinting - Apparatus, methods, and other embodiments associated with heteronuclear nuclear magnetic resonance fingerprinting (NMRfp) are described. One example apparatus includes individually controllable radio frequency transmission coils configured to apply varying NMRfp RF excitations to a sample. The NMR apparatus may apply excitations in parallel. The excitations cause different nuclei to produce different signal evolutions. Different pairs of nuclei may produce different signal evolutions depending on quantum correlations between the types of nuclei. | 2014-04-17 |
20140103925 | Determining Electrical Properties of Tissue Using Complex Magnetic Resonance Images - Exemplary embodiments are directed to estimating an electrical property of tissue using Magnetic Resonance (MR) images. In exemplary embodiments, complex MR images of a target tissue are obtained. An estimated value of an electrical property of the target tissue is determined based on complex values of the pixels in the complex MR images. The complex values are proportional to the product of the transmit radio frequency magnetic field and the receive RF magnetic field. | 2014-04-17 |
20140103926 | NOVEL MAGNETIC RESONANCE-BASED SYSTEMS FOR DETECTING CONTAMINATING PARTICLES AND METHODS THEREOF - The present invention provides an MRI-based hazard screening system for detecting contaminating particles within or on the surface of an object, the system characterized by
| 2014-04-17 |
20140103927 | LOW-FIELD MAGNETIC RESONANCE SYSTEM (LF-MRS) FOR PRODUCING AN MRI IMAGE - Low-field magnetic resonance system (LF-MRS) for producing a high-Q MRI image, said LF-MRS comprising: a. Low-field magnetic resonance device (LF-MRD); said LF-MRD is characterized by Q-value, Q | 2014-04-17 |
20140103928 | METHOD AND MAGNETIC RESONANCE DEVICE FOR IMAGE ACQUISITION - In a method and magnetic resonance apparatus for acquiring image data using a sequence in which k-space corresponding to the imaging area is scanned in a first region of k-space, which does not include the center of k-space, radially along spokes emanating from the center of k-space, with at least two phase coding gradients being completely ramped up before the excitation pulse, and in a second central region of k-space, which remains without the first region, in a Cartesian manner. For contrast increase, a pre-pulse is provided before a predetermined number of individual measurements. A portion of the measurement points of the second region of k-space, which portion is situated nearest the center of k-space, is scanned as central measurement points after the first administration of the pre-pulse immediately following a zero crossing of the contrast-relevant magnetization of one of at least two materials in the image. | 2014-04-17 |
20140103929 | SYSTEMS AND METHODS FOR SUSCEPTIBILITY TENSOR IMAGING IN THE P-SPACE - Systems and methods for susceptibility tensor imaging in the p-space are disclosed. An example method includes using an MRI system to generate an MRI signal of an object. The method may also include conducting a multipole analysis of the MRI signal in a subvoxel Fourier spectral space (p-space). Further, the method may include sampling the p-space with pulsed field gradients to determine a set of dipole and quadrupole susceptibility tensors. The method may also include generating an image of the object based on the set of dipole and quadrupole susceptibility tensors for depicting a characteristic of the object. | 2014-04-17 |
20140103930 | VENTILATION DEVICE FOR MAGNETIC REASONANCE IMAGING SYSTEM AND MAGNETIC REASONANCE IMAGING SYSTEM - A ventilation device for an MRI system and an MRI system are presented. The ventilation device has a fan and an adjustment component. The fan is used to generate a flow of air past an examination subject in the MRI system, and the adjustment component is used to adjust an operating parameter of the fan according to a heat signal indicating variation of heat in the examination subject. The ventilation device and MRI system enhance the user's experience of the MRI system, increase the examination subject's ability to undergo examinations of high SAR and long duration, and reduce medical risks associa. | 2014-04-17 |
20140103931 | HIGH FREQUENCY COIL UNIT AND MAGNETIC RESONANCE IMAGING APPARATUS - The present invention is directed to an elliptical birdcage coil which reduces time and effort upon manufacturing and production cost, with less variations in performance. There is provided a high frequency coil unit made up of the elliptical birdcage coil having plural capacitors arranged at least on either of the ring conductors and the rung conductors, the capacitance of the plural capacitors being uniform with respect to each conductor type on which the capacitors are placed. In this elliptical birdcage coil, a value of inductance and arrangement of the ring conductors and the rung conductors are determined in such a manner that the capacitance of the capacitors becomes identical with respect to each conductor type on which the capacitors are arranged. | 2014-04-17 |
20140103932 | SYSTEM AND METHOD FOR LIGHT INTENSITY MONITORING - A system is provided. The system includes a light emitting diode and a monitoring module. The monitoring module is communicably coupled to the light emitting diode. The monitoring module is configured to receive one or more signals indicative of power consumption of the light emitting diode. Further, the monitoring module is configured to determine a condition of the light emitting diode based, at least in part, on the received signals. | 2014-04-17 |
20140103933 | METHOD AND SYSTEM FOR ESTIMATING BATTERY CAPACITY IN A VEHICLE - A system and method is provided for estimating the capacity of a battery element in a vehicle, such as a hybrid electric vehicle. In one embodiment, the method determines if one or more threshold conditions have been met (e.g., conditions pertaining to battery temperature or battery state-of-charge (SOC)) and calculates the internal resistance of the battery element. When the threshold conditions have been met, the method uses the calculated internal resistance to estimate the capacity of the battery element. A corresponding battery system is also provided that includes a battery element, one or more battery sensors, and a control module configured to perform the method described above. | 2014-04-17 |
20140103934 | BATTERY DIAGNOSIS DEVICE AND METHOD - An apparatus is disclosed that includes a resistance measuring unit operable to determine a solution resistance Rsol and a charge transfer resistance Rct of a battery; and at least one computer-readable non-transitory storage medium comprising code, that, when executed by at least one processor, is operable to provide an estimate of the present value of the battery by: comparing Rsol and Rct to historical deterioration transition information; estimating the number of remaining charge cycles before a discharge capacity lower limit is reached by the battery using the comparison; and estimating the number of remaining charge cycles before a discharge time lower limit is reached by the battery using the comparison. The estimate of the present value of the battery includes the smaller of the number of remaining charge cycles before a discharge capacity lower limit is reached or the number of remaining charge cycles before a discharge time lower limit is reached. | 2014-04-17 |
20140103935 | OPTICAL TO OPTICAL TIME AND SPATIAL RESOLUTION ENHANCEMENTS FOR IMPROVING CHARACTERIZATION OF SECONDARY ELECTRON EMISSION AND CONTROL FOR ETCH-, ELECTRON-, AND ION-BEAM DEVICES - In decreasing the electron beam duration required for increased time resolution, the average beam current decreases, degrading measurement sensitivity and limiting practical systems to a time resolution of several hundred picoseconds. Optical non-invasive or non-destructive enhancements permits femto-second measurements and a new regime of internal device and process evaluation and quality control in integrated circuit (IC) manufacture, at every stage from the initial wafer to the point at which the wafer is diced into individual ICs. | 2014-04-17 |
20140103936 | METHOD FOR MONITORING INSULATION FAULTS IN AN ELECTRIC NETWORK AND VEHICLE COMPRISING AN INSULATION FAULT MONITOR - A method for monitoring an insulation fault in an electric network with at least one electric power system supplying electric power to one or more electric loads, and at least one insulation resistance monitor is provided, wherein the at least one electric power system includes at least one electrical power source, and wherein the at least one insulation resistance monitor monitors an insulation resistance between terminal leads of the at least one electric power source and at least one reference potential. The steps are performed of disconnecting the at least one electric power source from the one or more loads by opening each terminal lead; measuring the insulation resistance between the electric circuit of at least one electrical power source and the reference potential; measuring the insulation resistance for the total electric network; closing the second terminal lead with the first terminal lead open; and measuring the insulation resistance for the total electric network. | 2014-04-17 |
20140103937 | State of Health Estimation of Power Converters - Systems, methods and devices which utilize Spread Spectrum Time Domain Reflectometry (SSTDR) techniques to measure degradation of electronic components are provided. Such measurements may be implemented while the components “live” or otherwise functioning within an overall system. In one embodiment, monitoring a power converter in a high power system is accomplished. In this embodiment, degradation of components within the power converter (e.g. metal-oxide-semiconductor field-effect transistors (MOSFETs), capacitors, insulated-gate bipolar transistors (IGBTs), and the like) may be monitored by processing data from reflections of an SSTDR signal to determine changes in impedance, capacitance, or any other changes that may be characteristic of components degrading. For example, an aging MOSFET may experience an increase of drain to source resistance which adds additional resistance to a current path within a power converter. Such a change is able to be analyzed monitored upon processing the reflected test signals. | 2014-04-17 |
20140103938 | SELF-REGULATING HEATER CABLE FAULT DETECTOR - A method of determining a condition of a heater cable, the method including the steps of providing an electrical voltage to the heater cable; and analyzing electrical signals generated in the heater cable to determine the condition of the heater cable. | 2014-04-17 |
20140103939 | DETECTION OF AN INSULATION DEFECT - An electrical power supply device includes a DC voltage source with terminals, a controller, and an insulation-defect detecting device for detecting an insulation defect of the voltage source. The device has input terminals connected to source terminals, and circuits connected between respective input terminals and an intermediate point. The insulation-defect current-detection circuit connects between ground and the intermediate point. Both circuits have current-limiter circuits that open and close a connection between respective inputs and the intermediate point. Both current-limiter circuits are rated for traversal by a current of less than a standardized safety threshold when the first current-limiter circuit is closed and one of the terminals of the DC voltage source is shorted to ground. The control circuit is configured to simultaneously keep one current-limiter circuits open and the other closed. | 2014-04-17 |
20140103940 | SENSOR FOR WEAR MEASUREMENT, METHOD OF MAKING, AND METHOD OF OPERATING SAME - A wear sensor comprising:
| 2014-04-17 |
20140103941 | CAPACITIVE SENSING ARRAY DEVICE WITH HIGH SENSITIVITY AND ELECTRONIC APPARATUS USING THE SAME - A capacitive sensing array device of an electronic apparatus includes sensing electrodes, a shielding conductor layer, a coupling signal source, a constant voltage source and switch modules. The coupling signal source provides a coupling signal coupled to an object. The constant voltage source provides a constant voltage to the shielding conductor layer to form a stable vertical parasitic capacitor between the shielding conductor layer and each sensing electrode. Each switch module is electrically connected to the constant voltage source via the corresponding sensing electrode. When one sensing electrode is selected to perform sensing, the corresponding switch module is configured as an open-circuited state such that the selected sensing electrode is disconnected from the constant voltage source, while the other sensing electrodes are electrically connected to the constant voltage source to form a stable horizontal parasitic capacitor between the selected sensing electrode and the other sensing electrodes. | 2014-04-17 |
20140103942 | SENSOR FOR WEAR MEASUREMENT, METHOD OF MAKING, AND METHOD OF OPERATING SAME - A wear sensor comprising:
| 2014-04-17 |
20140103943 | FINGERPRINT SENSOR AND BUTTON COMBINATIONS AND METHODS OF MAKING SAME - It will be understood by those skilled in the art that there is disclosed in the present application a biometric sensor that may comprise a plurality of a first type of signal traces formed on a first surface of a first layer of a multi-layer laminate package; at least one trace of a second type, formed on a second surface of the first layer or on a first surface of a second layer of the multi-layer laminate package; and connection vias in at least the first layer electrically connecting the signal traces of the first type or the signal traces of the second type to respective circuitry of the respective first or second type contained in an integrated circuit physically and electrically connected to one of the first layer, the second layer or a third layer of the multilayer laminate package. | 2014-04-17 |
20140103944 | FAST RESPONSE CAPACITIVE GAUGING SYSTEM FEATURING STEEP SLOPE FILTER DISCRIMINATION CIRCUIT - The high speed, high accuracy capacitive gauging system employs an oscillator fed through steep slope filter that is discriminates between very small changes in capacitance even in the presence of electrical noise. During intervals when the probe tip is retracted, the oscillator frequency is calibrated to match the sweet spot in the center of the linear operative region of the steep slope filter. This calibrates the system to overcome the effects of varying temperature and humidity in the manufacturing environment. | 2014-04-17 |
20140103945 | APPARATUS AND METHOD FOR DEMONSTRATING QUANTIZED CONDUCTANCE - A lab experiment device and method that demonstrate quantized conductance as a macroscopic gold wire is elongated and broken. The device utilizes a mechanically controlled break junction to demonstrate conductance quantization. A preferred assembly includes a rigid plate with a block to which a micrometer mounts. Spaced posts are mounted to the plate forming a gap between the posts and the block, and a flexible beam is seated against the posts with the anvil of the micrometer seated against the beam. A wire that is mounted to the beam elongates when the anvil forces the beam into a bending configuration. By passing current through the wire and detecting the voltage through a constriction formed in the wire, one can witness conductance quantization as the wire elongates at the constriction to form a conductor of one atom. | 2014-04-17 |
20140103946 | Device for Actively Improved Impedance Synthesis - An impedance control device for tuning a device under test comprising: a first terminal port arranged for connecting a device under test, a second terminal port arranged for connecting a termination, a first signal path for a signal travelling between the first and the second terminal port, first coupling means arranged for picking up a part of the signal travelling in the first signal path, a second signal path arranged for receiving the part of the signal from the first coupling means, said second signal path comprising a correction circuit for adapting as a function of frequency the amplitude and phase of the received part of the signal, second coupling means arranged for coupling back into the first signal path an adapted signal outputted by the correction circuit, and an attenuator and phase shifter for applying attenuation and phase shifting on the signals travelling between the first and the second terminal port. | 2014-04-17 |
20140103947 | THERMAL RELIABILITY TESTING SYSTEMS WITH THERMAL CYCLING AND MULTIDIMENSIONAL HEAT TRANSFER - Devices, methods, and systems for facilitating heat transfer around an electronic component during thermal-cycle testing are presented. A system may include a core, a plurality of solid state heating/cooling devices, and a plurality of heat sinks. The core defines one or more cavities for receiving an electronic component. The system may include an air mover and a duct. In operation, the system may cool an electronic component to sub-ambient temperatures and heat it to above the boiling point of water. A method of thermal-cycle testing may include a core defining a cavity for receiving an electronic component, selectively inducing said heating/cooling devices to operate in a heating mode or a cooling mode, and measuring and recording conditions during the test. | 2014-04-17 |
20140103948 | PROBE CARD HAVING CONFIGURABLE STRUCTURE FOR EXCHANGING OR SWAPPING ELECTRONIC COMPONENTS FOR IMPEDANCE MATCHING - A probe card having a configurable structure for exchanging/swapping electronic components for impedance matching is provided. In the probe card, an applied force is exerted on the electronic component so as to make the electronic component electrically connected with at least one conductive contact pad of a supporting unit. The supporting unit is a circuit board or a space transformer. In order to facilitate the exchange or swap of the electronic component, the applied force can be removed. The probe card includes a pressing plate which can be moved between a pressing position and a non-pressing position. The pressing plate has a pressing surface which is contacted with the top end of the electronic component while the pressing plate is in the pressing position. Therefore, the applied force can be generated or removed by changing the positioning of the pressing plate. | 2014-04-17 |
20140103949 | Electrically Conductive Kelvin Contacts For Microcircuit Tester - Terminals of a device under test are connected to corresponding contact pads or leads by a series of electrically conductive contacts. Each terminal testing connects with both a “force” contact and a “sense” contact. In one embodiment, the sense contact partially or completely laterally surrounds the force contact, so that it need not have its own resiliency. The sense contact has a forked end with prongs that extend to opposite sides of the force contact. Alternatively, the sense contact surrounds the force contact and slides laterally to match a lateral translation component of a lateral cross-section of the force contact during longitudinal compression of the force contact. Alternatively, the sense contact includes rods that have ends on opposite sides of the force contact, and extend parallel. | 2014-04-17 |
20140103950 | GUIDED WAVE RADAR PROBE WITH LEAK DETECTION - A probe defining a transmission line for use with a measurement instrument includes a pulse circuit connected to the probe for generating pulses on the transmission line and receiving reflected pulses on the transmission line. The probe comprises a conductive outer sleeve for mounting to a process vessel. A center conductor is coaxial with the outer sleeve for conducting the pulses. A primary seal element between the outer sleeve and the center conductor is spaced a select distance from a near end of the outer sleeve. A secondary seal element between the outer sleeve and the center conductor is spaced proximate the near end of the outer sleeve, to define a generally tubular space between the primary seal element and the secondary seal element. A dielectric insert fills a portion of the tubular space proximate the secondary seal element. A leak detection tube is in the tubular space between the dielectric insert and the primary seal element. The leak detection tube has an inner diameter greater than an outer diameter of the center conductor to define a void. The dielectric insert and the leak detection tube provide a substantially continuous uniform impedance under dry conditions. | 2014-04-17 |
20140103951 | AUTOMATIC PROBE GROUND CONNECTION CHECKING TECHNIQUES - A test system can include a probe suitable to be coupled between a test measurement device and a device under test (DUT). The probe can include a signal input to receive an active signal from the DUT and a signal output to provide the active signal to the test measurement device. The probe can also include an input ground to connect to the DUT ground and an output ground to connect to the test measurement device ground. A probe ground connection checking device can automatically determine whether the probe ground connections to the DUT ground and test measurement device ground are solid. | 2014-04-17 |
20140103952 | GROUND CONTACT OF AN INTEGRATED CIRCUIT TESTING APPARATUS - A ground electrical contact for an integrated circuit (IC) testing apparatus that comprises: a rigid bottom member having two planar surfaces that slope towards each other, so that the bottom member forms a partial wedge shape with the top end of the wedge being narrower than the bottom end; a flexible top member having two arms extending over said bottom member such that the top member forms an inverted U-shape, said two arms having an inwards bias such that an inner surface of each arm is pressed in contact with each planar surface; and a compressible member located between the narrower end of said bottom member and a bifurcation inner surface, which is an inner surface where the two arms bifurcate in the top member. The bottom member and top member are made of an electrically conductive material. | 2014-04-17 |
20140103953 | CHUCKS FOR SUPPORTING SOLAR CELL IN HOT SPOT TESTING - In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a cavity between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion. | 2014-04-17 |
20140103954 | TEST SYSTEM WITH ROTATIONAL TEST ARMS FOR TESTING SEMICONDUCTOR COMPONENTS - A test system with rotational test arms for testing semiconductor components includes a transport device, a first test socket, a second test socket, a first test arm, and a second test arm. The first test socket and the second test socket are electrically connected to different test signals respectively and correspond to the first test arm and the second test arm. The first test arm and the second test arm test arms operate rotationally to carry and place the semiconductor components to the transport device, the first test socket and the second test socket, so the test time is improved. | 2014-04-17 |
20140103955 | SYSTEM AND METHOD FOR AUTOMATED FAILURE DETECTION OF HOLD-UP POWER STORAGE DEVICES - A fault detection circuit is utilized to automatically detect faults in hold-up power storage devices. The fault detection circuit includes a hold-up monitoring circuit and a memory device. The hold-up monitoring circuit is connected to monitor output of the hold-up power storage device, wherein the hold-up monitoring circuit measures a duration of time that the hold-up power storage device provides sufficient power following a loss of normal power and detects faults based on the measured duration of time. The memory device is connected to store the duration of time measured by the hold-up power storage device following a loss of normal power | 2014-04-17 |
20140103956 | POWER SUPPLY DETECTION CIRCUIT AND METHOD - A power supply detection circuit includes a controller including a power module for supplying an input voltage to a to-be-tested power supply unit, a controlling module, a signal module, and a detection module, a resistor, and a MOSFET. A first end of the resistor connects an output end of the power supply unit. A second end of the resistor connects to the MOSFET. The MOSFET connects to the signal module. The detection module connects the output end. The control module controls the signal module to generate a pulse signals. The MOSFET is turned on to connect the resistor to the power supply unit to generate a fast-rising current when the pulse signal is in a high level. The detection module detects an output voltage of the output end, to confirm whether the output voltage is equal to the input voltage. This patent further discloses a power supply detection method. | 2014-04-17 |
20140103957 | REACTIVE MATERIAL FOR INTEGRATED CIRCUIT TAMPER DETECTION AND RESPONSE - The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material. An exothermic reaction in the at least one reactive material causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes a substrate, at least one gate on the substrate, and a reactive material between a first well and a second well of the at least one gate. A reaction in the reactive material causes a short in the gate. | 2014-04-17 |
20140103958 | PROGRAMMABLE LOGIC DEVICE AND METHOD FOR DRIVING PROGRAMMABLE LOGIC DEVICE - Configuration is performed in accordance with a plurality of states when power supply voltage is supplied intermittently. At the time of start of supply of power supply voltage with configuration, a programmable logic device is sequentially changed into a first state where configuration data is not set in a configuration memory, a second state where the configuration memory is initialized, and a third state where the configuration data can be set in the configuration memory. At the time of start of supply of power supply voltage without configuration, the programmable logic device is sequentially changed into a fourth state where the configuration data is not set in the configuration memory and the third state. The first to fourth states are switched to any one of the states by control of a first state signal and a second state signal. | 2014-04-17 |
20140103959 | Architectural Floorplan for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node or Smaller - A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer. | 2014-04-17 |
20140103960 | PROGRAMMABLE LOGIC DEVICE - To obtain a PLD that achieves high-speed configuration capable of dynamic configuration, consumes less power, and has a short startup time and a PLD that has a smaller number of transistors or a smaller circuit area than a PLD using an SRAM as a configuration memory, a plurality of logic elements arranged in an array and a switch for selecting electrical connection between the logic elements are provided. The switch includes a first transistor including a multilayer film including an oxide layer and an oxide semiconductor layer, a node that becomes floating when the first transistor is turned off, and a second transistor in which electrical continuity between a source and a drain is determined based on configuration data held at the node. | 2014-04-17 |
20140103961 | PHASE FREQUENCY DETECTOR CIRCUIT - A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal. | 2014-04-17 |
20140103962 | HIGH-SPEED GATE DRIVER FOR POWER SWITCHES WITH REDUCED VOLTAGE RINGING - A fast power switch comprises one or more field-effect transistors, such as pull-up and pull-down transistors, that are coupled to a load. Respective driver electronic circuits for each of the field-effect transistors include parallel first and second drivers with a shared driver output coupled to a gate of the field-effect transistor. The first and second drivers are operative to switch the shared driver output for the appropriate field-effect transistor in response to a transition (e.g., low-to-high or high-to-low) at a driver input terminal. A control circuit enables the stronger second driver in response to a transition at the driver input terminal and subsequently disables the second driver once a transition threshold at the gate of the field-effect transistor(s) is crossed. The weaker first driver is sized to damp reactive energy at the load to minimize ringing. | 2014-04-17 |
20140103963 | CURRENT DRIVER WITH OUTPUT CURRENT CLAMPING - In one aspect, a current driver, includes an operational amplifier that includes a first input port configured to receive a reference signal and a second input port configured to receive a variable signal. The variable signal is a function of an output current of the current driver. The reference signal corresponds to a selected maximum output current of the current driver. The current driver also includes a feedback transistor comprising a gate coupled to the output of the operational amplifier and a summing junction coupled to a drain of the feedback transistor and configured to receive a signal from the drain to enable clamping of the output current of the current driver to the maximum output current when the variable signal exceeds the reference signal. The summing junction is coupled to a set of transistors configured to provide the output current of the current driver. | 2014-04-17 |
20140103964 | Output Driver Having Improved Electromagnetic Compatibility (EMC) and Associated Methods - An integrated circuit includes an output driver circuit having a plurality of output driver devices connected in a parallel arrangement and an output driver controller that is capable of individually controlling the conducting states of the output driver devices. In at least one embodiment, the controller is capable of achieving any of a plurality of different fall times (and/or rise times) in an output signal by appropriately controlling the conducting states of the output devices if a change in the state of the output signal is desired, in some implementations, the controller is capable of achieving different waveshapes during rising and/or failing edges of an output signal. | 2014-04-17 |
20140103965 | TWO-STAGE POST DRIVER CIRCUIT - A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress. | 2014-04-17 |
20140103966 | METHOD OF CONTROLLING TWO-STAGE POST DRIVER CIRCUIT - A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress. | 2014-04-17 |
20140103967 | LEVEL SHIFTERS, METHODS FOR MAKING THE LEVEL SHIFTERS AND METHODS OF USING INTEGRATED CIRCUITS - A method of making a level shifter includes coupling a driver stage between an input end and an output end, the driver stage comprising a first transistor and a second transistor. An inverter having an input is coupled with the input end. A third transistor having a gate end is coupled with an output of the inverter, the third transistor having a terminal coupled to a pumped voltage (VPP). Additionally, the method includes coupling a fourth transistor with the output end, the fourth transistor having a terminal coupled to the pumped voltage. A fifth transistor is coupled with the input end, the fifth transistor having a terminal coupled to the third and fourth transistors. A sixth transistor is coupled with the input end, the sixth transistor having a terminal. | 2014-04-17 |
20140103968 | FIELD PLATE ASSISTED RESISTANCE REDUCTION IN A SEMICONDUCTOR DEVICE - Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described. | 2014-04-17 |
20140103969 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF DRIVING THE SAME - According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other. | 2014-04-17 |
20140103970 | SYSTEMS AND METHODS FOR DRIVING TRANSISTORS WITH HIGH TRESTHOLD VOLTAGES - System and method are provided for driving a transistor. The system includes a floating-voltage generator, a first driving circuit, and a second driving circuit. The floating-voltage generator is configured to receive a first bias voltage and generate a floating voltage, the floating-voltage generator being further configured to change the floating voltage if the first bias voltage changes and to maintain the floating voltage to be lower than the first bias voltage by a first predetermined value in magnitude. The first driving circuit is configured to receive an input signal, the first bias voltage and the floating voltage. The second driving circuit is configured to receive the input signal, a second bias voltage and a third bias voltage, the first driving circuit and the second driving circuit being configured to generate an output signal to drive a transistor. | 2014-04-17 |
20140103971 | METHODS AND APPARATUS FOR SOURCE-SYNCHRONOUS CIRCUITS - Source-synchronization between a source module and a responder module generally includes providing, at the source module, an initial determinism reconciliation signal, propagating the initial determinism reconciliation signal from the source module to the responder module and back to the source module to produce a received determinism reconciliation signal, and compensating for an intrinsic delay of the circuit based on the initial determinism reconciliation signal and the received determinism reconciliation signal. | 2014-04-17 |
20140103972 | DUTY CYCLE PROTECTION CIRCUIT - A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal. | 2014-04-17 |
20140103973 | SYSTEM AND METHOD FOR SCALING POWER OF A PHASE-LOCKED LOOP ARCHITECTURE - Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system. | 2014-04-17 |
20140103974 | Synchronization Signal Processing Method and Apparatus - The present invention provides a synchronization signal processing method and apparatus, which solves problems of low accuracy and a slow speed of synchronization operation executed on the synchronization signal. The specific steps include: acquiring multiple to-be-processed signals of a power supply, where the to-be-processed signals are signals changing periodically; generating a synchronization signal that has the same period as the to-be-processed signals by generating pulses in each period of the to-be-processed signals, where each period of the synchronization signal includes at least two pulses; detecting whether the synchronization signal is normal by determining whether parameters of all the pulses in the synchronization signal are accurate; and if the synchronization signal is normal, synchronizing the to-be-processed signals by performing time alignment on the pulses in the synchronization signal. The synchronization signal processing method and apparatus can be applied in a synchronization operation between signals. | 2014-04-17 |
20140103975 | CHARGING/DISCHARGING CIRCUIT AND PLL CIRCUIT USING THE SAME - A charging/discharging circuit includes a connection terminal, a reference current providing module, an up current module and a down current module. The down current module includes: a first switch module, having a first control terminal, for receiving the down signal to determine whether the first switch module is turned on; a first bias transistor, having a first terminal coupled to the connection terminal, a second terminal coupled to the first switch module, and a control terminal coupled to the reference current providing module; and a first capacitor simulation transistor, having a first terminal and a second terminal coupled to the control terminal of the first switch module, and a control terminal coupled to the control terminal of the first bias transistor. | 2014-04-17 |
20140103976 | MULTI-OUTPUT PHASE DETECTOR - Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference. | 2014-04-17 |
20140103977 | Use of Frequency Addition in a PLL Control Loop - A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added, to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal. | 2014-04-17 |
20140103978 | LOW POWER DATA RECOVERY - In one embodiment, an apparatus may include a pulse generator to generate an oversampled clock signal. The apparatus may also include a sample and hold unit to provide at least two differential input signals based on the oversampled clock signal. The apparatus may further include a conversion unit to generate a single-ended signal based on the at least two differential input signals. The apparatus may also include a counter to determine a count of rising and falling edges of the single-ended signal based on the oversampled clock signal. | 2014-04-17 |
20140103979 | METHOD AND SYSTEM FOR COMPENSATING MODE CONVERSION OVER A COMMUNICATIONS CHANNEL - A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power. | 2014-04-17 |
20140103980 | Method and Apparatus for Reducing the Contribution of Noise to Digitally Sampled Signals - The contribution of noise to digitally sampled signals is reduced using a statistical processor and a slope limiter. The statistical processor determines an average value (mean and/or standard deviation) of the filtered signal which is used to determine a slope limit corresponding to an expected maximum first derivative value of a target signal frequency. This slope limit is applied to constrain the output of an analog to digital converter, to prevent the output of the analog to digital converter from exceeding this maximum rate of rise or fall. By constraining the output of the analog to digital converter, it is possible to digitally sample analog signals without first utilizing an anti-aliasing filter, since the post processing of the digitally sampled signals limits the contribution of the higher frequency components of the signal to thereby enable a fully digital sampling and filtering circuit to be provided for receiving signals. | 2014-04-17 |
20140103981 | COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME - A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result. | 2014-04-17 |
20140103982 | POWER MANAGEMENT DEVICE AND POWER MANAGEMENT METHOD OF TOUCHABLE CONTROL SYSTEM - A power management device of a touchable control system includes a boost circuit boosting an output voltage according to an input voltage, a controlling signal for ballasting charging, and a controlling signal for boosting charging, a detection circuit detecting a predetermined value of the output voltage, a modulation circuit, and a loading circuit. The modulation circuit separately modulates the output voltage by the controlling signal for ballasting charging after the output voltage reaches the predetermined value and by the controlling signal for boosting charging before the output voltage reaches the predetermined value according to the detecting of the detection circuit. The loading circuit receives the reached predetermined value of the output voltage according to the modulation of the modulation circuit, wherein the controlling signal for boosting charging modulating the output voltage is more rapid than the controlling signal for ballasting charging modulating the output voltage. | 2014-04-17 |
20140103983 | GATE DRIVING CIRCUIT - A shift register of a gate driving circuit includes a pull-up unit for pulling up a first output signal and a first gate signal to a high voltage level according to a driving voltage and a high-frequency clock signal, a start-up unit for transmitting a second gate signal, an energy-store unit for providing the driving voltage to the pull-up unit according to the second gate signal, a first discharging unit for pulling down the driving voltage to a first voltage level according to a first control signal, a first leakage-preventing unit for turning off the first discharging unit when the first gate signal reaches the high voltage level, a first pull-down unit for respectively pulling down the first output and first gate signals to the first and a second voltage levels according to the first control signal, and a first control unit for generating the first control signal. | 2014-04-17 |
20140103984 | QUADRATURE SYMMETRIC CLOCK SIGNAL GENERATION - Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverters may be coupled to at least two dynamic logic cells of the plurality of dynamic logic cells. Each inverter may be configured to output a twenty-five percent duty cycle clock signal. | 2014-04-17 |
20140103985 | Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface - A Digitally Controlled Delay Line (DCDL) for a Structured ASIC chip is used to delaying input or output signals into or out of core logic in a Structured ASIC. The DCDL has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel CMOS transistors whose gates are biased with a voltage control signal that is thermometer coded. The fine-tune stages are followed by coarse delay stages that use gate-level delay. A DCDL controller outputs control signals that are Grey coded and converted to thermometer coded control signals by a Binary-to-Thermometer Decoder. The DCDL circuit block and accompanying Structured ASIC are manufactured on a 28 nm CMOS process lithographic node or smaller. A high speed routing fabric using a balanced binary tree is employed with the DCDL. | 2014-04-17 |
20140103986 | MUX-BASED DIGITAL DELAY INTERPOLATOR - A digital delay interpolator may include an array of multiplexers, each multiplexer configured to be input with first and second input voltages, one of the first and second input voltages being delayed in respect to the other, and receive a respective selection signal. The digital delay interpolator may include output lines respectively coupled to the array of multiplexers, and an output terminal configured to be coupled in common to the output lines. Each multiplexer may be configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal. | 2014-04-17 |
20140103987 | PHASE DIFFERENCE QUANTIZATION CIRCUIT, DELAY VALUE CONTROL CIRCUIT THEREOF, AND DELAY CIRCUIT - A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to N | 2014-04-17 |
20140103988 | VOLTAGE SWITCH CIRCUIT - A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process. | 2014-04-17 |
20140103989 | SEMICONDUCTOR POWER MODULES AND DEVICES - An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion. | 2014-04-17 |
20140103990 | Fault Tolerant Fail-Safe Link - The present disclosure is generally directed to a plurality of solid state switches of varying periphery sizes connected in series between a power source and a load. A built-in test circuit senses an overvoltage condition across one or more of the varying periphery sizes and opens or closes the one or more of the varying periphery sizes in accordance with a measured voltage across at least one solid state switch of the plurality of solid state switches. | 2014-04-17 |
20140103991 | BOUNDED BIAS CIRCUIT WITH EFFICIENT VT-TRACKING FOR HIGH VOLTAGE SUPPLY/LOW VOLTAGE DEVICE - Disclosed is a device and method for providing a bounded bias voltage with improved Process Voltage Temperature (PVT) adjustment. An embodiment may include a bias_n generation circuit that adjusts a bias_n voltage for PVT as a function of two bias_n NMOS transistors/diodes and a bias_p generation circuit that adjusts a bias_p voltage for PVT as a function of two bias_p PMOS transistors/diodes. An embodiment may further include a PVT adjusted bounded bias voltage circuit comprised of a NMOS transistor with the bias_n voltage at the gate and a PMOS transistor with the bias_p voltage at the gate such that a common connection between the NMOS and PMOS transistors generates a bounded bias voltage adjusted for PVT as a function of two body biased voltages (bias_n/bias_p). The bounded bias voltage may be used to provide a low supply voltage to a low voltage device using an available high voltage supply. | 2014-04-17 |
20140103992 | BIASING IN CMOS INVERTER - Biasing circuit for providing a supply voltage (Vdd) for an inverter based circuit. The biasing circuit is provided on a same die as the inverter based circuit, and includes a first shorted inverter circuit (T | 2014-04-17 |
20140103993 | CHIP DYNAMIC VOLTAGE REGULATOR CIRCUIT AND TERMINAL DEVICE - The present invention provides a chip dynamic voltage regulator circuit and a terminal device. The voltage regulator circuit includes: a parameter detecting module, configured to detect an attribute parameter of a chip; a Pulse Width Modulation (PWM) signal generating module, configured to generate a corresponding PWM digital signal according to the detected attribute parameter, and convert the PWM digital signal into an analog signal having a direct-current voltage; and a power supply module, including a DC-DC converter or a low-dropout regulator, which is configured to regulate an output voltage according to the analog signal that is fed back and a feedback signal of the voltage output end of the voltage regulator circuit. The present invention is capable of accurately regulating an output voltage according to an analog signal converted from a PWM digital signal, thereby implementing dynamic voltage regulation for a chip at a low cost and avoiding power waste. | 2014-04-17 |
20140103994 | DETECTION DEVICE PROVIDED WITH A TRANSIMPEDANCE CIRCUIT - The invention concerns a detection device including a photodiode (Ph) designed to capture a luminous signal to transform it into a current (lph) and including first and second terminals, a transimpedance amplifier circuit connected between the first terminal and the second terminal of the photodiode (Ph) and designed to amplify the current (lph) coming from the photodiode (Ph). The transimpedance amplifier circuit includes a plurality of operational amplifiers (AOP | 2014-04-17 |
20140103995 | Control Circuit and Method for Controlling an Operation of a Power Amplifier - A control circuit and a method for controlling an operation of a power amplifier core are provided. The power amplifier core is switchable between an envelope tracking operation mode and a non-envelope tracking operation mode. The control circuit is configured to provide a control signal for controlling the operation of the power amplifier core or to process an amplified signal received from the power amplifier core in dependence on the operation mode of the power amplifier core. | 2014-04-17 |
20140103996 | FRONT-END AMPLIFIER - A front-end amplifier has an impedance detector that detects an impedance seen looking into an antenna side from a power amplifier from a radio-frequency signal output from the power amplifier and a radio-frequency signal reflected from the antenna, in which a control circuit decides on whether the impedance detected by the impedance detector belongs to a specific region or not, and controls, if the impedance belongs to the specific region, at least one of the bias condition of the power amplifier and the impedance of a variable-matching circuit. | 2014-04-17 |
20140103997 | POWER AMPLIFIER ASSEMBLY COMPRISING SUSPENDED STRIP LINES - It is presented a power amplifier assembly comprising; a radio frequency multi-order power amplifier comprising a circuit board; a grounding structure connected to the radio frequency multi-order power amplifier and comprising a recess; a combining network connected to a plurality of outputs of the radio frequency multi-order power amplifier. The combining network comprises: a plurality of input connection points, wherein each of the plurality of input connection points is connected to a respective output of the plurality of outputs of the radio frequency multi-order power amplifier; an output connection point; and a conductor arrangement comprising a plurality of conductive paths arranged between the plurality of input connection points and the output connection point; wherein at least one of the plurality of conductive paths is at least partly formed by a suspended conductor positioned in the recess of the grounding structure. | 2014-04-17 |
20140103998 | RADIO FREQUENCY SIGNAL GAIN CONTROL - An RE receiver is described comprising a common gate common source LNA with a variable resistor in the source of the common gate transistor, a variable resistor in the source of the common source transistor, and a variable resistor in the RE input. A Smart Gain Control varies the resistance in the resistors to produce linear amplification in the LNA while maintaining input matching. Further, a broad dynamic range RSSI is described that implements a feedback control loop to maintain signal power within a sensitivity range of the power detector in the RSSI. | 2014-04-17 |
20140103999 | AMPLIFIER, FULLY-DIFFERENTIAL AMPLIFIER AND DELTA-SIGMA MODULATOR - An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level; a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier; an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor; | 2014-04-17 |
20140104000 | FEED-FORWARD CIRCUIT TO PREVENT PHASE INVERSION - An amplifier includes a bootstrap circuit for improving a linearity of the amplifier and a feed-forward circuit for modifying a voltage of the bootstrap circuit in response to a change in an input signal. Modifying the voltage using the feed-forward circuit prevents a phase-inversion condition of the amplifier. | 2014-04-17 |
20140104001 | AMPLIFIER CIRCUIT - An amplifier circuit includes a differential amplifier circuit configured to amplify a voltage between a signal input to a first input terminal and a signal input to a second input terminal, a plurality of output circuits each configured to output a signal corresponding to a signal output from the differential amplifier circuit, and a control circuit configured to set a selected one of the plurality of output circuits in an operating state to drive an output terminal of the selected output circuit, and set a remaining output circuit in a non-operating state and set an output terminal of the remaining output circuit in a high impedance state. | 2014-04-17 |
20140104002 | CIRCUIT AND METHOD FOR ADJUSTING THE ELECTRIC POWER SUPPLY OF AN ENERGY-SCAVENGING SYSTEM - A differentiator generates a time derivative signal from a time-variable signal. A transconductance amplifier generates a biasing control signal as a function of the time derivative signal. A supply network functions to supply the differentiator and transconductance amplifier. The supply network is driven by the biasing control signal output from the transconductance amplifier. With this configuration, speed of operation of the differentiator and transconductance amplifier vary with the supply provided by the supply network, and the supply is modulated as a function of the received time-variable signal. | 2014-04-17 |
20140104003 | OPERATIONAL AMPLIFIER CIRCUIT AND METHOD IMPLEMENTING THE SAME - The disclosure provides an operational amplifier circuit, in which a power supply of an amplifying circuit is coupled to a first voltage clamping circuit, and the first voltage clamping circuit clamps a supply voltage of the amplifying circuit when the supply voltage exceeds a normal-operation allowable voltage of the amplifying circuit. The disclosure also provides a method for implementing the operational amplifier circuit. According to the disclosure, the operational circuit may be avoided from subject to an excessive supply voltage, which may damage devices in the amplifying circuit of the operational amplifier. | 2014-04-17 |
20140104004 | AMPLIFIER CIRCUITS - Radio Frequency (RF) amplifier circuits are disclosed which may exhibit improved video/instantaneous bandwidth performance compared to conventional circuits. For example, disclosed RF amplifier circuits may employ a baseband decoupling network connected in parallel with a low-pass RF matching network of the amplifier circuit. | 2014-04-17 |
20140104005 | VOLTAGE-TO-CURRENT CONVERTER AND VOLTAGE CONTROLLED OSCILLATOR HAVING VOLTAGE-TO-CURRENT CONVERTER - A voltage controlled oscillator includes a voltage-to-current converter and a current controlled oscillator, where the voltage-to-current converter is used for converting an input voltage to generate an output current, and the current controlled oscillator is used for generating an output frequency signal according to the output current. In addition, the voltage-to-current converter includes an input terminal, a resistor, a current mirror and a current generating circuit, where the input terminal is for receiving the input voltage; the resistor is coupled to the input terminal; the current mirror is coupled to the resistor, and is used for mirroring a reference current to generate a mirrored current, where the reference current is formed according to at least a current flowing through the resistor; and the current generating circuit is coupled to the current mirror, and is used for generating the output current according to at least the mirrored current. | 2014-04-17 |
20140104006 | PASSIVE AND ACTIVE SUPPRESSION OF VIBRATION INDUCED PHASE NOISE IN OSCILLATORS - An oscillator system having: an UHF oscillator, such as a SAW oscillator, for producing a signal having a controllable frequency; a passive vibration, suppressor mechanically coupled to the UHF oscillator for suppressing vibrations above a predetermined bandwidth BW1 on the UHF oscillator; and an active vibration suppressor. The active vibration suppressor includes an accelerometer for sensing vibrations within a predetermined bandwidth BW2 on the UHF oscillator; and an HF or VHF oscillator, such as a crystal oscillator, producing a signal having a frequency controlled by the accelerometer. A control loop having a bandwidth changeable with sensed vibration level is fed the oscillator and the UHF oscillator for controlling the frequency of the signal produced by the SAW oscillator is accordance with a difference between the signal produced the HF or VHF oscillator and the signal produced by the UHF oscillator, the control loop having a bandwidth BW3; where BW12014-04-17 | |
20140104007 | Method and Apparatus of a Resonant Oscillator Separately Driving Two Independent Functions - Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function: thereby providing two simultaneous operations being determined in place of the one differential function. | 2014-04-17 |
20140104008 | DEVICE, SYSTEM, AND METHOD OF FREQUENCY GENERATION USING AN ATOMIC RESONATOR - Some demonstrative embodiments include devices, systems and/or methods of generating a frequency reference using a solid-state atomic resonator formed by a solid-state material including an optical cavity having color centers. A device may include a solid-state atomic clock to generate a clock frequency signal, the solid-state atomic clock including a solid state atomic resonator formed by a solid-state material including au optical cavity having color centers, which are capable of exhibiting hyperfine transition, wherein the solid-state atomic clock may generate the clock frequency signal based on a hyperfine resonance frequency of the color centers. | 2014-04-17 |
20140104009 | CRYSTAL OSCILLATOR WITH ELECTROSTATIC DISCHARGE (ESD) COMPLIANT DRIVE LEVEL LIMITER - A crystal oscillator may be configured to limit crystal drive level in the crystal oscillator by clamping via a diode-resistor branch, voltage applied to a drain pad of the crystal oscillator. The crystal oscillator may incorporate Pierce crystal oscillator based implementation. The crystal oscillator may comprise an on-chip main branch, comprising at least one transistor element; an on-chip drain branch connecting the main branch to a drain pad; an on-chip gate branch connecting the main branch to a gate pad. The diode-resistor branch may be connected to the drain branch, and may comprise at least one diode and at least one resistor element. The at least one diode and the at least one resistor element may be connected in series in the diode-resistor branch. The clamped voltage may be applied from an off-chip drain node, through the drain pad. | 2014-04-17 |
20140104010 | Method and Apparatus for a Duty-Cycled Harmonic Injection Locked Oscillator - A method and an apparatus for a duty-cycled injection locked oscillator is provided for frequency shift keyed (FSK) signal transmissions. The oscillator includes a resonance LC tank and a first switching device. The first switching device is coupled to the resonance LC tank and injects an initial current pulse with a predetermined pulse magnitude into the resonance LC tank. The initial current pulse also fixes an initial phase of the duty-cycled injection locked free-running oscillator in response to the predetermined magnitude of the initial current pulse to enable fast settling of injection locking and high data rate operation of the duty-cycled injection locked oscillator. The oscillator also includes a second switching device, such as a differential pair of switching devices. The second switching device is coupled to the LC resonance tank for injecting a gated periodic reference signal having a duty cycle modified to reduce power of the reference signal by approximately seventy-five per cent. | 2014-04-17 |
20140104011 | PIEZOELECTRIC OSCILLATOR - Provided is a piezoelectric oscillator to attain high-frequency performance and frequency stabilization with the use of reflection characteristics of a reflective element. A piezoelectric oscillator is configured such that a resonant circuit is connected to a gate of a field effect transistor; an output terminal is connected to a drain and a power supply voltage V is applied to the drain; a piezoelectric resonator is connected to a source, as a reflective element; and a resonance frequency of the resonant circuit and an oscillation frequency of the piezoelectric resonator as a reflective element are set to substantially the same frequency, and further, the piezoelectric oscillator may be configured such that a first matching circuit is provided between the resonant circuit and the gate, second matching circuit is provided between the drain and the output terminal, and a third matching circuit is provided between the source and the reflective element. | 2014-04-17 |