16th week of 2020 patent applcation highlights part 61 |
Patent application number | Title | Published |
20200119130 | DISPLAY DEVICE - A display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction, data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction, and a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and including a first dummy data line and a first dummy power pattern extending in parallel to the data lines. | 2020-04-16 |
20200119131 | DISPLAY DEVICE - Disclosed is a display device including: a substrate; a first insulating film over the substrate, the first insulating film exposing a part of the substrate to provide an exposed surface to the substrate; a second insulating film in contact with the exposed surface and a first side surface of the first insulating film; and a first wiring over the second insulating film and in contact with the exposed surface, the first insulating film, and the second insulating film. The display device may further possess a third insulating film spaced from the second insulating film and in contact with the exposed surface. The first insulating film has a second side surface opposing the first side surface through the exposed surface. The third insulating film may be in contact with the second side surface, and the wiring may be located over and in contact with the third insulating film. | 2020-04-16 |
20200119132 | TRIMMABLE SILICON-BASED THERMISTOR WITH REDUCED STRESS DEPENDENCE - Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate. | 2020-04-16 |
20200119133 | LOCOS WITH SIDEWALL SPACER FOR DIFFERENT CAPACITANCE DENSITY CAPACITORS - An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors. | 2020-04-16 |
20200119134 | EMBEDDED STACK CAPACITOR WITH HIGH PERFORMANCE LOGIC - A semiconductor structure with embedded stacked capacitors and a method for fabricating the same are provided. In an embodiment, a method for fabricating logic and memory devices with an embedded stack capacitor includes forming a semiconductor chip having a logic region and a memory region. The method also includes forming back-end-of-line (BEOL) metallization over the logic region but not over the memory region. The method also includes forming a stack capacitor over the memory region. | 2020-04-16 |
20200119135 | Hybrid Decoupling Capacitor and Method Forming Same - A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly. | 2020-04-16 |
20200119136 | BURIED MIM CAPACITOR STRUCTURE WITH LANDING PADS - A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates. | 2020-04-16 |
20200119137 | CAPACITOR - A capacitor that includes a substrate having a first main surface and a second main surface that are opposite to each other, and a plurality of trench portions on the first main surface; a dielectric film adjacent the first main surface of the substrate and extending into interiors of the plurality of trench portions; a conductor film on the dielectric film and extending into the interiors of the plurality of trench portions; and a bonding pad electrically connected to the conductor film. In a plan view from a direction normal to the first main surface of the substrate, the plurality of trench portions are arranged in second regions disposed along a second direction and not in first regions disposed along a first direction in which a bonding wire electrically connected to the bonding pad extends. | 2020-04-16 |
20200119138 | CAPACITOR INCLUDING MULTILAYER DIELECTRIC STACK - Techniques are disclosed for forming an integrated circuit including a capacitor having a multilayer dielectric stack. For example, the capacitor may be a metal-insulator-metal capacitor (MIMcap), where the stack of dielectric layers is used for the insulator or ‘I’ portion of the MIM structure. In some cases, the composite or multilayer stack for the insulator portion of the MIM structure may include a first oxide layer, a dielectric layer, a second oxide layer, and a high-k dielectric layer, as will be apparent in light of this disclosure. Further, the multilayer dielectric stack may include an additional high-k dielectric layer, for example. Use of such multilayer dielectric stacks can enable increases in capacitance density and/or breakdown voltage for a MIMcap device. Further, use of a multilayer dielectric stack can enable tuning of the breakdown and capacitance characteristics as desired. Other embodiments may be described and/or disclosed. | 2020-04-16 |
20200119139 | METHODS AND APPARATUSES INCLUDING A BOUNDARY OF A WELL BENEATH AN ACTIVE AREA OF A TAP - Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well has an edge that is substantially beneath an edge of an active area of a tap to the well. | 2020-04-16 |
20200119140 | RECTIFIER DEVICE, RECTIFIER, GENERATOR DEVICE, AND POWERTRAIN FOR VEHICLE - Provided is a rectifier device for a vehicle alternator including a rectifying element for rectifying in an alternator. The rectifying element has an Enhanced Field Effect Semiconductor Diode (EFESD). The EFESD includes a lateral conducting silicide structure and a field effect junction structure integrating side by side. A rectifier, a generator device, and a powertrain for a vehicle are also provided. | 2020-04-16 |
20200119141 | SEMICONDUCTOR DEVICE - A gate connection layer ( | 2020-04-16 |
20200119142 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes a semiconductor layer having first and second plane, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type between the first semiconductor region and the first plane, third semiconductor regions of a first conductivity type provided between the first semiconductor region and the first plane and provided between the second semiconductor regions, a fourth semiconductor region provided between the second semiconductor regions and the first plane, and having a higher second conductivity-type impurity concentration than the second semiconductor regions, a fifth semiconductor region of a first conductivity type between the fourth semiconductor region and the first plane, a sixth semiconductor region provided between the second semiconductor regions and the fourth semiconductor region, and having a higher electric resistance per unit depth than the second semiconductor regions, a gate electrode, and a gate insulating film. | 2020-04-16 |
20200119143 | SEMICONDUCTOR DEVICE INCLUDING ISOLATION REGIONS - A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion. | 2020-04-16 |
20200119144 | SEMICONDUCTOR DEVICE WITH LOW RANDOM TELEGRAPH SIGNAL NOISE - A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects. | 2020-04-16 |
20200119145 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device includes a first stacked structure including word lines and dielectric layers alternately stacked over a substrate. The semiconductor device also includes a plurality of first vertical channel structures formed through the first stacked structure and a second stacked structure including gate electrodes and dielectric layers alternately stacked over the first stacked structure. The semiconductor device further includes a plurality of second vertical channel structures formed through the second stacked structure, wherein the plurality of second vertical channel structures are respectively connected to the plurality of first vertical channel structures. The semiconductor device additionally includes an isolating layer for isolating the plurality of second vertical channel structures into first and second regions. Both sidewalls of the isolating layer contact sidewalls of the second vertical channel structures of the plurality of second vertical channel structures positioned at the boundary between the first and second regions. | 2020-04-16 |
20200119146 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall. | 2020-04-16 |
20200119147 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A trench gate MOSFET has at an n-type current spreading region between an n | 2020-04-16 |
20200119148 | GaN Lateral Vertical HJFET with Source-P Block Contact - A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has an improved barrier layer for p-GaN block layer and enhanced Ohmic contact with source. In one embodiment, regrowth of lateral channel is provided so that counter doping surface Mg will be buried. In another embodiment, a dielectric layer is provided to protect p-type block layer during the processing, and later make Ohmic source and p-type block layer. Method of a barrier regrown layer for enhanced lateral channel performance is provided where a regrown barrier layer is deposited over the drift layer. The barrier regrown layer is an anti-p-doping layer. Method of a patterned regrowth for enhanced Ohmic contact is provided where a patterned masked is used for the regrowth. | 2020-04-16 |
20200119149 | LOCOS WITH SIDEWALL SPACER FOR TRANSISTORS AND OTHER DEVICES - An integrated circuit (IC) includes a first field-plated field effect transistor (FET), and a second field-plated FET, and functional circuitry configured together with the field-plated FETs for realizing at least one circuit function in a semiconductor surface layer on a substrate. The field-plated FETs include a gate structure including a gate electrode partially over a LOCOS field relief oxide and partially over a gate dielectric layer. The LOCOS field relief oxide thickness for the first field-plated FET is thicker than the LOCOS field relief oxide thickness for the second field-plated FET. There are sources and drains on respective sides of the gate structures in the semiconductor surface layer. | 2020-04-16 |
20200119150 | SEMICONDUCTOR DEVICES - A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment. | 2020-04-16 |
20200119151 | Low-k Feature Formation Processes and Structures Formed Thereby - Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material. | 2020-04-16 |
20200119152 | Low Resistant Contact Method and Structure - A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening. | 2020-04-16 |
20200119153 | SEMICONDUCTOR DEVICE WITH SIDEWALL PASSIVATION AND METHOD OF MAKING - One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening. | 2020-04-16 |
20200119154 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - A thin film transistor, a manufacturing method thereof, an array substrate and a display device are provided. The thin film transistor includes a first electrode on a substrate, a first insulating layer on the first electrode with the first insulating layer having a sidewall, an active layer on the first insulating layer with the active layer connected to the first electrode and comprising a portion on the sidewall which is configured as a channel of the thin film transistor, and a second electrode on the active layer with the second electrode connected to the active layer. | 2020-04-16 |
20200119155 | Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices - A semiconductor device includes a substrate having an I/O region and a core region; a first transistor in the I/O region; and a second transistor in the core region, wherein the first transistor includes a first gate structure having: an interfacial layer; a first high-k region over the interfacial layer; and a conductive layer over the first high-k region, wherein the second transistor includes a second gate structure having: the interfacial layer; a second high-k region over the interfacial layer; and the conductive layer over the second high-k region, and where in the first high-k region is thicker than the second high-k region. | 2020-04-16 |
20200119156 | Device and Method for Tuning Threshold Voltage by Implementing Different Work Function Metals in Different Segments of a Gate - A semiconductor device includes an active region spanning along a first direction. The semiconductor device includes a first elongated gate spanning along a second direction substantially perpendicular to the first direction. The first elongated gate includes a first portion that is disposed over the active region and a second portion that is not disposed over the active region. The first portion and the second portion include different materials. The semiconductor device includes a second elongated gate spanning along the second direction and separated from the first elongated gate in the first direction. The second elongated gate includes a third portion that is disposed over the active region and a fourth portion that is not disposed over the active region. The third portion and the fourth portion include different materials. | 2020-04-16 |
20200119157 | SEMICONDUCTOR DEVICES - A semiconductor device includes a base substrate; a plurality of doped regions formed in the base substrate; and a target capping layer formed on surfaces of the doped regions. The target capping layer includes a silicide region and a non-silicide region surrounding the silicide region, and the silicide region has a reduced thickness compared with a thickness of the non-silicide region. The semiconductor device further includes a metal silicide layer formed in the silicide region of the target capping layer and having the reduced thickness; a dielectric layer formed on the target capping layer and the base substrate; and a plurality of vias formed in the dielectric layer and connected to the metal silicide layer. | 2020-04-16 |
20200119158 | MIXED TRENCH JUNCTION BARRIER SCHOTTKY DIODE AND METHOD FABRICATING SAME - A method for manufacturing a SiC mixed trench Schottky diode may include steps of providing a substrate and an epitaxial layer on top of the substrate; forming a plurality of trenches on a surface of the epitaxial layer; conducting ion implantation at a bottom portion of each trench; conducting ion implantation at sidewalls of each trench; forming an ohmic contact metal at a bottom portion of the Schottky diode; forming a Schottky contact metal on top of the epitaxial layer and in the trenches. In one embodiment, the substrate is an N | 2020-04-16 |
20200119159 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a first dielectric fin, a second dielectric fin, a semiconductor fin, an epitaxy structure, and a metal gate structure. The first dielectric fin and the second dielectric fin disposed over the substrate. The semiconductor fin is disposed over the substrate, in which the semiconductor fin is between the first dielectric fin and the second dielectric fin. The epitaxy structure covers at least two surfaces of the semiconductor fin, in which the epitaxy structure is in contact with the first dielectric fin and is separated from the second dielectric fin. The metal gate structure crosses the first dielectric fin, the second dielectric fin, and the semiconductor fin. | 2020-04-16 |
20200119160 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin, a gate structure, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin and a second semiconductor fin extend upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The shallow trench isolation (STI) oxide has a horizontal portion extending along a top surface of the substrate and vertical portions extending upwardly from the horizontal portion along the first and second semiconductor fins. The dielectric layer has a horizontal portion extending along a top surface of the horizontal portion of the STI oxide and vertical portions extending upwardly from the horizontal portion of the dielectric layer to a position higher than top ends of the vertical portions of the STI oxide. | 2020-04-16 |
20200119161 | Source and Drain Structure with Reduced Contact Resistance and Enhanced Mobility - A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region. | 2020-04-16 |
20200119162 | High Electron Mobility Transistor with Dual Thickness Barrier Layer - A semiconductor device includes a heterojunction semiconductor body including a first and second type III-V semiconductor layers with different bandgaps such that a first two-dimensional charge carrier gas forms at an interface between the two layers. The second type III-V semiconductor layer includes a thicker section and a thinner section. A first input-output electrode is on the thicker section and is in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section and is in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section and is configured to control a conductive connection between the first and second input-output electrodes. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer. | 2020-04-16 |
20200119163 | SELF-ALIGNED GATE CUT METHOD AND MULTILAYER GATE-CUT PILLAR STRUCTURE - One illustrative method disclosed herein includes forming a sacrificial gate structure and a gate-cut structure within the sacrificial gate structure at a location positioned above the isolation material, the gate-cut structure having an upper portion and a lower portion, and forming a replacement gate cavity by removing the sacrificial gate structure and the lower portion of the gate-cut structure. The method further includes forming a final gate structure that includes forming a gate insulation layer of the final gate structure on all exposed surfaces of the upper portion of the gate-cut structure, removing the upper portion of the gate-cut structure, removing the exposed portion of the final gate structure to define a gate-cut opening that separates the final gate structure into the first and second final gate structures, and forming a gate separation structure in the gate-cut opening. | 2020-04-16 |
20200119164 | Tuning Threshold Voltage in Field-Effect Transistors - A method includes removing a dummy gate structure to form a gate trench over a semiconductor layer, forming a high-k gate dielectric layer over an interfacial layer exposed in the gate trench, depositing a metal-containing precursor over the high-k gate dielectric layer to form a metal-containing layer, and subsequently depositing an aluminum-containing precursor over the metal-containing layer, where depositing the aluminum-containing precursor forms an aluminum oxide layer at an interface between the high-k gate dielectric layer and the interfacial layer and where the metal-containing precursor includes a metal different from aluminum. The method further includes, subsequent to depositing the aluminum-containing precursor, removing a portion of the metal-containing layer, depositing a work-function metal layer over a remaining portion of the metal-containing layer, and forming a bulk conductive layer over the work-function metal layer, resulting in a metal gate structure. | 2020-04-16 |
20200119165 | FIN FIELD-EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME - A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers. | 2020-04-16 |
20200119166 | METHOD FOR PRODUCING PILLAR-SHAPED SEMICONDUCTOR DEVICE - The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO | 2020-04-16 |
20200119167 | Semiconductor Device and Method - Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps. | 2020-04-16 |
20200119168 | SELF-ALIGNED TUNNELING FIELD EFFECT TRANSISTORS - Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer. | 2020-04-16 |
20200119169 | QUANTUM DOT DEVICES - Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers. | 2020-04-16 |
20200119170 | VERTICAL FIN TYPE BIPOLAR JUNCTION TRANSISTOR (BJT) DEVICE WITH A SELF-ALIGNED BASE CONTACT - A method of forming a silicon-germanium heterojunction bipolar transistor (hbt) device is provided. The method includes forming a stack of four doped semiconductor layers on a semiconductor substrate. The method further includes forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers, and removing portions of the second, third, and fourth semiconductor layers to form a vertical fin. The method further includes recessing the second and fourth doped semiconductor layers, and depositing a condensation layer on the second, third, and fourth doped semiconductor layers. The method further includes reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion. | 2020-04-16 |
20200119171 | BIPOLAR TRANSISTOR AND METHOD FOR PRODUCING THE SAME - A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer. | 2020-04-16 |
20200119172 | ADVANCED WAFER BONDED HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODS OF MANUFACTURE OF ADVANCED WAFER BONDED HETEROJUNCTION BIPOLAR TRANSISTORS - Methods of manufacturing a heterojunction bipolar transistor are described herein. An exemplary method can include providing a base/emitter stack, the base/emitter stack comprising a substrate, an etch stop layer over the substrate, an emitter contact layer over the etch stop layer, an emitter over the emitter contact layer, and/or a base over the emitter. The exemplary method further can include forming a collector. The exemplary method also can include wafer bonding the base to the collector. Other embodiments are also disclosed herein. | 2020-04-16 |
20200119173 | ADVANCED FIELD STOP THYRISTOR STRUCTURE AND MANUFACTURE METHODS - A power switching device may include a semiconductor substrate and a body region comprising an n-type dopant, the body region disposed in an inner portion of the semiconductor substrate; a first base layer disposed adjacent a first surface of the semiconductor substrate, the first p-base layer comprising a p-type dopant; a second base layer disposed adjacent a second surface of the semiconductor substrate, the second base layer comprising a p-type dopant; a first emitter region, disposed adjacent the first surface of the semiconductor substrate, the first emitter region comprising a n-type dopant; a second emitter-region, disposed adjacent the second surface of the semiconductor substrate, the second emitter-region comprising a n-type dopant; a first field stop layer arranged between the first base layer and the body region, the first field stop layer comprising a n-type dopant; and a second field stop layer arranged between the second base layer and the body region, the second field stop layer comprising a n-type dopant. | 2020-04-16 |
20200119174 | METHOD FOR FORMING A TRANSITION METAL DICHALCOGENIDE - GROUP III-V HETEROSTRUCTURE AND A TUNNELING FIELD EFFECT TRANSISTOR - A method for forming a Transition Metal Dichalcogenide (TMD)—Group III-V semiconductor heterostructure comprises forming an insulating layer on an upper surface of a substrate, wherein the upper surface of the substrate is formed by a (111)-surface of a group IV semiconductor, forming a first aperture in the insulating layer, the aperture exposing a portion of the upper surface of the substrate, forming in a first epitaxial growth process, a semiconductor structure formed by a group III-V semiconductor comprising a pillar extending through the first aperture and a micro disc extending horizontally along a first portion of the upper surface of the insulating layer, and forming in a second epitaxial growth process, a TMD layer on an upper surface of the micro disc. | 2020-04-16 |
20200119175 | GRADED CHANNELS FOR HIGH FREQUENCY III-N TRANSISTORS - Techniques are disclosed for forming III-N transistor structures that include a graded channel region. The disclosed transistors may be implemented with various III-N materials, such as gallium nitride (GaN) and the channel region may be graded with a gradient material that is a different III-N compound, such as indium gallium nitride (InGaN), in some embodiments. The grading of the channel region may provide, in some cases, a built in polarization field that may accelerate carriers travelling between the source and drain, thereby reducing transit time. In various embodiments where GaN is used as the semiconductor material for the transistor, the GaN may be epitaxially grown to expose either the c-plane or the m-plane of the crystal structure, which may further contribute to the built-in polarization field produced by the graded channel. | 2020-04-16 |
20200119176 | GROUP III-N TRANSISTORS INCLUDING SOURCE TO CHANNEL HETEROSTRUCTURE DESIGN - Techniques are disclosed for forming group III-N transistors including a source to channel heterostructure design. As will be apparent in light of this disclosure, the source to channel heterostructure design may include inserting a relatively high bandgap material layer (e.g., relative to the bandgap of the channel material) between the source and channel of the III-N transistor. In some such embodiments, the relatively high bandgap material layer may be a portion of the polarization charge inducing layer formed over the III-N layer including the channel (e.g., to form a heterojunction/2DEG configuration) that is purposefully left in the source region when forming the source/drain trenches. The source to channel heterostructure design can be used to enhance the high frequency performance of the III-N transistor. Other embodiments may be described and/or disclosed. | 2020-04-16 |
20200119177 | Enhancement-mode Device and Method for Manufacturing the Same - An enhancement-mode device includes: a substrate; a channel layer and a barrier layer successively formed on the substrate; an n-type semiconductor layer formed on the barrier layer, a gate region being defined on a surface of the n-type semiconductor layer; a groove that is formed in the gate region and at least partially runs through the n-type semiconductor layer; and a p-type conductor material that is formed on the surface of the n-type semiconductor layer and at least fills the inside of the groove. | 2020-04-16 |
20200119178 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer disposed above the substrate; a second nitride semiconductor layer disposed above the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a third nitride semiconductor layer selectively disposed above the second nitride semiconductor layer and containing a p-type first impurity element; a high resistance region disposed in the third nitride semiconductor layer, the high resistance region containing a second impurity element and having a specific resistance higher than a specific resistance of the third nitride semiconductor layer; and a gate electrode disposed above the high resistance region, wherein an end of the high resistance region is inside a surface end of the third nitride semiconductor layer. | 2020-04-16 |
20200119179 | LATERAL III-NITRIDE DEVICES INCLUDING A VERTICAL GATE MODULE - A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage. | 2020-04-16 |
20200119180 | METHOD OF FORMING WRAP-AROUND-CONTACT AND THE RESULTING DEVICE - A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts. | 2020-04-16 |
20200119181 | SEMICONDUCTOR DEVICES - Provided in a semiconductor device including a substrate, an active region upwardly protruding from the substrate, a plurality of active fins upwardly protruding from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being provided in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, and an isolation structure provided on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin among the plurality of active fins has a staircase shape, the first active fin being provided on a first edge of the active region in the second direction. | 2020-04-16 |
20200119182 | FINFET ISOLATION STRUCTURE - A device includes a semiconductive substrate, a stop layer over the semiconductive substrate, first and second semiconductive fins over the stop layer, a fin isolation structure between the first and second semiconductive fins, and a spacer at least partially extending along a sidewall of the fin isolation structure. A bottom of the fin isolation structure is lower than a top of the stop layer. | 2020-04-16 |
20200119183 | Isolation Structure Having Different Distances to Adjacent FinFET Devices - A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device. | 2020-04-16 |
20200119184 | DEVICE OF DIELECTRIC LAYER - A device includes a semiconductor fin and a shallow trench isolation (STI) structure. The semiconductor fin extends from a semiconductor substrate. The STI structure is around a lower portion of the semiconductor fin, and the STI structure includes a liner layer and an isolation material. The liner layer includes a metal-contained ternary dielectric material. The isolation material is over the liner layer. | 2020-04-16 |
20200119185 | MOS DEVICE WITH ISLAND REGION - A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region comprising: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench; and an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; wherein the active region contact trench has a non-uniform depth. | 2020-04-16 |
20200119186 | Lateral MOSFET with Dielectric Isolation Trench - A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region. | 2020-04-16 |
20200119187 | MOSFET, METHOD OF MANUFACTURING MOSFET, AND POWER CONVERSION CIRCUIT - A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region. | 2020-04-16 |
20200119188 | SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION - A semiconductor device includes a semiconductor substrate having a first conductivity type, a first well region formed in a portion of the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A second well region is formed in a portion of the first well region, having the first conductivity type. A first gate structure is formed over a portion of the second well region and a portion of the first well region. A first doped region is formed in a portion of the second well region. A second doped region is formed in a portion of the first well region, having the second conductivity type. A second dielectric layer is formed over a portion of the first gate structure, a portion of the first well region, and a portion of the second doped region. | 2020-04-16 |
20200119189 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, a drift oxide region, and a top region. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a first trench bottom surface of the first trench. The top region is formed in the well right below the drift oxide region, and is in contact with the drift oxide region. | 2020-04-16 |
20200119190 | VERTICAL TRANSISTOR DEVICES WITH COMPOSITE HIGH-K AND LOW-K SPACERS WITH A CONTROLLED TOP JUNCTION - A method of forming a vertical fin field effect transistor device is provided. The method includes forming a vertical fin and fin template on a bottom source/drain layer, wherein the fin template is on the vertical fin. The method further includes forming a gate structure on the vertical fin and fin template, and forming a top spacer layer on the gate structure. The method further includes removing the fin template to form an opening in the top spacer layer, and removing a portion of a gate electrode of the gate structure to form a cavity; and removing a portion of a gate dielectric layer of the gate structure to form a groove around the vertical fin. | 2020-04-16 |
20200119191 | VERTICAL FIELD EFFECT TRANSISTOR WITH REDUCED EXTERNAL RESISTANCE - A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and at least one semiconductor fin contacting the substrate. A first source/drain layer contacts the substrate. A silicide contacts and wraps around the first source/drain layer. The structure also includes a second source/drain layer above the first source/drain layer. The method comprises forming a structure including at least a substrate, a first source/drain layer, and at least one semiconductor fin disposed on and in contact with substrate. A silicide is formed in contact with and wrapping around the first source/drain layer. A gate structure is formed in contact with at least the at least one semiconductor fin. A second source/drain layer is formed above the first source/drain layer. | 2020-04-16 |
20200119192 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film. | 2020-04-16 |
20200119193 | METHOD FOR PRODUCING A PILLAR-SHAPED SEMICONDUCTOR DEVICE - An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions. | 2020-04-16 |
20200119194 | SEMICONDUCTOR DEVICE HAVING CURVED GATE ELECTRODE ALIGNED WITH CURVED SIDE-WALL INSULATING FILM AND STRESS-INTRODUCING LAYER BETWEEN CHANNEL REGION AND SOURCE AND DRAIN REGIONS - A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region. | 2020-04-16 |
20200119195 | Field Effect Transistor Contact with Reduced Contact Resistance Using Implantation Process - Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process. | 2020-04-16 |
20200119196 | Method for Fabricating a Strained Structure and Structure Formed - A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer. | 2020-04-16 |
20200119197 | FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack. | 2020-04-16 |
20200119198 | SEMICONDUCTOR DEVICE - A device includes a semiconductive fin, a first gate stack, a second gate stack, an insulating structure, and a spacer. The semiconductive fin extends along a first direction. The first gate stack extends along a second direction and across the semiconductive fin. The first gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is over the semiconductive fin. The gate electrode is over the high-κ dielectric layer. The second gate stack extends along the second direction and is substantially aligned with the first gate stack along the second direction. The insulating structure is between the first gate stack and the second gate stack. The high-κ dielectric layer is spaced apart from the insulating structure. The spacer extends along a sidewall of the first gate stack and beyond a first sidewall of the insulating structure that faces the first gate stack. | 2020-04-16 |
20200119199 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device having favorable characteristics is provided. | 2020-04-16 |
20200119200 | SEMICONDUCTOR DEVICE - A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor. | 2020-04-16 |
20200119201 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction. | 2020-04-16 |
20200119202 | METAL OXIDE FILM, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device which includes a metal oxide film including a crystal part is provided. A semiconductor device which has a metal oxide film and high field-effect mobility is provided. A highly reliable semiconductor device including a metal oxide film is provided. The semiconductor device includes a first insulator, a first conductor formed over the first insulator, a second insulator formed over the first conductor, an oxide formed over the second insulator, a third insulator formed over the oxide, a second conductor formed over the third insulator, a fourth insulator formed over the third insulator and the second conductor, and a fifth insulator formed over the fourth insulator. The oxide contains In, M (M is Al, Ga, Y, or Sn), and Zn. The oxide includes a first crystal part and a second crystal part. The first crystal part has c-axis alignment. The second crystal part does not have c-axis alignment. | 2020-04-16 |
20200119203 | Gate All-Around Device - Gate all-around devices are disclosed in which an angled channel including a semiconducting nanostructure is located between a source and a drain. The angled channel has an axis that is oriented at an angle to the top surface of the substrate at an angle in a range of about 1° to less than about 90°. The gate all-around device is intended to meet design and performance criteria for the 7 nm technology generation. | 2020-04-16 |
20200119204 | IMPACT IONIZATION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional ( | 2020-04-16 |
20200119205 | WAVEGUIDE-INTEGRATED PHOTODETECTOR - An exemplary photodetector can be provided, which can include, for example, a metal contact, a metal stripe coupled to the metal contact, and a photon absorbing material(s) surrounding the metal stripe on at least four sides of the metal stripe. The photon absorbing material(s) can be germanium. The photon absorbing material(s) can be configured to absorb photons in a wavelength range of about 1.1 μm to about 1.7 μm. | 2020-04-16 |
20200119206 | PEROVSKITE SOLAR CELL - A perovskite solar cell adopts a compound having a specific central backbone having a carbazolylamino group as a substituent, and more particularly, to the perovskite solar cell adopts a compound, as a hole transport material, having a specific central backbone having a carbazolylamino group as a substituent, and a spirobifluorene compound having a carbazolylphenylamino group. The perovskite solar cell has very excellent high-temperature stability while having a high power generation efficiency. | 2020-04-16 |
20200119207 | CURRENT GENERATION FROM RADIATION WITH DIAMOND DIODE-BASED DEVICES FOR DETECTION OR POWER GENERATION - Diamond diode-based devices are configured to convert radiation energy into electrical current, useable for sensing (i.e., detection) or delivery to a load (i.e., energy harvesting). A diode-based detector includes an intrinsic diamond layer arranged between p-type diamond and n-type diamond layers, with the detector further including at least one of (i) a boron containing layer arranged proximate to the n-type and/or the intrinsic diamond layers, or (ii) an intrinsic diamond layer thickness in a range of 10 nm to 300 microns. A diode-based detector may be operated in a non-forward biased state, with a circuit used to transmit a current pulse in a forward bias direction to reset a detection state of the detector. An energy harvesting device may include at least one p-i-n stack (including an intrinsic diamond layer between p-type diamond and n-type diamond layers), with a radioisotope source arranged proximate to the at least one p-i-n stack. | 2020-04-16 |
20200119208 | BIFACIAL P-TYPE PERC SOLAR CELL AND MODULE, SYSTEM, AND PREPARATION METHOD THEREOF - Provided are a bifacial P-type PERC solar cell, preparation method, module and system. The bifacial P-type PERC solar cell consecutively comprises a rear silver electrode ( | 2020-04-16 |
20200119209 | SHINGLED SOLAR CELL MODULE EMPLOYING CENTRALLY CONVERGED GRID LINE ELECTRODE - The disclosure provides a shingled solar cell module employing a centrally converged grid line electrode including main electrode points and secondary grid lines disposed on a cell slice, wherein the secondary grid line is a divergent pattern centering on the main electrode points, and converging currents to the main electrode points in a way of converging from periphery to center. According to the disclosure, areas of main grid line electrodes in front and back sides of a solar cell are reduced, thereby reducing the consumption of silver paste and conductive adhesive. Moreover, as a number and a cross-sectional area of the secondary grid lines are optimized, a photoelectric conversion efficiency of shingled cell slices with such patterns is improved in comparison with the conventional shingled cell slices with parallel secondary grid lines. | 2020-04-16 |
20200119210 | LIGHT RECEIVING ELEMENT, IMAGE CAPTURING ELEMENT INCLUDING THE LIGHT RECEIVING ELEMENT AND IMAGE CAPTURING APPARATUS INCLUDING THE IMAGE CAPTURING ELEMENT - A light receiving element includes a surface recombination prevention layer composed of a first compound semiconductor on which light is incident; a photoelectric conversion layer composed of a second compound semiconductor; and a compound semiconductor layer composed of a third compound semiconductor, the surface recombination prevention layer having a thickness of 30 nm or less. Also, there are provided an image capturing element including the light receiving element, and an image capturing apparatus including the image capturing element. | 2020-04-16 |
20200119211 | POWER DISTRIBUTION AND CELL STORAGE APPARATUS - An apparatus and method for the localized capture, storage and specialized use of power generated from natural sources, such as solar power or hydropower. The apparatus can be used, for example, on a deck or a side of a marine vessel, or on a land-based structure, where there is a requirement for power generation and storage | 2020-04-16 |
20200119212 | SOLAR PHOTOELECTRIC PANEL AND AN ASSEMBLING STRUCTURE THEREOF - The present invention is a solar photoelectric panel and an assembling structure of the solar photoelectric panel, the solar photoelectric panel comprises a back plate, a glass plate, and solar cells, the glass plate is provided above the back plate, the solar cells are fixed between the back plate and the glass plate through a plastic film, wherein a fixing part for fixing the solar photoelectric panel at a building is provided by the back plate. The present invention itself is capable of being a building material and the present invention complies with the building functions requirement of heat insulation, waterproof, durable, fireproof, load-bearing, etc. | 2020-04-16 |
20200119213 | MULTIJUNCTION SOLAR CELLS HAVING A GRADED-INDEX STRUCTURE - A multijunction solar cells that include one or more graded-index structures disposed directly above the growth substrate beneath a base layer of a solar subcells. In some embodiments, the graded-index reflector structure is constructed such that (i) at least a portion of light of a first spectral wavelength range that enters and passes through a solar cell above the graded-index reflector structure is reflected back into the solar subcell by the graded-index reflector structure; and (ii) at least a portion of light of a second spectral wavelength range that enters and passes through the solar cell above the graded-index reflector structure is transmitted through the graded-index reflector structure to layers disposed beneath the graded-index reflector structure. The second spectral wavelength range is composed of greater wavelengths than the wavelengths of the first spectral wavelength range. | 2020-04-16 |
20200119214 | LIGHT REDIRECTING FILM USEFUL WITH SOLAR MODULES - A light redirecting film defining a longitudinal axis, and including a base layer, an ordered arrangement of a plurality of microstructures, and a reflective layer. The microstructures project from the base layer, and each extends across the base layer to define a corresponding primary axis. The primary axis of at least one of the microstructures is oblique with respect to the longitudinal axis. The reflective layer is disposed over the microstructures opposite the base layer. When employed, for example, to cover portions of a PV module tabbing ribbon, or areas free of PV cells, the films of the present disclosure uniquely reflect incident light. | 2020-04-16 |
20200119215 | BANDGAP-SHIFTED SEMICONDUCTOR SURFACE AND METHOD FOR MAKING SAME, AND APPARATUS FOR USING SAME - Titania is a semiconductor and photocatalyst that is also chemically inert. With its bandgap of 3.2 and greater, to activate the photocatalytic property of titania requires light of about 390 nm wavelength, which is in the ultra-violet, where sunlight is very low in intensity. A method and devices are disclosed wherein stress is induced and managed in a thin film of titania in order to shift and lower the bandgap energy into the longer wavelengths that are more abundant in sunlight. Applications of this stress-induced bandgap-shifted titania photocatalytic surface include photoelectrolysis for production of hydrogen gas from water, photovoltaics for production of electricity, and photocatalysis for detoxification and disinfection. | 2020-04-16 |
20200119216 | OPTOELECTRONIC DEVICES MANUFACTURED USING DIFFERENT GROWTH SUBSTRATES - A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described. | 2020-04-16 |
20200119217 | VOLTAGE TUNABLE SOLAR BLINDNESS IN TFS GROWN EG/SIC SCHOTTKY CONTACT BIPOLAR PHOTOTRANSISTORS - A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor. | 2020-04-16 |
20200119218 | UNIT PIXEL OF IMAGE SENSOR AND LIGHT-RECEIVING ELEMENT THEREOF - Provided are a light-receiving element which has more capability of detecting wavelengths than that of existing silicon light-receiving elements and a unit pixel of an image sensor by using it. The light-receiving element includes: a light-receiving unit which is floated or connected to external voltage and absorbs light; an oxide film which is formed to come in contact with a side of the light-receiving unit; a source and a drain which stand off the light-receiving unit with the oxide film in between and face each other; a channel which is formed between the source and the drain and forms an electric current between the source and the drain; and a wavelength expanding layer which is formed in at least one among the light-receiving unit, the oxide film and the channel and forms a plurality of local energy levels by using strained silicon. | 2020-04-16 |
20200119219 | ELECTRONIC DEVICE COMPRISING A CHIP PROVIDED WITH AN OPTICAL SENSOR - An electronic device, comprising: a support plate having a rear face and a front face; an electronic integrated circuit chip having a rear face mounted on the front face of the support plate and including an optical component in a front face; and a sleeve forming a traversing passage and having a rear edge and a front edge at the opposite ends of the traversing passage, the rear edge being mounted on the front face of the chip, in such a position that the optical component of the chip is facing the traversing passage of the sleeve. | 2020-04-16 |
20200119220 | TRI-LAYER SEMICONDUCTOR STACKS FOR PATTERNING FEATURES ON SOLAR CELLS - Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure. | 2020-04-16 |
20200119221 | ASSEMBLY METHOD AND COMBINED BIVALENT STATION FOR PHOTOVOLTAIC PANELS - An assembly method and a combined and bivalent workstation for automatically assembling photovoltaic panels, with printing of ECA on cell portions and progressive arrangement with a partial superimposition on the contacts, pre-forming shingled strings in a continuous cycle, which are ready for loading on a backsheet, without dry-curing. The method provides a macro-phase of lay-up entirely made in the station, with simultaneous and coordinated sub-phases: picking of portions with a first handler and control, oriented loading on a vacuum belt, control of positioning on the belt, printing of ECA, control of printing and positioning, progressive superimpositions on a shuttle-tray with bidirectional translation coordinated with a second handler with chocked vacuum, picking of the shingled string with a third handler, control of string alignment, loading and pre-fixing. Vision systems are integrated for the execution of said sub-phases. | 2020-04-16 |
20200119222 | METHODS OF MANUFACTURING OPTOELECTRONIC DEVICES USING DIFFERENT GROWTH SUBSTRATES - A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described. | 2020-04-16 |
20200119223 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD OF LIGHT EMITTING DIODE - A light emitting diode (LED) includes: a device substrate; a first semiconductor layer above the device substrate, and doped with an n-type dopant; a second semiconductor layer above the first semiconductor layer, and doped with a p-type dopant; an active layer between the first semiconductor layer and the second semiconductor layer and configured to provide light; a transparent electrode layer adjacent to an upper part of the second semiconductor layer; and a first electrode pad and a second electrode pad between the device substrate and the first semiconductor layer, the first electrode pad electronically connected with the first semiconductor layer and the second electrode pad electrically connected with the second semiconductor layer, wherein light provided by the active layer is irradiated to an outside in a direction from the active layer to the second semiconductor layer. | 2020-04-16 |
20200119224 | MULTI-LAYERED TUNNEL JUNCTION STRUCTURE, LIGHT EMITTING DEVICE HAVING THE SAME, AND PRODUCTION METHOD OF SUCH DEVICE - A multi-layered tunnel junction structure adapted to be disposed between two light emitting structures includes an n-type doped insulation layer, as well as an n-type heavily doped layer, a metal atom layer, a p-type heavily doped layer, and a p-type doped insulation layer which are disposed on the n-type doped insulation layer in such sequential order. A light emitting device having the multi-layered tunnel junction structure and a production method of such light emitting device are also disclosed. | 2020-04-16 |
20200119225 | SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor stack, a trench formed in the semiconductor stack, a current confinement layer, a first electrode and a second electrode. The semiconductor stack includes a first reflective structure, a second reflective structure, and a cavity region. The cavity is between the first reflective structure and the second reflective structure and has a first surface and a second surface opposite to the first surface. The current confinement layer is in the second reflective structure. The first electrode and the second electrode are on the first surface. | 2020-04-16 |
20200119226 | RESONANT OPTICAL CAVITY LIGHT EMITTING DEVICE - Resonant optical cavity light emitting devices are disclosed, where the device includes an opaque substrate, a first spacer region, a first reflective layer, a light emitting region, a second spacer region, and a second reflective layer. The light emitting region is configured to emit a target emission deep ultraviolet wavelength, and is positioned at a separation distance from the reflector. The second reflective layer may have a metal composition comprising elemental aluminum and a thickness less than 15 nm. The device has an optical cavity comprising the first spacer region, the second spacer region and the light emitting region, where the optical cavity has a total thickness less than or equal to K·λ/n. K is a constant ranging from 0.25 to 10, λ is the target wavelength, and n is an effective refractive index of the optical cavity at the target wavelength. | 2020-04-16 |
20200119227 | Semiconductor Layer Sequence and Method for Producing a Semiconductor Layer Sequence - A semiconductor layer sequence and a method for producing a semiconductor layer sequence are disclosed. In an embodiment a semiconductor layer sequence includes a first nitridic compound semiconductor layer, an intermediate layer, a second nitridic compound semiconductor layer and an active layer, wherein the intermediate layer comprises an AlGaN layer with an Al content of at least 5%, wherein the second nitridic compound semiconductor layer has a lower proportion of Al than the AlGaN layer such that relaxed lattice constants of the AlGaN layer of the intermediate layer and of the second nitridic compound semiconductor layer differ, wherein the second nitridic compound semiconductor layer and the active layer are grown on the intermediate layer in a lattice-matched manner, wherein the active layer comprises one or more layers of AlInGaN, and wherein an In content in each of the layers of AlInGaN is at most 12%. | 2020-04-16 |
20200119228 | Component Having Enhanced Efficiency and Method for Production Thereof - A component having an enhanced efficiency and a method for producing a component are disclosed. In an embodiment, a component includes a semiconductor layer sequence comprising a p-conducting semiconductor layer, an n-conducting semiconductor layer and an active zone located therebetween, wherein the active zone comprises recesses on a side of the p-conducting semiconductor layer, each recess having facets extending obliquely to a main surface of the active zone, and wherein the p-conducting semiconductor layer extends into the recesses, and a barrier structure, wherein the active zone is arranged between the barrier structure and the n-conducting semiconductor layer so that an injection of positively charged charge carriers into the active zone via the main surface is hindered in a targeted manner so that an injection of positively charged charge carriers into the active zone via the facets is promoted. | 2020-04-16 |
20200119229 | INDIUM GALLIUM NITRIDE RED LIGHT EMITTING DIODE AND METHOD OF MAKING THEREOF - A red-light emitting diode includes an n-doped portion, a p-doped portion, and a light emitting region located between the n-doped portion and a p-doped portion. The light emitting region includes a light-emitting indium gallium nitride layer emitting light at a peak wavelength between 600 and 750 nm under electrical bias thereacross, an aluminum gallium nitride layer located on the light-emitting indium gallium nitride layer. and a GaN barrier layer located on the aluminum gallium nitride layer. | 2020-04-16 |