16th week of 2020 patent applcation highlights part 60 |
Patent application number | Title | Published |
20200119030 | 3D NAND STRUCTURES INCLUDING GROUP III-N MATERIAL CHANNELS - Techniques are disclosed for forming three-dimensional (3D) NAND structures including group III-nitride (III-N) material channels. Typically, polycrystalline silicon (poly-Si) channels are used for 3D NAND structures, such as 3D NAND flash memory devices. However, using III-N channel material for 3D NAND structures offers numerous benefits over poly-Si channel material, such as relatively lower resistance in the channel, relatively higher current densities, and relatively lower leakage. Therefore, using III-N channel material enables an increased number of floating gates or storage cells to be stacked in 3D NAND structures, thereby leading to increased capacity for a given integrated circuit footprint (e.g., increased GB/cm | 2020-04-16 |
20200119031 | VERTICAL MEMORY DEVICES - Aspects of the disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are stacked alternatingly along a first direction perpendicular to a substrate of the semiconductor device in a first region upon the substrate. The gate layers and the insulating layers are stacked of a stair-step form in a second region. The semiconductor device includes a channel structure that is disposed in the first region. The channel structure and the gate layers form a stack of transistors in a series configuration with the gate layers being gates for the transistors. The semiconductor device includes a contact structure disposed in the second region, and a first dummy channel structure disposed in the second region and around the contact structure. The first dummy channel structure is patterned with a first shape that is different from a second shape of the channel structure. | 2020-04-16 |
20200119032 | TERMINATION STRUCTURES IN STACKED MEMORY ARRAYS - In an example, a method of forming a stacked memory array includes, forming a termination structure passing through a stack of alternating first and second dielectrics in a first region of the stack; forming first and second sets of contacts through the stack of alternating first and second dielectrics in a second region of the stack concurrently with forming the termination structure; forming an opening through the stack of alternating first and second dielectrics between the first and second sets of contacts so that the opening terminates at the termination structure; and removing the first dielectrics from the second region by accessing the first dielectrics through the opening so that the first and second sets of contacts pass through the second dielectrics alternating with spaces corresponding to the removed first dielectrics. | 2020-04-16 |
20200119033 | Multi-Level Cell Thin-Film Transistor Memory and Method of Fabricating the Same - A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein- the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density | 2020-04-16 |
20200119034 | Flash Memory Structure with Reduced Dimension of Gate Structure and Methods of Forming Thereof - An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices include a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures. | 2020-04-16 |
20200119035 | MEMORY DEVICE - A memory device includes a semiconductor substrate, a logic transistor, and a storage transistor. The semiconductor substrate has a logic region and a memory region. The logic transistor is disposed on the logic region, in which the logic transistor comprises a high-k metal gate structure. The storage transistor is disposed on the memory region, in which the storage transistor includes a charge storage structure and a high-k metal gate structure. The charge storage structure is disposed on the memory region. The high-k metal gate structure is disposed on the charge storage structure. | 2020-04-16 |
20200119036 | FORMING TERMINATIONS IN STACKED MEMORY ARRAYS - A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment. | 2020-04-16 |
20200119037 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells. | 2020-04-16 |
20200119038 | SEMICONDUCTOR DEVICES AND SYSTEMS WITH CHANNEL OPENINGS OR PILLARS EXTENDING THROUGH A TIER STACK, AND METHODS OF FORMATION - Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack. | 2020-04-16 |
20200119039 | DIELECTRIC EXTENSIONS IN STACKED MEMORY ARRAYS - In an example of forming a stacked memory array, a stack of alternating first and second dielectrics is formed. A dielectric extension is formed through the stack such that a first portion of the dielectric extension is in a first region of the stack between a first group of semiconductor structures and a second group of semiconductor structures in a second region of the stack and a second portion of the dielectric extension extends into a third region of the stack that does not include the first and second semiconductor structures. An opening is formed through the first region, while the dielectric extension couples the alternating first and second dielectrics in the third region to the alternating first and second dielectrics in the second region. | 2020-04-16 |
20200119040 | FORMATION OF TERMINATION STRUCTURES IN STACKED MEMORY ARRAYS - In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered. | 2020-04-16 |
20200119041 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a three-dimensional memory device, comprising: forming a ridge-shaped stack including a plurality of conductive strips stacked on the substrate along a first direction and extending along a second direction; forming a memory layer stacked on a vertical sidewall of the ridge-shaped stack along a third direction; forming a channel layer stacked on a vertical sidewall of the memory layer along the third direction and having a narrow sidewall with a long side extending along the first direction; forming a capping layer stacked on the ridge-shaped stack in the first direction, the capping layer covering the memory layer and the channel layer; and forming a conductive connecting layer stacked on the narrow sidewall along the second direction. | 2020-04-16 |
20200119042 | METHOD FOR FORMING CHANNEL HOLE IN THREE-DIMENSIONAL MEMORY DEVICE USING NONCONFORMAL SACRIFICIAL LAYER - Embodiments of methods for forming channel holes in 3D memory devices using a nonconformal sacrificial layer are disclosed. In an example, a dielectric stack including interleaved first dielectric layers and second dielectric layers is formed on a substrate. An opening extending vertically through the dielectric stack is formed. A nonconformal sacrificial layer is formed along a sidewall of the opening, such that a variation of a diameter of the opening decreases. The nonconformal sacrificial layer and part of the dielectric stack abutting the nonconformal sacrificial layer are removed. A channel structure is formed in the opening after removing the nonconformal sacrificial layer and part of the dielectric stack. | 2020-04-16 |
20200119043 | VERTICAL MEMORY DEVICES - A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length. | 2020-04-16 |
20200119044 | SEMICONDUCTOR DEVICE INCLUDING STACK STRUCTURES - A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes. | 2020-04-16 |
20200119045 | THREE-DIMENSIONAL MEMORY DEVICES HAVING PLURALITY OF VERTICAL CHANNEL STRUCTURES - A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other. | 2020-04-16 |
20200119046 | THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME - Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described. | 2020-04-16 |
20200119047 | SEMICONDUCTOR DEVICE HAVING FERROELECTRIC MATERIAL AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer. | 2020-04-16 |
20200119048 | SEMICONDUCTOR DEVICE INCLUDING STANDARD CELLS - A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction. | 2020-04-16 |
20200119049 | METHOD FOR MANUFACTURING A TRANSISTOR HAVING A SHARP JUNCTION BY FORMING RAISED SOURCE-DRAIN REGIONS BEFORE FORMING GATE REGIONS AND CORRESPONDING TRANSISTOR PRODUCED BY SAID METHOD - A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region. | 2020-04-16 |
20200119050 | DISPLAY PANEL AND DISPLAY - The present disclosure discloses a display panel which includes a substrate and plurality of insulating layers disposed on the substrate, and a plurality of metal routings, and includes a display region and a first non-display region at left and right sides of the display region, and a display, the plurality of metal routings being at the first non-display region and insulated from each other, and at least adjacent two of the metal routings being positioned on different layers of the insulating layers. An interval between adjacent metal routings on different insulating layers in a horizontal direction can be reduced through the above wiring manner, thereby reducing a space occupied by the first non-display region. | 2020-04-16 |
20200119051 | Semiconductor Device and Electronic Device - To provide a novel shift register. Transistors | 2020-04-16 |
20200119052 | DISPLAY SUBSTRATE, FABRICATING METHOD THEREOF AND DISPLAY DEVICE - The present disclosure provides a display substrate, a fabricating method thereof, and a display device. The method includes forming a light shielding layer on a surface of a base substrate, and forming a plurality of thin film transistors on a side of the light shielding layer away from the base substrate. Forming a plurality of thin film transistors on a side of the light shielding layer away from the base substrate includes forming a semiconductor layer at a position where an active layer is to be formed in each of the plurality of thin film transistors, generating heat using the light shielding layer, and utilizing the heat to crystallize the semiconductor layer. | 2020-04-16 |
20200119053 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction. | 2020-04-16 |
20200119054 | DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - A display substrate, a method for manufacturing the display substrate, and a display device are provided in the present disclosure. The display substrate includes: a substrate; a first insulation layer on the substrate; a first signal line on a side of the first insulation layer distal to the substrate; a second insulation layer covering the first signal line; and a second signal line on a side of the second insulation layer distal to the substrate, the second signal line overlapping with the first signal line at an overlap region. A concave portion is formed in the first insulation layer. At least at the overlap region, the first signal line is in the concave portion. | 2020-04-16 |
20200119055 | DISPLAY SUBSTRATE AND REPAIRING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure provides a display substrate, a repairing method, and a display device, the display substrate includes a plurality of driving circuits, each of which is configured to drive a display element in each of at least one sub-pixel to display, an output terminal of each driving circuit is coupled to the display element in the sub-pixel driven by the driving circuit through a branch having a switching element, the display substrate further includes: at least one repair line, which is configured to be associated with at least two driving circuits and initially decoupled from an output terminal of at least one of the at least two driving circuits, and the repair line is couplable to the output terminals of the at least two driving circuits with which the repair line is associated in response to a failure of one of the at least two driving circuits. | 2020-04-16 |
20200119056 | ELECTRONIC MODULATING DEVICE - An electronic modulating device is provided. The electronic modulating device includes a first modulating unit. The first modulating unit includes a first transistor including a channel arranged in an extending direction. The first modulating unit also includes a first modulating electrode electrically connected to the first transistor and arranged in a first longitudinal direction. The electronic modulating device also includes a second modulating unit. The second modulating unit includes a second transistor including a channel arranged in the extending direction. The second modulating unit also includes a second modulating electrode electrically connected to the second transistor and arranged in a second longitudinal direction that is different from the first longitudinal direction. The first included angle between the extending direction and the first longitudinal direction is different from a second included angle between the extending direction and the second longitudinal direction. | 2020-04-16 |
20200119057 | ARRAY SUBSTRATE - An array substrate including a substrate, pixel structures, color filter patterns, a first common electrode layer, a second common electrode layer, a conductive structure, and a conductive pattern is provided. The substrate has a display area and a peripheral area. Each pixel structure is disposed in the display area and includes an active device and a pixel electrode. The color filter patterns are respectively disposed corresponding to the pixel structures. The first common electrode layer and the second common electrode layer are sequentially disposed on the color filter patterns, and are structurally separated from the pixel electrodes. The conductive structure is disposed in the peripheral area, and includes a first conductive layer, a second conductive layer and a third conductive layer sequentially disposed on the substrate, wherein the first conductive layer and the first common electrode layer belong to a first same layer, the second conductive layer and the pixel electrodes belong to a second same layer, the third conductive layer and the second common electrode layer belong to a third same layer. The conductive pattern is disposed in the peripheral area, and is electrically connected to the conductive structure. | 2020-04-16 |
20200119058 | DISPLAY PANEL AND METHOD OF FABRICATING THE SAME - A display panel includes: a base layer; a signal line disposed on the base layer, the signal line including: a first layer including aluminum; and a second layer directly disposed on the first layer, the second layer including a niobium-titanium alloy; a first thin film transistor connected to the signal line; a second thin film transistor disposed on the base layer; a capacitor electrically connected to the second thin film transistor; and a light emitting element electrically connected to the second thin film transistor. | 2020-04-16 |
20200119059 | METHOD OF MANUFACTURING ARRAY SUBSTRATE AND ARRAY SUBSTRATE - The present disclosure provides a method of manufacturing array substrate, including: providing a substrate; and forming a metal layer, a gate layer, an insulation layer, and a protective layer on the substrate sequentially. Wherein, the metal layer is formed on a drive line on the substrate, and the metal layer is arranged in at least one of a position between the substrate and the insulation layer and a position between the insulation layer and the protective layer. In the present disclosure, an electrostatic discharge path is increased through the floating metal layer. Even though the floating metal layer is burned down, a display quality would not be affected, the product yield is improved. Besides, it only needs to adjust a photomask pattern. Therefore, a production procedure needs not to be adjusted. | 2020-04-16 |
20200119060 | IMAGE SENSOR WITH A GATED STORAGE NODE LINKED TO TRANSFER GATE - A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel. | 2020-04-16 |
20200119061 | SENSING DRIVING CIRCUIT, DISPLAY PANEL, AND DISPLAY DEVICE - A display device can include a display panel including a plurality of gate lines, a plurality of data lines and a plurality of subpixels; at least one display driving transistor disposed in each of the plurality of subpixels; a sensing transistor disposed in each of the plurality of subpixels; a driver circuit configured to control the sensing transistor; and a sensing circuit electrically connected to a first electrode of the sensing transistor, in which a gate electrode of the at least one display driving transistor and a gate electrode of the sensing transistor are disposed on opposite sides of an active layer in a top-down direction. | 2020-04-16 |
20200119062 | Backside Illuminated Image Sensor and Method of Manufacturing Same - Disclosed is a backside illuminated image sensor and a method of manufacturing the same and, more particularly, a backside illuminated image sensor and a method of manufacturing the same, in which a height difference is between a pixel region and a surrounding region having a boundary between on an uppermost or back surface of a substrate, thereby eliminating one or more problems that occur when a thickness of a color filter in the pixel region is uneven. | 2020-04-16 |
20200119063 | INFRARED DETECTOR HAVING A DIRECTLY BONDED SILICON SUBSTRATE PRESENT ON TOP THEREOF - A direct bonding method for infrared focal plane arrays, includes steps of depositing a thin adhesion layer on infrared radiation detecting material, removing a portion of the thin adhesion layer with a chemical-mechanical polishing process, forming a bonding layer at a bonding interface, and bonding the infrared radiation detecting material to a silicon wafer with the thin adhesion layer as a bonding layer. The thin adhesion layer may include SiO | 2020-04-16 |
20200119064 | IMAGE SENSORS - Image sensors are provided. The image sensors may include a substrate including first, second, third and fourth regions, a first photoelectric conversion element in the first region, a second photoelectric conversion element in the second region, a third photoelectric conversion element in the third region, a fourth photoelectric conversion element in the fourth region, a first microlens at least partially overlapping both the first and second photoelectric conversion elements, and a second microlens at least partially overlapping both the third and fourth photoelectric conversion elements. The image sensors may also include a floating diffusion region and first, second and third pixel transistors configured to perform different functions from each other. Each of the first, second and third pixel transistors may be disposed in at least one of first, second, third and fourth pixel regions. The first pixel transistor may include multiple first pixel transistors. | 2020-04-16 |
20200119065 | IMAGE SENSORS - Image sensors are provided. The image sensors may include a substrate including first, second, third and fourth regions, a first photoelectric conversion element in the first region, a second photoelectric conversion element in the second region, a third photoelectric conversion element in the third region, a fourth photoelectric conversion element in the fourth region, a first microlens at least partially overlapping both the first and second photoelectric conversion elements, and a second microlens at least partially overlapping both the third and fourth photoelectric conversion elements. The image sensors may also include a floating diffusion region and first, second and third pixel transistors configured to perform different functions from each other. Each of the first, second and third pixel transistors may be disposed in at least one of first, second, third and fourth pixel regions. The first pixel transistor may include multiple first pixel transistors. | 2020-04-16 |
20200119066 | IMAGE SENSORS - Image sensors are provided. The image sensors may include a substrate including first, second, third and fourth regions, a first photoelectric conversion element in the first region, a second photoelectric conversion element in the second region, a third photoelectric conversion element in the third region, a fourth photoelectric conversion element in the fourth region, a first microlens at least partially overlapping both the first and second photoelectric conversion elements, and a second microlens at least partially overlapping both the third and fourth photoelectric conversion elements. The image sensors may also include a floating diffusion region and first, second and third pixel transistors configured to perform different functions from each other. Each of the first, second and third pixel transistors may be disposed in at least one of first, second, third and fourth pixel regions. The first pixel transistor may include multiple first pixel transistors. | 2020-04-16 |
20200119067 | IMAGE SENSOR - An imaging device may include regions of active pixels, which are included in the generation of a photoelectric signal, and dummy pixels, which are not included in the generation of a photoelectric signal. Electrical characteristics of the dummy pixels may affect the photoelectric signal produced by the active pixels unless isolation is provided to reduce the electrical conductivity therebetween. An image sensor includes a substrate including an active pixel region and a dummy pixel region, a pixel isolation structure at least partially penetrating the substrate and configured to reduce electrical conductivity between an active pixel in the active pixel region and a dummy pixel in the dummy pixel region, and a dummy isolation structure at least partially penetrating the substrate of the dummy pixel region. | 2020-04-16 |
20200119068 | PIXEL-LEVEL BACKGROUND LIGHT SUBTRACTION - A pixel circuit, a method for performing a pixel-level background light subtraction, and an imaging device are disclosed. In one example of the present disclosure, the pixel circuit includes an overflow gate transistor, a photodiode, and two taps. Each tap of the two taps is configured to store a background signal that is integrated by the photodiode, subtract the background signal from a floating diffusion, store a combined signal that is integrated by the photodiode at the floating diffusion, and generate a demodulated signal based on a subtraction of the background signal from the floating diffusion and a storage of the combined signal that is integrated at the floating diffusion. | 2020-04-16 |
20200119069 | IMAGING DEVICE - An imaging device includes: a semiconductor substrate including a first diffusion region of a first conductivity type and a second diffusion region of the first conductivity type; a first plug that is connected to the first diffusion region and that contains a semiconductor; a second plug that is connected to the second diffusion region and that contains a semiconductor; and a photoelectric converter that is electrically connected to the first plug. An area of the second plug is larger than an area of the first plug in a plan view. | 2020-04-16 |
20200119070 | SENSOR PACKAGE STRUCTURE - A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of metal wires electrically connecting the substrate and the sensor chip, a glass cover disposed on the sensor chip, and an adhesive layer connecting the glass cover to the substrate. The substrate is made of a material having a coefficient of thermal expansion (CTE) that is less than 10 ppm/° C. The glass cover includes a board body and an annular supporting body connected to the board body. The annular supporting body of the glass cover is fixed onto the substrate through the adhesive layer, so that the glass cover and the substrate jointly surround an enclosed accommodating space. The sensor chip and the metal wires are arranged in the accommodating space, and the sensing region of the sensor chip faces the light-permeable portion of the board body. | 2020-04-16 |
20200119071 | STRUCTURE, METHOD FOR PRODUCING STRUCTURE, COMPOSITION FOR FORMING ABSORPTION LAYER, SOLID-STATE IMAGING ELEMENT, AND IMAGE DISPLAY DEVICE - A structure has a color filter having two or more different types of pixels and an absorption layer including at least one selected from a yellow colorant or a colorant having a maximum absorption wavelength in a wavelength range of 400 to 500 nm, in which the structure has the absorption layer on an optical path of at least one pixel of the pixels of the color filter and on the side through which light is incident on the pixel. | 2020-04-16 |
20200119072 | IMAGE SENSOR INCLUDING LASER SHIELD PATTERN - An image sensor includes a substrate including a plurality of unit pixels, a stack structure on the substrate, and a grid pattern between ones of the plurality of unit pixels on the stack structure. The grid pattern includes a lower grid pattern and an upper grid pattern on the lower grid pattern, the lower grid pattern including lanthanum oxide (LaO), amorphous silicon (a-Si), or polysilicon (poly-Si) and the upper grid pattern including a conductive material. | 2020-04-16 |
20200119073 | SOLID-STATE IMAGING APPARATUS - An imaging device includes one or more insulating layers on a substrate; an effective region including: a polarization layer in the one or more insulating layers and including one or more polarizers that polarize light; and at least one first photoelectric conversion region in the substrate and that converts incident light polarized by the one or more polarizers into electric charge; and a peripheral region outside the effective region and including: one or more wiring layers that include a pad portion in a same layer of the one or more insulating layers as the polarization layer. | 2020-04-16 |
20200119074 | 3DIC Seal Ring Structure and Methods of Forming Same - A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip. | 2020-04-16 |
20200119075 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto. | 2020-04-16 |
20200119076 | SEMICONDUCTOR IMAGE SENSOR - A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, and a color filter disposed over the pixel sensor. The pixel sensor includes a plurality of first micro structures disposed over the back side of the substrate. The color filter includes a plurality of second micro structures disposed over the back side of the substrate. Each of the first micro structures has a first height, and each of the second micro structures has a second height. The second height is less than the first height. | 2020-04-16 |
20200119077 | IMAGING ELEMENT, STACKED IMAGING ELEMENT, AND SOLID-STATE IMAGING DEVICE - An imaging element has at least a photoelectric conversion section, a first transistor TR | 2020-04-16 |
20200119078 | IMAGING ELEMENT, STACKED IMAGING ELEMENT, AND SOLID-STATE IMAGING APPARATUS - An imaging element includes a photoelectric conversion unit including a first electrode, a photoelectric conversion layer, and a second electrode that are stacked, in which an inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer, and the inorganic oxide semiconductor material layer includes at least two types of elements selected from the group consisting of indium, tungsten, tin, and zinc. Alternatively, a LUMO value E | 2020-04-16 |
20200119079 | SENSORS FOR SIMULTANEOUS PASSIVE IMAGING AND RANGE FINDING - A sensor includes a sensor array. The sensor array includes a plurality of passive imaging pixels and a plurality of time of flight (TOF) imaging pixels. A method of imaging includes collecting passive imaging data from a sensor array and collecting time of flight (TOF) imaging data from the sensor array. Collecting passive imaging data and collecting TOF imaging data can be performed at least partially at the same time and along a single optical axis without parallax. | 2020-04-16 |
20200119080 | Methods of Making Semiconductor X-Ray Detector - Disclosed herein is an image sensor and a method of making the image sensor. The image sensor may comprise one or more packages of semiconductor radiation detectors. Each of the one or more packages may comprise a radiation detector that comprises a radiation absorption layer on a first strip of semiconductor wafer and an electronics layer on a second strip of semiconductor wafer. The radiation absorption layer may be continuous along the first strip of semiconductor wafer with no coverage gap. The first strip and the second strip may be longitudinally aligned and bonded together. The radiation detector may be mounted on a printed circuit board (PCB) and electrically connected to the PCB close to an edge of the radiation detector. | 2020-04-16 |
20200119081 | Method of Forming Deep Trench Isolation in Radiation Sensing Substrate and Image Sensor Device - A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiC | 2020-04-16 |
20200119082 | IMAGE SENSOR INCLUDING ACTIVE REGIONS - An image sensor is provided to include an active region which comprises: a floating diffusion region; a transfer transistor gate region; transistor active regions; and a well-tap region. The transfer transistor gate region may have a diagonal bar shape to isolate the floating diffusion region in a first corner of the active region. The well-tap region may be positioned between the transfer transistor gate region and the transistor active regions, and isolate the transfer transistor gate region from the transistor active regions. | 2020-04-16 |
20200119083 | TIME DELAY INTEGRATION IMAGE SENSORS WITH NON-DESTRUCTIVE READOUT CAPABILITIES - A time delay integration image sensor may include a number of charge coupled devices (CCDs) that transfer charge in synchronization with the movement of an object being imaged. To increase the dynamic range of the image sensor, the image sensor may include circuitry configured to non-destructively sample the charge as it is transferred through the charge coupled devices. Floating gates may be included in the image sensor and may have a voltage that is proportional to the charge accumulated under the floating gates. Each floating gate may be coupled to a respective readout circuit in an additional substrate by a metal interconnect layer. | 2020-04-16 |
20200119084 | Luminescence Diode and Method for Producing the Same - A luminescence diode and a method for producing a luminescence diode are disclosed. In an embodiment a luminescence diode includes a carrier substrate, a first semiconductor layer sequence including a first active layer suitable for emitting radiation having a first dominant wavelength λ | 2020-04-16 |
20200119085 | VERTICAL STACKS OF LIGHT EMITTING DIODES AND CONTROL TRANSISTORS AND METHOD OF MAKING THEREOF - A light emitting device includes a vertical stack of a light emitting diode and a field effect transistor that controls the light emitting diode. An isolation layer is present between the light emitting diode and the field effect transistor, and an electrically conductive path electrically shorts a node of the light emitting diode to a node of the field effect transistor. The field effect transistor may include an indium gallium zinc oxide (IGZO) channel and may be located over the isolation layer. Alternatively, the field effect transistor may be a high-electron-mobility transistor (HEMT) including an epitaxial semiconductor channel layer and the light emitting diode may be located over the HEMT. | 2020-04-16 |
20200119086 | OPTOELECTRONIC DEVICE - An optoelectronic device comprises a substrate; a first optoelectronic unit formed on the substrate; a second optoelectronic unit formed on the substrate; a plurality of third optoelectronic units formed on the substrate, electrically connected to the first optoelectronic unit and the second optoelectronic unit; a plurality of first electrodes respectively formed on the first optoelectronic unit, the second optoelectronic unit and the plurality of third optoelectronic units; a plurality of second electrodes respectively formed on the first optoelectronic unit, the second optoelectronic unit and the plurality of third optoelectronic units; an optical layer surrounding the first optoelectronic unit, the second optoelectronic unit and the plurality of third optoelectronic units in a top view of the optoelectronic device; a third electrode formed on the first optoelectronic unit and one of the plurality of third optoelectronic units; and a fourth electrode formed on the second optoelectronic unit and another one of the plurality of third optoelectronic units. | 2020-04-16 |
20200119087 | TECHNIQUES FOR MONOLITHIC CO-INTEGRATION OF POLYCRYSTALLINE THIN-FILM BULK ACOUSTIC RESONATOR DEVICES AND MONOCRYSTALLINE III-N SEMICONDUCTOR TRANSISTOR DEVICES - Techniques are disclosed for monolithic co-integration of thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices and III-N semiconductor transistor devices. In accordance with some embodiments, one or more TFBAR devices including a polycrystalline layer of a piezoelectric III-N semiconductor material may be formed alongside one or more III-N semiconductor transistor devices including a monocrystalline layer of III-N semiconductor material, over a commonly shared semiconductor substrate. In some embodiments, either (or both) the monocrystalline and the polycrystalline layers may include gallium nitride (GaN), for example. In accordance with some embodiments, the monocrystalline and polycrystalline layers may be formed simultaneously over the shared substrate, for instance, via an epitaxial or other suitable process. This simultaneous formation may simplify the overall fabrication process, realizing cost and time savings, at least in some instances. | 2020-04-16 |
20200119088 | FABRICATING EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE WITH V SHAPED MAGNETIC TUNNEL JUNCTION PROFILE - Fabricating a magnetoresistive random access memory (MRAM) device includes receiving a wafer structure having a first inter-layer dielectric (ILD) layer and a metal material disposed within the first ILD layer. A second ILD layer is deposited upon a top surface of the first ILD layer and the metal material. A trench is formed within the second ILD layer extending to the top surface of the metal material. A plurality of magnetic stack layers of a magnetic stack and an electrode layer are deposited within the trench. Portions of each of the magnetic stack layers of the magnetic stack and the electrode layer are removed to form a v-shaped magnetic tunnel junction (MTJ) in contact with the metal material. | 2020-04-16 |
20200119089 | DIELECTRIC FILL FOR MEMORY PILLAR ELEMENTS - A method for fabricating a semiconductor device includes forming one or more encapsulation spacers each about respective ones of one more memory pillar elements to have a geometry, including forming each encapsulation spacer to have a footing of at least about twice a critical dimension of its corresponding pillar, and depositing dielectric material on the one or more memory pillar elements and the one or more encapsulation spacers to form an interlayer dielectric free of voids based on the geometry. | 2020-04-16 |
20200119090 | ELECTRONIC DEVICES WITH SEED AND MAGNETIC REGIONS AND METHODS OF FABRICATION - A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed. | 2020-04-16 |
20200119091 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely. | 2020-04-16 |
20200119092 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line. | 2020-04-16 |
20200119093 | MAGNETORESISTIVE RANDOM ACCESS MEMORY THIN FILM TRANSISTOR UNIT CELL - A MRAM-TFT unit cell and a method for fabricating the same. The MRAM-TFT unit cell includes a MRAM device and a TFT device electrically coupled to the MRAM device. The MRAM device and the TFT device are situated within a common plane of the MRAM-TFT cell. The method includes forming a TFT device comprising a source/drain region, and a semiconducting layer on a substrate. A magnetic tunnel junction stack (MTJ) is formed in contact with the source region. A first contact is formed on the MTJ, and a second contact is formed on the drain region. A first interconnect metal layer is formed in contact with the first contact, and a second first interconnect metal layer is formed in contact with the second contact. A third contact is formed on a gate region of the TFT device. A third interconnect metal layer is formed in contact with the third contact. | 2020-04-16 |
20200119094 | MULTI-LAYERED CONDUCTIVE METAL OXIDE STRUCTURES AND METHODS FOR FACILITATING ENHANCED PERFORMANCE CHARACTERISTICS OF TWO-TERMINAL MEMORY CELLS - A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO. | 2020-04-16 |
20200119095 | VARIABLE RESISTANCE MEMORY DEVICES - A variable resistance memory device may include a plurality of stacked structures. Each of the stacked structures may be formed on a substrate, and may include a lower electrode, a variable resistance pattern and a selection pattern sequentially stacked. A threshold voltage control pattern may be formed on the stacked structures, may extend in a second direction parallel to an upper surface of the substrate and may be configured to either increase or decrease a threshold voltage of each selection pattern. An upper electrode may be formed on the threshold voltage control pattern and may extend in the second direction. A first conductive line may contact respective lower surfaces of the lower electrodes of the stacked structures and extend in a first direction perpendicular to the second direction. A second conductive line may contact an upper surface of the upper electrode and extend in the second direction. | 2020-04-16 |
20200119096 | SEMICONDUCTOR IMAGE SENSORS HAVING MULTI-LAYER TRANSPARENT ELECTRODES THEREIN AND METHODS OF FORMING SAME - A semiconductor image sensor includes a substrate and an isolation insulating pattern having a trench therein, on the substrate. A lower transparent electrode is provided within the trench. This lower transparent electrode includes a first layer and a different second layer on the first layer. An organic photoelectric layer is provided on the lower transparent electrode, and an upper transparent electrode is provided on the organic photoelectric layer. The first layer may contact a bottom and a side surface of the trench, and may have a seam therein, which is at least partially filled by a portion of the second layer. The first layer may have a higher light transmission efficiency relative to the second layer and a lower electrical resistance relative to the second layer. | 2020-04-16 |
20200119097 | IMAGE SENSOR - An image sensor includes a first organic photoelectric conversion layer on a base layer, a floating diffusion region in the base layer, a first storage node including a first electrode layer, which is configured to receive a bias signal, a first portion of a first semiconductor layer which includes a semiconductor material, and a first portion of a first dielectric layer. The first dielectric layer extends between the first electrode layer and the first semiconductor layer. The first storage node is electrically connected to the first organic photoelectric conversion layer. The image sensor includes a first transfer transistor including the first dielectric layer, the first semiconductor layer, and a first transfer gate electrode which is configured to receive first transfer control signal. The first transfer transistor has a first end electrically connected to the first storage node and a second end electrically connected to the floating diffusion region. | 2020-04-16 |
20200119098 | IMAGING DEVICE AND MANUFACTURING METHOD THEREOF - An imaging device according to one aspect of the present disclosure includes: a semiconductor substrate; and pixels. Each of the pixels includes: a photoelectric converter that converts incident light into electric charge; a diffusion region provided in the semiconductor substrate and electrically connected to the photoelectric converter; a first transistor including a gate, and the diffusion region as one of a source and a drain; and a plug that is directly connected to the diffusion region, is electrically connected to the photoelectric converter, and includes a semiconductor. The height of the plug and the height of the gate from the surface of the semiconductor substrate are equal to each other. | 2020-04-16 |
20200119099 | IMAGING DEVICE AND IMAGING APPARATUS - An imaging device according to an embodiment of the present disclosure includes: a pixel region in which a plurality of pixels is disposed; a surrounding region provided around the pixel region; an organic photoelectric conversion layer continuously provided from the pixel region to a portion of the surrounding region; an electrically-conducive layer provided on the organic photoelectric conversion layer from a periphery of the pixel region to the surrounding region; and a black layer provided on the electrically-conducive layer. The electrically-conducive layer has a light-shielding property. | 2020-04-16 |
20200119100 | PHOTOELECTRIC CONVERSION ELEMENT, IMAGE PICKUP ELEMENT, LAMINATED IMAGE PICKUP ELEMENT, AND SOLID-STATE IMAGE PICKUP DEVICE - An image pickup element is constituted by laminating at least a first electrode, an organic photoelectric conversion layer, and a second electrode in order, and the organic photoelectric conversion layer includes a first organic semiconductor material having the following structural formula (1). | 2020-04-16 |
20200119101 | DISPLAY PANEL AND DISPLAY APPARATUS HAVING THE SAME - A display panel, including a light source configured to emit blue light; and a quantum dot color filter layer including: a red light converter including a red quantum dot particle configured to convert the blue light into red light, a green light converter including a green quantum dot particle configured to convert the blue light into green light, a light transmitting portion configured to transmit the blue light, and a white light generator including a first region and a second region, wherein the first region comprises a plurality of yellow quantum dot particles configured to convert the blue light into yellow light, wherein the second region transmits the blue light. | 2020-04-16 |
20200119102 | Organic Light Emitting Display Having Touch Sensors and Method of Fabricating the Same, and Display Device - Disclosed is a display device comprising: a substrate comprising an active region and a non-active region; a light emitting device that emits light in the active area of the substrate; a touch sensor in the active area of the substrate that senses touch of the display device, the touch sensor including a plurality of conductive layers arranged in a stacking sequence; and a plurality of routing lines in the non-active region of the substrate that are connected to the touch sensor, each of the plurality of routing lines including a plurality of routing layers, each of the plurality of routing layers made of a same material as a corresponding one of the plurality of conductive layers included in the touch sensor, and the plurality of routing layers arranged in a same stacking sequence as the stacking sequence of the plurality of conductive layers of the touch sensor. | 2020-04-16 |
20200119103 | DISPLAY DEVICE - An EL display device includes a TFT substrate on which a scanning line extends in a first direction, a video signal line extends in a second direction, and an EL element having an anode, a luminous layer and a cathode. A protective film covers the scanning line, the video signal line and the EL element. A touch panel detection electrode is disposed above the protective film, and connected to a wiring which is disposed under the protective film via a through hole of the protective film. The touch panel detection electrode has an angle to intersect with the video signal line. | 2020-04-16 |
20200119104 | DISPLAY DEVICE - A display device includes a pixel circuit substrate, a plurality of light emitting devices, a driver circuit substrate, a plurality of connection terminals, and an electrically conductive adhesion layer. The light emitting devices are electrically connected to the pixel circuit substrate. The driver circuit substrate is disposed on a back side of the pixel circuit substrate. The connection terminals electrically connect the driver circuit substrate to the pixel circuit substrate. The electrically conductive adhesion layer is disposed between the pixel circuit substrate and the driver circuit substrate. | 2020-04-16 |
20200119105 | DISPLAY APPARATUS - A display apparatus includes a substrate including a display region and a non-display region, a blue sub-pixel in the display region of the substrate, an imaginary line extending across the blue sub-pixel, a first sub-unit on a first side of the imaginary line, the first sub-unit including a red sub-pixel, a green sub-pixel, and a white sub-pixel, and a second sub-unit on a second side of the imaginary line, the second sub-unit including a red sub-pixel, a green sub-pixel, and a white sub-pixel, wherein the first sub-unit and the blue sub-pixel constitute a first pixel, and the second sub-unit and the blue sub-pixel constitute a second pixel, and wherein the blue sub-pixel emits light according to a data signal generated based on blue-related data of first pixel data corresponding to the first pixel and blue-related data of second pixel data corresponding to the second pixel. | 2020-04-16 |
20200119106 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - The present disclosure provides an organic light-emitting display device that includes a substrate. A plurality of sub-pixels are arranged on the substrate, and each of the sub-pixels includes an organic light-emitting diode having a first electrode. A first bank has a plurality of first openings, and each of the first openings at least partially exposes a respective first electrode. A second bank has a plurality of second openings, and each of the second openings at least partially exposes one or more of the first electrodes. Each of a first set of the second openings exposes n first electrodes (n is a natural number equal to or greater than 1), and each of a second set of the second openings exposes m first electrodes (m is a natural number equal to or greater than 1), wherein n and m are different values. | 2020-04-16 |
20200119107 | PIXEL ARRANGEMENT STRUCTURE, DISPLAY SUBSTRATE, AND DISPLAY DEVICE - A pixel arrangement structure, a display substrate, and a display device. The pixel arrangement structure includes a plurality of pixel sets; each pixel set comprises a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel; in the pixel set, a line connecting the center of the second sub-pixel and the center of the third sub-pixel is a first line segment; the first sub-pixel and the fourth sub-pixel are located between the second sub-pixel and the third sub-pixel and are respectively disposed at two sides of the first line segment; a line connecting the center of the first sub-pixel and the center of the fourth sub-pixel is a second line segment, and the length of the second line segment is shorter than the length of the first line segment. | 2020-04-16 |
20200119108 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a light emitting layer for emitting light and for displaying an image, a fingerprint sensor for detecting a fingerprint, and a circuit element layer disposed between the light emitting layer and the fingerprint sensor and configured to control the light emitting layer. The fingerprint sensor includes a light receiver. The light receiver overlaps the light emitting layer and has an uneven surface. | 2020-04-16 |
20200119109 | DISPLAY SYSTEM COMPRISING AN IMAGE SENSOR - A display system including a display screen having first and second display sub-pixels where each first display sub-pixel includes a first light-emitting component emitting a first radiation and covered with a first colored filter and first conductive tracks and where each second display sub-pixel includes a second light-emitting component emitting a second radiation and covered with a second colored filter and second conductive tracks. The display system further includes an image sensor detecting the first or second radiation or a third radiation. The first display sub-pixels include first elements absorbing the first radiation and the second radiation and covering the first conductive tracks. The first absorbing elements and/or the first colored filter delimit a first passageway along the stacking direction for the first, second, or third radiation. | 2020-04-16 |
20200119110 | FLEXIBLE ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING SAME - A flexible organic light emitting diode (OLED) display device and a method for fabricating the same are disclosed. The flexible OLED display device includes a first flexible substrate, an inorganic layer, a second flexible substrate, a thin film transistor (TFT) layer, and an OLED light emitting layer; wherein the flexible OLED display device includes a display area and a non-display area. The first flexible substrate and the inorganic layer are located in the display area, and the second flexible substrate and the TFT layer extend from the display area to the non-display area. | 2020-04-16 |
20200119111 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device according to an embodiment includes a substrate having a display area, and a peripheral area outside the display area including a first peripheral area adjacent to the display area, a first bending area extending from the first peripheral area, and a second peripheral area extending from the first bending area, and overlapping the first peripheral area, a display member at the display area, and including a first display area, and a second display area around the first display area, and a plurality of align keys on the substrate, wherein the first peripheral area includes a flat peripheral area corresponding to an area between the first display area and the first bending area, and a second bending area between the second display area and an end of the substrate, and wherein the plurality of align keys include a first align key at the flat peripheral area, and a second align key at the second peripheral area. | 2020-04-16 |
20200119112 | DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME - The present disclosure provides a display panel and method for manufacturing same. The method for manufacturing the display panel includes providing an array substrate, wherein a source/drain metal is disposed on the array substrate; sequentially forming a planarization layer and a pixel defining layer on the array substrate, wherein the pixel defining layer comprises a plurality of pixel defining bodies that are spaced apart from each other, and a region located between any two adjacent pixel defining bodies constitutes a pixel area; and forming an anode layer in the pixel area, wherein an edge of the anode layer is attached to the pixel defining layer. | 2020-04-16 |
20200119113 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device including a base layer; an insulating layer disposed on the base layer and including a flat region having a flat surface and a lens region having a concave or convex surface; a dam disposed on the insulating layer and defining an opening exposing the lens region; and a color filter disposed on the lens region of the insulating layer and filling the opening, The dam includes a sensing electrode. | 2020-04-16 |
20200119114 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a substrate, a pixel defining layer, a spacer, an auxiliary electrode, and an organic light emitting diode. The substrate includes a light emitting area and a non-light emitting area adjacent to the light emitting area. The pixel defining layer is disposed on the non-light emitting area of the substrate. The spacer is disposed on the pixel defining layer. The auxiliary electrode is disposed on the spacer. The organic light emitting diode is disposed on the substrate, and at least a portion thereof is disposed in the light emitting area. The organic light emitting diode includes a pixel electrode, an intermediate layer disposed on the pixel electrode and including an organic light emitting layer, and an opposite electrode disposed on the intermediate layer and electrically connected to the auxiliary electrode. | 2020-04-16 |
20200119115 | DISPLAY APPARATUS - A display apparatus having an opening ratio that provides a high resolution and improved luminous quality and including: a substrate; a first driving thin-film transistor (TFT) and a first storage capacitor, the first storage capacitor for emitting light of a first color and on the substrate; a data wiring unit including a first data line, a second data line, and a third data line, at a first side of the first storage capacitor, extending along a first direction and spaced apart from one another along a second direction, intersecting the first direction, by a predetermined distance; a driving voltage line at a second side of the first storage capacitor and extending along the first direction; and a first pixel electrode electrically connected to the first driving TFT. | 2020-04-16 |
20200119116 | FLEXIBLE ORGANIC ELECTROLUMINESCENT DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a flexible organic electroluminescent device and a method for fabricating the same. In the flexible electroluminescent device, line hole patterns are formed on surfaces of a plurality of inorganic layers positioned in a pad region in which a flexible printed circuit board is connected to prevent a path of cracks caused by repeated bending and spreading of the organic electroluminescent device from spreading to the interior of the device. | 2020-04-16 |
20200119117 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate, a first semiconductor element, a second semiconductor element, a protection electrode, and a light emitting structure. The protection electrode is disposed between the second active layer and the second source electrode and the second drain electrode, and has an opening that exposes a portion of the second active layer and the light emitting structure is disposed on the first and second semiconductor elements. | 2020-04-16 |
20200119118 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device is disclosed, which removes an inorganic film from a bending area and minimizes a crack of a routing line to enable an extreme bending. The organic light emitting display device comprises a substrate having a display area and a bending area; a display assembly provided on a display area of the substrate; a routing line arranged on the bending area of the substrate and connected to the display assembly; and an organic layer provided on the bending area of the substrate, covering the routing line, wherein the bending area of the substrate has only the routing line and the organic layer. | 2020-04-16 |
20200119119 | BACKPLANE SUBSTRATE, MANUFACTURING METHOD FOR THE SAME, AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE USING THE SAME - Disclosed are a backplane substrate, which is devised to attain circuit characteristics for realizing sufficient gradation even in smaller pixels of a super-high-resolution structure, a manufacturing method for the same, and an organic light-emitting display device using the same, inn the backplane substrate, a driving thin-film transistor has a stack structure different from that of other thin-film transistors so that only the S-factor of the driving thin-film transistor is increased. | 2020-04-16 |
20200119120 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE - An array substrate includes a base substrate and a plurality of pixel units disposed on a base substrate, and at least one pixel unit includes a plurality of thin film transistors, a first electrode, and a second electrode. The plurality of thin film transistors include at least one first thin film transistor including a first active pattern, a first gate, a first source and a first drain. The first electrode is disposed in a same layer as the first active pattern, the first electrode is coupled to the first drain, and the second electrode is disposed in a same layer as the first gate. Orthographic projections of any two in a group consisting of the first electrode, the second electrode, and the first drain on the base substrate have an overlapping region. | 2020-04-16 |
20200119121 | ARRAY SUBSTRATE - The present disclosure provides an array substrate, including: a base substrate, a first metal, a buffer layer, a second metal, a second buffer layer, a third metal. A via is defined in the first buffer layer and the second buffer layer to electrically interconnect the first metal and the third metal, so that the first metal, the second metal and the third metal constitute parallel capacitors. | 2020-04-16 |
20200119122 | Display Panel and Display Device - A display panel and a display device includes a high-permittivity material disposed between electrodes of capacitor disposed in a subpixel. This increases the capacitance per area of the capacitor, such that a high-resolution display device is provided. A high-permittivity material is disposed in the insulating layer, and the surface of the insulating layer is planarized by polishing. The high-permittivity material is prevented from residing in any area, except for the area in which the capacitor is disposed. An unnecessary increase in load in the subpixel is prevented, and the capacitance of the capacitor is increased. | 2020-04-16 |
20200119123 | DISPLAY DEVICE, DISPLAY DEVICE MANUFACTURING METHOD, AND DISPLAY DEVICE MANUFACTURING APPARATUS - To reduce a possibility of short circuiting between a wiring line that connects to a terminal unit and a pixel electrode, a display device is provided that includes a first lead wiring line that extends from a display area to a frame area while intersecting with an end portion of a flattening film, a second lead wiring line that is in a layer more on an upper side than the first lead wiring line and extends to a terminal unit while coming into contact with and intersecting with a first bank formed in a periphery of a second electrode, and a first wiring line contact part through which the first lead wiring line and the second lead wiring line connect to each other, the first wiring line contact part being provided between an end portion of the flattening film and the first bank. | 2020-04-16 |
20200119124 | DISPLAY APPARATUS - A display apparatus including a flexible substrate, the flexible substrate including a first area where an image is displayed, a second area separated from the first area, and a bending area between the first area and the second area; a display on the first area of the substrate; a pad on the second area of the substrate; and a plurality of wirings on the substrate, the plurality of wirings including a first wiring having a first shape; and a second wiring having a second shape that is different from the first shape, the first wiring and the second wiring passing through the bending area. | 2020-04-16 |
20200119125 | DISPLAY DEVICE - According to an exemplary embodiment of the present invention, a display device includes a static electricity blocking circuit having a first conductive layer, a first semiconductor portion, a second semiconductor portion, a channel portion disposed therebetween, a first electrode connected to the first semiconductor portion through first signal line contact holes, and a second electrode connected to the second semiconductor portion through first power line contact holes. The first signal line contact holes are disposed closer to an outermost edge of the first semiconductor portion than an innermost edge thereof. The first power line contact holes are disposed closer to an outermost edge of the second semiconductor portion than an innermost edge thereof. The second conductive layer is closer to the innermost edge of the first semiconductor portion than the outermost edge thereof and is closer to the innermost edge of the second semiconductor portion than the outermost edge thereof. | 2020-04-16 |
20200119126 | DISPLAY DEVICE - There is provided a display device. The display device includes a first data line on a first interlayer insulating layer over a substrate, a first power line and a second power line on a second interlayer insulating layer, the second interlayer insulating layer covering the first data line, and a plurality of pixels. A first pixel among the plurality of pixels includes a display element including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode, the second power line being connected to the opposite electrode, and a driving thin film transistor between the substrate and the display element and including a driving semiconductor layer, a driving gate electrode, a driving source electrode, and a driving drain electrode, the first interlayer insulating layer covering the driving gate electrode, and the first power line being connected to the driving source electrode. | 2020-04-16 |
20200119127 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel has a display area. The display panel includes: a base substrate; a driving circuit and at least one signal line on the base substrate; and at least one insulating layer between the driving circuit and the at least one signal line. The driving circuit is disposed in a periphery of the display area; and an orthogonal projection of at least one of the signal lines on the base substrate has an overlapping area with an orthogonal projection of the driving circuit on the base substrate. | 2020-04-16 |
20200119128 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - The organic light emitting display device according to the exemplary aspect of the present disclosure includes a flexible substrate which includes a first area, a second area, and a bending area between the first area and the second area, and a wiring line on the bending area of the flexible substrate. The wiring line has a plurality of unit patterns having a rhombic shape. In this case, each of plurality of unit patterns shares a part of one side with the adjacent unit pattern. According to the organic light emitting display device according to an exemplary aspect of the present disclosure, a wiring line having a new shape is disposed in the bending area so that a stress which is applied to the wiring line and the protective layer formed in the bending area may be minimized. | 2020-04-16 |
20200119129 | DISPLAY APPARATUS - A display apparatus including a first conductive layer; a first insulating layer including a first opening exposing a first upper surface of the first conductive layer and covering at least a part of an upper edge of the first conductive layer, wherein the first upper surface of the first conductive layer includes a center portion of an upper surface of the first conductive layer; a second conductive layer on a part of the first upper surface of the first conductive layer and on the first insulating layer; and a second insulating layer including a second opening exposing a second upper surface of the second conductive layer and covering a part of an upper edge of the second conductive layer, wherein the second upper surface of the second conductive layer includes a center portion of the upper surface of the second conductive layer. | 2020-04-16 |