16th week of 2015 patent applcation highlights part 39 |
Patent application number | Title | Published |
20150104896 | HOLLOW CATHODE SYSTEM, DEVICE AND METHOD FOR THE PLASMA-ASSISTED TREATMENT OF SUBSTRATES - A hollow cathode system, a device and a method for the plasma-assisted treatment of substrates includes at least one hollow cathode, which can be connected to a power supply. The hollow cathode includes an electrically conducting main body with an opening which is bounded by ribs, follows a spiral or meandering path and allows a gas to pass through in a direction perpendicular to a surface of the main body. Connecting bridge elements are provided on the ribs. The bridge elements serve ensure mechanical stability of the hollow cathode and optimize potential distribution of the hollow cathode. With the hollow cathode system, high treatment rates are achieved for homogeneous treatment of substrates of a large surface area with high plasma stability. | 2015-04-16 |
20150104897 | DEVICE FOR THE HOMOGENEOUS WET-CHEMICAL TREATMENT OF SUBSTRATES - A device for wet-chemical treatment of substrates includes: an accommodation device for a substrate and a process medium, the substrate having a treatment side in operative connection with the process medium; a fluid guidance element, having a specified surface texture, housed in the accommodation device, the specified surface texture being configured to provide a guidance of the process medium along the specified surface texture, the specified surface texture being positioned lying opposite and at a predetermined fixed recess at a distance from the treatment side of the substrate; and the process medium being moved in the intervening space between the specified surface texture of the fluid guidance element and the treatment side of the substrate. | 2015-04-16 |
20150104898 | METHOD FOR MANUFACTURING INVERTED METAMORPHIC MULTIJUNCTION SOLAR CELLS - A method of fabricating both a multijunction solar cell and an inverted metamorphic multijunction solar cell in a single process using a MOCVD reactor by forming a first multijunction solar cell on a semiconductor substrate; forming a release layer over the first solar cell; forming an inverted metamorphic second solar cell over the release layer; and etching the release layer so as to separate the multijunction first solar cell and the inverted metamorphic second solar cell. | 2015-04-16 |
20150104899 | Manufactoring Semiconductor-Based Multi-Junction Photovoltaic Devices - Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs. Certain solar cells may further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device. | 2015-04-16 |
20150104900 | METHOD FOR FORMING STRUCTURES IN A SOLAR CELL - A conductive contact pattern is formed on a surface of solar cell by forming a thin conductive layer over at least one lower layer of the solar cell, and ablating a majority of the thin conductive layer using a laser beam, thereby leaving behind the conductive contact pattern. The laser has a top-hat profile, enabling precision while scanning and ablating the thin layer across the surface. Heterocontact patterns are also similarly formed. | 2015-04-16 |
20150104901 | OXIDE SEMICONDUCTOR FILM AND SEMICONDUCTOR DEVICE - It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed. | 2015-04-16 |
20150104902 | METHOD FOR FASTENING CHIPS WITH A CONTACT ELEMENT ONTO A SUBSTRATE PROVIDED WITH A FUNCTIONAL LAYER HAVING OPENINGS FOR THE CHIP CONTACT ELEMENTS - A method for tacking of chips onto a substrate at chip positions which are distributed on a surface of the substrate. The method includes the following steps: formation or application of a function layer onto the substrate, removing the function layer from the substrate at the chip positions at least in the region of contacts to uncover the contacts, tacking chips onto one chip contact side of the function layer at the chip positions and contacting the chips with the contacts via contact elements. | 2015-04-16 |
20150104903 | Treating Copper Surfaces for Packaging - A die has a top surface, and a metal pillar having a portion protruding over the top surface of the die. A sidewall of the metal pillar has nano-wires. The die is bonded to a package substrate. An underfill is filled into the gap between the die and the package substrate. | 2015-04-16 |
20150104904 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface of the first electrode, the surface of the third semiconductor chip and the upper surface of the fourth electrode, the surface of the fourth semiconductor chip and the upper surface of the fifth electrode, and the upper surface of the second electrode and the upper surface of the third electrode are coupled to each other by first to fifth conductive members, respectively; and the back surfaces of the first to fifth electrodes are exposed from a resin molding. The invention makes it possible to reduce the size and the thickness of a semiconductor device configuring a diode bridge circuit. | 2015-04-16 |
20150104905 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE - A semiconductor package includes a circuit board having an inner circuit pattern and a plurality of contact pads connected to the inner circuit pattern, at least one integrated circuit (IC) device on the circuit board and making contact with the contact pads, a mold on the circuit board, the mold fixing the IC device to the circuit board, and a surface profile modifier on a surface of the IC device and a surface of the mold, and the surface profile modifier enlarging a surface area of the IC device and the mold to dissipate heat. | 2015-04-16 |
20150104906 | PACKAGE FOR HIGH-POWER SEMICONDUCTOR DEVICES - Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed. | 2015-04-16 |
20150104907 | BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER - An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface. | 2015-04-16 |
20150104908 | High-Voltage Packaged Device - Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described. | 2015-04-16 |
20150104909 | APPARATUS AND METHOD FOR SELF-ALIGNING CHIP PLACEMENT AND LEVELING - An approach is provided for aligning and leveling a chip package portion. The approach involves filling, at least partially, a reservoir formed between a first sidewall portion having a first slanted surface and a second sidewall portion having a second slanted surface with a fluid. The approach also involves placing a chip package portion into the reservoir. The approach further involves draining the fluid from the reservoir to cause the chip package portion to align with respect to a center of the reservoir. The chip package portion aligns with respect to the center of the reservoir and levels based on a relationship between the chip package portion, an angle of the first slanted surface, an angle of the second slanted surface, and the fluid. The chip package portion is secured in the aligned and leveled state by a molding compound. | 2015-04-16 |
20150104910 | TFT FLAT SENSOR AND MANUFACTURING METHOD THEREFOR - A TFT flat sensor comprises pixel units each comprising: a common electrode and a common electrode insulating layer on a substrate, wherein a first via hole is provided in the common electrode insulating layer at a location corresponding to the common electrode; a gate electrode on the common electrode insulating layer; a first conductive film layer on the common electrode and the gate electrode wherein the first conductive film layer contacts the common electrode through a first via hole; a gate insulating layer, an active layer, a drain electrode and a source electrode, a second conductive film layer, a protection layer and a third conductive film layer on the first conductive film layer; a second via hole is provided in the protection layer at a location corresponding to the source electrode through which the third conductive film layer contacts the source electrode. | 2015-04-16 |
20150104911 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer. | 2015-04-16 |
20150104912 | VERTICAL GALLIUM NITRIDE POWER DEVICE WITH BREAKDOWN VOLTAGE CONTROL - A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction. | 2015-04-16 |
20150104913 | Simultaneous Formation of Source/Drain Openings with Different Profiles - A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening. | 2015-04-16 |
20150104914 | SEMICONDUCTOR PROCESS - A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is cryo-implanted with at least two of multiple species including a germanium species, a carbon species and a p- or n-type species, at a temperature ranging between −40° C. and −120° C. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating. | 2015-04-16 |
20150104915 | MEMORY CELL WITH DECOUPLED CHANNELS - A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel. | 2015-04-16 |
20150104916 | Method of Manufacturing Three Dimensional Semiconductor Memory Device - A method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately stacking a first insulation film, a first sacrificial film, alternating second insulation films and second sacrificial films, a third sacrificial film and a third insulation film on a substrate. A channel hole is formed to expose a portion of the substrate while passing through the first insulation film, the first sacrificial film, the second insulation films, the second sacrificial films, the third sacrificial film and the third insulation film. The method further includes forming a semiconductor pattern on the portion of the substrate exposed in the channel hole by epitaxial growth. Forming the semiconductor pattern includes forming a lower epitaxial film, doping an impurity into the lower epitaxial film, and forming an upper epitaxial film on the lower epitaxial film. Forming the lower epitaxial film, doping the impurity into the lower epitaxial film and forming the upper epitaxial film are all performed in-situ, and the semiconductor pattern includes a doped region and an undoped region. | 2015-04-16 |
20150104917 | Power MOSFET and Methods for Forming the Same - A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region. | 2015-04-16 |
20150104918 | FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS - Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges. | 2015-04-16 |
20150104919 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE, VARIABLE RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The method may include forming a source on a semiconductor substrate, sequentially forming a first semiconductor layer formed of a first material, a second semiconductor layer formed of a second material having a higher oxidation rate than that of the first material, and a third semiconductor layer formed of the first material on the source; patterning the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; forming a lightly doped drain (LDD) region in the second semiconductor layer and a drain in the third semiconductor layer; oxidizing outer circumferences of the first semiconductor layer, the LDD region and the drain region to form a gate insulating layer; forming a gate on an outer circumference of the gate insulating layer to overlap the first semiconductor layer and a portion of the LDD region; foaming a heating electrode on the drain; and forming a variable resistance layer on the heating electrode. | 2015-04-16 |
20150104920 | SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region. | 2015-04-16 |
20150104921 | Method of Fabricating A Variable Reistance Memory Device - A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles. The cell diode includes a first impurity pattern and a second impurity pattern, the dummy diode includes a first lightly doped impurity pattern and a second impurity pattern, and the variable resistive element includes a first electrode, a variable resistor, and a second electrode. | 2015-04-16 |
20150104922 | INTEGRATED DEVICE WITH DEFINED HEAT FLOW - An integrated device includes at least one heat generating component which generates heat when operated, at least one temperature-sensitive component, and one or more hollow insulation regions arranged between the at least one heat generating component and the at least one temperature-sensitive component. The hollow insulation region may be provided as a vacuum gap. | 2015-04-16 |
20150104923 | Mechanism of Forming a Trench Structure - Embodiments of a mechanism for forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer are provided. The mechanism involves using one or more low-temperature thermal anneal processes with oxygen sources and one or more microwave anneals to convert a flowable dielectric material to silicon oxide. The low-temperature thermal anneal processes with oxygen sources and the microwave anneals are performed at temperatures below the ranges that could cause significant dopant diffusion, which help dopant profile control for advanced manufacturing technologies. In some embodiments, an implant to generate passages in the upper portion of the flowable dielectric layer is also used in the mechanism. | 2015-04-16 |
20150104924 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer. | 2015-04-16 |
20150104925 | Noise Decoupling Structure with Through-Substrate Vias - A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate. | 2015-04-16 |
20150104926 | METHOD OF MANUFACTURING HIGH RESISTIVITY SOI SUBSTRATE WITH REDUCED INTERFACE CONDUCITIVITY - A method of preparing a high resistivity single crystal semiconductor handle wafer comprising implanting He ions through a front surface of the high resistivity single crystal semiconductor handle wafer, which is followed by an anneal sufficient to form a nanocavity layer in the damage region formed by He ion implantation. The anneal may be prior to or concurrent with thermal oxidation to prepare a front oxidized surface layer. | 2015-04-16 |
20150104927 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for fabricating a semiconductor device is provided. The method includes: providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit; thinning the second wafer from the second rear surface; and forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit. | 2015-04-16 |
20150104928 | WAFER PROCESSING METHOD - After performing a dividing step to divide a wafer into individual chips, an irradiation step is performed to apply ultraviolet radiation or plasma to the mount side of each chip, thereby generating ozone and active oxygen, which functions to remove organic matter sticking to the mount side of each chip. Accordingly, it is possible to remove from the mount side of each chip not only foreign matter sticking to the wafer during handling the wafer, but also foreign matter generated in dividing the wafer, so that faulty mounting of each chip can be reduced. | 2015-04-16 |
20150104929 | METHOD AND APPARATUS FOR DICING WAFERS HAVING THICK PASSIVATION POLYMER LAYER - Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a front surface having a plurality of integrated circuits thereon involves forming a mask layer above the front surface of the semiconductor wafer. The method also involves laser scribing the mask layer and the front surface of the semiconductor wafer to provide scribe lines in the mask layer and partially into the semiconductor wafer. The laser scribing involves use of a dual focus lens to provide a dual focus spot beam. The method also involves etching the semiconductor wafer through the scribe lines to singulate the integrated circuits. | 2015-04-16 |
20150104930 | WAFER PROCESSING METHOD - A wafer processing method divides a wafer into a plurality of individual devices along a plurality of crossing division lines formed on the front side of the wafer. The method includes a functional layer removing step of applying a CO | 2015-04-16 |
20150104931 | APPARATUS, DEVICE AND METHOD FOR WAFER DICING - An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging. | 2015-04-16 |
20150104932 | COMPOSITIONS FOR ETCHING AND METHODS OF FORMING A SEMICONDUCTOR DEVICE USING THE SAME - Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided. | 2015-04-16 |
20150104933 | SYSTEMS AND METHODS FOR ANNEALING SEMICONDUCTOR DEVICE STRUCTURES USING MICROWAVE RADIATION - Systems and methods are provided for annealing a semiconductor device structure using microwave radiation. For example, a semiconductor device structure is provided. An interfacial layer is formed on the semiconductor device structure. A high-k dielectric layer is formed on the interfacial layer. Microwave radiation is applied to anneal the semiconductor device structure for fabricating semiconductor devices. | 2015-04-16 |
20150104934 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including an active region, an insulation layer formed over the substrate, a plurality of openings formed in the insulation layer, a plurality of contact plugs filling the plurality of openings, a silicide layer formed over the substrate and between the substrate and each contact plug of the contact plugs in order to cover a bottom of each contact plug. The semiconductor device may decrease contact resistance by forming a silicide layer before the formation of openings regardless of the linewidth and aspect ratio of the openings. Also, because it does not have to consider step coverage based on the aspect ratio of openings, there is no limitation in the method of depositing a metal layer. Therefore, productivity may be improved. | 2015-04-16 |
20150104935 | REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN - Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. | 2015-04-16 |
20150104936 | CONDUCTIVE NANOWIRE FILMS - The invention provides a novel conductive film and a multilayered conductive structure, comprising a plurality of metal nanowires arranged in clusters and having an average aspect ratio of least 100,000, optionally decorated by metal nanoparticles. It is also disclosed a process for preparation of a conductive film comprising metal nanowires by surfactant/template assisted method which involves the use of a precursor solution based on surfactant (such as CTAB), metal precursor (such as HAuC14 and AgN03) and reducing agent (such as metal borohydride or sodium ascorbate). | 2015-04-16 |
20150104937 | SIGNAL LINE FABRICATION METHOD, ARRAY SUBSTRATE FABRICATION METHOD, ARRAY SUBSTRATE AND DISPLAY DEVICE - Embodiments of the disclosure provide a signal line fabrication method, an array substrate fabrication method, an array substrate and a display device. The signal line fabrication method includes: sequentially forming a material layer for forming the signal line, a material layer for forming a first barrier layer and a material layer for forming a second barrier layer; forming the first barrier layer and the second barrier layer by a patterning process; and forming the signal line by a patterning process. | 2015-04-16 |
20150104938 | METHOD FOR FORMING DAMASCENE OPENING AND APPLICATIONS THEREOF - A method for forming a damascene opening, wherein the method comprises steps as follows: Firstly, a semiconductor structure comprising an inter-metal dielectric (IMD), a first hard mask layer and a second hard mask layer stacked in sequence is provided, wherein the semiconductor structure has at least one trench extending downwards from the second hard mask layer to the IMD. A plasma treatment is then performed to modify a portion of the first hard mask layer exposed from the trench. Subsequently, a wet treatment is performed to remove the second hard mask layer and a portion of the first hard mask layer, wherein the plasma-modified portion of the first patterned hard mask layer has a first removing rate substantially less than a second removing rate of the second hard mask layer in the wet treatment. | 2015-04-16 |
20150104939 | WET-PROCESS CERIA COMPOSITIONS FOR POLISHING SUBSTRATES, AND METHODS RELATED THERETO - Disclosed are a chemical-mechanical polishing composition and a method of polishing a substrate. The polishing composition comprises low average particle size (e.g., 30 nm or less) wet-process ceria abrasive particles, at least one alcohol amine, and water, wherein said polishing composition has a pH of about 6. The polishing composition can be used, e.g., to polish any suitable substrate, such as a polysilicon wafer used in the semiconductor industry. | 2015-04-16 |
20150104940 | BARRIER CHEMICAL MECHANICAL PLANARIZATION COMPOSITION AND METHOD THEREOF - A barrier chemical mechanical planarization polishing composition is provided that includes the suitable chemical additives. The suitable chemical additives are organic polymer molecules containing ethylene oxide repeating units having the general molecular structure of | 2015-04-16 |
20150104941 | BARRIER CHEMICAL MECHANICAL PLANARIZATION COMPOSITION AND METHOD THEREOF - A barrier chemical mechanical planarization polishing composition is provided that includes suitable chemical additives. The suitable chemical additives are organic polymer molecules containing ethylene oxide repeating units having the general molecular structure of | 2015-04-16 |
20150104942 | Method of Manufacturing Semiconductor Device - A method of manufacturing a semiconductor device includes processing a semiconductor substrate using a plasma etching apparatus provided with a processing chamber. The semiconductor substrate has an uneasily-etched material formed thereabove and at least an upper layer film formed above the uneasily-etched material. The method includes etching the upper layer film after loading the semiconductor substrate into the processing chamber; forming a lift-off layer along an inner wall of the processing chamber with the semiconductor substrate loaded in the processing chamber; etching the uneasily-etched material and causing deposition of a reactive product of the uneasily-etched material along the lift-off layer; and cleaning, by removing the reactive product by removing the lift-off layer, the inner wall of the processing chamber after the semiconductor substrate is unloaded from the plasma etching apparatus. | 2015-04-16 |
20150104943 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure. A dielectric layer including adjacent first and second dielectric regions is formed on a substrate. The dielectric layer includes a curable material. The first dielectric region is cured. A portion of the second dielectric region is etched to form an opening and leave a remaining portion of the second dielectric region. After the etching step, the remaining portion of the second dielectric region is cured. | 2015-04-16 |
20150104944 | METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE - There is provided a method of forming patterns for a semiconductor device. The method sequentially forming a first mask layer and a second mask layer on a substrate. The method also includes forming a second mask pattern layer by patterning the second mask layer. The method further includes forming a first mask pattern layer having a negative slope portion, by etching the first mask layer exposed through the second mask pattern layer. The method also includes forming a thin film layer on the substrate exposed through the first mask pattern layer. | 2015-04-16 |
20150104945 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. In the method, a first hard mask layer is formed on a stepped structure. The first hard mask layer has a level top surface and thickness sufficient to etch the structure. A second hard mask pattern is formed on the first hard mask layer. The first hard mask layer is etched using the second hard mask pattern. Size dispersion of the patterns may be reduced by the first hard mask layer. | 2015-04-16 |
20150104946 | METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICES - Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings. | 2015-04-16 |
20150104947 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING HARD MASKS - Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1. | 2015-04-16 |
20150104948 | FACILITATING ETCH PROCESSING OF A THIN FILM VIA PARTIAL IMPLANTATION THEREOF - Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated. | 2015-04-16 |
20150104949 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD THEREOF - In some embodiments of the present disclosure, an apparatus includes an ionizer. The ionizer is configured to dispatch a reactive ion on a surface. The apparatus also has an implanter and the implanter has an outlet releasing an accelerated charged particle on the surface. | 2015-04-16 |
20150104950 | PLASMA PROCESSING METHOD - A plasma processing method for processing a silicon containing film formed on a substrate including a step of removing a reaction product with a first plasma formed from a first gas containing halogen, hydrogen, and carbon in a case where the reaction product is formed when performing an etching process on the silicon containing film by using an etching mask having an etching pattern. | 2015-04-16 |
20150104951 | METHOD FOR ETCHING COPPER LAYER - Provided is a method of etching a copper layer. The method includes generating plasma of a processing gas within a processing container which accommodates an object to be processed that includes the copper layer and a metal mask formed on the copper layer. The metal mask contains titanium. In addition, the processing gas includes CH | 2015-04-16 |
20150104952 | METHOD AND COMPOSITION FOR SELECTIVELY REMOVING METAL HARDMASK AND OTHER RESIDUES FROM SEMICONDUCTOR DEVICE SUBSTRATES COMPRISING LOW-K DIELECTRIC MATERIAL AND COPPER - An aqueous removal composition having a pH in the range of from 2 to 14 and method for selectively removing an etching mask consisting essentially of TiN, TaN, TiNxOy, TiW, W, or alloy of Ti or W relative to low-k materials from a semiconductor substrate comprising said low-k materials having a TiN, TaN, TiNxOy, TiW, W, or alloy of Ti or W etching mask thereon wherein the removal composition comprises at least one oxidizing agent and a carboxylate compound. | 2015-04-16 |
20150104953 | HIGH UV CURING EFFICIENCY FOR LOW-K DIELECTRICS - One embodiment is a method for semiconductor processing. In this method, a precursor film is provided over a semiconductor substrate, where the precursor film is made of a structural former and porogen. Prior to cross-linking, the porogen is removed by exposure to UV radiation having one or more wavelengths in the range of 150 nm to 300 nm, while a temperature of 300° C. to 500° C. is applied to the semiconductor substrate. Meanwhile, a Argon:Helium flow rate of 80>Ar>10 slm, 80>He>10 slm is set for the ambient substrate environment where the ratio of Ar:He ranges from 0:1 to 1:0 by volume or molality. | 2015-04-16 |
20150104954 | DEPOSITION OF BORON AND CARBON CONTAINING MATERIALS - Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film. | 2015-04-16 |
20150104955 | DEPOSITION OF BORON AND CARBON CONTAINING MATERIALS - Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film. | 2015-04-16 |
20150104956 | ADJUSTABLE SPATIAL FILTER FOR LASER SCRIBING APPARATUS - An apparatus for radiatively scribing a substantially planar semiconductor substrate along a scribelane that extends between opposing rows of semiconductor devices on a target surface of the substrate, said scribelane having a length extending parallel to a first direction and a width extending parallel to a second direction, these first and second directions lying respectively parallel to X and Y axes of a Cartesian coordinate system, comprising:
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20150104957 | RESIST MASK PROCESSING METHOD - A method for processing a resist mask includes: (a) a step of preparing, in a processing chamber, a target object to be processed having a patterned resist mask provided thereon; and (b) a step of generating a plasma of the hydrogen-containing gas by supplying a hydrogen-containing gas and supplying a microwave into the processing chamber. The hydrogen-containing gas may be, e.g., H | 2015-04-16 |
20150104958 | ROTATING VACUUM CHAMBER COUPLING ASSEMBLY - A coupling ( | 2015-04-16 |
20150104959 | ELECTRICAL CONNECTOR WITH MAGNETIC ELEMENT - An electrical connector comprises an insulative housing, a plurality of conductive terminals secured in the insulative housing, a metal shell shielding around the insulative housing and a magnetic element retained in the metal shell. The metal shell forms an accommodating room for receiving the magnetic element. The magnetic element has an outer surface and a recess defined on the outer surface. The metal shell has a retaining arm corresponding to the recess. The design of the recess and the retaining arm make a better retaining effectivity for the electrical connector. | 2015-04-16 |
20150104960 | SAFE OUTLET - Provided in a safe outlet further including a rotary type locking body in which the rotary type locking body falls down when a plug is not plugged into the outlet, to thereby make outlet terminals not opened, to thus prevent an electric shock accident in advance, and to thereby entirely block foreign substances such as dust from entering an earth terminal hole. | 2015-04-16 |
20150104961 | MOTOR VEHICLE CHARGING INLET STRUCTURE - A motor vehicle charging inlet structure includes: a first charging socket disposed in a recess portion of a vehicle body and connected to an electricity storage unit of a motor vehicle, the first charging socket being configured to be connected to a charging connector which supplies electric power from an external power supply to the electricity storage unit; a lid configured to open and close the recess portion; and a lock member configured to, when the lid is closed, come into engagement with the lid to fix the lid in a closed state and configured to, when the charging connector is connected to the first charging socket in a state in which the engagement of the lock member with the lid is released, come into press-contact with the charging connector to fix the charging connector in a connected state. | 2015-04-16 |
20150104962 | ELECTRONIC DEVICE - According to one embodiment, an electronic device includes a first connector, a second connector, a engage portion, and a fixing portion. The second connector is configured to be connected to the first connector. The engage portion is in the first connector and movable between a first position where the engage portion is configured to engage the second connector and a second position where the engage portion is configured to disengage the second connector. The fixing portion is configured to be attached to the first and the second connectors to fix the first connector to the second connector, and to be separated from the second connector to move the engage portion from the first position to the second position. | 2015-04-16 |
20150104963 | CONNECTOR - In a connector, interference portions for interfering with lances in accordance with an engagement state between lock holes of female terminals and the lances are provided in a male terminal housing to protrude toward a female terminal housing. The interference portions interfere with the lances to restrain male terminals from sliding against contact point members of the female terminals before the lock holes of the female terminals are engaged with the lances. The interference portions allow the male terminals to be connected to the female terminals without interfering with the lances after the lock holes of the female terminals are engaged with the lances. | 2015-04-16 |
20150104964 | Underwater Electrical Connection - An underwater electrical connection assembly is provided, where the assembly includes (1) a contact pin including an axially extending conductive core and an axially extending annular insolation portion around the conductive core, (2) a front end portion of the conductive core having an electrical contact surface, (3) a rear end portion of the conductive core having an electrical contact surface, and (4) an intermediate portion of the conductive core extending axially at an intermediate location between the front and rear end portions. In the assembly, the rear end portion of the conductive core of the pin includes a diameter larger than the diameter of the intermediate portion thereof, and the annular insulation portion includes an inner insulating layer around the intermediate portion of the conductive core and an insulating sleeve around the inner insulating layer. | 2015-04-16 |
20150104965 | TERMINAL LOCKING STRUCTURE FOR ELECTRICAL CONNECTOR - Provided is a terminal locking structure for an electrical connector excellent in assembly even when the locking position of a lance of a terminal is restricted, wherein, in the terminal locking structure that locks a terminal into a housing of the electrical connector with a lance, the terminal includes the lance and a stabilizer on an outer circumference of a cylindrical part thereof, the housing includes: an insertion part into which the terminal is inserted; a lance locking part provided only at a predetermined position along an inner circumference of the insertion part; and a guide part for the stabilizer, the guide part being inserted along the insertion part. | 2015-04-16 |
20150104966 | Method and Apparatus for Improving Connector Security and Device Coexistance - Embodiments of the present disclosure include an apparatus and a method for connecting a first device and second device. An apparatus includes an angled connector configured to connect to a first device to a second device, the first device and the second device configured to communicate through signal paths in the connector, the signal paths configured to pass digital data signals, a fastening device configured to secure the angled connector to the first device. | 2015-04-16 |
20150104967 | POSITIVE LOCK CONNECTOR FOR SMALL POWER COUPLERS - A coupler including a housing is configured to affix individual lines of a multiline cable within the housing, the housing including a front portion for engaging an inlet, a rear portion, and an upper portion including a raised central area and at least one lowered side area. A sliding lock including a lock housing is configured to slide over the raised central area and the at least one lowered side area and at least one spring arm affixed to the lock housing; and an outer mold configured to engage the rear portion of the housing and constrain the sliding lock within a gap formed between the housing and the outer mold. The sliding lock is configured to slide forward within the gap to engage the inlet and lock the sliding lock in place, thereby locking the connector to the inlet, and slide backward within the gap and disengage the inlet. | 2015-04-16 |
20150104968 | Apparatus for Retaining a Plug in a Receptacle - The present disclosure is an apparatus for retaining a plug within a receptacle. The apparatus for retaining a plug within a receptacle may include a receptacle body and a retention device. The retention device may include a face portion and at least one prong, each prong of the at least one prong including a barb. The retention device is configured to retain a plug inserted within the receptacle body by contact with a shroud of the plug from the barb of each prong of the at least one prong of the retention device. | 2015-04-16 |
20150104969 | FASTENER - A fastener is made of a plastic material by integrated injection molding and has a locking portion and an installation portion, wherein the locking portion has two arm levers extended and arranged at a predetermined interval, and at least a concave buckle corresponding to another is respectively protruded from inner sides of the two arm levers. The installation portion has a cap connected to the two arm levers. A channel passing between the two arm levers is disposed to the cap, and at least an elastic hook plate is disposed at a bottom of the cap. While in use, the locking portion is stretched into the fastener insertion hole preset at the side of the notch of the board insertion slot. The elastic hook plate at the bottom of the cap is mutually buckled with the buckle hole of an inner wall of the fastener insertion hole. | 2015-04-16 |
20150104970 | Mountable Cable Interface - A mounting plate assembly for securing a plug of a network cable to a jack of an electronic device. The assembly includes a mounting plate having an attachment mechanism that is configured for releasable locking engagement with the electronic device. Further, the mounting plate is adapted to be mounted to a mounting structure. The mounting plate includes inner passageway that is adapted to receive insertion of at least a portion of the plug. Additionally, the inner passageway is adapted to depress a locking clip of the inserted plug to a position that prevents the locking clip from lockingly engaging a protrusion in an aperture of the jack. Further, the retention member may include at least one arm that is configured to retain the plug in a relatively static position relative to the mounting plate when the plug is being received in, and removed from, the aperture of the jack. | 2015-04-16 |
20150104971 | CONNECTING MODULE, POWER SUPPLY MODULE AND CONNECTING SET FOR LIGHT STRIPS - Various embodiments may relate to a connecting module for mechanically connecting two light strips each having at least one semiconductor light source and having at least two electrical contacts arranged in a housing, which electrical contacts each have two contact sections for making electrical contact with the light strips. The electrical contacts in each case pass through the housing with a further contact section for connection to a power supply. | 2015-04-16 |
20150104972 | Connector - An electrical connector housing is disclosed having a first housing member, and a second housing member mated with the first housing member. A front wall is disposed on an outer surface of at least one of the housing members and extends perpendicular to an insertion direction. A first sidewall is disposed on the outer surface of the first housing member and extends along the insertion direction, perpendicular to the front wall. A second sidewall is disposed on the outer surface of the second housing member and extends along the insertion direction, parallel with the first sidewall and perpendicular to the front wall. A cantilevered first lock arm extends along an insertion direction and is positioned between the first sidewall and second sidewall. The lock arm includes a fixed end, a free end, and a hook. | 2015-04-16 |
20150104973 | METHOD AND DEVICE FOR PRODUCING AN OPERATIVE CONNECTION BETWEEN A CONNECTOR AND A CABLE - A method for producing an operative connection between a coaxial cable ( | 2015-04-16 |
20150104974 | ELECTRICAL COAXIAL CONNECTOR - An electrical coaxial connector comprising a signal-joining contacting conductor and a grounding contacting conductor each supported by an insulating base member, wherein a body portion of the signal-joining contacting conductor has a press-contacting part with a contacting protrusion for contacting with a signal-joining conductor in a mating connector and a first base part in such a manner that a measure of thickness of the press-contacting part including the contacting protrusion is not more than the maximum measure of thickness of the first base part, and an annular portion of the grounding contacting conductor has an engaging part with an engaging protrusion for engaging with a grounding conductor in the mating connector and a second base part in such a manner that a measure of thickness of the engaging part including the engaging protrusion is not more than to the maximum measure of thickness of the second base part. | 2015-04-16 |
20150104975 | ELECTRIC CONNECTOR AND TERMINAL INCLUDED IN THE SAME - There is provided a terminal made of a single metal sheet, the terminal including a support unit in which a core wire of a cable is sandwiched, the support unit including a first portion extensive in a direction perpendicular to a direction in which an axis of the core wire extends, and a second portion spaced away from the first portion, and extensive in a direction perpendicular to a direction in which the axis of the core wire extends, the first and second portions being connected at an end thereof to each other, the first and second portions being formed with a slit thereover, a center line of the slit existing in the first portion and a center line of the slit existing in the second portion deviating from each other when viewed in a direction in which the axis of the core wire extends. | 2015-04-16 |
20150104976 | CONNECTOR ASSEMBLY HAVING MULTIPLE SHIELD CURRENT PATHS - A connector assembly may include a housing that retains one or more contacts, a cable having a shield that surrounds one or more conductors that electrically connect to the one or more contacts, and a backshell that secures the housing to the cable. The backshell may include at least one wall having a backshell outer surface and a backshell inner surface, and one or more through-holes formed through the at least one wall. Each through-hole forms a current path between the backshell outer surface and the backshell inner surface. | 2015-04-16 |
20150104977 | ELECTRICAL CONNECTOR HAVING A CONNECTOR SHROUD - Electrical connector including a module assembly having a contact module. The contact module has a module body and signal conductors held by the module body. The module assembly has a shroud-engaging face. The signal conductors have respective signal members disposed along the shroud-engaging face. The electrical connector also includes a connector shroud that couples to the module assembly. The connector shroud has a mating side, a loading side, and a mating axis extending therebetween. The connector shroud includes contact passages that extend therethrough. The loading side interfaces with the shroud-engaging face. The connector shroud couples to the module assembly in first or second rotational positions about the mating axis. The contact passages align with the signal members for each of the first and second rotational positions. | 2015-04-16 |
20150104978 | ELECTRICAL CONNECTOR HAVING AN ARRAY OF SIGNAL CONTACTS - Electrical connector including a connector body having a mating side with a communication array of signal and ground contacts and first and second mounting sides with respective mounting arrays of signal and ground contacts. Each of the first and second mounting sides is configured to be mounted to a corresponding circuit board. The connector body includes signal and ground conductors that extend through the connector body and communicatively couple the communication array to each of the mounting arrays. The mating side faces along a mating axis and the first and second mounting sides face in opposite directions along a mounting axis. The mating and mounting axes are perpendicular to each other. | 2015-04-16 |
20150104979 | Subscriber Identity Module Connector - The present invention discloses a subscriber identity module connector which places a detecting terminal and a grounding terminal into a same contact area. The above placement of the detecting terminal and the grounding terminal form a circuit to determine if a SIM card is inserted appropriately. As a result, there is no need to set conventional detecting unit, and the space of the subscriber identity module connector are advantageously saved. It not only simplifies the placement of circuit board (PCB) and but also reduces the manufacturing cost. | 2015-04-16 |
20150104980 | METHOD AND APPARATUS FOR MOUNTING A CABLE CONNECTOR ONTO A PANEL - A method is provided for mounting a plurality of cable connectors onto a panel that defines a plurality of target mounting locations. At least two of the plurality of cable connectors defines at least a pair of cable retaining apertures. The pairs of cable retaining apertures of a first one of the two cable connectors are spaced apart in a first direction, and the pair of cable retaining apertures of a second one of the two cable connectors are spaced apart in a second direction that is different than the first direction. | 2015-04-16 |
20150104981 | CONNECTOR AND CONNECTION TERMINAL - A connector includes: a housing in which a communication groove that communicates between adjacent terminal accommodating chambers is formed in a partition wall; and a connection terminal having a terminal body section connected to a wire connection part. The terminal body section includes: a first side wall on which a male connection part is formed; a second side wall provided with a slit; and an elastic part and contact parts which are provided inside the terminal body section and which contact the male connection part inserted in the slit. The communication groove is provided at a position offset from the center in the vertical direction of the terminal accommodating chamber. The male connection part and the slit are provided at a position offset from the center in the vertical direction of the terminal body section so as to correspond to the communication groove. | 2015-04-16 |
20150104982 | CONDUCTING DEVICE AND SOCKET - The conducting device and the socket with stable electrical-connection ability are provided. The socket comprises a socket body, the conducting device arranged in an accommodating slot of the socket body, and an ending cap arranged on the socket body. The conducting device comprises a movable spring plate, a stationary spring plate and a reset spring member. The movable spring plate is rotatably connected with the stationary spring plate. The reset spring member is located in the outer side of the movable spring plate and contacts with the movable spring plate. An inserting slot is formed between the movable spring plate and the stationary spring plate. The width of the inserting slot is gradually decreased from inner part to outer part. The ending cap blocks the reset spring member and is adaptive with the socket body. | 2015-04-16 |
20150104983 | JOINT STRUCTURE BETWEEN END OF COAXIAL CABLE AND TERMINAL, AND JOINING METHOD THEREBETWEEN - The present invention relates to a joint structure for joining an end of an outer conductor of a coaxial cable in which the outer conductor including a plurality of outer core wires is coaxially and integrally formed with and around an inner conductor via an insulation inner coat with a terminal, a joint end is formed by bending the plurality of outer core wires in a direction crossing a longitudinal direction of the cable, and a joint portion is formed by joining the joint end with a conductor connection portion of the terminal disposed in a direction crossing an axial direction of the cable. | 2015-04-16 |
20150104984 | SOCKET COVER - A socket cover contains: a cap, a first lid, and a second lid. The cap has an orifice defined thereon, the first lid is disposed on a first side of the orifice of the cap and covers a first part of the orifice, and the first lid has a cutout defined on a non-closed position thereof opposite to the orifice of the cap. The second lid is disposed on a second side of the orifice of the cap and covers a second part of the orifice which is not covered by the first lid, and the second lid has a projection corresponding to the cutout of the first lid. Thereby, when a plug is inserted in a socket, the cap is positioned stably to enhance using safety and aesthetics appearance. | 2015-04-16 |
20150104985 | WEIGHT-SHIFT CONTROLLED PERSONAL HYDROFOIL WATERCRAFT - A passively stable personal hydrofoil watercraft that has a floation device, wherein a user can ride in a prone, kneeling, or standing position. The watercraft includes a strut having an upper end interconnected with the flotation device and lower end connected with a hydrofoil. The hydrofoil greatly reduces the power required to travel at higher speed. The watercraft also includes a propulsion system connected to the hydrofoil. Both longitudinal and directional control of the watercraft is via weight shift, eliminating the need of any movable surfaces. The floation device, strut, and hydrofoil may be permanently interconnected or may be detachable. | 2015-04-16 |
20150104986 | Handle-Actuated Aquatic Device - A handle-actuated aquatic device comprising a paddlewheel and a body board, wherein the body board is buoyant in water and configured to engage a portion of a user's body, and a first handle and a second handle are operatively connected to the paddlewheel, wherein each handle is configured to rotate the paddle wheel, and wherein the paddlewheel is attached to a body board frame, the body board frame also being configured to receive at least a portion of the body board. | 2015-04-16 |
20150104987 | WAKEBOARD BINDINGS, WAKEBOARDS INCLUDING SUCH BINDINGS, AND RELATED METHODS - Wakeboard bindings may comprise a first member configured for connection to a wakeboard. A selective retaining device comprising at least one retaining member may be connected to and disposed at a periphery of the first member. A second member may be rotatable with respect to the first member and may comprise at least one engagement member. The at least one retaining member may be engaged with the at least one engagement member to preclude rotation of the second member in a rotation-precluding position and may be disengaged from the at least one engagement member to permit rotation of the second member in a rotation-permitting position. A releasable step-in connection device comprising a first connection member and a second connection member biased toward a connection position and movable to a release position may be connected to the second member and configured to releasably connect to a foot restraint. | 2015-04-16 |
20150104988 | Watercraft Fin - In one aspect, the present invention provides a watercraft fin including a first side surface and a second side surface wherein at least one of the first side surface or the second side surface includes a plurality of dimples. | 2015-04-16 |
20150104989 | SAFETY BELT SWIM TRAINER - A safety-retrieval system comprised of three components, a life jacket with reinforced tethering points, a waist belt with tethering points to be worn around a secondary person's waist, and a tethering line/leash to connect the life jacket to the waist belt. | 2015-04-16 |
20150104990 | HYGRO MATERIALS FOR USE IN MAKING YARNS AND FABRICS - A process is described wherein pile yarn is woven with cotton weft and warp yarns to produce terry fabrics, such as towels. The fabric is then washed in warm water to dissolve the PVA fibers. The amount of fibers dissolved, depends upon the count of the yarn or yarns used. By dissolving the PVA fibers, a hollow air space is produced throughout the pile yarn, corresponding to an increase in the air space in the pile yarn. By increasing the air space in the pile yarn, the resulting towels are softer and bulkier than standard cotton towels. The present invention further relates to pile yarn in terry woven fabric (warp yarn), or weft yarn, in the case of flat fabrics. | 2015-04-16 |
20150104991 | METHOD FOR PROVIDING A LIGHT ASSEMBLY EMITTING LIGHT WITH A DESIRED COLOR TEMPERATURE AND SYSTEM FOR TESTING AND CORRECTING COLOR TEMPERATURES OF LIGHT ASSEMBLIES - The present invention refers to a method for providing a light assembly emitting light with a desired color temperature comprising the steps of providing a light source in a first step measuring the color temperature of the light source in a second step, comparing the measured color temperature with the desired color temperature in a third step and printing an optical compensation means for compensating differences between the measured color temperature and the desired color temperature in a fourth step, if the measured color temperature deviates from the desired color temperature. | 2015-04-16 |
20150104992 | PLAYTHING - A plaything including unit blocks connected to each other using a connection tube is provided. Each unit block includes a spherical capsule and a plurality of connection members protruding at regular angular intervals from the surface of the spherical capsule. A shock detector emitting light in response to an external shock is installed inside the unit block. When connecting the unit blocks, the connection members of different unit blocks are inserted into the same connection tube from opposite directions. A structure formed by only one unit block or by connecting two or more unit blocks may be used as an educational tool or a shaking tool shaken in a manner of jig fishing. | 2015-04-16 |
20150104993 | MODULAR CONSTRUCTION PANEL - A modular construction panel is provided. The modular construction panel has a panel having a plurality of fasteners disposed within or thereon, each fastener permitting adjoining to a like construction panel for creating a structure. The panels are provided in shapes optimizing modularity when mated to other panels. | 2015-04-16 |
20150104994 | CONSTRUCTION TOY SET FOR TODDLERS AND YOUNG CHILDREN - A construction toy set that stimulates young children to plan and construct objects with which they can play or interact when finished. The set includes pieces with joints that allow the child to build an object having parts that turn or rotate, allowing him or her to play actively with the object when fully assembled. Many of the pieces are relatively large and brightly colored, and have soft textured surfaces that stimulate the child's senses of sight and touch. The rotatable pieces turn in response to a moderate force while emitting a pleasant clicking sound that appeals to the child's sense of hearing. Accordingly, the inventive toy set enhances the child's creativity, imagination, and dexterity by encouraging him or her to plan, assemble, and then interact with a finished object or model. Further, the finished object can be easily disassembled and then reassembled as often as desired by the child. | 2015-04-16 |
20150104995 | Animated Figure - A figure includes a frame having a body portion and at least two appendages extending from and fixed relative to the body portion. The body portion has an aperture positioned therein. The figure also includes a casing, a motor coupled to the casing, and a crank rotatably coupled to the motor. The crank has a crank pin that is spaced from a center of the crank and engages the aperture of the frame. When the motor is activated, the crank moves the casing relative to the frame while the frame remains substantially stationary. | 2015-04-16 |