16th week of 2009 patent applcation highlights part 18 |
Patent application number | Title | Published |
20090096423 | METHOD AND SYSTEM FOR PULSE CHARGING AN AUTOMOTIVE BATTERY - A pulse charging profile for a vehicle battery is synchronized with driver or vehicle demanded current disturbances by phase tracking the fundamental frequency of the desired pulse charging profile to those driver or vehicle demanded current disturbances. When these driver or vehicle demanded disturbances are not active, the tracked charging profile is honored. | 2009-04-16 |
20090096424 | Battery management and equalization system for batteries using power line carrier communications - A battery charging system uses power line carrier communications, for communicating battery state information associated with charging batteries, between a battery charger and a battery management system (BMS) located on the battery or battery pack. The power line carrier includes transmitters and receivers transmitting and receiving battery state information, such as current, voltage and temperature, as digital signals on existing cable conductors located between the battery/battery pack and the battery charger. The battery management system (BMS), which is physically located on the battery pack, receives the information from the power line carrier, in order to measure a variety of parameters relating to charging the battery, which may be a motor vehicle battery or a battery for operating machinery, such as fork lifts, bulldozers and other earth moving and product transportation vehicles. | 2009-04-16 |
20090096425 | Method For Charging Rechargeable Lithium Accumulators - A method and a charging device serve for charging rechargeable lithium accumulators. A charging current is injected into the accumulator, and the voltage is monitored on the accumulator during the injection process. Additionally, the variation in time of at least one state variable characteristic of the accumulator is monitored and injection of the charging current into the accumulator is continued until the variation in time of the state variable exceeds a predefined limit value. | 2009-04-16 |
20090096426 | GENERATOR CONTROLLER - A generator controller, in its various embodiments, displays genset fault messages, a genset elapsed time hour meter, service countdown reminder, monitors battery voltage changes over multiple periods of time to establish and display the “battery level,” uses the “battery level” to automatically start and stop the genset, and accepts multiple run requests from AC loads such as HVAC systems, and incorporates safety or other start inhibit features. | 2009-04-16 |
20090096427 | Apparatus for detecting end-of-charge for a battery charger - An apparatus and method for accurate end-of-charge (EOC) detection in a battery charger is provided. An EOC circuit determines that a battery has been fully charged when two conditions are met. The first condition for EOC detection is that the battery has reached a predetermined voltage and, as a result, the battery charger has transitioned to a constant voltage phase of the charging process. The second condition for EOC detection is that the battery current has fallen below a predetermined, set level. When both of these conditions are met, EOC is detected. This bi-condition EOC detection scheme is capable of accurate EOC detection, i.e. determining when the battery is fully charged. | 2009-04-16 |
20090096428 | Battery charging method and device thereof - A battery charging method and device thereof are disclosed. The method includes the following steps. First, a charging current is supplied into a plurality of cell blocks of a battery module for charging, and the terminal voltages of the cell blocks are detected, when one of said terminal voltages exceeds a first threshold, the charging is kept continuously over a first preset time period. If one of said terminal voltages of said cell blocks exceeds a second threshold, an over voltage protection is performed, else the charging current is reduced and the battery module is charged by the reduced charging current continuously over a second preset time period and if the cell blocks are determined that they are fully charged, the charging is stopped, otherwise, the battery module is charged continuously. Therefore, the battery charging method and device thereof in accordance with the present invention can prevent the battery module from being overcharged and prolong its life. | 2009-04-16 |
20090096429 | Control Unit For Triggering a Personal Protection Arrangement - A control unit for triggering the personal protection arrangement, including a first semiconductor module that is configured to make available various supply voltages and to charge an energy reserve, and including at least one second semiconductor module that is likewise configured to charge the energy reserve, the first and the second semiconductor module each having a semiconductor support. | 2009-04-16 |
20090096430 | CHARGING AND RECHARGABLE DEVICES - A capacitor-based (supercapacitor, ultracapictor or psudeocapcitor) electrical charger, rechargeable device and energy storage pack for use with a rechargeable power tool. The rechargeable device includes a storage capacitor. The electrical charger includes a supply capacitor electrically connected to an electrical contact, the supply capacitor being charged when the electrical charger is connected to a power source. While in use, any charge in the supply capacitor is rapidly distributed between the supply capacitor and the storage capacitor when the rechargeable device is mounted in the receiver of the electrical charger. The electrical charger includes a safety interlock switch which only supplies power to the electrical contact of the charger after electrical terminal of the rechargeable device have engaged the electrical contact. | 2009-04-16 |
20090096431 | Optimal load controller method and device - A method and device for optimizing power output of a power generation system having a load engaging system, a load optimizing system, a load selection system, a motive driver and one or more loads or power transfer parameters. The power generation system is configured using an electrical generator to consume system power out. The load engaging system decides when and how the load or power transfer parameters are applied to and removed from the system. The load selection system enables multiple power transfer parameters to be optimized by selecting and isolating one power transfer parameter at a time to be optimized. The load optimizing system optimizes system power output by manipulating the selected power transfer parameter, dynamically in response to change in power output. | 2009-04-16 |
20090096432 | Loading reduction device and method - An active loading-reduction device is provided for a circuit. The circuit has functional circuitry coupled to a terminal to receive an alternating voltage. The circuit also has an electrostatic discharge protector that is coupled to the terminal. The active loading-reduction device includes active circuitry that is adapted to be coupled to a power supply to provide a reactance to counteract a reactance provided by the electrostatic discharge protector at the terminal of the circuit. | 2009-04-16 |
20090096433 | LDO With Large Dynamic Range of Load Current and Low Power Consumption - An electronic device has an LDO regulator for varying loads. The LDO regulator includes a primary supply node coupled to a primary voltage supply. An output node provides a secondary supply voltage and a load current. A bias current source generates a bias current. A gain stage coupled to the bias current source increases the maximum available load current. The gain stage includes a first MOS transistor biased in weak inversion coupled to a current mirror which mirrors the drain current through the first MOS transistor to the output node. The gate-source voltage of the first MOS transistor increases in response to a decreasing secondary supply voltage level at the output node to increase the available load current. | 2009-04-16 |
20090096434 | NMOSFET-base linear charger - In an NMOSFET-base linear charger, a pair of common gate charging NMOSFET and sensing NMOSFET have their sources coupled together or virtually shorted to each other, so that these two NMOSFETs have a same gate-source voltage and thereby the sensing NMOSFET reflects the drain-source current of the charging NMOSFET on its drain-source current. From the drain-source current of the sensing NMOSFET, a current sensing signal is generated to control the gate voltage of the charging NMOSFET. By implementing the current source with NMOSFETs, the linear charger has smaller die area and less power loss. | 2009-04-16 |
20090096435 | LAYOUT SCHEMES AND APPARATUS FOR HIGH PERFORMANCE DC-DC OUTPUT STAGE - A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconductor die, each switching element including a plurality of discrete transistors configured to have a substantially reduced ON resistance; and forming a plurality of gate driver circuits on the same die among the switching elements, all using a single metal process. Each gate driver circuit placed substantially close to and dedicated to drive only one switching element so that the gate coupling capacitance resistance product is substantially reduced. | 2009-04-16 |
20090096436 | DC-DC CONVERTER - A DC-DC converter includes a series circuit of a main switch and a choke coil and an output capacitor connected to one end of the series circuit and outputs a DC voltage from the one end of the series circuit. A first MOS transistor is connected in parallel to the series circuit and a second MOS transistor is connected in parallel to the output capacitor. A control circuit controls the gate voltages of the first MOS transistor and/or the second MOS transistor so that the first MOS transistor and/or the second MOS transistor outputs a changed target output voltage, whereby the output voltage is made equal to the target voltage at high speed. | 2009-04-16 |
20090096437 | AUTOMATIC POWER SUPPLY CONVERTING CIRCUIT - An automatic power supply converting circuit includes a live input terminal, a neutral input terminal, a relay, a regulator, a voltage divider circuit, an identifying circuit, a switch circuit and a voltage doubling circuit. The live input terminal and the neutral input terminal are configured for receiving a first alternating current (AC) voltage. The regulator is configured for filtering and steadying the first AC voltage and outputting a regulated voltage. The voltage divider circuit is configured for sampling the first AC voltage and outputting a divided voltage. The identifying circuit is configured for comparing a divided voltage with a reference voltage, and outputting a control signal. The switch circuit is configured for controlling the relay to be conductive or not. The voltage doubling circuit is capable of being controlled by the relay and outputting a doubled voltage. | 2009-04-16 |
20090096438 | VOLTAGE CONTROL CIRCUIT - A voltage control circuit accepts an input voltage and produces a regulated output voltage. Embodiments provide improved responsiveness to variations in input voltage, load current, and ambient temperature. Exemplary embodiments include an NPN transistor connected between the input and output terminals, which is controlled by a feedback circuit. In an embodiment, the feedback circuit includes a PMOS transistor and in another embodiment the feedback circuit includes a PNP transistor. | 2009-04-16 |
20090096439 | BUILT-IN JITTER MEASUREMENT CIRCUIT - A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal. | 2009-04-16 |
20090096440 | Methods and Systems for Measurement of Fluid Electrical Stability - The invention relates particularly to methods and apparatuses for characterizing water-in-oil or invert emulsion fluids for use in drilling well bores in hydro-carbon bearing subterranean formations. A fluid stability measurement device is disclosed. The device comprises a reference electrode and a second electrode coupled to an insulating body. A guard electrode is placed in the path between the reference electrode and the second electrode on the surface of the insulating body. | 2009-04-16 |
20090096441 | Sensor-equipped rolling bearing apparatus - An annular member is mounted on an outer ring, and a sensor is fixed to the annular member. The annular member includes a fixing portion, and a cover portion. The sensor is fixed to the fixing portion by a bolt and a nut. The fixing portion is fixed to the cover portion by bolts. The cover portion is separate from the fixing portion, and therefore does not have an opening extending in a circumferential direction, and covers a magnet rotor fitted on an inner ring in the circumferential direction. | 2009-04-16 |
20090096442 | MAGNETIC SYSTEM FOR BIOSENSORS - The invention relates to a magnetic system for biosensors. It aims at developing a magnetic system for biosensors, which can switch between attraction force and repulsion force near the sensor surface. The arrangement has at least a coil and a ferromagnetic core generating a magnetic field, and a sensor or sensor surface which corresponds with the magnetic field in a way, that the ferromagnetic core is equipped with an opening on the side where the sensor is located in order to produce a local high density of inhomogeneous magnetic field lines, along which the sensor is movable between at least two definable positions. | 2009-04-16 |
20090096443 | COIL ARRANGEMENT FOR AN ELECTROMAGNETIC TRACKING SYSTEM - An electromagnetic tracking system comprising at least one electromagnetic transmitter assembly or at least one electromagnetic receiver assembly with two coils attachable to a trackable object to be tracked. The two coils including a first large coil and a second small coil, with the second small coil positioned asymmetrically with respect to the first large coil. The electromagnetic tracking system enables a medical professional to continually track the position and orientation of the object during a medical procedure. | 2009-04-16 |
20090096444 | Pulsar Ring of Magnetic Rotary Encoder - To hold a pulsar ring ( | 2009-04-16 |
20090096445 | Method and device for determining angular position - A method for determining angular position, which removes a systematic error in the angular position determination and requires a low calculating effort, by determining a first factor and a second factor as a function of an angular position, forming a first product from a first signal and the first factor, and a second product of the second signal and the second factor, forming a subtraction result by the subtraction of the second product from the first product, and comparing the subtraction result to a quantity. | 2009-04-16 |
20090096446 | Polishing monitoring method, polishing apparatus and monitoring apparatus - The present invention provides a method for monitoring a change in thickness of a conductive film brought into sliding contact with a polishing surface of a polishing pad using an eddy current sensor. The output signal of the eddy current sensor comprises two signals corresponding to a resistance component and an inductive reactance component of an impedance of an electric circuit including a coil of the eddy current sensor. The method includes acquiring the output signal of the eddy current sensor when the eddy current sensor is facing the conductive film, defining the two signals as coordinates on a coordinate system, repeating the acquiring of the output signal and the defining of the coordinates, determining a center of curvature of an arc specified by at least three sets of coordinates on the coordinate system, determining an angle of inclination of a line connecting the center of curvature and a latest one of the at least three sets of coordinates, and monitoring a change in thickness of the conductive film by monitoring a change in the angle of inclination. | 2009-04-16 |
20090096447 | ELECTRIC POTENTIAL SENSOR FOR USE IN THE DETECTION OF NUCLEAR MAGNETIC RESONANCE SIGNALS - The present invention provides nuclear magnetic resonance apparatus comprising means for applying a static magnetic field (H | 2009-04-16 |
20090096448 | b-Value Optimization for Diffusion Weighted Magnetic Resonance Imaging - A method for selecting the b-values for diffusion weighted magnetic resonance scans. The method includes: identifying a single reference slice within a volume of interest (VOI); progressively changing b-values over a plurality of scans of the reference slice wherein each one of the scans has a different b-value to obtain a plurality of diffusion weighted images; calculating ADC maps for combinations of b-values from the obtained plurality of diffusion weighted images; evaluating the calculated ADC maps; selecting from the evaluation optimal b-values; and using the selected b-values for subsequent scans. | 2009-04-16 |
20090096449 | LOW POWER BROADBAND SPIN DECOUPLING - In a magnetic resonance data acquisition method, magnetic resonance is excited ( | 2009-04-16 |
20090096450 | BO FIELD DRIFT CORRECTION IN A TEMPERATURE MAP GENERATED BY MAGNETIC RESONANCE TOMOGRAPHY - In a method to correct a B | 2009-04-16 |
20090096451 | Nmr Machine Comprising Solenoid Gradient Coils which are Incorporated into Tubes - The nuclear magnetic resonance machine comprises a device ( | 2009-04-16 |
20090096452 | HELIUM COMPRESSOR WITH CONTROL FOR REDUCED POWER CONSUMPTION - A magnetic resonance imaging system has a superconducting magnet housed within a cryostat, a cryogenic refrigerator that cools within the cryostat, a helium compressor that supplies compressed helium to the cryogenic refrigerator and to receive a return flow of compressed helium from the refrigerator, and a magnet supervisory system controlling operation of the magnet resonance imaging system. An apparatus is provided for controlling the speed and/or timing of operation of the helium compressor in accordance with predefined algorithms in response to system state data. | 2009-04-16 |
20090096453 | PASSIVE SHIMMING OF MAGNET SYSTEMS - In a method and an arrangement for shimming a cylindrical magnet system, that has a cylindrical magnet having a bore therein with an axis extending therethrough, and a gradient coil assembly located within the bore, shimming is accomplished by stacking a number of planar pieces of shim material in each of said tubes, with each of the tubes having an axis parallel to the axis of the cylindrical magnet, and with the planar pieces of shim material and stacked in the tubes in respective planes that are perpendicular to the axis fo the cylindrical magnet. | 2009-04-16 |
20090096454 | Methods For Rectification of B0 Inhomogeneity effects in Magnetic Resonance Images - A method for reducing B0 inhomogeneous effects in magnetic resonance imaging (MRI). The method includes: obtaining a high-resolution volumetric MR image of the patient, such high-resolution volumetric MR image having B0 inhomogeneous effects; calculating distortion within obtained the high-resolution volumetric MR image of the patient; and correcting the B0 inhomogeneous effects in the obtained high-resolution volumetric image using the calculated distortion. | 2009-04-16 |
20090096455 | ARRANGEMENT TO TRANSMIT MAGNETIC RESONANCE SIGNALS - An arrangement to transmit magnetic resonance signals has at least two reception branches. Each reception branch contains a single antenna of a local coil as well as an amplifier connected with the single antenna, such that an amplified magnetic resonance signal is formed from a magnetic resonance signal that is acquired via the single antenna. In a multiplexer, each input is connected with a respective reception branch, such that the amplified magnetic resonance signals of the reception branch are combined by the multiplexer into a resulting signal using a time multiplexing method. A transmission path is connected on one side with an output of the multiplexer and on the other side with a receiver, such that the resulting signal is transmitted from the multiplexer to the receiver via the transmission path. | 2009-04-16 |
20090096456 | ARRANGEMENT FOR TRANSMISSION OF MAGNETIC RESONANCE SIGNALS - An arrangement to transmit magnetic resonance signals has a local coil composed of a number of individual antennas for acquisition of radio-frequency signals of a magnetic resonance examination. Preamplifiers amplify the radio-frequency signals, and a transmission device transmits the radio-frequency signals from the local coil to the preamplifiers. The transmission device is fashioned as a readout coil and has a number of individual antennas. The individual antennas of the readout coil are magnetically coupled with the individual antennas of the local coil, with the individual antennas of the local coil and the individual antennas of the readout coil forming a linear MIMO transmission system describable by a transmission matrix. | 2009-04-16 |
20090096457 | Method for determining earth vertical electrical anisotropy in marine electromagnetic surveys - A method is disclosed for determining earth vertical electrical anisotropy from offshore electromagnetic survey measurements. The method requires both online and offline data, which includes at least one electromagnetic field component sensitive at least predominantly to vertical resistivity and another component sensitive at least predominantly to horizontal resistivity. Using a horizontal electric dipole source, online E | 2009-04-16 |
20090096458 | Adapter For Supplying Electrolyte To A Potentiometric Sensor - An adapter for a potentiometric sensor having a sensor shaft, which has a reference liquid opening in its exterior surface. The adapter comprises an annular chamber member having a sensor opening for receiving the sensor shaft. Arranged in the sensor opening are first and second sealing rings for the sensor shaft. The axial position of the reference liquid opening lies between the first and second sealing rings. Formed between the sealing rings and the sensor shaft is an annular chamber, which is in communication with the reference liquid opening. The annular chamber member further includes a duct extending between the annular chamber and a reference feed opening. The adapter further includes a process connection member having a process connection opening, which surrounds the sensor shaft, and whose axis is aligned with the axis of the sensor opening. The axial position of the process connection member is fixed relative to the annular chamber member, and the process connection member is freely rotatable relative to the annular chamber member. | 2009-04-16 |
20090096459 | METHOD OF MEASURING CHARACTERISTICS REGARDING SAFETY OF BATTERY - A measuring method of a battery includes the step of measuring frequency characteristics of an internal impedance of the battery by an AC impedance method, and determining a parameter of an element representing ease of mobility of charges on a surface of a positive electrode of the battery and that of an element representing the ease of mobility of charges on the surface of a negative electrode. | 2009-04-16 |
20090096460 | IONIZATION VACUUM GAUGE - An ionization vacuum gauge which has at least three electrodes of a grid ( | 2009-04-16 |
20090096461 | TEST STRUCTURE AND METHOD FOR RESISTIVE OPEN DETECTION USING VOLTAGE CONTRAST INSPECTION - A test structure for resistive open detection using voltage contrast (VC) inspection and method for using such structure are disclosed. The test structure may include a comparator within the IC chip for comparing a resistance value of a resistive element under test to a reference resistance and outputting a result of the comparing that indicates whether the resistive open exists in the resistive element under test, wherein the result is detectable by the voltage contrast inspection. | 2009-04-16 |
20090096462 | Wafer testing method - A wafer testing method for wafer testing system comprises the steps: loading a wafer and then positioning the wafer relatively to a map file image stored in a map file. The map file is of a first file type. The next step is inspecting the appearance of the wafer. When the user detects defects on the wafer, the positions of the defects are directly recorded in the map file and then the modified map file is saved. The map file can be directly modified when the wafer is in the testing procedure so that the testing time is reduced. Furthermore, the precision of the testing is improved. | 2009-04-16 |
20090096463 | HYBRID VEHICLE TESTING SYSTEM AND METHOD - In a hybrid vehicle, first, an engine is locked by an engine shaft locking mechanism. A first motor is connected to a first inverter circuit and a second motor is connected to a second inverter circuit and then both the motors are operated, and the output characteristics of each motor are obtained. Further, the first motor is connected to the second inverter circuit and the second motor is connected to the first inverter circuit and then both the motors are operated, and the output characteristics of each motor are obtained. Based on the obtained output characteristics, it is determined whether each of the motors and the inverter circuits is normal or not. | 2009-04-16 |
20090096464 | Electrical leakage detecting device for a fuel cell system - An electrical leakage determining circuit determines the occurrence of electrical leakage at a negative electrode of a fuel cell when a potential difference V between a positive electrode of the fuel cell and ground, which is detected by a potential difference detecting circuit, exceeds a preset potential difference threshold Vth, and determines the occurrence of electrical leakage at the positive electrode of the fuel cell when an insulation resistance R between the positive electrode of the fuel cell and ground, which is detected by a resistance detection circuit, falls below a resistance threshold Rth preset to be equal to or smaller than a resistance value Rw of a coolant. Upon determination of the occurrence of electrical leakage, the electrical leakage determining circuit opens a switching contact provided on a power supply line to interrupt power supply from the fuel cell to various power consumption components. | 2009-04-16 |
20090096465 | TEST EQUIPMENT - A test apparatus for a DUT having a bidirectional differential interface is provided. | 2009-04-16 |
20090096466 | Passive Intermodulation Test Apparatus - A portable test apparatus for conducting a plurality of tests on a communications device is provided. The unit | 2009-04-16 |
20090096467 | Contact Free Absolute Position Determination of a Moving Element in a Medication Delivery Device - The present invention relates to a medication delivery device for expelling set doses of medicament, the medication delivery device comprising a position determining assembly for detecting absolute positions of a rotatably mounted member arranged within the device, the position determining assembly comprising a plurality of transmitter electrodes arranged on a first exterior surface part of the rotatably mounted member, a plurality of receiver electrodes arranged on a second exterior surface part of the rotatably mounted member. A number of transmitter electrodes form pairs of interconnected electrodes with a number of receiver electrodes. A reading assembly fixedly arranged relative to for example the housing of the medication delivery device is also provided. The reading assembly comprises a plurality of transmitters arranged to electrically couple to one or more receiver electrodes, the reading assembly further comprising a plurality of receivers arranged to electrically couple to one or more transmitter electrodes. | 2009-04-16 |
20090096468 | HEAD REST DEVICE FOR VEHICLE - When moving a head rest front portion in a full-open position direction, an ECU determines that the head rest front portion comes close to an occupant head portion on the basis of a detection result of an electrostatic capacitance sensor so as to stop the head rest front portion, and determines that the head rest front portion comes close to the occupant head portion on the basis of an absolute capacitance change with respect to a reference electrostatic capacitance value of the electrostatic capacitance sensor. Alternatively, the ECU determines that the head rest front portion comes close to the occupant head portion on the basis of a change amount of the electrostatic capacitance value of the electrostatic capacitance sensor. | 2009-04-16 |
20090096469 | Determining Key Resistance Values - A system for determining a correct resistor key value for a vehicle equipped with a theft deterrent system includes a test key having two electrical contacts positioned to engage respective contacts of a vehicle theft deterrent system when the test key is inserted into a vehicle ignition key receptacle, and a scanner connected to the electrical contacts of the test key. The scanner includes a controller configured to sequentially apply a series of discrete, fixed electrical resistance values across the key contacts while the key is inserted in the receptacle, to determine which resistance value corresponds to a resistance value required to activate the ignition. | 2009-04-16 |
20090096470 | Systems and Methods for Measuring the Electrical Properties of a Microparticle - A method of measuring the electrical properties of a microparticle is provided, which can include multiple steps. Steps can include situating the microparticle within an array of electrodes submerged in a conductive medium so that the microparticle and electrodes are in electrical communication when the electrodes are energized, and delivering an electrical signal into the medium from one electrode to an immediately adjacent electrode. High frequency signals can be used to penetrate the microparticle boundary and characterize the same, and low frequency signals can be used to characterize the shape and orientation of the microparticle. Characterization can be carried out by measuring the impedance affecting the current using at least one of a remaining electrode in the array. | 2009-04-16 |
20090096471 | Method and apparatus for electrochemical corrosion monitoring - A method and apparatus for simultaneously and continuously monitoring both the general and localized corrosion of a working metallic electrode is provided, wherein a low frequency, low amplitude periodic potential excitation is used to perturb the electrode around its free corrosion potential. The potential is controlled with respect to a reference electrode by means of a potentiostat, and an auxiliary electrode used to stimulate current flow. The current response of the working electrode is monitored and analyzed continuously for general and localized corrosion activity. Means are provided for validation of the integrity of the current response to the applied potential excitation. Simultaneous and continuous outputs for both general and localized corrosion activity are also provided. | 2009-04-16 |
20090096472 | Replaceable Probe Apparatus for Probing Semiconductor Wafer - A probe apparatus is provided with a plurality of probe tiles, an interchangeable plate for receiving the probe tiles, a floating plate being disposed between the respective probe tile and a receiving hole on the interchangeable plate, and a control mechanism providing multi-dimensional freedom of motions to control a position of the probe tile relative to the respective receiving hole of the interchangeable plate. A method of controlling the floating plate is also provided by inserting a pair of joysticks into two respective adjustment holes disposed on the floating plate and moving the pair of joysticks to provide translational motions (X-Y) and rotational (theta) motion of the floating plate, and turning the pair of jack screws clockwise and counter-clockwise to provide a translational motion (Z) and two rotational (pitch and roll) motions of the floating plate. | 2009-04-16 |
20090096473 | TESTING PROBE AND ELECTRICAL CONNECTION METHOD USING THE SAME - A testing probe including a shaft body and a plurality of claws is provided. Each cross section of the shaft body has a substantially identical shape and a substantially identical outer diameter. The claws are formed integrally with the shaft body at an end thereof. An orthogonal projection of the claws on any one of the cross sections of the shaft body is within the contour of the cross section. Contacting a solder bump on a test pad of a circuit board with the claws of the testing probe increases the test yield of the circuit board. | 2009-04-16 |
20090096474 | DIE DESIGN WITH INTEGRATED ASSEMBLY AID - Methods and systems for inserting and replacing swaged probe pins in a lower die portion of a head having an array of micro-holes for receiving the probe pins are disclosed. The methods and systems include the following: swaged probe pins including substantially cylindrical ends and a swaged center portion; and an assembly aid film including an array of slotted holes, each of the slotted holes including a substantially round portion for receiving the substantially cylindrical ends of the swaged probe pins and slot portions for receiving the swaged center portion of the swaged probe pins. The array of slotted holes is configured to properly align the swaged probe pins with the array of micro-holes. | 2009-04-16 |
20090096475 | TEST DEVICE - A test device includes a movable mounting table having a temperature controlling mechanism therein; a probe card provided with a plurality of probes positioned above the mounting table; and a first temperature control unit for controlling the temperature controlling mechanism so that a target object on the mounting table can be heated to a predetermined temperature to test electrical characteristics of the target object. The mounting table is provided with a heater facing a plurality of probes protruding from the mounting table in the high-temperature test on the target object. | 2009-04-16 |
20090096476 | Method of inspecting semiconductor circuit having logic circuit as inspection circuit - A semiconductor circuit includes an inspection circuit for inspecting terminal open of the semiconductor circuit. The semiconductor circuit has a plurality of input terminals. The semiconductor circuit includes an input circuit portion connected to the plurality of input terminals. The inspection circuit includes a logic circuit, supplied with a plurality of input signals from the input circuit portion, for performing a predetermined logic operation to the plurality of input signals to produce a logic operation result. Whereby the semiconductor circuit enables to decide the presence or absence of the terminal open on the basis of the logic operation result. | 2009-04-16 |
20090096477 | APPARATUS AND METHODS FOR PERFORMING A TEST - A circuit structure has a circuit portion with negative resistance and a test resonator structure. Furthermore, the circuit structure has a unit for coupling the test resonator structure to the circuit portion with negative resistance during testing and for decoupling the test resonator structure from the circuit portion with negative resistance after testing. | 2009-04-16 |
20090096478 | RECONFIGURABLE CONNECTIONS FOR STACKED SEMICONDUCTOR DEVICES - Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections. | 2009-04-16 |
20090096479 | System and method for automated detection of singular faults in diode or'd power bus circuits - A system automatically detects singular faults in diode or'd power bus circuit comprised of a plurality of diodes. The system includes a diode test circuit that selectively applies a voltage pulse to one of the plurality of diodes and detects the presence of singular faults based on the monitored response to the voltage pulse. | 2009-04-16 |
20090096480 | IO DRIVER WITH SLEW RATE BOOST CIRCUIT - An IO driver utilizes a slew rate boost circuit coupled to an IO driver circuit to improve the slew rate of the driver during transitions on the output of the driver. One or more additional output stages are coupled in parallel with a primary output stage of the driver, and are temporarily activated responsive to a transition in an input signal to the driver to effectively decrease the output impedance and boost the pull-up and pull-down time response characteristics of the driver during the transition of the output. The additional output stages are active only for a small part of a cycle, so the slew rate is thereby increased while the effective output impedance during most of the cycle is essentially unaffected. | 2009-04-16 |
20090096481 | SCHEDULER DESIGN TO OPTIMIZE SYSTEM PERFORMANCE USING CONFIGURABLE ACCELERATION ENGINES - A reusable hardware control structure is provided for a hardware acceleration engine that can be configured for implementation within an electronic integrated circuit design according to any one of a plurality of configuration alternatives. The reusable hardware control structure comprises a digital logic circuit design developed to receive configuration data from the hardware acceleration engine describing a selected configuration alternative. The selected configuration alternative is any one of the plurality of configuration alternatives. The digital logic circuit design is developed to process the configuration data to provide an evaluation of an input-to-output latency and an input blocking pattern of the hardware acceleration engine configured according to the selected configuration alternative. The evaluation is capable of being leveraged by control logic within the electronic integrated circuit design to increase utilization of the hardware acceleration engine. | 2009-04-16 |
20090096482 | INTEGRATED CIRCUIT HAVING A CONFIGURABLE LOGIC GATE - In one general aspect, a system may include a circuit board, a first integrated circuit attached to the circuit board, and a second integrated circuit attached to the circuit board being separate from the first integrated circuit and configured to operate in multiple power domains that include at least a core power domain and an I/O power domain and that is configured with a logic gate to receive and process external requests from the first integrated circuit and internal requests from the second integrated circuit for a common external resource. | 2009-04-16 |
20090096483 | Asynchronous Clock Gate With Glitch Protection - A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an input signal to the tristate buffer and a gating stage having inputs for the input signal, a delayed input signal and an asynchronous tristate control signal and an output supplying the configuration signal to the tristate buffer. The gating stage sets the configuration signal to the high impedance mode only when the tristate control signal is set and the input signal and the delayed input signal have logic levels indicating that no signal transition of the input signal propagates within the delay stage. Depending upon signal polarity, the input signal and the delayed input signal are required to have the same digital state or opposite digital states. | 2009-04-16 |
20090096484 | LEVEL SHIFTERS - Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises first and second output terminals. First and second drivers are coupled between the first output terminal and the first power voltage and between the second output terminal and the second power voltage respectively. When one of the first and second power voltages is not ready during power-up, the first driver matches a voltage level on the first output terminal with the first power voltage by AC coupling and the second driver pulls low or maintains a voltage level on the second output terminal. | 2009-04-16 |
20090096485 | Systems and Methods for Dynamic Logic Keeper Optimization - Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic devices with a logic circuit that includes an inverting output buffer, a logic function, a bias transistor, and a current circuit. An input of the logic function is electrically coupled to a logic input, an output of the logic function is electrically coupled to an input of the inverting output buffer, and the logic function exhibits a leakage current. The gate of the bias transistor is electrically coupled to an output of the inverting buffer, and a first leg of the bias transistor is electrically coupled to the input of the inverting buffer. The current circuit supplies a current corresponding to the to a second leg of the bias transistor. In some cases, an improved performance may be achieved for a given leakage, or a reduced leakage may be achieved for a given performance. | 2009-04-16 |
20090096486 | Structure for Transmission Gate Multiplexer - A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer. | 2009-04-16 |
20090096487 | SENSE AMPLIFIER CONTROL CIRCUIT - The present invention discloses a sense amplifier control circuit which controls the sense amplifier. A sense amplifier control circuit comprises a voltage comparing unit outputting delay control signals having a value corresponding to each of divided voltages obtained by dividing a potential of a power supply voltage and a pull-up control signal generating unit outputting an overdrive control signal and a pull-up control signal by an active signal and changing an enable pulse width of the overdrive control signal in response to the delay control signals, whereby it is possible to reduce current consumption caused by unnecessary overdrive operation and prevent a potential drop of the power supply voltage and thus provide operational stability of the semiconductor memory device by providing the overdrive control signal of which the enable pulse width is controlled in response to the potential of the power supply voltage. | 2009-04-16 |
20090096488 | TIME CONSTANT CALIBRATION DEVICE AND RELATED METHOD THEREOF - A time constant calibration device includes: a first voltage generating circuit utilizing a first current passing through a capacitive component to generate a first voltage; a second voltage generating circuit utilizing a second current passing through a resistive component to generate a second voltage; and a comparing circuit for comparing the first voltage with the second voltage to generate a comparing signal, wherein the first voltage generating circuit comprises an analog adjusting component for adjusting the first voltage according to the comparing signal until the first voltage is equal to the second voltage whereby an RC time constant defined by an equivalent capacitance corresponding to the first current passing through the capacitive component and an equivalent impedance corresponding to the second current passing through the resistive component reaches a predetermined value. | 2009-04-16 |
20090096489 | HIGH VOLTAGE TOLERANT OVER-CURRENT DETECTOR - A system comprising an over-current detector configured to receive a switching voltage signal and to produce a first and a second current signal; an current-to-voltage converter configured to convert the first and second current signals into a first and a second voltage signal; and a current mirror amplifier configured to utilize the first and second voltage signals to output an over-current condition signal when the switching signal has exceeded a threshold value. | 2009-04-16 |
20090096490 | Transconductor - A transconductor to convert an input voltage to an output current, includes: a primary transconductance stage to provide the output current from the input voltage and a driving current; an adaptive transconductance stage coupled in series with the primary transconductance stage to generate the driving current from the input voltage; and a bias circuit coupled to provide a primary bias voltage to the primary transconductance stage and an adaptive bias voltage to the adaptive transconductance stage. | 2009-04-16 |
20090096491 | DRIVER CIRCUIT, DATA DRIVER, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT - A driver circuit includes a first capacitor provided between a first node and a reference node, a second capacitor provided between a second node and the reference node, a first switch element provided between the first node and an input node, a second switch element provided between the first node and an analog reference power supply, a third switch element provided between the second node and an output node, a fourth switch element provided between the second node and the analog reference power supply, and a fifth switch element provided between the output node and the reference node. A first capacitor area and a second capacitor area are disposed along a first direction. The first switch element and the second switch element are disposed in a third direction with respect to the first capacitor area and the second capacitor area. The third switch element and the fourth switch element are disposed in the first direction with respect to the first capacitor area and the second capacitor area. A reference node line is provided in a second direction with respect to the first switch element, the second switch element, the third switch element, and the fourth switch element. | 2009-04-16 |
20090096492 | Output Driver Equipped with a Sensing Resistor for Measuring the Current in the Output Driver - An electronic circuit has an output driver for providing a driving signal. The output driver has a transistor with a first main terminal, a second main terminal and a control terminal coupled to receive a control signal, a power supply terminal, an output terminal for providing the driving signal that is coupled to the second main terminal, and a sensing resistor coupled between the power supply terminal and the first main terminal. The output driver further has means for temporarily disabling the coupling between the control terminal and the control signal during a peak voltage across the sensing resistor. The means may have a circuit that has a unidirectional current behavior, such as a diode, in series with the control terminal of the transistor. | 2009-04-16 |
20090096493 | Driving circuit, LED head and image forming apparatus - A driving circuit is supplied capable of preventing excessive overshoot from occurring when electric current of LED rises; preventing degradation of LED that is caused by peak electric current; and preventing the life of LED from shortening. In the driving circuit, a drive transistor supplies drive electric current to record elements to construct an array, and a reference electric current generating circuit that provides a control voltage to the drive transistor and controls the drive electric current, wherein the drive transistor is composed of a first PMOS transistor and a second PMOS transistor that are connected in series; and the reference electric current generating circuit has a resistance element and a operational amplifier that are used to set a reference electric current for deciding the control voltage, wherein an output of the operational amplifier is provided to a control terminal of the first PMOS transistor; and a drive electric current ON/OFF signal to control on/off of the drive electric current is provided to a control terminal of the second PMOS transistor. | 2009-04-16 |
20090096494 | Circuit Arrangement For Generating A Complex Signal And The Use Of This Circuit Arrangement In A High-Frequency Transmitter Or Receiver - A circuit arrangement for generating an IQ signal which comprises an oscillator ( | 2009-04-16 |
20090096495 | Ring oscillator for temperature sensor, temperature sensor circuit, and semiconductor device having the same - A ring oscillator includes an odd number of unit circuits connected in series each of which includes an inverter. Each of the unit circuits includes the inverter and a MOSFET. The MOSFET is an FET which is a temperature sensor, and uses a drain-source leakage current in a state that the FET is normally turned off. | 2009-04-16 |
20090096496 | PHASE-LOCKED LOOP AND CONTROL METHOD UTILIZING THE SAME - A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode. | 2009-04-16 |
20090096497 | DESIGN STRUCTURES INCLUDING MULTIPLE REFERENCE FREQUENCY FRACTIONAL-N PLL (PHASE LOCKED LOOP) - A design structure including a system. The system includes a fractional-N phase-locked loop (PLL). The PLL includes a PLL input and a PLL output. The fractional-N PLL further includes a multiplexer. The multiplexer includes a multiplexer output electrically coupled to the PLL input. The multiplexer further includes M multiplexer inputs, M being an integer greater than 1. Two or more reference frequencies are applied to the inputs of the multiplexer, by the selection of one from the reference frequencies, the low spur can be reached. | 2009-04-16 |
20090096498 | Receiver system and method for automatic skew-tuning - A receiver system is provided. The receiver system includes a control unit for outputting a control signal and a selective signal, a PLL unit for generates PLL clock signals based on an initial clock signal, a phase select unit for selecting one of the PLL clock signals as a base clock signal according to the selective signal, a DLL unit for generating DLL clock signals based on the base clock signal, a sampling clock unit for generating left and right clock signals based on the DLL clock signals and a data latch unit for sampling bit data according to the left, DLL, and right clock signals to obtain left, middle and right data, which are feedback to the control unit for outputting the control signal and the selective signal to adjust the left, DLL and right clock signals or select the base clock signal for next bit data. | 2009-04-16 |
20090096499 | Apparatus and method for power amplification with delay control in wireless communication system - A transmitting apparatus and method for power amplification with delay control in a wireless communication system are provided. The apparatus includes signal converters, a delay difference measurer, and a delay controller. The signal converters separate a baseband signal into an envelope signal and a phase modulated signal. The delay difference measurer measures a delay difference between an envelope signal path and a phase modulated signal path using a correlation coefficient extraction and interpolation technique. The delay controller sets a delay in a clock period unit to a signal path having a small delay and sets a delay by a remainder delay difference to a signal path having a large delay, depending on the measured delay difference. | 2009-04-16 |
20090096500 | SKEW COMPENSATION CIRCUIT - The present invention describes a skew compensation circuit that can compensate for changes in signal skew in response to changes in external environments and processes. The skew compensation circuit includes a controller for outputting a control signal according to whether an external power supply is supplied and its operation mode. The skew compensation circuit also includes a signal output unit which selects either a normal path or a skew reduction path according to the control signal and outputs an input signal through the selected path. | 2009-04-16 |
20090096501 | APPARATUS AND METHOD FOR PREVENTING SNAP BACK IN INTEGRATED CIRCUITS - A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on. | 2009-04-16 |
20090096502 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device includes arms formed by two semiconductor elements, a map memory device which stores therein a correlation map between a control value for each of the arms and an optimized dead time to be set for the control value or is capable of storing the same therein, drive control value acquiring means for acquiring a drive control value of each of the arms, and a dead time generating circuit for extracting the optimized dead time corresponding to the drive control value from the correlation map. The time taken until the other of the semiconductor elements is turned on after one thereof has received a command to turn off the same is the optimized dead time extracted by the dead time generating circuit. | 2009-04-16 |
20090096503 | SEMICONDUCTOR DEVICE COMPRISING A HOUSING CONTAINING A TRIGGERING UNIT - A housing for a semiconductor device is disclosed. In an exemplary embodiment of the present invention, the housing comprises a semiconductor substrate that is arranged between two contact elements, one contact element forming an anode contact element and another contact element forming a cathode contact element, the semiconductor substrate having, on at least one surface, a gate electrode that is contacted by a gate contact element, the first contact element forming a surface arranged across from the gate electrode and at a distance from the gate electrode. Also included is at least one driver unit for generating a gate current, the driver unit comprising a first terminal that is contacted with the gate contact element, and a second terminal that is contacted with a first of the two contact elements. A housing according to an exemplary embodiment of the present invention additionally comprises a spring element arranged so that a spring force brings the gate contact element into pressure contact with the gate electrode and, at substantially the same time, the spring force brings the second terminal of the driver unit into pressure contact with the surface of the first contact element that is located across from the gate electrode. | 2009-04-16 |
20090096504 | Data reception apparatus and microcomputer having the same - A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value. | 2009-04-16 |
20090096505 | SYSTEMS, CIRCUITS AND METHODS FOR REDUCING THERMAL DAMAGE AND EXTENDING THE DETECTION RANGE OF AN INSPECTION SYSTEM - Inspection systems, circuits, and methods are provided to enhance defect detection by reducing thermal damage to large particles by dynamically altering the incident laser beam power level supplied to the specimen during a surface inspection scan. In one embodiment, an inspection system includes an illumination subsystem for directing light to a specimen at a first power level, a detection subsystem for detecting light scattered from the specimen, and a power attenuator subsystem for dynamically altering the power level directed to the specimen based on the scattered light detected from the specimen. For example, the power attenuator subsystem may reduce the directed light to a second power level, which is lower than the first, if the detected scattered light exceeds a predetermined threshold level. In addition reducing thermal damage, the systems and methods described herein may be used to extend the measurement detection range of an inspection system by providing a variable-power inspection system. | 2009-04-16 |
20090096506 | POWER SUPPLY CIRCUIT - According to an aspect of the present invention, there is provided a power supply circuit including: a detection circuit that is connected to an external power supply voltage and that outputs a first signal indicating whether the external power supply voltage is in a dropped-state in which the external power supply voltage is dropped below a reference voltage; a control circuit that includes: a delay circuit that outputs a second signal acquired by delaying the first signal for a reference time; and a determination circuit that outputs a third signal based on the first signal and the second signal; a generation circuit that generates internal power supply voltage from the external power supply voltage and that supplies the internal power supply voltage; and an interruption circuit that interrupts the internal power supply voltage supplied from the generation circuit based on the third signal. | 2009-04-16 |
20090096507 | Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor - An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results. | 2009-04-16 |
20090096508 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention provides a charge pump circuit capable of achieving desired boosting operation even when a high-side switch for precharge or a low-side switch for driving output is constructed by a low-withstand-voltage transistor. The high level of a drive input signal for driving a high-side switch for precharge and a low-side switch for driving output in response to a clock signal is set to the level of a boosted output voltage. The low level of the drive input signal is set to the level of an input voltage, not ground potential. | 2009-04-16 |
20090096509 | Bandgap Reference Circuits for Providing Accurate Sub-1V Voltages - A reference voltage circuit includes a first PMOS device having a first source, a first gate, and a first drain, wherein the first source is coupled to a power supply node; and a second PMOS device having a second source, a second gate and, a second drain. The second source is coupled to the power supply node. The first and the second PMOS devices have constant source-drain currents. The reference voltage circuit further includes a third PMOS device having a third source, a third gate, and a third drain; and a resistor coupled between the third drain and the ground. The third source is coupled to the power supply node. The first, the second, and the third gates are interconnected. The first, the second, and the third drains are virtually interconnected. | 2009-04-16 |
20090096510 | REFERENCE VOLTAGE GENERATING CIRCUIT FOR USE OF INTEGRATED CIRCUIT - An amplifying circuit receives an output from a comparator. The output is provided to each gate of first, second and third transistors. First and second resistors are connected in series. The first and second resistors and a first diode are connected to a drain of the first transistor. Second diodes are connected in parallel. The second diodes are connected to one end of a third resistor. The other end of the third resistor is connected to a drain of the second transistor. Fourth and fifth resistors are connected in series. One end of the fourth resistor is connected to the drain of the second transistor. The comparator receives first and second feedback voltages respectively obtained from a connection node between the first and second resistors and a connection node between the fourth and fifth resistors. A drain of the third transistor outputs a reference voltage. | 2009-04-16 |
20090096511 | METHOD AND APPARATUS FOR HIGH PERFORMANCE SWITCH MODE VOLTAGE REGULATORS - A circuit configuration for a high power switch-mode voltage regulator circuit is disclosed that includes an array of Metal Oxide Semiconductor (MOS) switching transistors electrically coupled to one another at their drains and sources, and a plurality of gate driver circuits. Each gate driver circuit is coupled substantially close to the gate and dedicated to driving only one MOS switching transistor. | 2009-04-16 |
20090096512 | Standby modes for integrated circuit devices - An integrated circuit device comprises an internal pull up current source Ipup and a pull up resistor Rpup connected in parallel between a voltage supply pin Vs and an output node OUT. A standby switch SBY is connected in series with the pull up resistor Rpup. The standby switch SBY is controlled by a standby detect means SBY Detect, which is also connected to the output node OUT. If it is desired to switch the device to standby mode, the output node OUT is externally drawn to ground by microprocessor | 2009-04-16 |
20090096513 | Multiple circuit blocks with interblock control and power coservation - A semiconductor integrated circuit is provided including a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The integrated circuit includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off. | 2009-04-16 |
20090096514 | METHOD AND APPARATUS FOR PROVIDING CANCELLATION OF HARMONICS SIGNALS WITH MODULATED SIGNALS FOR MULTI-CHANNELS - A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal. | 2009-04-16 |
20090096515 | FILTER ADJUSTMENT METHOD AND FILTER ADJUSTMENT APPARATUS AS WELL AS FILTER CIRCUIT - The object is to provide a filter circuit as well as a filter adjustment method and a filter adjustment apparatus that can adjust the characteristics of an analog filter by use of a simple configuration. | 2009-04-16 |
20090096516 | Semiconductor integrated circuit device having control circuit to selectively activate decoupling cells - The semiconductor integrated circuit device includes a plurality of decoupling cells that suppress power noise respectively, a plurality of power switches that connect the decoupling cells to a power line respectively, and a control circuit that controls the number of power switches selected from among the plurality of power switches and to be turned on according to power noise to be changed according to the operation state of each of internal circuits driven by a power supplied from the power line. | 2009-04-16 |
20090096517 | Filtering apparatus and method for dual-band sensing circuit - A filtering apparatus and method for dual-band sensing circuit are disclosed. The invention features a dual-band sensing unit disposed in a filtering device that receives the signals from a sub-system with variable frequency spectrum. The signals are split up into several bands. After that, one or more frequency detecting units are used to detect the power of high-band and low-band signals, and convert the power into a voltage signal. Users can externally adjust the gain of a tunable gain amplifier for the voltage signal. Further, a comparison operation is processed by a comparator, and a signal resulted from the comparison operation is used to control the switch timing for an RF switching unit. Consequently, this like adaptive notch filter is achieved to determine the intensity of noise and thereby to turn on the high-band or low-band notch filters, so as to reduce the in-band loss. | 2009-04-16 |
20090096518 | Matrix Converters - A matrix converter that can be used as part of a two-stage power converter has three ac three ac voltage lines AC | 2009-04-16 |
20090096519 | CONFIGURABLE DEMODULATOR AND DEMODULATION METHOD - A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison. | 2009-04-16 |
20090096520 | DETECTOR OF A RADIO-FREQUENCY SIGNAL - A method and a circuit for detecting a radio-frequency signal, including at least one first MOS transistor with a channel of a first type, having its gate coupled to an input terminal capable of receiving said signal; a circuit for biasing the first transistor, capable of biasing it to a level lower than its threshold voltage; and a circuit for determining the average value of the current in the first transistor. | 2009-04-16 |
20090096521 | POWER AMPLIFIER PREDISTORTION METHODS AND APPARATUS USING ENVELOPE AND PHASE DETECTOR - An embodiment of the invention is a predistortion approach to linearize a power amplifier without frequency conversion of the RF signals by using envelope and phase detectors to detect the error to be corrected, and then one or more analog multiplier(s) and a DSP-based processor. For the analog embodiment, the inherent nature of the analog circuitries allows digital predistortion processing structured directly at the RF band, and enables a single power amplifier to support multi-modulation schemes, multi-carriers and multi-channels. As a result, the predistortion architecture is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems. The wireless system performance can be improved and upgraded just by using the new PA module rather than change or rebuild new subsystem in existing base station. The analog embodiment can also mix and match its analog multipliers with other analog components such as phase splitters, phase shifters, attenuators, filters, couplers, mixers, low-noise amplifiers, buffers, envelope detectors, and etc., to provide additional features. | 2009-04-16 |
20090096522 | AMPLIFIER CIRCUIT - An amplifier circuit easily suppresses an intermodulation distortion signal incident to amplification. An input signal is class A amplified to be | 2009-04-16 |